US20020127772A1 - Bumpless flip chip assembly with solder via - Google Patents

Bumpless flip chip assembly with solder via Download PDF

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Publication number
US20020127772A1
US20020127772A1 US09/852,824 US85282401A US2002127772A1 US 20020127772 A1 US20020127772 A1 US 20020127772A1 US 85282401 A US85282401 A US 85282401A US 2002127772 A1 US2002127772 A1 US 2002127772A1
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solder
metallization
recited
via hole
chip
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US09/852,824
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Charles Lin
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Definitions

  • This invention relates generally to a semiconductor device assembly, and in particular, relates to a connection of integrated circuit (IC) chip or chips to substrate circuitry, printed circuit board, and interconnect components.
  • IC integrated circuit
  • wire bonding has been the far most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one wire bond at a time between the semiconductor chip's bonding pads and the appropriate interconnect points. Furthermore, because of the ever increasing operational frequency of the device, the length of the interconnects needs to be shorter to minimize inductive noise in power and ground, and also to minimize crosstalk between the signal leads.
  • An example of such a method is disclosed in U.S. Pat. No. 5,397,921 issued to Karnezos.
  • Flip chip technology is characterized by mounting of the unpackaged semiconductor chip with the active side facing down to an interconnect substrate through contact anchors such as solder, gold or organic conductive adhesive bumps.
  • the major advantage of flip chip technology is the short interconnects which can, therefore, handle high speed or high frequency signals. There are essentially no parasitic elements, such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated.
  • Flip chip also allows an array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al.
  • Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a reflow step to form the solder contacts.
  • evaporation and sputtering can potentially offer high density bumps, these processes need very tight control and normally result in poor yield.
  • a conventional flip chip assembly is not only very costly but also suffers from very serious reliability problems and a high fatality ratio.
  • the device and method of the present invention involve the bonding of substrate circuitry to a semiconductor device through the reflowing of pre-deposited solder to connect via apertures or holes of the substrate to terminal pads of the semiconductor device without the need for conventional bumps, bonding wire, or other media.
  • the present invention relates to a chip assembly that includes a single or multi-layered substrate of which circuitry is connected to the input/output terminal pads of the IC chip through solder reflow in the via holes.
  • the solder deposition techniques include electrolytic plating, electroless (chemical) plating, wave soldering, meniscus coating and solder printing.
  • soldering material directly reflowed between a via hole and a terminal pad can effectively connect an IC chip and dielectric substrate circuitry without external bumps or wires.
  • This approach allows a reliable, low profile, high performance and low cost assembly to be achieved.
  • a small via hole formed by laser drilling or other techniques allows a very fine pitch terminal pad to be interconnected, which can significantly enhance the capability of packaging future high 1 / 0 semiconductor chips.
  • FIG. 1A is a fragmented partial sectional side elevational view of a substrate before plating the via hole with solder.
  • FIG. 1B is a fragmented partial sectional side elevational view of the substrate of the type shown in FIG. 1A after plating the via hole with solder.
  • FIG. 1C is a fragmented partial sectional side elevational view of a semiconductor chip having a terminal pad.
  • FIG. 1D is a fragmented partial sectional side elevational view of a chip assembly after a semiconductor chip of the type shown in FIG. 1C has been attached to a substrate of the type shown in FIG. 1B.
  • FIG. 1E is a fragmented partial sectional side elevational view of the chip assembly of the type shown in FIG. 1D after a solder reflow process.
  • the bumpless flip chip assembly of the present invention includes a rigid or flexible dielectric substrate having a plurality of electrically conductive circuitry traces and a plurality of via apertures or holes.
  • the conductive traces on the surface of the substrate extend into the via holes through the conductive material deposited on the via hole walls.
  • This plated through-hole (PTH) material such as plated copper, gold, nickel, titanium or palladium provides a conductive base for solder deposition or solder wetting.
  • Soldering material such as tin-lead alloy or lead-free solder is pre-deposited in the via hole or on the terminal pad. This readily available solder serves as the joint material after the substrate is attached to the semiconductor chip.
  • the orientation of the attachment between the chip and substrate circuitry ensures that at least one of the via holes in the dielectric substrate is aligned with a terminal pad.
  • the IC chip is brought in contact with the dielectric substrate through an adhesive film or paste, or mechanical techniques such as mechanical clamping.
  • This soft or proximity contact ensures that the pre-deposited soldering material is able to reflow into the via hole as well as onto the terminal pad when it is molten.
  • Heat which serves to activate the flux and bring the solder to its melting point, is used to effect the metallurgical bonding.
  • This re-flow process results in a solder joint which electrically and physically connects the via hole and IC pad. This not only assures a very cost effective and simple process, but also provides a compliant joint with significant stress release which results in a very reliable connection between the substrate circuitry and IC chip.
  • the preferred embodiment is particularly directed to the bonding of an integrated circuit (IC) chip to a flexible circuitized substrate, or to a more rigid, circuitized substrate, a particular example of the latter being a printed circuit board. It is to be understood, however, that the invention is not limited to the attachment to printed circuit boards, in that other circuitized substrates, including known plastic and ceramic substrates, may be employed. Typically, an organic-type substrate is preferable for lower cost and superior dielectric property whereas an inorganic-type substrate is preferable when high thermal dissipation and matched coefficient of expansion are desired.
  • substrate as used herein is defined as at least one layer of dielectric material having at least one conductive layer thereon.
  • Such structures may include many more electrically conductive layers than those depicted in FIGS. 1A through 1E, depending on the desired operational characteristics. As is known, such electrically conductive layers may function as signal, power, and/or ground layers.
  • the solder pre-deposition is in the via hole.
  • the via holes are first metallized with a base metal by a conventional plated through hole (PTH) technique followed by solder deposition.
  • PTH plated through hole
  • Solder deposition techniques include electroplating, electroless plating, wave soldering, meniscus solder coating, solder paste printing and dispensing to accomplish the pre-coating of solder material onto the metallized hole wall. It is understood that the particular solder or solder paste and methods of dispensing depicted herein are not meant to limit the invention.
  • the solder pre-deposition is on the IC terminal pad.
  • a barrier layer over-coated on an aluminum pad before solder deposition is preferred. This is to provide a good solder wetting surface and protect the aluminum surface against leaching, oxidation or degradation resulting from heat and soldering contact.
  • This coating can be accomplished by sputtering a stake of thin film or by wet chemical direct plating of electroless nickel and immersion gold.
  • the pre-treatment may not be necessary when the surface is free of oxide and contamination.
  • the via holes of the substrate can be formed by various techniques including mechanical drilling, punching, plasma etching or laser drilling. They are formed in the substrate before or after the circuitry patterning depending on the various fabrication processes. The via holes are formed at locations that can be aligned with and expose input/output terminal pads of the semiconductor chip or chips that are subsequently mounted on the side of the substrate opposite the side where the electrical circuitry is formed.
  • a preferred application of heat to reflow pre-deposited solder is by a convection oven.
  • the heat may be applied by a laser to effect solder reflow and bonding to the IC terminal pads which are in the vicinity of the via holes.
  • Another example of such an approach is an infrared (IR) continuous belt reflow oven.
  • hot nitrogen gas may be directed onto the solder members of the assembly. It is understood that the particular re-flow techniques depicted above are not meant to limit the invention, in that it is also possible to reflow the solder using a vapor phase reflow system.
  • the finished product is, for instance, a ball grid array package
  • solder balls will normally be placed on the specific traces on the surface of the dielectric substrate.
  • This finished package can be connected to a printed circuit board by reflowing the solder balls to form an attachment to the conductors of the printed circuit board.
  • FIGS. 1A to 1 E are diagrammatic cross-sectional views showing steps involved in the manufacturing of an integrated circuit assembly by pre-depositing solder in the substrate via hole and re-flowing the solder to connect the terminal pad.
  • a substrate 101 having a plurality of electrically conductive circuitry traces 102 partially covered by the solder mask 103 is shown.
  • the traces 102 on the substrate 101 extend into a plurality of via holes 104 by a thin layer of plated through-hole copper 105 deposited on the via hole walls.
  • FIG. 1B shows the substrate 101 immersed in a solder plating solution and a layer of solder 106 is electroplated on the metallized via hole wall as well as on the solder opening site.
  • FIG. 1C shows an integrated circuit chip 107 having various types of transistors, wires and the like (not shown), which has a plurality of exposed input/output terminal pads 108 . These pads 108 are formed with a stake of thin film 109 in the structure of titanium (500 Angstroms)/nickel (700 Angstroms)/gold (1000 Angstroms) to serve as the barrier and adhesive layer. Passivation is disposed on chip 107 outside pads 108 .
  • FIG. 1D shows IC chip 107 securely attached to the substrate 101 by adhesive paste ABLESTIK “ABLEBOND 961-2” 110 to form an assembly 111 .
  • the orientation of the attachment is arranged in such a manner that a specific terminal pad 108 of the integrated circuit chip 107 is in contact with the solder 106 inside a specific via hole 104 .
  • the via hole 104 serves as an electrically connecting channel for the respective trace 102 of the substrate 101 .
  • FIG. 1E shows the input/output terminal pad 108 firmly joined together with a specific via hole 104 by solder joint 112 to become an integral part after the assembly 111 is placed in an oven that causes solder 106 to reflow.
  • This simultaneously-reflowed joint 112 provides an effective electrical and mechanical connection between IC chip 107 and substrate 101 .
  • the soldering material 113 deposited in the solder mask opening serves as the contacting material for the next level assembly.
  • solder systems including lead-free ones can also be applied and serve the connection purpose.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes which serve as the connection between the semiconductor device and substrate circuitry. The method of manufacturing the flip chip assembly includes the steps of attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of via holes. The via holes are aligned with the terminal pads so that the respective traces on the substrate can be connected to the respective terminal pads through the via holes. After attachment, the pre-deposited solder inside the via holes or on the terminal pads is re-flowed. This re-flow soldering process electrically connects the IC chip to the substrate. The solder can be deposited by plating, wave soldering, meniscus coating, and screen printing techniques.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application is continuation of U.S. application Ser. No. 09/465,024 filed on Dec. 16, 1999, which is an application filed in accordance with 35 U.S.C. §119 and claims the benefit of earlier filed Singapore application number 9804817-6 filed on Dec. 17, 1998.[0001]
    • 1. FIELD OF THE INVENTION
  • This invention relates generally to a semiconductor device assembly, and in particular, relates to a connection of integrated circuit (IC) chip or chips to substrate circuitry, printed circuit board, and interconnect components. [0002]
    • 2. BACKGROUND OF THE INVENTION
  • Recent developments of semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip and hence smaller input/output terminal pad pitch, shrinking die and package footprints, and higher operational frequencies that generate more heat, thus requiring advanced heat dissipation designs. All of these considerations must be met and, as usual, placed in addition to the cost that packaging adds to the overall semiconductor manufacturing costs. [0003]
  • Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely wire bonding, tape automated bonding (TAB) and flip chip (FC) to electrically or mechanically connect integrated circuits to leadframe or substrate circuitry. Wire bonding has been the far most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one wire bond at a time between the semiconductor chip's bonding pads and the appropriate interconnect points. Furthermore, because of the ever increasing operational frequency of the device, the length of the interconnects needs to be shorter to minimize inductive noise in power and ground, and also to minimize crosstalk between the signal leads. An example of such a method is disclosed in U.S. Pat. No. 5,397,921 issued to Karnezos. [0004]
  • Flip chip technology is characterized by mounting of the unpackaged semiconductor chip with the active side facing down to an interconnect substrate through contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of flip chip technology is the short interconnects which can, therefore, handle high speed or high frequency signals. There are essentially no parasitic elements, such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al. [0005]
  • While flip chip technology has tremendous advantages over wire bonding, its cost and technical limitations are significant. First of all, prior art flip chip technology must confront the challenge of having to form protruded contact anchors or bumps to serve as electrical connections between the integrated circuit chip and substrate circuitry. Examples of such an approach are disclosed in U.S. Pat. No. 5,803,340 issued to Yeh et al. and U.S. Pat. No. 5,736,456 issued to Akram. These approaches typically include a very costly vacuum process to deposit an intermediate under-bump layer that serves as an adhesive and diffusion barrier. This barrier layer is typically composed of a film stack that can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a reflow step to form the solder contacts. Although evaporation and sputtering can potentially offer high density bumps, these processes need very tight control and normally result in poor yield. As a result, a conventional flip chip assembly is not only very costly but also suffers from very serious reliability problems and a high fatality ratio. [0006]
  • Techniques for fabricating the intermediate under-bump barrier layer as well as the bump material utilizing electroless plating are also known in the prior art. An example of such a method is described in the U.S. Pat. No. 5,583,073 issued to Lin et al. Although the electroless technique provides an economical, simple and effective method for providing an under-bump barrier layer, contacting material such as solder or adhesive is still required for assembling. Solder dipping or screen printing of solder paste onto these bumps has been explored but has been met with very limited success due to lack of solder bridging control and non-uniform deposition of solder on the metal bumps. This process also suffers from poor process control as input/output terminal pad spacing gets smaller. [0007]
  • In view of the limitations of currently available integrated circuit assembling methods, a high performance, reliable and economical device and method that can effectively interconnect integrated circuits to the external circuitry would be greatly desirable. [0008]
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a flip chip assembly to address high density, low cost and high performance requirements of semiconductor packaging. The device and method of the present invention involve the bonding of substrate circuitry to a semiconductor device through the reflowing of pre-deposited solder to connect via apertures or holes of the substrate to terminal pads of the semiconductor device without the need for conventional bumps, bonding wire, or other media. [0009]
  • More specifically, the present invention relates to a chip assembly that includes a single or multi-layered substrate of which circuitry is connected to the input/output terminal pads of the IC chip through solder reflow in the via holes. The solder deposition techniques include electrolytic plating, electroless (chemical) plating, wave soldering, meniscus coating and solder printing. [0010]
  • In summary, using soldering material directly reflowed between a via hole and a terminal pad can effectively connect an IC chip and dielectric substrate circuitry without external bumps or wires. This approach allows a reliable, low profile, high performance and low cost assembly to be achieved. In particular, a small via hole formed by laser drilling or other techniques allows a very fine pitch terminal pad to be interconnected, which can significantly enhance the capability of packaging future high [0011] 1/0 semiconductor chips.
    •  BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a fragmented partial sectional side elevational view of a substrate before plating the via hole with solder. [0012]
  • FIG. 1B is a fragmented partial sectional side elevational view of the substrate of the type shown in FIG. 1A after plating the via hole with solder. [0013]
  • FIG. 1C is a fragmented partial sectional side elevational view of a semiconductor chip having a terminal pad. [0014]
  • FIG. 1D is a fragmented partial sectional side elevational view of a chip assembly after a semiconductor chip of the type shown in FIG. 1C has been attached to a substrate of the type shown in FIG. 1B. [0015]
  • FIG. 1E is a fragmented partial sectional side elevational view of the chip assembly of the type shown in FIG. 1D after a solder reflow process.[0016]
    • DETAILED DESCRIPTION OF THE INVENTION
  • The bumpless flip chip assembly of the present invention includes a rigid or flexible dielectric substrate having a plurality of electrically conductive circuitry traces and a plurality of via apertures or holes. The conductive traces on the surface of the substrate extend into the via holes through the conductive material deposited on the via hole walls. This plated through-hole (PTH) material such as plated copper, gold, nickel, titanium or palladium provides a conductive base for solder deposition or solder wetting. Soldering material such as tin-lead alloy or lead-free solder is pre-deposited in the via hole or on the terminal pad. This readily available solder serves as the joint material after the substrate is attached to the semiconductor chip. The orientation of the attachment between the chip and substrate circuitry ensures that at least one of the via holes in the dielectric substrate is aligned with a terminal pad. [0017]
  • After alignment, the IC chip is brought in contact with the dielectric substrate through an adhesive film or paste, or mechanical techniques such as mechanical clamping. This soft or proximity contact ensures that the pre-deposited soldering material is able to reflow into the via hole as well as onto the terminal pad when it is molten. Heat, which serves to activate the flux and bring the solder to its melting point, is used to effect the metallurgical bonding. This re-flow process results in a solder joint which electrically and physically connects the via hole and IC pad. This not only assures a very cost effective and simple process, but also provides a compliant joint with significant stress release which results in a very reliable connection between the substrate circuitry and IC chip. [0018]
  • As defined herein, the preferred embodiment is particularly directed to the bonding of an integrated circuit (IC) chip to a flexible circuitized substrate, or to a more rigid, circuitized substrate, a particular example of the latter being a printed circuit board. It is to be understood, however, that the invention is not limited to the attachment to printed circuit boards, in that other circuitized substrates, including known plastic and ceramic substrates, may be employed. Typically, an organic-type substrate is preferable for lower cost and superior dielectric property whereas an inorganic-type substrate is preferable when high thermal dissipation and matched coefficient of expansion are desired. The term “substrate” as used herein is defined as at least one layer of dielectric material having at least one conductive layer thereon. Printed circuit boards of similar type are well known in the electronics industry, as well as the processes for making the same, and therefore, further definition is not believed to be necessary. Such structures may include many more electrically conductive layers than those depicted in FIGS. 1A through 1E, depending on the desired operational characteristics. As is known, such electrically conductive layers may function as signal, power, and/or ground layers. [0019]
  • In one embodiment of the invention, the solder pre-deposition is in the via hole. In this embodiment, the via holes are first metallized with a base metal by a conventional plated through hole (PTH) technique followed by solder deposition. Solder deposition techniques include electroplating, electroless plating, wave soldering, meniscus solder coating, solder paste printing and dispensing to accomplish the pre-coating of solder material onto the metallized hole wall. It is understood that the particular solder or solder paste and methods of dispensing depicted herein are not meant to limit the invention. [0020]
  • In another embodiment of the invention, the solder pre-deposition is on the IC terminal pad. In this method, a barrier layer over-coated on an aluminum pad before solder deposition is preferred. This is to provide a good solder wetting surface and protect the aluminum surface against leaching, oxidation or degradation resulting from heat and soldering contact. This coating can be accomplished by sputtering a stake of thin film or by wet chemical direct plating of electroless nickel and immersion gold. For copper terminal pads, the pre-treatment may not be necessary when the surface is free of oxide and contamination. [0021]
  • The via holes of the substrate can be formed by various techniques including mechanical drilling, punching, plasma etching or laser drilling. They are formed in the substrate before or after the circuitry patterning depending on the various fabrication processes. The via holes are formed at locations that can be aligned with and expose input/output terminal pads of the semiconductor chip or chips that are subsequently mounted on the side of the substrate opposite the side where the electrical circuitry is formed. [0022]
  • A preferred application of heat to reflow pre-deposited solder is by a convection oven. Alternatively, the heat may be applied by a laser to effect solder reflow and bonding to the IC terminal pads which are in the vicinity of the via holes. Another example of such an approach is an infrared (IR) continuous belt reflow oven. Alternatively, hot nitrogen gas may be directed onto the solder members of the assembly. It is understood that the particular re-flow techniques depicted above are not meant to limit the invention, in that it is also possible to reflow the solder using a vapor phase reflow system. [0023]
  • If the finished product is, for instance, a ball grid array package, solder balls will normally be placed on the specific traces on the surface of the dielectric substrate. This finished package can be connected to a printed circuit board by reflowing the solder balls to form an attachment to the conductors of the printed circuit board. [0024]
  • FIGS. 1A to [0025] 1E are diagrammatic cross-sectional views showing steps involved in the manufacturing of an integrated circuit assembly by pre-depositing solder in the substrate via hole and re-flowing the solder to connect the terminal pad.
  • Referring initially to FIG. 1A, a [0026] substrate 101 having a plurality of electrically conductive circuitry traces 102 partially covered by the solder mask 103 is shown. The traces 102 on the substrate 101 extend into a plurality of via holes 104 by a thin layer of plated through-hole copper 105 deposited on the via hole walls.
  • FIG. 1B shows the [0027] substrate 101 immersed in a solder plating solution and a layer of solder 106 is electroplated on the metallized via hole wall as well as on the solder opening site.
  • FIG. 1C shows an [0028] integrated circuit chip 107 having various types of transistors, wires and the like (not shown), which has a plurality of exposed input/output terminal pads 108. These pads 108 are formed with a stake of thin film 109 in the structure of titanium (500 Angstroms)/nickel (700 Angstroms)/gold (1000 Angstroms) to serve as the barrier and adhesive layer. Passivation is disposed on chip 107 outside pads 108.
  • FIG. 1D shows [0029] IC chip 107 securely attached to the substrate 101 by adhesive paste ABLESTIK “ABLEBOND 961-2” 110 to form an assembly 111. The orientation of the attachment is arranged in such a manner that a specific terminal pad 108 of the integrated circuit chip 107 is in contact with the solder 106 inside a specific via hole 104. The via hole 104 serves as an electrically connecting channel for the respective trace 102 of the substrate 101.
  • FIG. 1E shows the input/[0030] output terminal pad 108 firmly joined together with a specific via hole 104 by solder joint 112 to become an integral part after the assembly 111 is placed in an oven that causes solder 106 to reflow. This simultaneously-reflowed joint 112 provides an effective electrical and mechanical connection between IC chip 107 and substrate 101. The soldering material 113 deposited in the solder mask opening serves as the contacting material for the next level assembly.
  • Though only one integrated [0031] circuit chip 107 is shown, it is to be understood that additional integrated circuit chips, as well as passive components such as resistors or capacitors, can also be mounted on the substrate 101.
  • Likewise, it is to be understood that many solder systems including lead-free ones can also be applied and serve the connection purpose. [0032]
  • The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are, therefore, to be embraced therein.[0033]

Claims (55)

What is claimed is:
15. A method of making a flip chip assembly, comprising:
attaching a substrate to a semiconductor chip, wherein the substrate includes a dielectric layer and metallization, the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces, the metallization is disposed on walls of the via hole, the chip includes a terminal pad that is aligned with the via hole, and a reflowable material that contains solder contacts the metallization and the pad; and then
reflowing the reflowable material to provide an electrical connection between the metallization and the pad.
16. The method as recited in claim 15, wherein the reflowable material is deposited on the metallization before attaching the substrate to the chip, and during the reflowing the reflowable material wets and flows on an exposed portion of the pad beneath the via hole.
17. The method as recited in claim 15, wherein the reflowable material is deposited on the pad before attaching the substrate to the chip, and during the reflowing the reflowable material wets and flows on an exposed portion of the metallization in the via hole.
18. The method as recited in claim 15, wherein the pad is directly beneath substantially all surface area defined by the via hole after the attaching.
19. The method as recited in claim 15, wherein the metallization is electrolessly plated on the walls of the via hole.
20. The method as recited in claim 15, wherein the reflowable material fills a bottom portion of the via hole without filling a top portion of the via hole after the reflowing.
21. The method as recited in claim 15, wherein the reflowable material is solder paste.
22. The method as recited in claim 15, wherein the substrate remains at a fixed position relative to the chip during the reflowing.
23. The method as recited in claim 15, wherein substantially all of the reflowable material is within the via hole after the reflowing.
24. The method as recited in claim 15, wherein the metallization and the reflowable material are the only materials in the via hole after the reflowing.
25. A method of making a flip chip assembly, comprising the following steps in the sequence set forth:
providing a substrate that includes a dielectric layer, wherein the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces;
depositing metallization on walls of the via hole;
depositing solder on the metallization such that the solder is disposed in the via hole;
attaching the substrate to a semiconductor chip that includes a terminal pad, wherein the first surface faces away from the chip, the second surface faces towards the chip, the via hole is aligned with the pad and the solder contacts the pad; and
applying heat to reflow the solder to form a solder joint that contacts and electrically connects the metallization and the pad and prevents the via hole from exposing the pad.
26. The method as recited in claim 25, including depositing the metallization on the walls using electroless plating.
27. The method as recited in claim 25, including depositing the metallization on the walls such that substantially all of the metallization is within the via hole.
28. The method as recited in claim 25, including depositing the metallization on the walls such that the metallization extends along the walls to the first and second surfaces.
29. The method as recited in claim 25, including depositing the metallization on the walls such that the metallization is aligned with the second surface.
30. The method as recited in claim 25, including depositing the solder on the metallization using electroplating.
31. The method as recited in claim 25, including depositing the solder on the metallization using electroless plating.
32. The method as recited in claim 25, including depositing the solder on the metallization using wave soldering.
33. The method as recited in claim 25, including depositing the solder on the metallization using meniscus coating.
34. The method as recited in claim 25, including depositing the solder on the metallization using solder paste printing.
35. The method as recited in claim 25, including depositing the solder on the metallization such that solder extends along the metallization to the first and second surfaces.
36. The method as recited in claim 25, including attaching the substrate to the chip such that the via hole exposes the pad.
37. The method as recited in claim 25, including attaching the substrate to the chip such that the pad is directly beneath substantially all surface area defined by the via hole.
38. The method as recited in claim 25, including attaching the substrate to the chip using an adhesive between the substrate and the chip.
39. The method as recited in claim 25, including attaching the substrate to the chip using a mechanical clamp.
40. The method as recited in claim 25, including applying the heat to reflow the solder using a convection oven.
41. The method as recited in claim 25, including applying the heat to reflow the solder using a laser.
42. The method as recited in claim 25, including applying the heat to reflow the solder using an infrared continuous belt reflow oven.
43. The method as recited in claim 25, including applying the heat to reflow the solder using hot nitrogen gas.
44. The method as recited in claim 25, including applying the heat to reflow the solder using a vapor phase reflow system.
45. The method as recited in claim 25, including applying the heat to reflow the solder such that substantially all of the solder joint is within the via hole.
46. The method as recited in claim 25, including applying the heat to reflow the solder such that the solder joint fills a bottom portion of the via hole without filling a top portion of the via hole.
47 The method as recited in claim 25, including applying the heat to reflow the solder such that the solder wets and covers an exposed portion of the pad.
48. The method as recited in claim 25, including applying the heat to reflow the solder while maintaining the substrate at a fixed position relative to the chip.
49. The method as recited in claim 25, wherein the metallization and the solder joint are the only materials in the via hole after applying the heat.
50. A method of making a flip chip assembly, comprising the following steps in the sequence set forth:
providing a semiconductor chip that includes a terminal pad;
depositing solder on the pad;
attaching a substrate to the chip, wherein the substrate includes a dielectric layer and metallization, the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces, the metallization is disposed on walls of the via hole and extends along the walls to the first and second surfaces, the via hole is aligned with the pad and exposes the solder, the solder contacts the metallization, the metallization is spaced from the pad, the first surface faces away from the chip, the second surface faces towards the chip, and the substrate is at a fixed position relative to the chip; and
applying heat to reflow the solder such that the solder wets and flows on the metallization in the via hole and forms a solder joint that contacts and electrically connects the metallization and the pad while the substrate remains at the fixed position relative to the chip.
51. The method as recited in claim 50, wherein the metallization is aligned with the second surface.
52. The method as recited in claim 50, wherein essentially all of the solder joint is in the via hole.
53 The method as recited in claim 50, wherein the pad is directly beneath essentially all surface area defined by the via hole after attaching the substrate to the chip.
54. The method as recited in claim 50, wherein the metallization and the solder joint are the only materials in the via hole after applying the heat.
55. A method of making a flip chip assembly, comprising the following steps in the sequence set forth:
providing a substrate that includes a dielectric layer, wherein the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces;
electrolessly plating metallization on walls of the via hole, wherein the metallization extends along the walls to the first and second surfaces;
electroplating solder on the metallization such that the solder is disposed in the via hole;
attaching the substrate to a semiconductor chip using an adhesive therebetween, wherein the first surface faces away from the chip, the second surface faces towards the chip, the chip includes a terminal pad, the via hole is aligned with and exposes the pad, the solder contacts the pad and the metallization is spaced from the pad; and
applying heat to reflow the solder such that the solder wets and flows on the pad and forms a solder joint that contacts and electrically connects the metallization and the pad and prevents the via hole from exposing the pad.
56. The method as recited in claim 55, wherein the metallization is aligned with the second surface.
57. The method as recited in claim 55, wherein essentially all of the solder joint is in the via hole.
58 The method as recited in claim 55, wherein the pad is directly beneath essentially all surface area defined by the via hole after attaching the substrate to the chip.
59. The method as recited in claim 55, wherein the metallization and the solder joint are the only materials in the via hole after applying the heat.
60. A method of making a flip chip assembly, comprising the following steps in the sequence set forth:
providing a substrate that includes a dielectric layer and a conductive trace, wherein the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces, and the conductive trace includes metallization disposed on walls of the via hole and a bond site disposed on the first surface and spaced from the via hole;
depositing solder on the metallization and the bond site, wherein the solder on the metallization is in the via hole, the solder on the bond site is outside the via hole, and the solder on the metallization does not contact the solder on the bond site;
attaching the substrate to a semiconductor chip, wherein the first surface faces away from the chip, the second surface faces towards the chip, the chip includes a terminal pad, the solder on the metallization contacts the pad, the metallization does not contact the pad, and the solder on the bond site does not contact the chip; and
applying heat to reflow the solder such that the solder on the metallization forms a solder joint that contacts and electrically connects the metallization and the pad, the solder on the bond site forms a solder contact that does not contact the solder joint and does not contact the chip, and the conductive trace electrically connects the solder joint and the solder contact.
61. The method as recited in claim 60, including depositing the solder on the metallization and the bond site using electroplating.
62. The method as recited in claim 60, including depositing the solder on the metallization and the bond site using electroless plating.
63. The method as recited in claim 60, including depositing the solder on the metallization and the bond site using wave soldering.
64. The method as recited in claim 60, including depositing the solder on the metallization and the bond site using meniscus coating.
65. The method as recited in claim 60, including depositing the solder on the metallization and the bond site using solder paste printing.
66. The method as recited in claim 60, wherein the metallization is aligned with the second surface.
67. The method as recited in claim 60, wherein essentially all of the solder joint is in the via hole.
68. The method as recited in claim 60, wherein the metallization and the solder joint are the only materials in the via hole after applying the heat to reflow the solder.
69. The method as recited in claim 60, wherein the pad is directly beneath essentially all surface area defined by the via hole after attaching the substrate to the chip.
US09/852,824 1998-12-17 2001-05-10 Bumpless flip chip assembly with solder via Abandoned US20020127772A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100130000A1 (en) * 2008-11-21 2010-05-27 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device
US20100267200A1 (en) * 2006-04-06 2010-10-21 Hamza Yilmaz Semiconductor die packages using thin dies and metal substrates
US20160205765A1 (en) * 2013-10-01 2016-07-14 Fujikura Ltd. Wiring board assembly and method for producing same

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406939B1 (en) * 1998-05-02 2002-06-18 Charles W. C. Lin Flip chip assembly with via interconnection
TW444236B (en) * 1998-12-17 2001-07-01 Charles Wen Chyang Lin Bumpless flip chip assembly with strips and via-fill
TW396462B (en) * 1998-12-17 2000-07-01 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
US6815829B2 (en) * 2000-03-29 2004-11-09 Rohm Co., Ltd. Semiconductor device with compact package
EP1156521A3 (en) * 2000-04-24 2007-05-23 Interuniversitair Microelektronica Centrum Vzw Low cost electroless plating process for single chips and wafer parts and products obtained thereof
US6303469B1 (en) * 2000-06-07 2001-10-16 Micron Technology, Inc. Thin microelectronic substrates and methods of manufacture
JP2002026012A (en) * 2000-07-05 2002-01-25 Murata Mfg Co Ltd Semiconductor device and method of manufacturing the same
US6511865B1 (en) 2000-09-20 2003-01-28 Charles W. C. Lin Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly
US6494361B1 (en) 2001-01-26 2002-12-17 Amkor Technology, Inc. Semiconductor module package substrate fabrication method
US6445075B1 (en) * 2001-01-26 2002-09-03 Amkor Technology, Inc. Semiconductor module package substrate
US6833526B2 (en) * 2001-03-28 2004-12-21 Visteon Global Technologies, Inc. Flex to flex soldering by diode laser
US7831151B2 (en) * 2001-06-29 2010-11-09 John Trezza Redundant optical device array
US6881609B2 (en) * 2001-09-07 2005-04-19 Peter C. Salmon Component connections using bumps and wells
US7297572B2 (en) * 2001-09-07 2007-11-20 Hynix Semiconductor, Inc. Fabrication method for electronic system modules
US6927471B2 (en) * 2001-09-07 2005-08-09 Peter C. Salmon Electronic system modules and method of fabrication
KR100476301B1 (en) * 2002-07-27 2005-03-15 한국과학기술원 Fabrication Method of multilayer UBM by Electroplating for Flip chip Interconnections
US7505862B2 (en) * 2003-03-07 2009-03-17 Salmon Technologies, Llc Apparatus and method for testing electronic systems
US20050001316A1 (en) * 2003-07-01 2005-01-06 Motorola, Inc. Corrosion-resistant bond pad and integrated device
JP4634045B2 (en) * 2003-07-31 2011-02-16 富士通株式会社 Semiconductor device manufacturing method, through electrode forming method, semiconductor device, composite semiconductor device, and mounting structure
US7408258B2 (en) * 2003-08-20 2008-08-05 Salmon Technologies, Llc Interconnection circuit and electronic module utilizing same
US20050184376A1 (en) * 2004-02-19 2005-08-25 Salmon Peter C. System in package
US20050250346A1 (en) * 2004-05-06 2005-11-10 Applied Materials, Inc. Process and apparatus for post deposition treatment of low k dielectric materials
US20050255722A1 (en) * 2004-05-07 2005-11-17 Salmon Peter C Micro blade assembly
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate
US7918383B2 (en) * 2004-09-01 2011-04-05 Micron Technology, Inc. Methods for placing substrates in contact with molten solder
US7190157B2 (en) * 2004-10-25 2007-03-13 Agilent Technologies, Inc. Method and apparatus for layout independent test point placement on a printed circuit board
US7427809B2 (en) * 2004-12-16 2008-09-23 Salmon Technologies, Llc Repairable three-dimensional semiconductor subsystem
US20070007983A1 (en) * 2005-01-06 2007-01-11 Salmon Peter C Semiconductor wafer tester
DE102005011545A1 (en) * 2005-03-10 2006-09-21 Lpkf Laser & Electronics Ag Method for contacting printed conductors of a printed circuit board
US20060251827A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. Tandem uv chamber for curing dielectric materials
US20060249175A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. High efficiency UV curing system
US20070023889A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Copper substrate with feedthroughs and interconnection circuits
US7586747B2 (en) * 2005-08-01 2009-09-08 Salmon Technologies, Llc. Scalable subsystem architecture having integrated cooling channels
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US20070023923A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Flip chip interface including a mixed array of heat bumps and signal bumps
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
JP2007158279A (en) * 2005-12-09 2007-06-21 Hitachi Ltd Semiconductor device and electronic controller using the same
US7834462B2 (en) * 2007-09-17 2010-11-16 Qimonda Ag Electric device, stack of electric devices, and method of manufacturing a stack of electric devices
TWI397978B (en) * 2007-12-12 2013-06-01 Ind Tech Res Inst Structure of chip and process thereof and structure of flip chip package and process thereof
US8278733B2 (en) * 2009-08-25 2012-10-02 Mediatek Inc. Bonding pad structure and integrated circuit chip using such bonding pad structure
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
ITMI20112084A1 (en) * 2011-11-17 2013-05-18 St Microelectronics Srl WAVE WELDING ON PRINTED CIRCUIT BOARD OF SURFACE MOUNTED ELECTRONIC DEVICES
JP6945418B2 (en) * 2017-10-24 2021-10-06 三菱電機株式会社 Semiconductor devices and manufacturing methods for semiconductor devices

Citations (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673680A (en) * 1970-12-14 1972-07-04 California Computer Products Method of circuit board with solder coated pattern
US4104111A (en) * 1977-08-03 1978-08-01 Mack Robert L Process for manufacturing printed circuit boards
US4153988A (en) * 1977-07-15 1979-05-15 International Business Machines Corporation High performance integrated circuit semiconductor package and method of making
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
US4394712A (en) * 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4499655A (en) * 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US4525246A (en) * 1982-06-24 1985-06-25 Hadco Corporation Making solderable printed circuit boards
US4613891A (en) * 1984-02-17 1986-09-23 At&T Bell Laboratories Packaging microminiature devices
US4650548A (en) * 1984-11-07 1987-03-17 Dr.-Ing. Max Schlotter Gmbh & Co. Kg Process for preserving the solderability of through hole plated printed circuit boards
US4664309A (en) * 1983-06-30 1987-05-12 Raychem Corporation Chip mounting device
US4700473A (en) * 1986-01-03 1987-10-20 Motorola Inc. Method of making an ultra high density pad array chip carrier
US4705205A (en) * 1983-06-30 1987-11-10 Raychem Corporation Chip carrier mounting device
US4748130A (en) * 1984-03-26 1988-05-31 Unisearch Limited Method of making buried contact solar cell
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4804615A (en) * 1985-08-08 1989-02-14 Macdermid, Incorporated Method for manufacture of printed circuit boards
US4925723A (en) * 1988-09-29 1990-05-15 Microwave Power, Inc. Microwave integrated circuit substrate including metal filled via holes and method of manufacture
US4926549A (en) * 1988-05-31 1990-05-22 Canon Kabushiki Kaisha Method of producing electrical connection members
US4991290A (en) * 1988-07-21 1991-02-12 Microelectronics And Computer Technology Flexible electrical interconnect and method of making
US5048747A (en) * 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
US5058800A (en) * 1988-05-30 1991-10-22 Canon Kabushiki Kaisha Method of making electric circuit device
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5129142A (en) * 1990-10-30 1992-07-14 International Business Machines Corporation Encapsulated circuitized power core alignment and lamination
US5135606A (en) * 1989-12-08 1992-08-04 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5136359A (en) * 1989-12-19 1992-08-04 Nitto Denko Corporation Anisotropic conductive film with through-holes filled with metallic material
US5145552A (en) * 1989-12-21 1992-09-08 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5160579A (en) * 1991-06-05 1992-11-03 Macdermid, Incorporated Process for manufacturing printed circuit employing selective provision of solderable coating
US5192716A (en) * 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US5259110A (en) * 1992-04-03 1993-11-09 International Business Machines Corporation Method for forming a multilayer microelectronic wiring module
US5275330A (en) * 1993-04-12 1994-01-04 International Business Machines Corp. Solder ball connect pad-on-via assembly process
US5308443A (en) * 1989-11-30 1994-05-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5365403A (en) * 1992-07-17 1994-11-15 Vlt Corporation Packaging electrical components
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5401688A (en) * 1991-02-18 1995-03-28 Kabushiki Kaisha Toshiba Semiconductor device of multichip module-type
US5407864A (en) * 1992-07-24 1995-04-18 Samsung Electronics Co., Ltd. Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5432675A (en) * 1993-11-15 1995-07-11 Fujitsu Limited Multi-chip module having thermal contacts
US5435480A (en) * 1993-12-23 1995-07-25 International Business Machines Corporation Method for filling plated through holes
US5454928A (en) * 1994-01-14 1995-10-03 Watkins Johnson Company Process for forming solid conductive vias in substrates
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5484647A (en) * 1993-09-21 1996-01-16 Matsushita Electric Industrial Co., Ltd. Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same
US5510655A (en) * 1990-11-26 1996-04-23 The Boeing Company Silicon wafers containing conductive feedthroughs
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5558271A (en) * 1993-04-30 1996-09-24 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5600884A (en) * 1991-02-25 1997-02-11 Canon Kabushiki Kaisha Method of manufacturing electrical connecting member
US5608264A (en) * 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5637925A (en) * 1988-02-05 1997-06-10 Raychem Ltd Uses of uniaxially electrically conductive articles
US5644103A (en) * 1994-11-10 1997-07-01 Vlt Corporation Packaging electrical components having a scallop formed in an edge of a circuit board
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5682062A (en) * 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5691041A (en) * 1995-09-29 1997-11-25 International Business Machines Corporation Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer
US5719354A (en) * 1994-09-16 1998-02-17 Hoechst Celanese Corp. Monolithic LCP polymer microelectronic wiring modules
US5722160A (en) * 1994-10-28 1998-03-03 Hitachi, Ltd. Packaging method of BGA type electronic component
US5737833A (en) * 1994-10-07 1998-04-14 Kabushiki Kaisha Toshiba Method of producing a high-density printed wiring board for mounting
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5808358A (en) * 1994-11-10 1998-09-15 Vlt Corporation Packaging electrical circuits
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5860818A (en) * 1991-02-22 1999-01-19 Canon Kabushiki Kaisha Electrical connecting member
US5863406A (en) * 1995-07-06 1999-01-26 International Business Machines Corp. Method of manufacturing a printed circuit board
US5877559A (en) * 1995-06-12 1999-03-02 Nitto Denko Corporation Film carrier for fine-pitched and high density mounting and semiconductor device using same
US5876859A (en) * 1994-11-10 1999-03-02 Vlt Corporation Direct metal bonding
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US5920123A (en) * 1997-01-24 1999-07-06 Micron Technology, Inc. Multichip module assembly having via contacts and method of making the same
US5923955A (en) * 1998-05-28 1999-07-13 Xerox Corporation Fine flip chip interconnection
US5924622A (en) * 1996-07-17 1999-07-20 International Business Machines Corp. Method and apparatus for soldering ball grid array modules to substrates
US5937277A (en) * 1994-01-31 1999-08-10 Fujitsu Limited Semiconductor device with reliable electrodes of projecting shape and method of forming same
US5960538A (en) * 1995-01-20 1999-10-05 Matsushita Electric Industrial Co., Ltd. Printed circuit board
US6015520A (en) * 1997-05-15 2000-01-18 International Business Machines Corporation Method for filling holes in printed wiring boards
US6015081A (en) * 1991-02-25 2000-01-18 Canon Kabushiki Kaisha Electrical connections using deforming compression
US6051093A (en) * 1996-06-07 2000-04-18 Matsushita Electric Industrial Co., Ltd. Mounting method of semiconductor element
US6066402A (en) * 1998-05-22 2000-05-23 Innova Electronics, Inc. High temperature electronics assembly using lead-antimony-tin alloys
US6080936A (en) * 1996-04-26 2000-06-27 Ngk Spark Plug Co., Ltd. Connecting board with oval-shaped protrusions
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US6138349A (en) * 1997-12-18 2000-10-31 Vlt Corporation Protective coating for an electronic device
US6172591B1 (en) * 1998-03-05 2001-01-09 Bourns, Inc. Multilayer conductive polymer device and method of manufacturing same
US6195883B1 (en) * 1998-03-25 2001-03-06 International Business Machines Corporation Full additive process with filled plated through holes
US6222272B1 (en) * 1996-08-06 2001-04-24 Nitto Denko Corporation Film carrier and semiconductor device using same
US6236302B1 (en) * 1998-03-05 2001-05-22 Bourns, Inc. Multilayer conductive polymer device and method of manufacturing same
US6242078B1 (en) * 1998-07-28 2001-06-05 Isola Laminate Systems Corp. High density printed circuit substrate and method of fabrication
US6245594B1 (en) * 1997-08-05 2001-06-12 Micron Technology, Inc. Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly
US6448644B1 (en) * 1998-05-02 2002-09-10 Charles W. C. Lin Flip chip assembly with via interconnection
US20020125581A1 (en) * 1998-12-17 2002-09-12 Charles W.C. Lin. Bumpless flip chip assembly with solder via
US6449840B1 (en) * 1998-09-29 2002-09-17 Delphi Technologies, Inc. Column grid array for flip-chip devices
US6720500B1 (en) * 1996-07-22 2004-04-13 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, structure of connection of wiring board with plug member, unit of connection of electronic part with wiring board, and process for mounting electronic part

Family Cites Families (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577037A (en) * 1968-07-05 1971-05-04 Ibm Diffused electrical connector apparatus and method of making same
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3885834T2 (en) 1987-09-24 1994-04-28 Toshiba Kawasaki Kk Soldering point and method of accomplishing it.
US4984358A (en) * 1989-03-10 1991-01-15 Microelectronics And Computer Technology Corporation Method of assembling stacks of integrated circuit dies
US5106461A (en) 1989-04-04 1992-04-21 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for tab
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
DE69020077T2 (en) 1989-09-09 1995-11-09 Mitsubishi Electric Corp Integrated circuit card.
US5611140A (en) 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5074947A (en) 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5556810A (en) 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
JP2540652B2 (en) 1990-06-01 1996-10-09 株式会社東芝 Semiconductor device
EP0469216B1 (en) 1990-07-31 1994-12-07 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5260234A (en) 1990-12-20 1993-11-09 Vlsi Technology, Inc. Method for bonding a lead to a die pad using an electroless plating solution
US5167992A (en) 1991-03-11 1992-12-01 Microelectronics And Computer Technology Corporation Selective electroless plating process for metal conductors
WO1992021150A1 (en) 1991-05-23 1992-11-26 Motorola, Inc. Integrated circuit chip carrier
US5116463A (en) 1991-06-19 1992-05-26 Microelectroncs And Computer Technology Corporation Detecting completion of electroless via fill
US5209817A (en) 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
JPH0563029A (en) 1991-09-02 1993-03-12 Fujitsu Ltd Semiconductor device
JP2555811B2 (en) 1991-09-10 1996-11-20 富士通株式会社 Flip chip bonding method for semiconductor chips
JPH05206064A (en) 1991-12-10 1993-08-13 Nec Corp Manufacture of semiconductor device
US5483421A (en) 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
JP2601128B2 (en) 1992-05-06 1997-04-16 松下電器産業株式会社 Method of manufacturing circuit forming substrate and circuit forming substrate
US5261593A (en) 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
US5334804A (en) 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
JP2795788B2 (en) 1993-02-18 1998-09-10 シャープ株式会社 Semiconductor chip mounting method
JPH08510358A (en) 1993-04-14 1996-10-29 アムコール・エレクトロニクス・インク Interconnection of integrated circuit chips and substrates
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
JP3115155B2 (en) 1993-05-28 2000-12-04 株式会社東芝 Semiconductor device and manufacturing method thereof
US5439162A (en) 1993-06-28 1995-08-08 Motorola, Inc. Direct chip attachment structure and method
US5438477A (en) 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5410806A (en) 1993-09-15 1995-05-02 Lsi Logic Corporation Method for fabricating conductive epoxy grid array semiconductors packages
US5508561A (en) 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5480834A (en) 1993-12-13 1996-01-02 Micron Communications, Inc. Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent
CA2135241C (en) 1993-12-17 1998-08-04 Mohi Sobhani Cavity and bump interconnection structure for electronic packages
JPH07273118A (en) 1994-03-28 1995-10-20 Toshiba Corp Formation of wiring and electrode
US5753529A (en) 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
US5427301A (en) 1994-05-06 1995-06-27 Ford Motor Company Ultrasonic flip chip process and apparatus
US5493096A (en) 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
US5508229A (en) 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
JPH0817860A (en) 1994-06-30 1996-01-19 Oki Electric Ind Co Ltd Manufacture of electronic part
US5619791A (en) 1994-06-30 1997-04-15 Lucent Technologies Inc. Method for fabricating highly conductive vias
US5595943A (en) 1994-06-30 1997-01-21 Hitachi, Ltd. Method for formation of conductor using electroless plating
US5706174A (en) 1994-07-07 1998-01-06 Tessera, Inc. Compliant microelectrionic mounting device
JPH0831973A (en) * 1994-07-12 1996-02-02 Oki Electric Ind Co Ltd Packaging method of flip-chip ic and semiconductor device
KR960005765A (en) 1994-07-14 1996-02-23 모리시다 요이치 Electroless plating bath and wiring forming method of semiconductor device used for wiring formation of semiconductor device
US5614114A (en) 1994-07-18 1997-03-25 Electro Scientific Industries, Inc. Laser system and method for plating vias
CA2154409C (en) * 1994-07-22 1999-12-14 Yuzo Shimada Connecting member and a connecting method using the same
JP3238011B2 (en) 1994-07-27 2001-12-10 株式会社東芝 Semiconductor device
US5492266A (en) * 1994-08-31 1996-02-20 International Business Machines Corporation Fine pitch solder deposits on printed circuit board process and product
AU3415095A (en) 1994-09-06 1996-03-27 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US5656858A (en) 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5477933A (en) 1994-10-24 1995-12-26 At&T Corp. Electronic device interconnection techniques
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
JPH08167630A (en) 1994-12-15 1996-06-25 Hitachi Ltd Chip connection structure
JP2001523390A (en) 1994-12-22 2001-11-20 ベネディクト・ジー・ペース Module with high mounting efficiency, to which inverted chips are bonded
US5861663A (en) * 1994-12-27 1999-01-19 International Business Machines Corporation Column grid array or ball grid array pad on via
US5583073A (en) 1995-01-05 1996-12-10 National Science Council Method for producing electroless barrier layer and solder bump on chip
US5599744A (en) 1995-02-06 1997-02-04 Grumman Aerospace Corporation Method of forming a microcircuit via interconnect
US5542601A (en) 1995-02-24 1996-08-06 International Business Machines Corporation Rework process for semiconductor chips mounted in a flip chip configuration on an organic substrate
JP3484554B2 (en) 1995-02-28 2004-01-06 日本テキサス・インスツルメンツ株式会社 Semiconductor device
US5547740A (en) 1995-03-23 1996-08-20 Delco Electronics Corporation Solderable contacts for flip chip integrated circuit devices
EP0734059B1 (en) * 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
JP3226752B2 (en) 1995-04-12 2001-11-05 株式会社東芝 Method for manufacturing semiconductor device
US5613296A (en) 1995-04-13 1997-03-25 Texas Instruments Incorporated Method for concurrent formation of contact and via holes
US5564181A (en) 1995-04-18 1996-10-15 Draper Laboratory, Inc. Method of fabricating a laminated substrate assembly chips-first multichip module
JPH08298269A (en) 1995-04-25 1996-11-12 Toshiba Microelectron Corp Semiconductor device and manufacture thereof
FR2734314B1 (en) * 1995-05-16 1997-07-04 Inst Francais Du Petrole ANCHORING DEVICE WITH RETRACTABLE ARMS AND ADJUSTABLE FLEXIBILITY FOR A WELL TOOL
US5650595A (en) 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
US5627405A (en) 1995-07-17 1997-05-06 National Semiconductor Corporation Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5803340A (en) * 1995-09-29 1998-09-08 Delco Electronics Corporation Composite solder paste for flip chip bumping
US5637920A (en) 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5722162A (en) 1995-10-12 1998-03-03 Fujitsu Limited Fabrication procedure for a stable post
US5674785A (en) 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5611884A (en) 1995-12-11 1997-03-18 Dow Corning Corporation Flip chip silicone pressure sensitive conductive adhesive
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5801072A (en) 1996-03-14 1998-09-01 Lsi Logic Corporation Method of packaging integrated circuits
US5723369A (en) 1996-03-14 1998-03-03 Lsi Logic Corporation Method of flip chip assembly
US5789271A (en) 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
JP3863213B2 (en) 1996-03-27 2006-12-27 株式会社ルネサステクノロジ Semiconductor device
US5660321A (en) * 1996-03-29 1997-08-26 Intel Corporation Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
US5576052A (en) 1996-04-22 1996-11-19 Motorola, Inc. Method of metallizing high aspect ratio apertures
US5808360A (en) 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
US5994222A (en) 1996-06-24 1999-11-30 Tessera, Inc Method of making chip mountings and assemblies
US5757071A (en) 1996-06-24 1998-05-26 Intel Corporation C4 substrate contact pad which has a layer of Ni-B plating
US5811879A (en) 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US5822856A (en) 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
US5883435A (en) 1996-07-25 1999-03-16 International Business Machines Corporation Personalization structure for semiconductor devices
US5774340A (en) 1996-08-28 1998-06-30 International Business Machines Corporation Planar redistribution structure and printed wiring device
US5731223A (en) 1996-09-24 1998-03-24 Lsi Logic Corporation Array of solder pads on an integrated circuit
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
KR20040000387A (en) * 1996-10-08 2004-01-03 히다치 가세고교 가부시끼가이샤 Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film
US5764486A (en) 1996-10-10 1998-06-09 Hewlett Packard Company Cost effective structure and method for interconnecting a flip chip with a substrate
JPH10135270A (en) 1996-10-31 1998-05-22 Casio Comput Co Ltd Semiconductor device and manufacture thereof
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US5888630A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly
WO1998020533A2 (en) 1996-11-08 1998-05-14 W.L. Gore & Associates, Inc. Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality
US6103992A (en) 1996-11-08 2000-08-15 W. L. Gore & Associates, Inc. Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias
KR100214545B1 (en) 1996-12-28 1999-08-02 구본준 Making method of chip size semicomductor package
JP3176307B2 (en) 1997-03-03 2001-06-18 日本電気株式会社 Mounting structure of integrated circuit device and method of manufacturing the same
US5817541A (en) 1997-03-20 1998-10-06 Raytheon Company Methods of fabricating an HDMI decal chip scale package
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6013877A (en) * 1998-03-12 2000-01-11 Lucent Technologies Inc. Solder bonding printed circuit boards
US6040630A (en) * 1998-04-13 2000-03-21 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
US6103552A (en) 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
KR100269540B1 (en) * 1998-08-28 2000-10-16 윤종용 Method for manufacturing chip scale packages at wafer level
US6084297A (en) 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6046909A (en) * 1998-11-16 2000-04-04 Intel Corporation Computer card with a printed circuit board with vias providing strength to the printed circuit board

Patent Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673680A (en) * 1970-12-14 1972-07-04 California Computer Products Method of circuit board with solder coated pattern
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
US4153988A (en) * 1977-07-15 1979-05-15 International Business Machines Corporation High performance integrated circuit semiconductor package and method of making
US4104111A (en) * 1977-08-03 1978-08-01 Mack Robert L Process for manufacturing printed circuit boards
US4394712A (en) * 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4499655A (en) * 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US4525246A (en) * 1982-06-24 1985-06-25 Hadco Corporation Making solderable printed circuit boards
US4664309A (en) * 1983-06-30 1987-05-12 Raychem Corporation Chip mounting device
US4705205A (en) * 1983-06-30 1987-11-10 Raychem Corporation Chip carrier mounting device
US4613891A (en) * 1984-02-17 1986-09-23 At&T Bell Laboratories Packaging microminiature devices
US4748130A (en) * 1984-03-26 1988-05-31 Unisearch Limited Method of making buried contact solar cell
US4650548A (en) * 1984-11-07 1987-03-17 Dr.-Ing. Max Schlotter Gmbh & Co. Kg Process for preserving the solderability of through hole plated printed circuit boards
US4804615A (en) * 1985-08-08 1989-02-14 Macdermid, Incorporated Method for manufacture of printed circuit boards
US4700473A (en) * 1986-01-03 1987-10-20 Motorola Inc. Method of making an ultra high density pad array chip carrier
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5637925A (en) * 1988-02-05 1997-06-10 Raychem Ltd Uses of uniaxially electrically conductive articles
US5058800A (en) * 1988-05-30 1991-10-22 Canon Kabushiki Kaisha Method of making electric circuit device
US4926549A (en) * 1988-05-31 1990-05-22 Canon Kabushiki Kaisha Method of producing electrical connection members
US4991290A (en) * 1988-07-21 1991-02-12 Microelectronics And Computer Technology Flexible electrical interconnect and method of making
US4925723A (en) * 1988-09-29 1990-05-15 Microwave Power, Inc. Microwave integrated circuit substrate including metal filled via holes and method of manufacture
US5192716A (en) * 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US5048747A (en) * 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5308443A (en) * 1989-11-30 1994-05-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5135606A (en) * 1989-12-08 1992-08-04 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5136359A (en) * 1989-12-19 1992-08-04 Nitto Denko Corporation Anisotropic conductive film with through-holes filled with metallic material
US5145552A (en) * 1989-12-21 1992-09-08 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
US5129142A (en) * 1990-10-30 1992-07-14 International Business Machines Corporation Encapsulated circuitized power core alignment and lamination
US5510655A (en) * 1990-11-26 1996-04-23 The Boeing Company Silicon wafers containing conductive feedthroughs
US5401688A (en) * 1991-02-18 1995-03-28 Kabushiki Kaisha Toshiba Semiconductor device of multichip module-type
US5860818A (en) * 1991-02-22 1999-01-19 Canon Kabushiki Kaisha Electrical connecting member
US6511607B1 (en) * 1991-02-22 2003-01-28 Canon Kabushiki Kaisha Method of making an electrical connecting member
US6015081A (en) * 1991-02-25 2000-01-18 Canon Kabushiki Kaisha Electrical connections using deforming compression
US5600884A (en) * 1991-02-25 1997-02-11 Canon Kabushiki Kaisha Method of manufacturing electrical connecting member
US5160579A (en) * 1991-06-05 1992-11-03 Macdermid, Incorporated Process for manufacturing printed circuit employing selective provision of solderable coating
US5259110A (en) * 1992-04-03 1993-11-09 International Business Machines Corporation Method for forming a multilayer microelectronic wiring module
US5526234A (en) * 1992-07-17 1996-06-11 Vlt Corporation Packaging electrical components
US5778526A (en) * 1992-07-17 1998-07-14 Vlt Corporation Packaging electrical components
US5365403A (en) * 1992-07-17 1994-11-15 Vlt Corporation Packaging electrical components
US5663869A (en) * 1992-07-17 1997-09-02 Vlt Corporation Packaging electrical components
US5407864A (en) * 1992-07-24 1995-04-18 Samsung Electronics Co., Ltd. Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip
US5275330A (en) * 1993-04-12 1994-01-04 International Business Machines Corp. Solder ball connect pad-on-via assembly process
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
US5558271A (en) * 1993-04-30 1996-09-24 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5484647A (en) * 1993-09-21 1996-01-16 Matsushita Electric Industrial Co., Ltd. Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same
US5432675A (en) * 1993-11-15 1995-07-11 Fujitsu Limited Multi-chip module having thermal contacts
US5435480A (en) * 1993-12-23 1995-07-25 International Business Machines Corporation Method for filling plated through holes
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5454928A (en) * 1994-01-14 1995-10-03 Watkins Johnson Company Process for forming solid conductive vias in substrates
US5937277A (en) * 1994-01-31 1999-08-10 Fujitsu Limited Semiconductor device with reliable electrodes of projecting shape and method of forming same
US5719354A (en) * 1994-09-16 1998-02-17 Hoechst Celanese Corp. Monolithic LCP polymer microelectronic wiring modules
US5737833A (en) * 1994-10-07 1998-04-14 Kabushiki Kaisha Toshiba Method of producing a high-density printed wiring board for mounting
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5722160A (en) * 1994-10-28 1998-03-03 Hitachi, Ltd. Packaging method of BGA type electronic component
US5644103A (en) * 1994-11-10 1997-07-01 Vlt Corporation Packaging electrical components having a scallop formed in an edge of a circuit board
US5876859A (en) * 1994-11-10 1999-03-02 Vlt Corporation Direct metal bonding
US6096981A (en) * 1994-11-10 2000-08-01 Vlt Corporation Packaging electrical circuits
US5808358A (en) * 1994-11-10 1998-09-15 Vlt Corporation Packaging electrical circuits
US6119923A (en) * 1994-11-10 2000-09-19 Vlt Corporation Packaging electrical circuits
US5938104A (en) * 1994-11-10 1999-08-17 Vlt Corporation Direct metal bonding
US5906310A (en) * 1994-11-10 1999-05-25 Vlt Corporation Packaging electrical circuits
US5960538A (en) * 1995-01-20 1999-10-05 Matsushita Electric Industrial Co., Ltd. Printed circuit board
US5608264A (en) * 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5682062A (en) * 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5877559A (en) * 1995-06-12 1999-03-02 Nitto Denko Corporation Film carrier for fine-pitched and high density mounting and semiconductor device using same
US5863406A (en) * 1995-07-06 1999-01-26 International Business Machines Corp. Method of manufacturing a printed circuit board
US5691041A (en) * 1995-09-29 1997-11-25 International Business Machines Corporation Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6080936A (en) * 1996-04-26 2000-06-27 Ngk Spark Plug Co., Ltd. Connecting board with oval-shaped protrusions
US6051093A (en) * 1996-06-07 2000-04-18 Matsushita Electric Industrial Co., Ltd. Mounting method of semiconductor element
US5924622A (en) * 1996-07-17 1999-07-20 International Business Machines Corp. Method and apparatus for soldering ball grid array modules to substrates
US6720500B1 (en) * 1996-07-22 2004-04-13 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, structure of connection of wiring board with plug member, unit of connection of electronic part with wiring board, and process for mounting electronic part
US6222272B1 (en) * 1996-08-06 2001-04-24 Nitto Denko Corporation Film carrier and semiconductor device using same
US6046410A (en) * 1996-12-23 2000-04-04 General Electric Company Interface structures for electronic devices
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US5920123A (en) * 1997-01-24 1999-07-06 Micron Technology, Inc. Multichip module assembly having via contacts and method of making the same
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US6015520A (en) * 1997-05-15 2000-01-18 International Business Machines Corporation Method for filling holes in printed wiring boards
US6245594B1 (en) * 1997-08-05 2001-06-12 Micron Technology, Inc. Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly
US6138349A (en) * 1997-12-18 2000-10-31 Vlt Corporation Protective coating for an electronic device
US6172591B1 (en) * 1998-03-05 2001-01-09 Bourns, Inc. Multilayer conductive polymer device and method of manufacturing same
US6236302B1 (en) * 1998-03-05 2001-05-22 Bourns, Inc. Multilayer conductive polymer device and method of manufacturing same
US6195883B1 (en) * 1998-03-25 2001-03-06 International Business Machines Corporation Full additive process with filled plated through holes
US6448644B1 (en) * 1998-05-02 2002-09-10 Charles W. C. Lin Flip chip assembly with via interconnection
US6066402A (en) * 1998-05-22 2000-05-23 Innova Electronics, Inc. High temperature electronics assembly using lead-antimony-tin alloys
US5923955A (en) * 1998-05-28 1999-07-13 Xerox Corporation Fine flip chip interconnection
US6242078B1 (en) * 1998-07-28 2001-06-05 Isola Laminate Systems Corp. High density printed circuit substrate and method of fabrication
US6449840B1 (en) * 1998-09-29 2002-09-17 Delphi Technologies, Inc. Column grid array for flip-chip devices
US6528891B2 (en) * 1998-12-17 2003-03-04 Charles Wen Chyang Lin Bumpless flip chip assembly with solder via
US20020125581A1 (en) * 1998-12-17 2002-09-12 Charles W.C. Lin. Bumpless flip chip assembly with solder via

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100267200A1 (en) * 2006-04-06 2010-10-21 Hamza Yilmaz Semiconductor die packages using thin dies and metal substrates
US8329508B2 (en) * 2006-04-06 2012-12-11 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US20100130000A1 (en) * 2008-11-21 2010-05-27 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device
US8193084B2 (en) * 2008-11-21 2012-06-05 Semiconductor Components Industries, Llc Method of manufacturing semiconductor device
US20160205765A1 (en) * 2013-10-01 2016-07-14 Fujikura Ltd. Wiring board assembly and method for producing same
US10237971B2 (en) * 2013-10-01 2019-03-19 Fujikura Ltd. Wiring board assembly and method for producing same

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US6319751B1 (en) 2001-11-20
SG82591A1 (en) 2001-08-21
US20020125581A1 (en) 2002-09-12
US6528891B2 (en) 2003-03-04
TW396462B (en) 2000-07-01

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