US20020063276A1 - Method of forming a floating gate memory cell structure - Google Patents
Method of forming a floating gate memory cell structure Download PDFInfo
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- US20020063276A1 US20020063276A1 US09/332,109 US33210999A US2002063276A1 US 20020063276 A1 US20020063276 A1 US 20020063276A1 US 33210999 A US33210999 A US 33210999A US 2002063276 A1 US2002063276 A1 US 2002063276A1
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- 238000009413 insulation Methods 0.000 claims abstract description 112
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Definitions
- the present invention relates to a method of forming a semiconductor memory cell structure having a floating gate.
- FIG. 1A is a fragmentary plane view illustrative of a conventional flash memory.
- FIG. 1B is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an A-A′ line of FIG. 1A.
- the flash memory has an alignment of memory cells 241 which has the following structure.
- a floating gate 203 is formed over a gate insulation film 202 over a semiconductor substrate 201 .
- the floating gate 203 is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shaped floating gate 203 .
- the structure of the memory cell 241 will be described in detail with reference to FIG. 1B.
- Field oxide films 206 are selectively formed on a semiconductor substrate 201 to define an active region or a device region of the semiconductor substrate 201 .
- Source and drain regions 204 and 205 are selectively formed in the active region or the device region of the semiconductor substrate 201 , whereby a channel region is defined between the source and drain regions 204 and 205 .
- a gate insulation film 202 is formed on the channel region of the semiconductor substrate 201 .
- Source side and drain side interconnections 204 a and 205 a are formed on the source and drain regions 204 and 205 , wherein the source side and drain side interconnections 204 a and 205 a are made of polysilicon films doped with an impurity.
- the source and drain 204 and 205 serve as parts of bit lines.
- the formation of the source side and drain side interconnections 204 a and 205 a on and in contact with the source and drain regions 204 and 205 results in reduction in resistance of the source and drain 204 and 205 .
- a floating gate 203 is formed which comprises an lower part and an upper part. The upper part extends laterally from the opposite edges of the lower part so that the floating gate 203 is T-shaped. The lower part of the floating gate 203 is positioned on the gate insulation film 202 . Side wall oxide films 213 are formed on opposite side walls of the lower part of the floating gate 203 .
- Insulation films 216 are formed over the field oxide films 206 and the source side and drain side interconnections 204 a and 205 a as well as over the side wall oxide films 213 .
- the upper portion of the floating gate 203 extends over the lower part thereof and the insulation films 216 , so that opposite edges of the upper portion of the floating gate 203 are almost aligned to the edges of the source side and drain side interconnections 204 a and 205 a in plane view.
- An insulation film 207 made of ONO is formed on the upper portion of the floating gate 203 and on the insulation films 216 .
- a control gate 208 is formed on the insulation film 207 so that the floating gate 203 is separated and electrically floated from the control gate 208 and whereby the floating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell.
- the control gate 208 serves as a part of a word line in the memory.
- the above T-shape of the floating gate increases a capacitance thereof.
- the source and drain 204 and 205 are commonly used for a plurality of the memory cells 241 .
- the drain 05 is used as a part of the bit line so that a single bit contact is formed for the plural memory cells 241 so as to allow narrowing the distance between the memory cells, thereby reducing the cell size.
- FIGS. 2A through 2H are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 1A and 1B.
- a thin insulation film 202 a is formed on a surface of a semiconductor substrate 201 .
- a bottom floating gate part 203 a is selectively formed on a predetermined region of the thin insulation film 202 a , wherein a film of a electrode material such as an impurity doped polysilicon is entirely formed on the surface of the semiconductor substrate 201 before patterning the same to form the bottom floating gate part 203 a .
- the bottom floating gate part 203 a is used as a mask for carrying out an ion-implantation into selected upper regions of the semiconductor substrate 201 , whereby source and drain regions 204 and 205 are formed with a self-alignment technique in the selected upper regions of the semiconductor substrate 201 .
- the thin insulation film 202 a is removed except for its underlying part which underlies the bottom floating gate part 203 a , whereby the remaining underlying part of the thin insulation film 202 a serves as a gate insulation film 202 .
- An insulation film is entirely formed on the source and drain regions 204 and 205 as well as on opposite side walls and a top surface of the bottom floating gate part 203 a before an etch back process using a dry etching technique so that the insulation film remain only on the opposite side walls of the bottom floating gate part 203 a , whereby the side wall insulation films 213 are formed on the opposite side walls of the bottom floating gate part 203 a.
- an impurity doped polysilicon film is entirely deposited over the source and drain regions 204 and 205 and the side wall insulation films 213 and the bottom floating gate part 203 a .
- An etch back process is carried out to the impurity doped polysilicon film until the top of the bottom floating gate part 203 a is shown, whereby conductive films 214 are formed on the source and drain regions 204 and 205 and positioned outside the side wall insulation films 213 .
- an insulation film 216 is entirely formed over the field oxide films 206 , the source side and drain side interconnections 204 a and 205 a and the bottom floating gate part 203 a.
- an overlying part of the insulation film 216 overlying the bottom floating gate part 203 a is selectively removed by patterning the insulation film 216 with use of a photo-lithography and a subsequent dry etching technique, whereby the top of the bottom floating gate part 203 a is shown.
- an impurity doped polysilicon film is entirely formed which extends over the insulation films 216 and the bottom floating gate part 203 a .
- the impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a top floating gate part 203 b is formed which extends over the top of the bottom floating gate part 203 a and inside parts of the insulation films 216 so that opposite edges of the top floating gate part 203 b are aligned to outside edges of the source side and drain side interconnections 204 a and 205 a .
- a combination of the top floating gate part 203 b and the bottom floating gate part 203 a forms a T-shaped floating gate 203 .
- an insulation film 207 made of ONO is formed on the top floating gate part 203 b of the floating gate 203 and on the insulation films 216 .
- a control gate 208 is then formed on the insulation film 207 so that the floating gate 203 is separated and electrically floated from the control gate 208 and whereby the floating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell.
- the floating gate comprises two parts, for example, the top floating gate part 203 b and the bottom floating gate part 203 a which are formed in the different steps, whereby the number of the fabrication processes are increased.
- the present invention provides a floating gate memory cell structure comprising: a single pair of a first single insulation film unitary formed and a single floating gate electrode film unitary formed and laminated on the first single insulation film, the first single insulation film extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate; a second insulation film extending on side walls and a top surface of the single floating gate electrode film and a control electrode extending on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- the present invention also provides a method o forming a floating gate memory cell structure.
- the method comprising the following steps.
- a dummy pattern is selectively formed on a predetermined region of a semiconductor substrate.
- Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask.
- Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction.
- the dummy pattern is removed so that a channel region defined between the source and drain regions is shown.
- a first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films.
- a single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.
- a second insulation film is formed, which extends on side walls and a top surface of the single floating gate electrode film.
- a control electrode is formed, which extends on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- FIG. 1A is a fragmentary plane view illustrative of a conventional flash memory.
- FIG. 1B is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an A-A′ line of FIG. 1A.
- FIGS. 2A through 2H are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 1A and 1B.
- FIG. 3A is a fragmentary plane view illustrative of a the flash memory in a first embodiment in accordance with the present invention.
- FIG. 3B is a fragmentary cross sectional elevation view illustrative of the flash memory taken along an A-A′ line of FIG. 3A in a first embodiment in accordance with the present invention.
- FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of a novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- FIGS. 5A through 5H are fragmentary cross sectional elevation views illustrative of another novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B in a fourth embodiment in accordance with the present invention.
- the first present invention provides a floating gate electrode structure comprising: a single floating gate electrode film unitary formed and laminated on a first single insulation film being unitary formed and extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate.
- the first single insulation film has a thin portion and thick portions united with the thin portion, and the thin portion is positioned on the channel region and the thick portions are positioned on the inside walls and the top surfaces of the conductive films.
- the single floating gate electrode film has an almost uniform thickness.
- the second present invention provides a floating gate memory cell structure comprising: a single pair of a first single insulation film unitary formed and a single floating gate electrode film unitary formed and laminated on the first single insulation film, the first single insulation film extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate; a second insulation film extending on side walls and a top surface of the single floating gate electrode film and a control electrode extending on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- the first single insulation film has a thin portion and thick portions united with the thin portion, and the thin portion is positioned on the channel region and the thick portions are positioned on the inside walls and the top surfaces of the conductive films.
- the single floating gate electrode film has an almost uniform thickness.
- the third present invention provides a method o forming a floating gate memory cell structure.
- the method comprising the following steps.
- a dummy pattern is selectively formed on a predetermined region of a semiconductor substrate.
- Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask.
- Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction.
- the dummy pattern is removed so that a channel region defined between the source and drain regions is shown.
- a first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films.
- a single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.
- the first single insulation film is made by a single dry oxidation process to both the channel region and the conductive films.
- the fourth present invention provides a method o forming a floating gate memory cell structure.
- the method comprising the following steps.
- a dummy pattern is selectively formed on a predetermined region of a semiconductor substrate.
- Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask.
- Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction.
- the dummy pattern is removed so that a channel region defined between the source and drain regions is shown.
- a first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films.
- a single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.
- a second insulation film is formed, which extends on side walls and a top surface of the single floating gate electrode film.
- a control electrode is formed, which extends on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- the first single insulation film is made by a single dry oxidation process to both the channel region and the conductive films.
- FIG. 3A is a fragmentary plane view illustrative of a the flash memory in a first embodiment in accordance with the present invention.
- FIG. 3B is a fragmentary cross sectional elevation view illustrative of the flash memory taken along an A-A′ line of FIG. 3A in a first embodiment in accordance with the present invention.
- the flash memory has an alignment of memory cells 141 which has the following structure.
- a floating gate 103 is formed over a gate insulation film 102 over a semiconductor substrate 101 .
- the floating gate 103 is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shaped floating gate 103 .
- the structure of the memory cell 141 will be described in detail with reference to FIG. 3B.
- Field oxide films 106 are selectively formed on a semiconductor substrate 101 to define an active region or a device region of the semiconductor substrate 101 .
- Source and drain regions 104 and 105 are selectively formed in the active region or the device region of the semiconductor substrate 101 , whereby a channel region is defined between the source and drain regions 104 and 105 .
- a gate insulation film 102 is formed on the channel region of the semiconductor substrate 101 .
- Source side and drain side interconnections 104 a and 105 a are formed on the source and drain regions 104 and 105 , wherein the source side and drain side interconnections 104 a and 105 a are made of polysilicon films doped with an impurity.
- the source and drain 104 and 105 serve as parts of bit lines.
- the formation of the source side and drain side interconnections 104 a and 105 a on and in contact with the source and drain regions 104 and 105 results in reduction in resistance of the source and drain 104 and 105 .
- a floating gate 103 is formed which laterally extending upper portions which extends over source and drain regions 104 and 105 .
- the lower part of the floating gate 103 is positioned on the gate insulation film 102 .
- Insulation films 122 are united with the gate insulation film 102 , wherein the insulation films 122 extend on inside walls and top surfaces of the source side and drain side interconnections 104 a and 105 a .
- the laterally extending upper parts of the floating gate 103 extend over the insulation films 122 , so that opposite edges of the laterally extending upper parts of the floating gate 103 are almost aligned to the edges of the source side and drain side interconnections 104 a and 105 a in plane view.
- An insulation film 107 made of ONO is formed on the floating gate 103 .
- a control gate 108 is formed on the insulation film 107 so that the floating gate 103 is separated and electrically floated from the control gate 108 and whereby the floating gate 103 is completely surrounded by the insulation materials to be floated in the memory cell.
- the control gate 108 serves as a part of a word line in the memory.
- the source and drain 104 and 105 are commonly used for a plurality of the memory cells 141 .
- the drain 105 is used as a part of the bit line so that a single bit contact is formed for the plural memory cells 141 so as to allow narrowing the distance between the memory cells, thereby reducing the cell size.
- FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of a novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- a thin insulation film 121 is formed on a surface of a semiconductor substrate 101 .
- a dummy pattern 103 a is selectively formed on a predetermined region of the thin insulation film 121 , wherein the thin insulation film 121 may be made of silicon oxide and the dummy pattern 103 a may be made of silicon nitride.
- the dummy pattern 103 a may be formed by forming a silicon nitride film and subsequent patterning the same with use of a photo-lithography and a subsequent dry etching process.
- the insulation film 121 made of silicon oxide absorbs a stress generated by forming the dummy pattern 103 a made of silicon nitride.
- the dummy pattern 103 a is used as a mask for carrying out an ion-implantation into selected upper regions of the semiconductor substrate 101 , whereby source and drain regions 104 and 105 are formed with a self-alignment technique in the selected upper regions of the semiconductor substrate 101 .
- the thin insulation film 121 is removed except for its underlying part which underlies the dummy pattern 103 a , whereby the remaining underlying part of the thin insulation film 121 serves as a gate insulation film 121 .
- an impurity doped polysilicon film is entirely deposited over the source and drain regions 104 and 105 and the dummy pattern 103 a .
- An etch back process is carried out to the impurity doped polysilicon film until the top of the dummy pattern 103 a is shown, whereby conductive films 114 are formed on the source and drain regions 104 and 105 and positioned opposite side walls of the dummy pattern 103 a.
- parts of the conductive films 114 on isolation regions are selectively removed. Grooves are further formed on the isolation region in the semiconductor substrate 101 . An insulation material such as silicon oxide is buried within the grooves, whereby field oxide films 106 are then formed on the isolation regions. As a result, outside edges of the conductive films 114 as well as outside edges of the source and drain regions 104 and 105 are defined by inside boundaries of the field oxide films 106 , whereby source side and drain side interconnections 104 a and 105 a are formed.
- the dummy pattern 103 a and the thin insulation film 121 are removed by selective wet etching processes.
- the dummy pattern 103 a made of silicon nitride may be removed by a selective wet etching which uses a phosphoric acid solution as an etchant.
- the thin insulation film 121 made of silicon oxide may be removed by a subsequent selective wet etching which uses a hydrofluoric acid solution as an etchant.
- a top surface of the channel region of the semiconductor substrate 101 defined between the source and drain regions 104 and 105 is shown.
- a dry oxidation process is carried out at a temperature of about 850° C. in a dry oxygen atmosphere, thereby concurrently forming a gate oxide film 102 on the top surface of the channel region of the semiconductor substrate 101 and also forming interlayer insulators 122 on side walls and top surfaces of the source side and drain side interconnections 104 a and 105 a . Since the channel region is made is a single crystal silicon whilst the source side and drain side interconnections 104 a and 105 a are made of polysilicon, the same dry oxidation process results in formation of the thicker inter-layer insulators 122 by three or four times than the gate insulation film 102 .
- an impurity doped polysilicon film is entirely formed which extends over the inter-layer insulators 122 and the gate insulation film 102 as well as over the field oxide films 106 .
- the impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a floating gate electrode 103 is formed in a single pair of the film deposition and subsequent patterning processes, wherein opposite side edges of the floating gate electrode 103 are aligned to he opposite side edges of the inter-layer insulators 122 .
- This single pair of the deposition and subsequent patterning processes for the floating gate electrode 103 reduces the number of the fabrication processes.
- an insulation film 107 made of ONO is formed on the floating gate 103 and on the insulation films 106 .
- a control gate 108 is then formed on the insulation film 107 so that the floating gate 103 is separated and electrically floated from the control gate 108 and whereby the floating gate 103 is completely surrounded by the insulation materials to be floated in the memory cell.
- the floating gate comprises a single part which has laterally extending upper parts overlying the interconnections 104 a and 105 a over the source and drain regions 104 and 105 .
- the floating gate is formed by the single pair of the film deposition and subsequent patterning processes, whereby the number of the fabrication processes is reduced.
- FIGS. 5A through 5H are fragmentary cross sectional elevation views illustrative of another novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- a dummy pattern 103 a is selectively formed on a predetermined region of a semiconductor substrate 101 , wherein the dummy pattern 103 a may be made of silicon oxide.
- the dummy pattern 103 a may be formed by forming a silicon oxide film and subsequent patterning the same with use of a photo-lithography and a subsequent dry etching process.
- the dummy pattern 103 a is used as a mask for carrying out an ion-implantation into selected upper regions of the semiconductor substrate 101 , whereby source and drain regions 104 and 105 are formed with a self-alignment technique in the selected upper regions of the semiconductor substrate 101 .
- an impurity doped polysilicon film is entirely deposited over the source and drain regions 104 and 105 and the dummy pattern 103 a .
- An etch back process is carried out to the impurity doped polysilicon film until the top of the dummy pattern 103 a is shown, whereby conductive films 114 are formed on the source and drain regions 104 and 105 and positioned opposite side walls of the dummy pattern 103 a.
- parts of the conductive films 114 on isolation regions are selectively removed. Grooves are further formed on the isolation region in the semiconductor substrate 101 . An insulation material such as silicon oxide is buried within the grooves, whereby field oxide films 106 are then formed on the isolation regions. As a result, outside edges of the conductive films 114 as well as outside edges of the source and drain regions 104 and 105 are defined by inside boundaries of the field oxide films 106 , whereby source side and drain side interconnections 104 a and 105 a are formed.
- the dummy pattern 103 a is removed by a selective wet etching process.
- the dummy pattern 103 a made of silicon oxide may be removed by a selective wet etching which uses a hydrofluoric acid solution as an etchant.
- a top surface of the channel region of the semiconductor substrate 101 defined between the source and drain regions 104 and 105 is shown.
- a dry oxidation process is carried out at a temperature of about 850° C. in a dry oxygen atmosphere, thereby concurrently forming a gate oxide film 102 on the top surface of the channel region of the semiconductor substrate 101 and also forming interlayer insulators 122 on side walls and top surfaces of the source side and drain side interconnections 104 a and 105 a . Since the channel region is made is a single crystal silicon whilst the source side and drain side interconnections 104 a and 105 a are made of polysilicon, the same dry oxidation process results in formation of the thicker inter-layer insulators 122 by three or four times than the gate insulation film 102 .
- an impurity doped polysilicon film is entirely formed which extends over the inter-layer insulators 122 and the gate insulation film 102 as well as over the field oxide films 106 .
- the impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a floating gate electrode 103 is formed in a single pair of the film deposition and subsequent patterning processes, wherein opposite side edges of the floating gate electrode 103 are aligned to he opposite side edges of the inter-layer insulators 122 .
- This single pair of the deposition and subsequent patterning processes for the floating gate electrode 103 reduces the number of the fabrication processes.
- an insulation film 107 made of ONO is formed on the floating gate 103 and on the insulation films 106 .
- a control gate 108 is then formed on the insulation film 107 so that the floating gate 103 is separated and electrically floated from the control gate 108 and whereby the floating gate 103 is completely surrounded by the insulation materials to be floated in the memory cell.
- the floating gate comprises a single part which has laterally extending upper parts overlying the interconnections 104 a and 105 a over the source and drain regions 104 and 105 .
- the floating gate is formed by the single pair of the film deposition and subsequent patterning processes, whereby the number of the fabrication processes is reduced.
- the dummy pattern may be made of other materials than silicon nitride and silicon oxide, provided that the dummy pattern material should be selected to have such an etching selectivity that an etching rate of the dummy pattern is higher than that of the interconnections 104 a and 105 a over the source and drain regions 104 and 105 .
- Etch back process for forming the conductive films 114 may be carried out by a chemical mechanical polishing method.
- the dummy pattern 103 a may preferably be made of silicon nitride so that the dummy pattern 103 a may serve as an etching stopper to the chemical mechanical polishing.
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Abstract
Description
- The present invention relates to a method of forming a semiconductor memory cell structure having a floating gate.
- A conventional structure of a flash memory will be described. FIG. 1A is a fragmentary plane view illustrative of a conventional flash memory. FIG. 1B is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an A-A′ line of FIG. 1A. The flash memory has an alignment of
memory cells 241 which has the following structure. Afloating gate 203 is formed over agate insulation film 202 over asemiconductor substrate 201. Thefloating gate 203 is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shapedfloating gate 203. The structure of thememory cell 241 will be described in detail with reference to FIG. 1B. -
Field oxide films 206 are selectively formed on asemiconductor substrate 201 to define an active region or a device region of thesemiconductor substrate 201. Source anddrain regions semiconductor substrate 201, whereby a channel region is defined between the source anddrain regions gate insulation film 202 is formed on the channel region of thesemiconductor substrate 201. Source side anddrain side interconnections drain regions drain side interconnections memory cell 241, the source anddrain drain side interconnections drain regions drain floating gate 203 is formed which comprises an lower part and an upper part. The upper part extends laterally from the opposite edges of the lower part so that thefloating gate 203 is T-shaped. The lower part of thefloating gate 203 is positioned on thegate insulation film 202. Sidewall oxide films 213 are formed on opposite side walls of the lower part of thefloating gate 203.Insulation films 216 are formed over thefield oxide films 206 and the source side anddrain side interconnections wall oxide films 213. The upper portion of thefloating gate 203 extends over the lower part thereof and theinsulation films 216, so that opposite edges of the upper portion of thefloating gate 203 are almost aligned to the edges of the source side anddrain side interconnections insulation film 207 made of ONO is formed on the upper portion of thefloating gate 203 and on theinsulation films 216. Acontrol gate 208 is formed on theinsulation film 207 so that thefloating gate 203 is separated and electrically floated from thecontrol gate 208 and whereby thefloating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell. Thecontrol gate 208 serves as a part of a word line in the memory. The above T-shape of the floating gate increases a capacitance thereof. - The source and
drain memory cells 241. The drain 05 is used as a part of the bit line so that a single bit contact is formed for theplural memory cells 241 so as to allow narrowing the distance between the memory cells, thereby reducing the cell size. - The following descriptions will focus onto the fabrication method of the above flash memory. FIGS. 2A through 2H are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 1A and 1B.
- With reference to FIG. 2A, a
thin insulation film 202 a is formed on a surface of asemiconductor substrate 201. A bottom floatinggate part 203 a is selectively formed on a predetermined region of thethin insulation film 202 a, wherein a film of a electrode material such as an impurity doped polysilicon is entirely formed on the surface of thesemiconductor substrate 201 before patterning the same to form the bottom floatinggate part 203 a. The bottom floatinggate part 203 a is used as a mask for carrying out an ion-implantation into selected upper regions of thesemiconductor substrate 201, whereby source anddrain regions semiconductor substrate 201. - With reference to FIG. 2B, the
thin insulation film 202 a is removed except for its underlying part which underlies the bottom floatinggate part 203 a, whereby the remaining underlying part of thethin insulation film 202 a serves as agate insulation film 202. An insulation film is entirely formed on the source anddrain regions gate part 203 a before an etch back process using a dry etching technique so that the insulation film remain only on the opposite side walls of the bottom floatinggate part 203 a, whereby the sidewall insulation films 213 are formed on the opposite side walls of the bottom floatinggate part 203 a. - With reference to FIG. 2C, an impurity doped polysilicon film is entirely deposited over the source and
drain regions wall insulation films 213 and the bottom floatinggate part 203 a. An etch back process is carried out to the impurity doped polysilicon film until the top of the bottom floatinggate part 203 a is shown, wherebyconductive films 214 are formed on the source anddrain regions wall insulation films 213. - With reference to FIG. 2D, parts of the
conductive films 214 on isolation regions are selectively removed. Grooves are further formed on the isolation region in thesemiconductor substrate 201. An insulation material such as silicon oxide is buried within the grooves, wherebyfield oxide films 206 are then formed on the isolation regions. As a result, outside edges of theconductive films 214 are defined by inside boundaries of thefield oxide films 206, whereby source side anddrain side interconnections - With reference to FIG. 2E, an
insulation film 216 is entirely formed over thefield oxide films 206, the source side anddrain side interconnections gate part 203 a. - With reference to FIG. 2F, an overlying part of the
insulation film 216 overlying the bottom floatinggate part 203 a is selectively removed by patterning theinsulation film 216 with use of a photo-lithography and a subsequent dry etching technique, whereby the top of the bottom floatinggate part 203 a is shown. - With reference to FIG. 2G, an impurity doped polysilicon film is entirely formed which extends over the
insulation films 216 and the bottom floatinggate part 203 a. The impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a top floatinggate part 203 b is formed which extends over the top of the bottom floatinggate part 203 a and inside parts of theinsulation films 216 so that opposite edges of the top floatinggate part 203 b are aligned to outside edges of the source side anddrain side interconnections gate part 203 b and the bottom floatinggate part 203 a forms a T-shapedfloating gate 203. - With reference to FIG. 2H, an
insulation film 207 made of ONO is formed on the top floatinggate part 203 b of thefloating gate 203 and on theinsulation films 216. Acontrol gate 208 is then formed on theinsulation film 207 so that thefloating gate 203 is separated and electrically floated from thecontrol gate 208 and whereby thefloating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell. - In accordance with the above conventional fabrication processes, the floating gate comprises two parts, for example, the top floating
gate part 203 b and the bottom floatinggate part 203 a which are formed in the different steps, whereby the number of the fabrication processes are increased. - In the above circumstances, it had been required to develop a novel method of fabricating a T-shaped floating gate electrode of a memory cell in a flash memory with reduced number of the fabrication process for the T-shaped floating gate electrode.
- Accordingly, it is an object of the present invention to provide a novel method of fabricating a floating gate electrode of a memory cell in a flash memory with reduced number of the fabrication process for the T-shaped floating gate electrode.
- It is another object of the present invention to provide a novel floating gate electrode of a memory cell in a flash memory.
- The present invention provides a floating gate memory cell structure comprising: a single pair of a first single insulation film unitary formed and a single floating gate electrode film unitary formed and laminated on the first single insulation film, the first single insulation film extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate; a second insulation film extending on side walls and a top surface of the single floating gate electrode film and a control electrode extending on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- The present invention also provides a method o forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed. A second insulation film is formed, which extends on side walls and a top surface of the single floating gate electrode film. A control electrode is formed, which extends on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
- Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
- FIG. 1A is a fragmentary plane view illustrative of a conventional flash memory.
- FIG. 1B is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an A-A′ line of FIG. 1A.
- FIGS. 2A through 2H are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 1A and 1B.
- FIG. 3A is a fragmentary plane view illustrative of a the flash memory in a first embodiment in accordance with the present invention.
- FIG. 3B is a fragmentary cross sectional elevation view illustrative of the flash memory taken along an A-A′ line of FIG. 3A in a first embodiment in accordance with the present invention.
- FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of a novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- FIGS. 5A through 5H are fragmentary cross sectional elevation views illustrative of another novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B in a fourth embodiment in accordance with the present invention.
- The first present invention provides a floating gate electrode structure comprising: a single floating gate electrode film unitary formed and laminated on a first single insulation film being unitary formed and extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate.
- It is preferable that the first single insulation film has a thin portion and thick portions united with the thin portion, and the thin portion is positioned on the channel region and the thick portions are positioned on the inside walls and the top surfaces of the conductive films.
- It is also preferable that the single floating gate electrode film has an almost uniform thickness.
- The second present invention provides a floating gate memory cell structure comprising: a single pair of a first single insulation film unitary formed and a single floating gate electrode film unitary formed and laminated on the first single insulation film, the first single insulation film extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate; a second insulation film extending on side walls and a top surface of the single floating gate electrode film and a control electrode extending on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- It is preferable that the first single insulation film has a thin portion and thick portions united with the thin portion, and the thin portion is positioned on the channel region and the thick portions are positioned on the inside walls and the top surfaces of the conductive films.
- It is also preferable that the single floating gate electrode film has an almost uniform thickness.
- The third present invention provides a method o forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed.
- It is preferable that the first single insulation film is made by a single dry oxidation process to both the channel region and the conductive films.
- It is preferable to further comprise a silicon oxide thin film on the semiconductor substrate before the dummy pattern is selectively formed on the silicon oxide thin film, provided that the dummy pattern is made of silicon nitride.
- The fourth present invention provides a method o forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed. A second insulation film is formed, which extends on side walls and a top surface of the single floating gate electrode film. A control electrode is formed, which extends on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
- It is preferable that the first single insulation film is made by a single dry oxidation process to both the channel region and the conductive films.
- It is preferable to further comprise a silicon oxide thin film on the semiconductor substrate before the dummy pattern is selectively formed on the silicon oxide thin film, provided that the dummy pattern is made of silicon nitride.
- A first embodiment according to the present invention will be described in detail with reference to the drawings. The structure of the memory cell of the flash memory and the fabrication method thereof in the first embodiment in accordance with the present invention are different from the conventional ones shown in FIGS. 1A and 1B as well as FIGS. 2A through2H. FIG. 3A is a fragmentary plane view illustrative of a the flash memory in a first embodiment in accordance with the present invention. FIG. 3B is a fragmentary cross sectional elevation view illustrative of the flash memory taken along an A-A′ line of FIG. 3A in a first embodiment in accordance with the present invention. The flash memory has an alignment of
memory cells 141 which has the following structure. A floatinggate 103 is formed over agate insulation film 102 over asemiconductor substrate 101. The floatinggate 103 is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shaped floatinggate 103. The structure of thememory cell 141 will be described in detail with reference to FIG. 3B. -
Field oxide films 106 are selectively formed on asemiconductor substrate 101 to define an active region or a device region of thesemiconductor substrate 101. Source anddrain regions semiconductor substrate 101, whereby a channel region is defined between the source and drainregions gate insulation film 102 is formed on the channel region of thesemiconductor substrate 101. Source side and drainside interconnections regions side interconnections memory cell 141, the source and drain 104 and 105 serve as parts of bit lines. The formation of the source side and drainside interconnections regions gate 103 is formed which laterally extending upper portions which extends over source and drainregions gate 103 is positioned on thegate insulation film 102.Insulation films 122 are united with thegate insulation film 102, wherein theinsulation films 122 extend on inside walls and top surfaces of the source side and drainside interconnections gate 103 extend over theinsulation films 122, so that opposite edges of the laterally extending upper parts of the floatinggate 103 are almost aligned to the edges of the source side and drainside interconnections insulation film 107 made of ONO is formed on the floatinggate 103. Acontrol gate 108 is formed on theinsulation film 107 so that the floatinggate 103 is separated and electrically floated from thecontrol gate 108 and whereby the floatinggate 103 is completely surrounded by the insulation materials to be floated in the memory cell. Thecontrol gate 108 serves as a part of a word line in the memory. - The source and drain104 and 105 are commonly used for a plurality of the
memory cells 141. Thedrain 105 is used as a part of the bit line so that a single bit contact is formed for theplural memory cells 141 so as to allow narrowing the distance between the memory cells, thereby reducing the cell size. - The following descriptions will focus onto the novel fabrication method of the above flash memory. FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of a novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- With reference to FIG. 4A, a
thin insulation film 121 is formed on a surface of asemiconductor substrate 101. Adummy pattern 103 a is selectively formed on a predetermined region of thethin insulation film 121, wherein thethin insulation film 121 may be made of silicon oxide and thedummy pattern 103 a may be made of silicon nitride. Thedummy pattern 103 a may be formed by forming a silicon nitride film and subsequent patterning the same with use of a photo-lithography and a subsequent dry etching process. Theinsulation film 121 made of silicon oxide absorbs a stress generated by forming thedummy pattern 103 a made of silicon nitride. Thedummy pattern 103 a is used as a mask for carrying out an ion-implantation into selected upper regions of thesemiconductor substrate 101, whereby source and drainregions semiconductor substrate 101. - With reference to FIG. 4B, the
thin insulation film 121 is removed except for its underlying part which underlies thedummy pattern 103 a, whereby the remaining underlying part of thethin insulation film 121 serves as agate insulation film 121. - With reference to FIG. 4C, an impurity doped polysilicon film is entirely deposited over the source and drain
regions dummy pattern 103 a. An etch back process is carried out to the impurity doped polysilicon film until the top of thedummy pattern 103 a is shown, wherebyconductive films 114 are formed on the source and drainregions dummy pattern 103 a. - With reference to FIG. 4D, parts of the
conductive films 114 on isolation regions are selectively removed. Grooves are further formed on the isolation region in thesemiconductor substrate 101. An insulation material such as silicon oxide is buried within the grooves, wherebyfield oxide films 106 are then formed on the isolation regions. As a result, outside edges of theconductive films 114 as well as outside edges of the source and drainregions field oxide films 106, whereby source side and drainside interconnections - With reference to FIG. 4E, the
dummy pattern 103 a and thethin insulation film 121 are removed by selective wet etching processes. Thedummy pattern 103 a made of silicon nitride may be removed by a selective wet etching which uses a phosphoric acid solution as an etchant. Thethin insulation film 121 made of silicon oxide may be removed by a subsequent selective wet etching which uses a hydrofluoric acid solution as an etchant. As a result, a top surface of the channel region of thesemiconductor substrate 101 defined between the source and drainregions - With reference to FIG. 4F, a dry oxidation process is carried out at a temperature of about 850° C. in a dry oxygen atmosphere, thereby concurrently forming a
gate oxide film 102 on the top surface of the channel region of thesemiconductor substrate 101 and also forminginterlayer insulators 122 on side walls and top surfaces of the source side and drainside interconnections side interconnections thicker inter-layer insulators 122 by three or four times than thegate insulation film 102. - With reference to FIG. 4G, an impurity doped polysilicon film is entirely formed which extends over the
inter-layer insulators 122 and thegate insulation film 102 as well as over thefield oxide films 106. The impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a floatinggate electrode 103 is formed in a single pair of the film deposition and subsequent patterning processes, wherein opposite side edges of the floatinggate electrode 103 are aligned to he opposite side edges of theinter-layer insulators 122. This single pair of the deposition and subsequent patterning processes for the floatinggate electrode 103 reduces the number of the fabrication processes. - With reference to FIG. 4H, an
insulation film 107 made of ONO is formed on the floatinggate 103 and on theinsulation films 106. Acontrol gate 108 is then formed on theinsulation film 107 so that the floatinggate 103 is separated and electrically floated from thecontrol gate 108 and whereby the floatinggate 103 is completely surrounded by the insulation materials to be floated in the memory cell. - In accordance with the above novel fabrication processes, the floating gate comprises a single part which has laterally extending upper parts overlying the
interconnections regions - A second embodiment according to the present invention will be described in detail with reference to the drawings. A difference of the second embodiment from the first embodiment is only in the fabrication processes, for which reason the descriptions to the structure of the memory cell of this embodiment will be omitted. FIGS. 5A through 5H are fragmentary cross sectional elevation views illustrative of another novel method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 3A and 3B.
- With reference to FIG. 5A, A
dummy pattern 103 a is selectively formed on a predetermined region of asemiconductor substrate 101, wherein thedummy pattern 103 a may be made of silicon oxide. Thedummy pattern 103 a may be formed by forming a silicon oxide film and subsequent patterning the same with use of a photo-lithography and a subsequent dry etching process. Thedummy pattern 103 a is used as a mask for carrying out an ion-implantation into selected upper regions of thesemiconductor substrate 101, whereby source and drainregions semiconductor substrate 101. - With reference to FIG. 5B, an impurity doped polysilicon film is entirely deposited over the source and drain
regions dummy pattern 103 a. An etch back process is carried out to the impurity doped polysilicon film until the top of thedummy pattern 103 a is shown, wherebyconductive films 114 are formed on the source and drainregions dummy pattern 103 a. - With reference to FIG. 5C, parts of the
conductive films 114 on isolation regions are selectively removed. Grooves are further formed on the isolation region in thesemiconductor substrate 101. An insulation material such as silicon oxide is buried within the grooves, wherebyfield oxide films 106 are then formed on the isolation regions. As a result, outside edges of theconductive films 114 as well as outside edges of the source and drainregions field oxide films 106, whereby source side and drainside interconnections - With reference to FIG. 5D, the
dummy pattern 103 a is removed by a selective wet etching process. Thedummy pattern 103 a made of silicon oxide may be removed by a selective wet etching which uses a hydrofluoric acid solution as an etchant. As a result, a top surface of the channel region of thesemiconductor substrate 101 defined between the source and drainregions - With reference to FIG. 5E, a dry oxidation process is carried out at a temperature of about 850° C. in a dry oxygen atmosphere, thereby concurrently forming a
gate oxide film 102 on the top surface of the channel region of thesemiconductor substrate 101 and also forminginterlayer insulators 122 on side walls and top surfaces of the source side and drainside interconnections side interconnections thicker inter-layer insulators 122 by three or four times than thegate insulation film 102. - With reference to FIG. 5F, an impurity doped polysilicon film is entirely formed which extends over the
inter-layer insulators 122 and thegate insulation film 102 as well as over thefield oxide films 106. The impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a floatinggate electrode 103 is formed in a single pair of the film deposition and subsequent patterning processes, wherein opposite side edges of the floatinggate electrode 103 are aligned to he opposite side edges of theinter-layer insulators 122. This single pair of the deposition and subsequent patterning processes for the floatinggate electrode 103 reduces the number of the fabrication processes. - With reference to FIG. 5G, an
insulation film 107 made of ONO is formed on the floatinggate 103 and on theinsulation films 106. Acontrol gate 108 is then formed on theinsulation film 107 so that the floatinggate 103 is separated and electrically floated from thecontrol gate 108 and whereby the floatinggate 103 is completely surrounded by the insulation materials to be floated in the memory cell. - In accordance with the above novel fabrication processes, the floating gate comprises a single part which has laterally extending upper parts overlying the
interconnections regions - As a modification to the foregoing embodiments of the present invention, the dummy pattern may be made of other materials than silicon nitride and silicon oxide, provided that the dummy pattern material should be selected to have such an etching selectivity that an etching rate of the dummy pattern is higher than that of the
interconnections regions - Etch back process for forming the
conductive films 114 may be carried out by a chemical mechanical polishing method. In this case, thedummy pattern 103 a may preferably be made of silicon nitride so that thedummy pattern 103 a may serve as an etching stopper to the chemical mechanical polishing. - Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention.
Claims (12)
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JP10-164944 | 1998-06-12 | ||
JP16494498A JP3298509B2 (en) | 1998-06-12 | 1998-06-12 | Method for manufacturing semiconductor device |
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US20020063276A1 true US20020063276A1 (en) | 2002-05-30 |
US6429072B1 US6429072B1 (en) | 2002-08-06 |
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US09/332,109 Expired - Fee Related US6429072B1 (en) | 1998-06-12 | 1999-06-14 | Method of forming a floating gate memory cell structure |
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JP (1) | JP3298509B2 (en) |
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Cited By (1)
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US6714454B2 (en) * | 1999-12-10 | 2004-03-30 | Yueh Yale Ma | Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell |
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US6933554B1 (en) * | 2000-07-11 | 2005-08-23 | Advanced Micro Devices, Inc. | Recessed tunnel oxide profile for improved reliability in NAND devices |
US7371633B2 (en) | 2001-02-02 | 2008-05-13 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
KR100419744B1 (en) * | 2001-06-28 | 2004-02-25 | 주식회사 하이닉스반도체 | Method for manufacturing a transistor |
US6762092B2 (en) * | 2001-08-08 | 2004-07-13 | Sandisk Corporation | Scalable self-aligned dual floating gate memory cell array and methods of forming the array |
US6475863B1 (en) * | 2002-05-17 | 2002-11-05 | Advanced Micro Devices, Inc. | Method for fabricating self-aligned gate of flash memory cell |
US6894930B2 (en) | 2002-06-19 | 2005-05-17 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND |
US7745285B2 (en) * | 2007-03-30 | 2010-06-29 | Sandisk Corporation | Methods of forming and operating NAND memory with side-tunneling |
CN101814510B (en) * | 2010-04-29 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line |
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DE3413829A1 (en) * | 1984-04-10 | 1985-10-17 | Hahn-Meitner-Institut für Kernforschung Berlin GmbH, 1000 Berlin | MOS DOSIMETER |
JPH06104451A (en) * | 1992-09-22 | 1994-04-15 | Oki Electric Ind Co Ltd | Nonvolatile semiconductor storage device |
JP2889061B2 (en) * | 1992-09-25 | 1999-05-10 | ローム株式会社 | Semiconductor storage device and method of manufacturing the same |
JPH07106443A (en) | 1993-09-30 | 1995-04-21 | Nkk Corp | Nonvolatile semiconductor memory and fabrication thereof |
JPH08264664A (en) | 1995-03-17 | 1996-10-11 | Sony Corp | Nonvolatile semiconductor memory device and manufacture thereof |
KR100209724B1 (en) * | 1996-08-21 | 1999-07-15 | 구본준 | Flash memory and method of manufacturing the same |
TW466758B (en) * | 1998-10-26 | 2001-12-01 | United Microelectronics Corp | Manufacturing method of flash memory |
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1998
- 1998-06-12 JP JP16494498A patent/JP3298509B2/en not_active Expired - Fee Related
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1999
- 1999-06-11 KR KR1019990021802A patent/KR100334477B1/en not_active IP Right Cessation
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Cited By (1)
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US6714454B2 (en) * | 1999-12-10 | 2004-03-30 | Yueh Yale Ma | Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell |
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CN1111905C (en) | 2003-06-18 |
CN1239325A (en) | 1999-12-22 |
JP3298509B2 (en) | 2002-07-02 |
US6429072B1 (en) | 2002-08-06 |
KR20000006121A (en) | 2000-01-25 |
JPH11354655A (en) | 1999-12-24 |
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