US20020041519A1 - Single electron resistor memory device and method - Google Patents
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7888—Transistors programmable by two single electrons
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/937—Single electron transistor
Definitions
- This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for providing high density, high storage capacity, low power, nonvolatile memory devices.
- single electron devices and particularly single electron memory cells, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use.
- single electron device refers to an electronic device capable of providing a repeatable and measurable response to the presence or absence of a single electron.
- FETs field effect transistors
- FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device 20 , in accordance with the prior art.
- the single electron device 20 includes first 22 and second 24 electrodes and an island 26 formed from conductive material, which may be semiconductor material, as discussed in U.S. Pat. No. 5,731,598, entitled “Single Electron Tunnel Device And Method For Fabricating The Same” issued to H. Kado et al. (Mar. 24, 1998).
- the first 22 and second 24 electrodes are each separated from the island 26 by small insulating gaps 28 , 28 ′.
- the first 22 and second 24 electrodes, the island 26 and the gaps 28 , 28 ′ are all collectively mounted on an insulating substrate 30 or are surrounded by an insulator.
- the gaps 28 , 28 ′ may be formed of any insulating material but must be small enough to allow conduction band electrons 32 (hereinafter “electrons”) to tunnel through them in response to a voltage V coupled across the first 22 and second 24 electrodes.
- the voltage V is provided by an external source, represented in FIG. 1A by a battery 34 .
- a first condition for trapping one or more electrons 32 on the island 26 is that the resistance R between the island 26 and other structures on the substrate 30 must be greater than a quantum resistance R k , as is discussed, for example, in “Single-electron devices” by H. Ahmed et al., Microelectronic Engineering 32 (1996), pp. 297-315, and “Single electron electronics: Challenge for nanofabrication” by H. Ahmed, J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2101-2108.
- a primary resistance R between the island 26 and any other structure is set by tunneling resistances R t associated with the gaps 28 , 28 ′ separating the island 26 from the first 22 and second 24 electrodes.
- the quantum resistance R k equals h/q 2 , or about 26 k ⁇ , where h is Planck's constant and q represents the charge of a single electron. This first condition will be satisfied for all of the examples considered herein but is included for completeness sake.
- a second condition is that allowed states for these electrons 32 must be separated from a conduction band edge E C by an “electron charging energy” that is given as q 2 /2C, where C represents a capacitance of the island 26 .
- a first electron 32 that is introduced onto the island 26 will occupy an allowed state having a potential energy that is greater than that of the conduction band edge E C for the material forming the island 26 by q 2 /2C.
- a third condition is that, for the electron or electrons 32 to be trapped on the island 26 , the electron charging energy q 2 /2C must be substantially greater than an average thermal energy kT, or q 2 /2C>kT, where k represents Boltzmann's constant and T represents temperature in Kelvin.
- FIG. 1B is a simplified potential energy diagram for the device 20 of FIG. 1A showing a potential well 40 , in accordance with the prior art.
- FIG. 1B shows Fermi levels (“E F ”) 42 , 44 in the first 22 and second 24 electrodes, respectively, a lowest allowed state 46 for one electron 32 in the potential well 40 on the island 26 , and energy barriers 48 , 48 ′ associated with insulating materials forming the gaps 28 , 28 ′, respectively.
- An important property of the device 20 of FIG. 1A is that no significant current can flow through the device 20 until a magnitude of the potential V due to the external source 34 equals or exceeds the electron charging energy or V ⁇ q 2 /2C.
- FIG. 1C is a simplified potential energy diagram illustrating the potential V setting the Fermi level 42 at the left side of the Figure equal to the lowest allowed state of the potential well 40 , i.e., at the onset of conduction, in accordance with the prior art.
- FIG. 1D is a simplified graph of an I-V characteristic 50 for the device 20 of FIG. 1A, in accordance with the prior art.
- the I-V characteristic 50 shows essentially no conduction until the applied voltage V reaches a threshold V C , causing the Fermi level 42 on the electron supply side to be equal to the electron charging energy q 2 /2C.
- the region of essentially no conduction is known as the Coulomb blockade region.
- the applied voltage V reaches the threshold V C , known as the Coulomb gap voltage
- the energy barrier effectively vanishes. Linear I-V dependence is seen in FIG. 1D for voltages having an absolute magnitude exceeding V C .
- FIG. 2 is a simplified schematic illustration of a typical field effect transistor (“FET”) 60 that includes the island 26 of FIG. 1A for storing one or more electrons 32 , in accordance with the prior art.
- the FET 60 includes all of the elements of the two-terminal device 20 of FIG. 1 and additionally includes a gate 62 having a capacitance C G and a gate bias supply 64 .
- the gate bias supply 64 includes a first electrode coupled to the gate 62 and a second electrode coupled to one side of the supply 34 providing the voltage V.
- the FET 60 has a channel 66 formed from semiconductor material that is coupled to the first 22 and second 24 electrodes.
- FETs 60 capable of providing repeatable output signals indicative of single electron 32 storage on the islands 26 are described in “A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel” by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and “Fabrication And Characterization of Room Temperature Silicon Single Electron Memory” by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843.
- These FETs 60 employ a floating island 26 between the gate 62 and the channel 66 to modulate conductivity in the channel 66 .
- the island 26 spans the width of the channel 66 .
- the islands 26 may be employed. For example, shallow implantation of relatively high doses (e.g., ca. 5-50 ⁇ 10 14 /cm 2 ) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (September 1996), pp.
- Prior art FETs may provide multiple islands 26 between the gate 62 and the channel 66 , and are capable of storing multiple electrons 32 .
- these FETs are analogous to conventional flash memories and are capable of multilevel signal storage and readout.
- An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095.
- FETs 60 including one or more islands 26 suitable for capture of electrons 32 thus are able to provide measurable and repeatable changes in their electrical properties in response to capture of the electron or electrons 32 on at least one island 26 .
- these FETs 60 provide these changes in a convergent manner, i.e., the changes may be produced by storage of a single electron 32 and storage of that single electron 32 can inhibit storage of another electron 32 .
- some of the FETs 60 avoid some problems due to number fluctuations in the population of electrons 32 that could otherwise be troublesome for FETs 60 having very small populations of electrons 32 .
- the energy barriers 48 , 48 ′ cause the single electron device 20 and the FETs 60 to store trapped electrons 32 for significant periods of time, even in the absence of externally applied electrical power (e.g., voltage sources 34 , 64 ). As a result, a nonvolatile memory function is provided by these devices 20 and FETs 60 .
- the present invention includes a memory cell having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of conductive material having a maximum dimension of three nanometers and surrounded by an insulator having a thickness of between five and twenty nanometers.
- the islands and the insulator are formed in pores extending into the semiconductor material between the first and second electrodes.
- electrons may tunnel into or out of the islands with the assistance of externally-applied fields.
- the capacitance of the islands is small enough that single electrons stored on the islands provide consistent, externally observable changes in the memory cells.
- the present invention provides methods for reading data from, writing data to and erasing memory cells capable of storing data by the presence or absence of a single electron in an island of conductive material contained in the memory cells.
- the reading, writing and erasing operations may be accompanied by a verification process that compensates for stored charge, trap generation and the like that otherwise might obscure desired data.
- FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device, in accordance with the prior art.
- FIG. 1B is a simplified potential energy diagram for the device of FIG. 1A, in accordance with the prior art.
- FIG. 1C is a simplified potential energy diagram, illustrating the potential V setting the Fermi level at the left side of the Figure equal to the lowest allowed state of the potential well of FIG. 1B, in accordance with the prior art.
- FIG. 1D is a simplified graph of an I-V characteristic for the device of FIG. 1A, in accordance with the prior art.
- FIG. 2 is a simplified schematic illustration of a typical field effect transistor that includes the island of FIG. 1A for storing one or more electrons, in accordance with the prior art.
- FIG. 3A is a simplified plan view of a memory device including memory cells employing single electron memory devices having electrical characteristics similar to those of the devices of FIGS. 1 and 2, in accordance with embodiments of the present invention.
- FIG. 3B is a simplified isometric view of a single electron resistor memory device in the memory cell of FIG. 3A, in accordance with embodiments of the present invention.
- FIG. 3C is a simplified cross-sectional view of the device of FIG. 3B, showing islands included within the semiconductor material of the body, in accordance with embodiments of the present invention.
- FIG. 4 is a simplified flow chart of a process for reading the memory cell of FIGS. 3 A-C, in accordance with embodiments of the present invention.
- FIGS. 5 and 6 are simplified flow charts for processes for writing data to the memory cell of FIGS. 3 A-C and for erasing data stored in the memory cell, respectively, in accordance with embodiments of the present invention.
- FIG. 7 is a graph representing storage and erase time estimates for various energy barriers, in accordance with embodiments of the present invention.
- FIG. 8 is a simplified flowchart of a process for forming the islands of FIGS. 1 and 2, in accordance with embodiments of the present invention.
- FIGS. 9A and 9B are simplified cross-sectional views of the islands as they are being formed using the process of FIG. 8, in accordance with embodiments of the present invention.
- FIG. 10 is a simplified block diagram of a computer system including the memory device of FIGS. 3 A-C, in accordance with embodiments of the present invention.
- FIG. 3A is a simplified plan view of a memory device 72 including a memory cell 73 having electrical characteristics similar to those of the devices 20 and 60 of FIGS. 1 and 2, in accordance with embodiments of the present invention.
- the memory device 72 includes a column addressing circuit 74 coupled to a plurality of column address lines 75 , and a row addressing circuit 76 coupled to a plurality of row address lines 77 .
- the memory cell 73 is located at an intersection of a column address line 75 and a row address line 77 and is addressed by activation of the column 75 and row 77 address lines coupled to the memory cell 73 , as is discussed below in more detail.
- FIG. 3B is a simplified isometric view of a single electron resistor memory device 80 in the memory cell 73 of FIG. 3A, in accordance with embodiments of the present invention.
- the device 80 includes a body 82 having first 84 and second 86 electrodes formed at opposing ends.
- the first 84 and second 86 electrodes form low resistance contacts to the body 82 .
- the body 82 includes n-type semiconductor material having a donor concentration of about 10 15 /cm 3 or less and the first 84 and second 86 electrodes are N+ ohmic contacts to the body 82 .
- the first electrode 84 is coupled to a row address line 77 and the second electrode 86 is coupled to a column address line 75 .
- the device 80 also optionally includes one or more gates 88 , 88 ′ coupled to one or more erase lines 90 , 90 ′ for erasing data stored in the device 80 .
- the gates 88 , 88 ′ are formed from polysilicon using conventional processing techniques.
- FIG. 3C is a simplified cross-sectional view of the device 80 of FIG. 3B, showing islands 26 (see FIGS. 1 and 2) included within the semiconductor material 98 forming the body 82 of the device 80 , in accordance with embodiments of the present invention.
- Each island 26 is surrounded by a dielectric 100 that provides the energy barriers 48 , 48 ′ (FIGS. 1B and C) associated with the gaps 28 , 28 ′, which insulate the island 26 from other islands 26 and from the semiconductor material 98 .
- the device 80 of FIGS. 3 A-C has a first state exhibiting a first current-voltage characteristic when no electrons 32 are stored on the islands 26 within the device 80 .
- the device 80 has a second state exhibiting a second current-voltage characteristic when one or more electrons 32 are stored in one or more islands 26 contained in the body 82 of the device 80 .
- In the second state less current between the first electrode 84 and the second 86 electrode for a given voltage difference between the first 84 and second 86 electrodes than in the first state, and this difference may be detected by sensing circuitry (not illustrated) coupled to the column 75 or the row 77 address lines. Processes for switching the device 80 between the first and second states by storage and removal of electrons 32 from the island or islands 26 in the body 82 of the device 80 are explained in more detail below.
- the column address line 75 is coupled to a first voltage (e.g., ground) and the row address line 77 is coupled to a second voltage (e.g., four volts) sufficient to cause single electrons 32 (FIG. 1) to tunnel into and to be stored on one or more of the islands 26 in the body 82 of the device 80 , as is explained below in more detail with reference to FIG. 5.
- a first voltage e.g., ground
- a second voltage e.g., four volts
- the row 77 or column 75 (or both) address line is coupled to an electron sink (e.g., ground).
- the body 82 is depleted of mobile charge carriers by an externally-applied bias, which also tilts the barriers 48 , 48 ′ and results in field-assisted tunneling of electrons 32 stored in the potential wells 40 of the islands 26 from the islands 26 into the body 82 .
- a negative potential is applied to one or more gate electrodes 88 , 88 ′ sufficient to completely deplete the semiconductor material 98 forming the body 82 of mobile charge carriers (i.e., electrons 32 or holes) to allow any stored electrons 32 to tunnel out of the island or islands 26 . Electrons 32 tunneling out of the islands 26 are removed from the semiconductor material 98 by electrical fields induced by the voltage applied to the gate electrodes 88 , 88 ′. As a result, the device 80 is restored to the first state.
- mobile charge carriers i.e., electrons 32 or holes
- a change in a current I between the first 84 and the second 86 electrode, corresponding to a difference ⁇ I in the current I between the first and second states, can be estimated as follows.
- the body 82 of the device 80 has a cross-sectional area A, a length L between the first 84 and second 86 electrodes and a number n T of electrons 32 trapped on the islands 26 .
- a conductivity a for the semiconductor material 98 is given by nq ⁇ A/L, where ⁇ represents the electron mobility and n represents the number of mobile charge carriers (electrons 32 ) per cubic centimeter.
- a voltage V of one volt, a mobility ⁇ of 600 cm 2 /(v-sec) and a length L of one micrometer corresponds to a decrease in current ⁇ I due to one stored electron 32 of 10 nanoamperes.
- the body 82 of the device 80 may have a length L of about one micrometer (10 ⁇ 4 cm) and have a cross-sectional area A of about 10 ⁇ 8 cm 2 .
- a free carrier concentration of 10 15 /cm 3 or less allows the gates 88 , 88 ′ to be able to deplete the semiconductor material 98 with relatively low applied voltages.
- FIG. 4 is a simplified flow chart of a process 120 for reading the memory cell 73 of FIG. 3A, in accordance with embodiments of the present invention.
- the process 120 begins in a step 122 by activating one of the column address lines 75 and one of the row address lines 77 of FIGS. 3 A-C to address one of the memory cells 73 .
- a bias current I B or voltage V B is applied to the addressed memory cell 73 , as is discussed below in more detail.
- the addressed memory cell 73 is coupled to a sensing circuit (not shown).
- a query task 128 compares a measured response X M to a threshold X T to determine if a logical “1” or a logical “0” is stored in the memory cell 73 as is described below in more detail.
- the measured response X M is a voltage, measured, for example, across the first 84 and second 86 electrodes.
- the query task 128 determines that the measured response X M exceeds the threshold X T , at least one electron 32 is stored in the memory cell 73 and the memory cell 73 is storing a first logical state.
- the query task 128 determines that the measured response X M does not exceed the threshold X T , no electron 32 is stored in the memory cell 73 and the memory cell 73 is storing a second logical state.
- the measured response X M is a current, measured, for example, at the first electrode 84 .
- the query task 128 determines that the measured response X M exceeds the threshold X T , no electron 32 is stored in the memory cell 73 and the memory cell 73 is in the second logical state.
- the query task 128 determines that the measured response X M does not exceed the threshold X T , at least one electron 32 is stored in the memory cell 73 and the memory cell 73 is in the first logical state.
- the comparison circuit indicates that the memory cell 73 is in the first logical state, e.g., that a logical “1” is stored in the memory cell 73 , in a step 130 .
- the comparison circuit indicates that a logical “0” is stored in the memory cell 73 in a step 132 .
- the process 120 ends following either step 130 or step 132 .
- the query task 128 discriminates between a plurality of different logical values or states that may be stored in the memory cell 73 by comparing the measured response X M to a plurality of thresholds X Ti .
- An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095.
- FIGS. 5 and 6 are simplified flow charts for processes 140 and 160 for writing data to the memory cell 73 of FIG. 3A and for erasing data stored in the memory cell 73 , respectively, in accordance with embodiments of the present invention.
- the processes 140 and 160 both use a verification process similar to a conventional verification process used with flash memories to compensate for variations in memory cell characteristics from one memory cell 73 to another, as is described in “Verify: Key to the Stable Single-Electron-Memory Operation” by T. Ishii et al. (1997 IEDM), pp. 171-174.
- the write process 140 begins in a step 142 by activating one of the column address lines 75 and one of the row address lines 77 of FIGS. 3 A-C to address one of the memory cells 73 .
- a write pulse which may be either a current I W or a voltage V W pulse, is applied to the addressed memory cell 73 .
- the step 144 is used to write a binary value to the memory cell 73 .
- the step 144 is used to write one of a plurality of possible values or data entries to the memory cell 73 by injecting a controlled number of electrons 32 into the islands 26 of the memory cell 73 .
- an index variable n corresponding to a number of write cycles applied to this memory cell during this write process 140 , is incremented.
- the memory cell 73 is read by sampling a voltage or current associated with the memory cell 73 , i.e., the process 120 of FIG. 4.
- a query task 150 then compares the read data to the data written to the memory cell 73 in the step 144 .
- the process 140 ends.
- the maximum number of cycles N is despite differences in programming time between memory cells 73 , without wasting excessive amounts of time in attempts to program defective memory cells 73 .
- a step 154 records that a write failure has occurred and the process 140 ends.
- the record of a write failure that is generated in the step 154 may be used to construct a conventional memory map describing addresses of defective memory cells 73 .
- Memory maps are used in order to avoid writing data to, or attempting to write data to, or reading data from, memory cells 73 that are defective.
- the record of a write failure that is generated in the step 154 may be used to replace defective memory cells 73 with memory cells 73 that are known to be working properly, as is conventional in fabrication and repair of memory devices such as dynamic random access memories.
- step 144 where a write pulse is applied to the memory cell 73 , a finite number of electrons 32 are injected into the island or islands 26 .
- a probability of write failure is finite and nonzero because injection of electrons 32 into the potential wells 40 (FIG. 1C) is essentially stochastic. For example, a failure probability of 0.1% is unacceptable in modern memory devices. Additionally, characteristics of the memory cell 73 may change with time, due to generation of new trapping centers or by trapping of charge in or near the memory cell 73 .
- Reading data from the memory cell 73 after a write pulse has been applied to the memory cell allows determination that a write failure has occurred.
- the probability of trapping the desired number of electrons 32 increases substantially and may approach unity.
- a width W W of the write pulses I W or V W depends geometrically on n, e.g., W W (n) ⁇ 2 n , n ⁇ I ⁇ .
- the amplitude of the write pulses depends arithmetically on n, e.g., V W (n) ⁇ V W (o)(1+n/M), n ⁇ I ⁇ , where V W (o) represents an initial value and M represents a proportionality constant.
- the erase process 160 begins in a step 162 by activating one or more of the column address lines 75 and one or more of the row address lines 77 of FIGS. 3 A-C to address one or more of the memory cells 73 .
- the step 162 selects a group of memory cells 73 , which may be a subset of the memory cells on one memory device 72 , may be all of the memory cells 73 on a memory device 72 or may include memory cells 73 from more than one memory device 72 .
- an erase pulse which may be either a current I E or voltage V E , is applied to the addressed memory cell 73 .
- the erase pulse is applied to one or both of the erase gates 88 , 88 ′, with one or both of the electrodes 84 , 86 coupled to a suitable electron sink.
- an index variable n corresponding to a number of erase cycles applied to this memory cell 80 during this erase process 160 , is incremented.
- the memory cell 73 is read by sampling a voltage or current associated with the memory cell 73 .
- a query task 170 compares the read data to an expected value (e.g., corresponding to an absence of stored electrons 32 ) to determine if the contents of the memory cell 73 were erased in the step 164 .
- the process 160 ends.
- control passes to a query task 172 to determine if a maximum number of cycles N has been reached (i.e., is n ⁇ N?).
- N is chosen to balance differences in erase time from one memory cell 73 to another memory cell 73 without spending excessive time to erase defective memory cells 73 .
- control passes back to the step 164 , and steps 164 - 170 or 172 repeat.
- the erase pulses V E may be varied with n as described above for the write pulses I W or V W in connection with the process 140 of FIG. 5.
- a step 174 records that an erase failure has occurred The process then 160 ends.
- individual memory cells 73 are erased as needed for storage of new data.
- all of the memory cells 73 in a group or in an entire memory device 72 are erased en masse, by addressing a group of memory cells 73 in the step 162 and application of the erase pulses in the step 164 to all of the memory cells 73 in the group or in the memory device 72 simultaneously.
- the steps 166 - 174 are then carried out for each memory cell 73 individually, with a step of addressing the individual memory cells 73 being carried out prior to the step 166 of incrementing the index variable n.
- the memory cells are erased en masse, however, the steps 166 - 174 are carried out as steps 146 - 154 of the verified write process 140 of FIG. 5.
- An advantage of en masse erasure is that the erase process 160 is slow, typically requiring milliseconds. Erasure of the entire memory device 72 one memory cell 73 at a time takes much longer than erasure of the entire memory device 72 en masse, and this is more exaggerated as the number of memory cells 73 in the memory device 72 increases.
- ⁇ S storage times
- ⁇ S also known as latency
- ⁇ S storage times
- ⁇ S ⁇ e ( ⁇ E/kT) e (d/d o )
- ⁇ E represents the energy level difference between the energy barriers 48 , 48 ′ and the lowest allowed state in the island 26
- d/d o represents the relative thickness of the gaps 28, 28′.
- Larger ⁇ E values or large d/d o values provide for longer storage times but also require higher write and erase pulse magnitudes and greater pulse durations.
- ⁇ E is a function of the material forming the island 26 and the material forming the gaps 28 , 28 ′.
- Representative values for electron affinities ⁇ for several materials are summarized below in Table I. Measured or achieved electron affinities ⁇ depend strongly on surface treatment and surface contamination and may vary from the values given in Table I. TABLE I Electron affinities ⁇ for selected materials. ⁇ (eV) Material Use 4.05 Si Islands 3.6/3.7* SiC Islands 1.4** C (diamond) Islands 0.9-4.05 Silicon oxycarbide (projected) Islands 0.9 SiO 2 Gaps
- FIG. 7 is a graph representing estimated storage 176 and erase 178 time estimates for various island electron affinities ⁇ ISL together with SiO 2 barriers in accordance with embodiments of the present invention.
- the left ordinate corresponds to a logarithm of retention time 176 at constant temperature, while the right ordinate corresponds to a logarithm of erase time 178 at constant erase voltage.
- Erase times 178 for the memory device 72 are determined by the height of the energy barrier 48 , 48 ′ (FIGS. 1B and C) surrounding the island 26 .
- Lower energy barriers 48 , 48 ′ require lower voltage, shorter erase pulses because lower energy barriers 48 , 48 ′ provide shorter tunneling distances and much higher tunneling probabilities. Short erase times 178 are desirable for some applications of electronically-erasable memories such as the memory device 72 .
- Lower barriers 48 , 48 ′ also result in shorter retention times 176 due to thermal activation of electrons 32 over or through the energy barriers 48 , 48 ′.
- the islands 26 may be formed from silicon, from microcrystalline diamond-like films of Si (1-x) C x , with the composition ratio, x, ranging from 0.5 to one, or from silicon oxycarbide compounds, to provide electron affinities ⁇ ranging between about 4.05 eV and 0.9 eV or less (see Table I), corresponding to energy barriers ⁇ E ranging from about 3.95 to about 0 eV (ignoring the charging voltage).
- charge retention times 176 can be changed from seconds, characteristic of DRAMs, to years, characteristic of hard disk drives.
- the memory device 72 can either be made to emulate a DRAM or a hard disk drive by varying the composition of the islands 26 .
- One device type can then perform all memory functions.
- FIG. 7 illustrates that storage 176 and erase 178 times vary exponentially with the height of the energy barriers 48 , 48 ′.
- memories using polycrystalline silicon floating gates embedded in silicon dioxide are estimated to have charge retention times 176 of millions of years at 85° C. because the energy barriers 48 , 48 ′ are large (3.2 eV), resulting in erase times 178 in the millisecond range.
- the high electric fields required for erasure as a result of the large energy barriers 48 , 48 ′ may result in reliability problems or, in the worst case, lead to breakdown and catastrophic failure of the device 72 .
- An island 26 may be composed of a material of lower or adjusted energy barrier height, such as diamond-like compounds of silicon, carbon and oxygen, to provide desired energy barriers 48 , 48 ′.
- an acceptable retention time 176 can be established, whether seconds or years, by varying the relative concentrations of Si, C and O, thereby varying the electron affinity ⁇ for the islands 26 . This then determines the height of the energy barriers 48 , 48 ′ and therefore, in part, the erase time 178 for a particular erase voltage.
- FIG. 7 shows the concepts involved using rough order-of-magnitude estimates of the variations of storage and erasure times with barrier height.
- the same device structure can be used either as replacements for DRAMS or as replacements for hard disk drives. Only the composition of the island 26 needs to be changed in order to change the retention time and the erasure characteristics. This may be done on one integrated circuit so that radically different types of memory functions are realized on one integrated circuit.
- FIG. 8 is a simplified flowchart of a process 180 for forming the islands 26 of FIGS. 1 and 2, and FIGS. 9 A- 9 E are simplified cross-sectional views of the islands 26 as they are being formed using the process 180 of FIG. 8, in accordance with embodiments of the present invention.
- the process 180 begins in a step 182 with formation of voids or pores 202 (FIG. 9A) in a suitable silicon substrate or layer 98 (FIGS. 3 C and 9 A- 9 E).
- the voids or pores 202 are formed by processes similar to those described in “Formation Mechanism of Porous Silicon Layers Obtained by Anodization of Monocrystalline n-type Silicon in HF Solutions” by V.
- a current density of between 5 and 40 mA/cm 2 is employed together with 12-24% HF.
- N D silicon donor concentration
- HF concentration or anodization current density provides larger pores 202 and may lead to reentrant pores 202 .
- Pores 202 are readily and uniformly formed to have the desired characteristics when using simple and easily controlled processes.
- a step 184 the silicon 98 including interiors of the pores 202 is oxidized to provide a thin oxide layer 100 (FIG. 9B).
- the silicon 98 is oxidized to provide the oxide layer 100 to have a thickness of between 2.5 and ten nanometers.
- the oxidation step 184 may be carried out using conventional oxidation techniques.
- an inductively-coupled oxygen-argon mixed plasma is employed for oxidizing the silicon 98 , as described in “Low-Temperature Si Oxidation Using Inductively Coupled Oxygen-Argon Mixed Plasma” by M. Tabakomori et al., Jap. Jour. Appl. Phys., Part 1, Vol. 36, No.
- electron cyclotron resonance nitrous oxide plasma is employed for oxidizing the silicon 98 , as described in “Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and its Application to Polycrystalline Silicon Thin Film Transistors,” J. Lee et al., Jour. Electrochem. Soc., Vol. 144, No. 9 (September 1997), pp. 3283-3287 and “Highly Reliable Polysilicon Oxide Grown by Electron Cyclotron Resonance Nitrous Oxide Plasma” by N. Lee et al., IEEE El. Dev. Lett., Vol. 18, No. 10 (October 1997), pp. 486-488.
- a conductive material 204 (FIG. 9C) is formed over the surface of the silicon 98 and in the pores 202 .
- semiconductor material 204 is deposited over the surface of the silicon 98 and in the pores 202 .
- Examples of materials 204 that may be used in accordance with embodiments of the invention include the materials listed in Table I above.
- the material 204 within the pores 202 forms the islands 26 and is chosen to have an electron affinity ⁇ that, together with the thickness d/d o and the electron affinity ⁇ of the insulator 100 filling the gaps 28 , 28 ′ (FIGS. 1A and 2), provides storage times in a range of from hours to days or longer, together with practical erase parameters.
- silicon oxycarbide is employed as the material 204 in the step 186 .
- a process for forming thin microcrystalline films of silicon oxycarbide is described in “transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques” by R. Martins et al., Solar Energy Materials and Solar Cells 41/42 (1996), pp. 493-517.
- a diluent/reaction gas e.g., hydrogen
- the mixed gases containing the species to be deposited are introduced close to the region where the growth process takes place, which is often a substrate heater.
- a bias grid is located between the plasma ignition and the growth regions, spatially separating the plasma and growth regions.
- Deposition parameters for producing doped microcrystalline Si x :C y :O z :H films may be defined by determining the hydrogen dilution rate and power density that lead to microcrystallization of the grown film 204 .
- the power density is typically less than 150 milliWatts per cm 3 for hydrogen dilution rates of 90%+, when the substrate temperature is about 250° C. and the gas flow is about 150 sccm.
- the composition of the films may then be varied by changing the partial pressure of oxygen during film growth to provide the desired characteristics.
- SiC is employed as the material 204 in the step 186 .
- SiC films may be fabricated by chemical vapor deposition, sputtering, laser ablation, evaporation, molecular beam epitaxy or ion implantation.
- Vacuum annealing of silicon substrates is another method that may be used to provide SiC layers having thicknesses ranging from 20 to 30 nanometers, as described in “Localized Epitaxial Growth of Hexagonal and Cubic SiC Films on Si by Vacuum Annealing” by Luo et al., Appl. Phys. Lett. 69(7) (1996), pp. 916-918.
- the substrates Prior to vacuum annealing, the substrates are degreased with acetone and isopropyl alcohol in an ultrasonic bath for fifteen minutes, followed by cleaning in a solution of H 2 SO 4 :H 2 O 2 (3:1) for fifteen minutes. A five minute rinse in deionized water then precedes etching with a 5% HF solution.
- the substrates are blown dry using dry nitrogen and placed in a vacuum chamber. The chamber is pumped to a base pressure of 1-2 ⁇ 10 ⁇ 6 Torr. The substrate is heated to 750 to 800° C. for half an hour to grow the microcrystalline SiC film.
- silicon is employed as the material 204 in the step 186 .
- Methods for depositing high quality polycrystalline films of silicon on silicon dioxide substrates are given in “Growth of Polycrystalline Silicon at low Temperature on Hydrogenated Microcrystalline Silicon ( ⁇ c-Si:H) Seed Layer” by Parks et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp. 403-408, “Novel Plasma Control Method in PECVD for Preparing Microcrystalline Silicon” by Nishimiya et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp.
- a step 188 the portion of the materials 204 deposited in the step 186 that are located on the silicon surface are effectively removed.
- the portion of the materials 204 deposited in the step 186 that are located on the surface of the silicon body 98 are oxidized to provide a structure as illustrated in FIG. 9D.
- the step 188 proceeds until the material 204 on the surface is completely oxidized but does not proceed for long enough to oxidize all of the material 204 in the pores 202 .
- isolated islands 26 of semiconductor material 204 surrounded by silicon dioxide 100 are formed in the pores 202 in the single crystal silicon 98 forming the body 82 of the device 80 (FIGS. 3 A-C).
- the materials listed in Table I for use in the islands 26 can be oxidized to form silicon dioxide 208 or to form a volatile gas (CO 2 ).
- the islands 26 may be isolated from each other by a simple oxidation process that may not require a photolithographic step.
- an optional gate oxide 210 (FIG. 9E) is formed on the silicon surface and on top of the material 204 deposited in the pores 202 .
- the gate oxide is patterned using conventional techniques. The process 180 then ends and further fabrication is carried out using conventional processing. An advantage of the process 180 is that it does not rely on very-fine-line lithography for formation of the islands 26 .
- FIG. 3C it will be appreciated that other techniques for forming the islands 26 (FIG. 3C) may be employed. For example, shallow implantation of relatively high doses (e.g., ca. 5-50 ⁇ 10 14 /cm 2 ) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No.
- FIG. 10 is a simplified block diagram of a portion of a computer system 220 including the memory device 80 of FIGS. 3 A-C, in accordance with embodiments of the present invention.
- the computer system 220 includes a central processing unit 222 for performing various computing functions, such as executing specific software to perform specific calculations or tasks.
- the central processing unit 222 is coupled via a bus 224 to a memory 226 , a user input interface 228 , such as a keyboard or a mouse, and a display 230 .
- the memory 226 may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and read-write memory for temporary storage of data.
- the processor 222 operates on data from the memory 226 in response to input data from the user input interface 228 and displays results on the display 230 .
- the processor 222 also stores data in the read-write portion of the memory 226 .
- the integrated circuit 72 (FIG. 3A) is particularly useful when it is a memory integrated circuit in the read-write memory portion of the memory 226 , because it may then allow the memory 226 to provide increased information storage capacity and/or density.
- the embodiments of the present invention provide a compact, sensitive memory cell and permit very high storage capacity memories to be fabricated. Additionally, the inventive memory cell does not require high resolution lithography for fabrication of the islands that store charge.
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Abstract
Description
- This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for providing high density, high storage capacity, low power, nonvolatile memory devices.
- Single electron devices, and particularly single electron memory cells, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use. As used herein, the term “single electron device” refers to an electronic device capable of providing a repeatable and measurable response to the presence or absence of a single electron.
- As device sizes have shrunk over the last several decades, the number of electrons contributing to the drain current in field effect transistors (“FETs”) used in memory devices has correspondingly decreased. Extrapolation from these trends suggests that in another decade, FETs will have drain currents including as few as ten electrons at a time. When so few electrons contribute to a current and therefore to a signal, normal fluctuations in the number of electrons present in a volume of semiconductor material can lead to uncertainty or error in the signal that the current represents.
- Memories using single electron memory cells provide certainty in numbers of electrons representing data in a memory cell and therefore help to avoid problems due to fluctuations in the number of electrons that are present in a transistor at one time. Memory cells employing single electron transistors are also extremely simple and can be quite small. For example, a memory structure employing vertically stacked cells to provide an area per bit of 0.145 squared is described in “A 3-D Single-Electron-Memory Cell Structure with 2F2 per bit” by T. Ishii et al. (IEDM 97), pp. 924-926.
- The combination of size, power requirements and simplicity make single electron structures promising candidates for very high capacity memory integrated circuits. This is discussed in more detail in “Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage” by K. Yano et al., 1996 Intl. Solid State Circuits Conf. (Feb. 9, 1996), pp. 266-267 and “A 128 Mb Early Prototype for Gigascale Single-Electron Memories” by K. Yano et al., 1998 Intl. Solid State Circuits Conf. (Feb. 7, 1998), pp. 344-345.
- FIG. 1A is a simplified schematic diagram of a typical two-terminal
single electron device 20, in accordance with the prior art. Thesingle electron device 20 includes first 22 and second 24 electrodes and anisland 26 formed from conductive material, which may be semiconductor material, as discussed in U.S. Pat. No. 5,731,598, entitled “Single Electron Tunnel Device And Method For Fabricating The Same” issued to H. Kado et al. (Mar. 24, 1998). The first 22 and second 24 electrodes are each separated from theisland 26 by smallinsulating gaps island 26 and thegaps insulating substrate 30 or are surrounded by an insulator. Thegaps battery 34. - A first condition for trapping one or
more electrons 32 on theisland 26 is that the resistance R between theisland 26 and other structures on thesubstrate 30 must be greater than a quantum resistance Rk, as is discussed, for example, in “Single-electron devices” by H. Ahmed et al., Microelectronic Engineering 32 (1996), pp. 297-315, and “Single electron electronics: Challenge for nanofabrication” by H. Ahmed, J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2101-2108. When the first 22 and second 24 electrodes and theisland 26 are mounted on theinsulating substrate 30 and are surrounded by an insulator such as air, a primary resistance R between theisland 26 and any other structure is set by tunneling resistances Rt associated with thegaps island 26 from the first 22 and second 24 electrodes. The quantum resistance Rk equals h/q2, or about 26 kΩ, where h is Planck's constant and q represents the charge of a single electron. This first condition will be satisfied for all of the examples considered herein but is included for completeness sake. - A second condition is that allowed states for these
electrons 32 must be separated from a conduction band edge EC by an “electron charging energy” that is given as q2/2C, where C represents a capacitance of theisland 26. In other words, afirst electron 32 that is introduced onto theisland 26 will occupy an allowed state having a potential energy that is greater than that of the conduction band edge EC for the material forming theisland 26 by q2/2C. - A third condition is that, for the electron or
electrons 32 to be trapped on theisland 26, the electron charging energy q2/2C must be substantially greater than an average thermal energy kT, or q2/2C>kT, where k represents Boltzmann's constant and T represents temperature in Kelvin. The capacitance C must be on the order of one attoFarad forelectrons 32 to be trapped on theisland 26 for any appreciable length of time at room temperature (kT=0.026 eV at room temperature). For example, anisland 26 having a capacitance of 10−16 F is about 100 nanometers in diameter but can only exhibit single-electron effects at temperatures at or below about 4 Kelvin.Islands 26 having diameters of one to five nanometers exhibit significant single-electron effects at room temperature (circa 300 K). - FIG. 1B is a simplified potential energy diagram for the
device 20 of FIG. 1A showing apotential well 40, in accordance with the prior art. FIG. 1B shows Fermi levels (“EF”) 42, 44 in the first 22 and second 24 electrodes, respectively, a lowest allowedstate 46 for oneelectron 32 in thepotential well 40 on theisland 26, andenergy barriers gaps device 20 of FIG. 1A is that no significant current can flow through thedevice 20 until a magnitude of the potential V due to theexternal source 34 equals or exceeds the electron charging energy or V≧q2/2C. FIG. 1C is a simplified potential energy diagram illustrating the potential V setting the Fermilevel 42 at the left side of the Figure equal to the lowest allowed state of thepotential well 40, i.e., at the onset of conduction, in accordance with the prior art. - FIG. 1D is a simplified graph of an
I-V characteristic 50 for thedevice 20 of FIG. 1A, in accordance with the prior art. TheI-V characteristic 50 shows essentially no conduction until the applied voltage V reaches a threshold VC, causing the Fermilevel 42 on the electron supply side to be equal to the electron charging energy q2/2C. The region of essentially no conduction is known as the Coulomb blockade region. When the applied voltage V reaches the threshold VC, known as the Coulomb gap voltage, the energy barrier effectively vanishes. Linear I-V dependence is seen in FIG. 1D for voltages having an absolute magnitude exceeding VC. - FIG. 2 is a simplified schematic illustration of a typical field effect transistor (“FET”)60 that includes the
island 26 of FIG. 1A for storing one ormore electrons 32, in accordance with the prior art. The FET 60 includes all of the elements of the two-terminal device 20 of FIG. 1 and additionally includes agate 62 having a capacitance CG and agate bias supply 64. Thegate bias supply 64 includes a first electrode coupled to thegate 62 and a second electrode coupled to one side of thesupply 34 providing the voltage V. The FET 60 has achannel 66 formed from semiconductor material that is coupled to the first 22 and second 24 electrodes. - Several examples of
FETs 60 capable of providing repeatable output signals indicative ofsingle electron 32 storage on theislands 26 are described in “A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel” by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and “Fabrication And Characterization of Room Temperature Silicon Single Electron Memory” by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843.Similar FETs 60 are described in “Room Temperature Operation of Si Single-Electron-Memory with Self-Aligned Floating Dot Gate” (IEDM 1996), pp. 952-954, Appl. Phys. Lett. 70(13) (Mar. 13, 1997), pp. 1742-1744 and “Si Single Electron Tunneling Transistor With Nanoscale Floating Dot Stacked on a Coulomb Island by Self-Aligned Process,” Appl. Phys. Lett. 71(3) (Jul. 21, 1997), pp. 353-355, all by A. Nakajima et al. TheseFETs 60 employ feature sizes as small as 30 nanometers and require much closer alignment between elements than 30 nanometers. Formation of such small feature sizes using electron beam lithography does not presently lend itself to mass production. - These
FETs 60 employ a floatingisland 26 between thegate 62 and thechannel 66 to modulate conductivity in thechannel 66. In theseFETs 60, theisland 26 spans the width of thechannel 66. - It will be appreciated that other techniques for forming the
islands 26 may be employed. For example, shallow implantation of relatively high doses (e.g., ca. 5-50×1014/cm2) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (September 1996), pp. 1553-1558. Performance ofmemories using islands 26 formed from nanocrystals in proximity to thechannel 66 is discussed in “Single Charge and Confinement Effects in Nano-Crystal Memories” by S. Tiwari et al., Appl. Phys. Lett. 69(9) (Aug. 26, 1996), pp. 1232-1234. - Prior art FETs may provide
multiple islands 26 between thegate 62 and thechannel 66, and are capable of storingmultiple electrons 32. As a result, these FETs are analogous to conventional flash memories and are capable of multilevel signal storage and readout. An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095. -
FETs 60 including one ormore islands 26 suitable for capture ofelectrons 32 thus are able to provide measurable and repeatable changes in their electrical properties in response to capture of the electron orelectrons 32 on at least oneisland 26. Moreover, theseFETs 60 provide these changes in a convergent manner, i.e., the changes may be produced by storage of asingle electron 32 and storage of thatsingle electron 32 can inhibit storage of anotherelectron 32. In this way, some of theFETs 60 avoid some problems due to number fluctuations in the population ofelectrons 32 that could otherwise be troublesome forFETs 60 having very small populations ofelectrons 32. - Additionally, the
energy barriers single electron device 20 and theFETs 60 to store trappedelectrons 32 for significant periods of time, even in the absence of externally applied electrical power (e.g.,voltage sources 34, 64). As a result, a nonvolatile memory function is provided by thesedevices 20 andFETs 60. - While
single electron devices 20 andFETs 60 show great promise as memory cells for very high density memory arrays, fabrication difficulties prevent mass production of memory arrays using thesedevices islands 26 and the thickness of the surrounding dielectric materials forming thegaps devices - There is therefore a need for a method for fabricating single electron devices that is robust and that provides reproducible single-electron device characteristics.
- In one aspect, the present invention includes a memory cell having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of conductive material having a maximum dimension of three nanometers and surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, electrons may tunnel into or out of the islands with the assistance of externally-applied fields. The capacitance of the islands is small enough that single electrons stored on the islands provide consistent, externally observable changes in the memory cells.
- In other aspects, the present invention provides methods for reading data from, writing data to and erasing memory cells capable of storing data by the presence or absence of a single electron in an island of conductive material contained in the memory cells. The reading, writing and erasing operations may be accompanied by a verification process that compensates for stored charge, trap generation and the like that otherwise might obscure desired data.
- FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device, in accordance with the prior art.
- FIG. 1B is a simplified potential energy diagram for the device of FIG. 1A, in accordance with the prior art.
- FIG. 1C is a simplified potential energy diagram, illustrating the potential V setting the Fermi level at the left side of the Figure equal to the lowest allowed state of the potential well of FIG. 1B, in accordance with the prior art.
- FIG. 1D is a simplified graph of an I-V characteristic for the device of FIG. 1A, in accordance with the prior art.
- FIG. 2 is a simplified schematic illustration of a typical field effect transistor that includes the island of FIG. 1A for storing one or more electrons, in accordance with the prior art.
- FIG. 3A is a simplified plan view of a memory device including memory cells employing single electron memory devices having electrical characteristics similar to those of the devices of FIGS. 1 and 2, in accordance with embodiments of the present invention.
- FIG. 3B is a simplified isometric view of a single electron resistor memory device in the memory cell of FIG. 3A, in accordance with embodiments of the present invention.
- FIG. 3C is a simplified cross-sectional view of the device of FIG. 3B, showing islands included within the semiconductor material of the body, in accordance with embodiments of the present invention.
- FIG. 4 is a simplified flow chart of a process for reading the memory cell of FIGS.3A-C, in accordance with embodiments of the present invention.
- FIGS. 5 and 6 are simplified flow charts for processes for writing data to the memory cell of FIGS.3A-C and for erasing data stored in the memory cell, respectively, in accordance with embodiments of the present invention.
- FIG. 7 is a graph representing storage and erase time estimates for various energy barriers, in accordance with embodiments of the present invention.
- FIG. 8 is a simplified flowchart of a process for forming the islands of FIGS. 1 and 2, in accordance with embodiments of the present invention.
- FIGS. 9A and 9B are simplified cross-sectional views of the islands as they are being formed using the process of FIG. 8, in accordance with embodiments of the present invention.
- FIG. 10 is a simplified block diagram of a computer system including the memory device of FIGS.3A-C, in accordance with embodiments of the present invention.
- FIG. 3A is a simplified plan view of a
memory device 72 including amemory cell 73 having electrical characteristics similar to those of thedevices memory device 72 includes acolumn addressing circuit 74 coupled to a plurality ofcolumn address lines 75, and arow addressing circuit 76 coupled to a plurality of row address lines 77. Thememory cell 73 is located at an intersection of acolumn address line 75 and arow address line 77 and is addressed by activation of thecolumn 75 androw 77 address lines coupled to thememory cell 73, as is discussed below in more detail. - FIG. 3B is a simplified isometric view of a single electron
resistor memory device 80 in thememory cell 73 of FIG. 3A, in accordance with embodiments of the present invention. Thedevice 80 includes abody 82 having first 84 and second 86 electrodes formed at opposing ends. In one embodiment, the first 84 and second 86 electrodes form low resistance contacts to thebody 82. In one embodiment, thebody 82 includes n-type semiconductor material having a donor concentration of about 1015/cm3 or less and the first 84 and second 86 electrodes are N+ ohmic contacts to thebody 82. Thefirst electrode 84 is coupled to arow address line 77 and thesecond electrode 86 is coupled to acolumn address line 75. - The
device 80 also optionally includes one ormore gates lines device 80. In one embodiment, thegates - FIG. 3C is a simplified cross-sectional view of the
device 80 of FIG. 3B, showing islands 26 (see FIGS. 1 and 2) included within thesemiconductor material 98 forming thebody 82 of thedevice 80, in accordance with embodiments of the present invention. Eachisland 26 is surrounded by a dielectric 100 that provides theenergy barriers gaps island 26 fromother islands 26 and from thesemiconductor material 98. - The
device 80 of FIGS. 3A-C has a first state exhibiting a first current-voltage characteristic when noelectrons 32 are stored on theislands 26 within thedevice 80. Thedevice 80 has a second state exhibiting a second current-voltage characteristic when one ormore electrons 32 are stored in one ormore islands 26 contained in thebody 82 of thedevice 80. In the second state, less current between thefirst electrode 84 and the second 86 electrode for a given voltage difference between the first 84 and second 86 electrodes than in the first state, and this difference may be detected by sensing circuitry (not illustrated) coupled to thecolumn 75 or therow 77 address lines. Processes for switching thedevice 80 between the first and second states by storage and removal ofelectrons 32 from the island orislands 26 in thebody 82 of thedevice 80 are explained in more detail below. - To store one or
more electrons 32 in thebody 82 of thedevice 80, thecolumn address line 75 is coupled to a first voltage (e.g., ground) and therow address line 77 is coupled to a second voltage (e.g., four volts) sufficient to cause single electrons 32 (FIG. 1) to tunnel into and to be stored on one or more of theislands 26 in thebody 82 of thedevice 80, as is explained below in more detail with reference to FIG. 5. As a result, thedevice 80 changes from the first state to the second state. - To erase information represented by one or more stored
electrons 32 stored on the island orislands 26 within thebody 82 of thedevice 80, therow 77 or column 75 (or both) address line is coupled to an electron sink (e.g., ground). Thebody 82 is depleted of mobile charge carriers by an externally-applied bias, which also tilts thebarriers electrons 32 stored in thepotential wells 40 of theislands 26 from theislands 26 into thebody 82. In one embodiment, a negative potential is applied to one ormore gate electrodes semiconductor material 98 forming thebody 82 of mobile charge carriers (i.e.,electrons 32 or holes) to allow any storedelectrons 32 to tunnel out of the island orislands 26.Electrons 32 tunneling out of theislands 26 are removed from thesemiconductor material 98 by electrical fields induced by the voltage applied to thegate electrodes device 80 is restored to the first state. - A change in a current I between the first84 and the second 86 electrode, corresponding to a difference ΔI in the current I between the first and second states, can be estimated as follows. The
body 82 of thedevice 80 has a cross-sectional area A, a length L between the first 84 and second 86 electrodes and a number nT ofelectrons 32 trapped on theislands 26. A conductivity a for thesemiconductor material 98, as could be measured between the first 84 and second 86 electrodes, is given by nqμA/L, where μ represents the electron mobility and n represents the number of mobile charge carriers (electrons 32) per cubic centimeter. Assuming that each of the nT trappedelectrons 32 results in one fewermobile electron 32 per cubic centimeter, the change in current ΔI through thedevice 80 may be estimated as ΔI=(nT/AL)(qμAV/L)=nTqμV/L2. A voltage V of one volt, a mobility μ of 600 cm2/(v-sec) and a length L of one micrometer corresponds to a decrease in current ΔI due to one storedelectron 32 of 10 nanoamperes. - In one embodiment, the
body 82 of thedevice 80 may have a length L of about one micrometer (10−4 cm) and have a cross-sectional area A of about 10−8 cm2. A free carrier concentration of 1015/cm3 or less allows thegates semiconductor material 98 with relatively low applied voltages. - FIG. 4 is a simplified flow chart of a
process 120 for reading thememory cell 73 of FIG. 3A, in accordance with embodiments of the present invention. Theprocess 120 begins in astep 122 by activating one of thecolumn address lines 75 and one of therow address lines 77 of FIGS. 3A-C to address one of thememory cells 73. In astep 124, a bias current IB or voltage VB is applied to the addressedmemory cell 73, as is discussed below in more detail. In astep 126, the addressedmemory cell 73 is coupled to a sensing circuit (not shown). In some embodiments, aquery task 128 then compares a measured response XM to a threshold XT to determine if a logical “1” or a logical “0” is stored in thememory cell 73 as is described below in more detail. - In one embodiment, when a bias current IB is supplied from a current source (not shown) to, for example, the
first electrode 84 of the addressedmemory cell 73, the measured response XM is a voltage, measured, for example, across the first 84 and second 86 electrodes. When thequery task 128 determines that the measured response XM exceeds the threshold XT, at least oneelectron 32 is stored in thememory cell 73 and thememory cell 73 is storing a first logical state. When thequery task 128 determines that the measured response XM does not exceed the threshold XT, noelectron 32 is stored in thememory cell 73 and thememory cell 73 is storing a second logical state. - Conversely, in another embodiment, when a bias voltage VB is supplied from a voltage source (not shown) to, for example, one or both of the
gates memory cell 73, the measured response XM is a current, measured, for example, at thefirst electrode 84. When thequery task 128 determines that the measured response XM exceeds the threshold XT, noelectron 32 is stored in thememory cell 73 and thememory cell 73 is in the second logical state. When thequery task 128 determines that the measured response XM does not exceed the threshold XT, at least oneelectron 32 is stored in thememory cell 73 and thememory cell 73 is in the first logical state. - When the
query task 128 determines that thememory cell 73 is in the first logical state, the comparison circuit indicates that thememory cell 73 is in the first logical state, e.g., that a logical “1” is stored in thememory cell 73, in astep 130. When thequery task 128 determines that thememory cell 73 is in the second logical state, the comparison circuit indicates that a logical “0” is stored in thememory cell 73 in astep 132. Theprocess 120 ends following either step 130 orstep 132. - In another embodiment, the
query task 128 discriminates between a plurality of different logical values or states that may be stored in thememory cell 73 by comparing the measured response XM to a plurality of thresholds XTi. An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095. An example of a circuit and method for programming, reading and erasing multiple single electron differences in theFETs 80 of FIGS. 3A-C is given in “Multi-State Flash Memory Cell and Method for Programming Single Electron Differences” by L. Forbes, U.S. Pat. No. 5,740,104. After thequery task 128 determines the correct logical value for the data stored in thememory cell 73, the data comparison circuit indicates the correct logical value in steps 130-132 and theprocess 120 ends. - FIGS. 5 and 6 are simplified flow charts for
processes memory cell 73 of FIG. 3A and for erasing data stored in thememory cell 73, respectively, in accordance with embodiments of the present invention. Theprocesses memory cell 73 to another, as is described in “Verify: Key to the Stable Single-Electron-Memory Operation” by T. Ishii et al. (1997 IEDM), pp. 171-174. - With reference now to FIG. 5, the
write process 140 begins in astep 142 by activating one of thecolumn address lines 75 and one of therow address lines 77 of FIGS. 3A-C to address one of thememory cells 73. In astep 144, a write pulse, which may be either a current IW or a voltage VW pulse, is applied to the addressedmemory cell 73. In some embodiments, thestep 144 is used to write a binary value to thememory cell 73. In other embodiments, thestep 144 is used to write one of a plurality of possible values or data entries to thememory cell 73 by injecting a controlled number ofelectrons 32 into theislands 26 of thememory cell 73. - In a
step 146, an index variable n, corresponding to a number of write cycles applied to this memory cell during thiswrite process 140, is incremented. In astep 148, thememory cell 73 is read by sampling a voltage or current associated with thememory cell 73, i.e., theprocess 120 of FIG. 4. Aquery task 150 then compares the read data to the data written to thememory cell 73 in thestep 144. - When the
query task 150 determines that the read data and the write data agree, theprocess 140 ends. When thequery task 150 determines that the read data and the write data do not agree, control passes to aquery task 152 to determine if a maximum number of cycles N has been reached (i.e., is n≧N?). The maximum number of cycles N is despite differences in programming time betweenmemory cells 73, without wasting excessive amounts of time in attempts to programdefective memory cells 73. When thequery task 152 determines that the maximum number of cycles N has not been reached, control passes to thestep 144, and steps 144-150 or 152 repeat. When thequery task 152 determines that the maximum number of cycles N has been reached, astep 154 records that a write failure has occurred and theprocess 140 ends. - In some embodiments, the record of a write failure that is generated in the
step 154 may be used to construct a conventional memory map describing addresses ofdefective memory cells 73. Memory maps are used in order to avoid writing data to, or attempting to write data to, or reading data from,memory cells 73 that are defective. In some embodiments, the record of a write failure that is generated in thestep 154 may be used to replacedefective memory cells 73 withmemory cells 73 that are known to be working properly, as is conventional in fabrication and repair of memory devices such as dynamic random access memories. - In the
step 144, where a write pulse is applied to thememory cell 73, a finite number ofelectrons 32 are injected into the island orislands 26. A probability of write failure is finite and nonzero because injection ofelectrons 32 into the potential wells 40 (FIG. 1C) is essentially stochastic. For example, a failure probability of 0.1% is unacceptable in modern memory devices. Additionally, characteristics of thememory cell 73 may change with time, due to generation of new trapping centers or by trapping of charge in or near thememory cell 73. - Reading data from the
memory cell 73 after a write pulse has been applied to the memory cell allows determination that a write failure has occurred. By making the write pulses IW or VW longer as n increases, the probability of trapping the desired number ofelectrons 32 increases substantially and may approach unity. In one embodiment, a width WW of the write pulses IW or VW depends geometrically on n, e.g., WW(n)∝2n, nε{I}. In another embodiment, the amplitude of the write pulses depends arithmetically on n, e.g., VW(n)∝VW(o)(1+n/M), nε{I}, where VW(o) represents an initial value and M represents a proportionality constant. - With reference now to FIG. 6, the erase
process 160 begins in astep 162 by activating one or more of thecolumn address lines 75 and one or more of therow address lines 77 of FIGS. 3A-C to address one or more of thememory cells 73. In one embodiment, thestep 162 selects a group ofmemory cells 73, which may be a subset of the memory cells on onememory device 72, may be all of thememory cells 73 on amemory device 72 or may includememory cells 73 from more than onememory device 72. In astep 164, an erase pulse, which may be either a current IE or voltage VE, is applied to the addressedmemory cell 73. In one embodiment, the erase pulse is applied to one or both of the erasegates electrodes step 166, an index variable n, corresponding to a number of erase cycles applied to thismemory cell 80 during this eraseprocess 160, is incremented. In astep 168, thememory cell 73 is read by sampling a voltage or current associated with thememory cell 73. Aquery task 170 then compares the read data to an expected value (e.g., corresponding to an absence of stored electrons 32) to determine if the contents of thememory cell 73 were erased in thestep 164. - When the
query task 170 determines that the contents of thememory cell 73 were erased, theprocess 160 ends. When thequery task 170 determines that the contents of thememory cell 73 were not erased, control passes to aquery task 172 to determine if a maximum number of cycles N has been reached (i.e., is n≧N?). As with thewrite process 140 of FIG. 5, N is chosen to balance differences in erase time from onememory cell 73 to anothermemory cell 73 without spending excessive time to erasedefective memory cells 73. When thequery task 172 determines that the maximum number of cycles N has not been reached, control passes back to thestep 164, and steps 164-170 or 172 repeat. In accordance with embodiments of the invention, the erase pulses VE may be varied with n as described above for the write pulses IW or VW in connection with theprocess 140 of FIG. 5. When thequery task 172 determines that the maximum number of cycles N has been reached, astep 174 records that an erase failure has occurred The process then 160 ends. - In one embodiment,
individual memory cells 73 are erased as needed for storage of new data. In another embodiment, all of thememory cells 73 in a group or in anentire memory device 72 are erased en masse, by addressing a group ofmemory cells 73 in thestep 162 and application of the erase pulses in thestep 164 to all of thememory cells 73 in the group or in thememory device 72 simultaneously. The steps 166-174 are then carried out for eachmemory cell 73 individually, with a step of addressing theindividual memory cells 73 being carried out prior to thestep 166 of incrementing the index variable n. In another embodiment, the memory cells are erased en masse, however, the steps 166-174 are carried out as steps 146-154 of the verifiedwrite process 140 of FIG. 5. - An advantage of en masse erasure is that the erase
process 160 is slow, typically requiring milliseconds. Erasure of theentire memory device 72 onememory cell 73 at a time takes much longer than erasure of theentire memory device 72 en masse, and this is more exaggerated as the number ofmemory cells 73 in thememory device 72 increases. - Several factors affect storage times τS, also known as latency, for
memory cells 73 incorporatingislands 26 for storage of one ormore electrons 32. In general, τS∝e(ΔE/kT)e(d/d o ), where ΔE represents the energy level difference between theenergy barriers island 26 and d/do represents the relative thickness of thegaps island 26 and the material forming thegaps gaps island 26 and then adding the electron charging energy q2/2C, i.e., ΔE=χISL−χINS+q2/2C. Representative values for electron affinities χ for several materials are summarized below in Table I. Measured or achieved electron affinities χ depend strongly on surface treatment and surface contamination and may vary from the values given in Table I.TABLE I Electron affinities χ for selected materials. χ (eV) Material Use 4.05 Si Islands 3.6/3.7* SiC Islands 1.4** C (diamond) Islands 0.9-4.05 Silicon oxycarbide (projected) Islands 0.9 SiO2 Gaps - FIG. 7 is a graph representing estimated
storage 176 and erase 178 time estimates for various island electron affinities χISL together with SiO2 barriers in accordance with embodiments of the present invention. The left ordinate corresponds to a logarithm ofretention time 176 at constant temperature, while the right ordinate corresponds to a logarithm of erasetime 178 at constant erase voltage. Erasetimes 178 for thememory device 72 are determined by the height of theenergy barrier island 26.Lower energy barriers lower energy barriers times 178 are desirable for some applications of electronically-erasable memories such as thememory device 72. -
Lower barriers shorter retention times 176 due to thermal activation ofelectrons 32 over or through theenergy barriers islands 26 may be formed from silicon, from microcrystalline diamond-like films of Si(1-x)Cx, with the composition ratio, x, ranging from 0.5 to one, or from silicon oxycarbide compounds, to provide electron affinities χ ranging between about 4.05 eV and 0.9 eV or less (see Table I), corresponding to energy barriers ΔE ranging from about 3.95 to about 0 eV (ignoring the charging voltage). By changing the composition of theislands 26 and the thickness of the surrounding insulator, and thus the height of theenergy barriers charge retention times 176 can be changed from seconds, characteristic of DRAMs, to years, characteristic of hard disk drives. As a result, thememory device 72 can either be made to emulate a DRAM or a hard disk drive by varying the composition of theislands 26. One device type can then perform all memory functions. - FIG. 7 illustrates that
storage 176 and erase 178 times vary exponentially with the height of theenergy barriers charge retention times 176 of millions of years at 85° C. because theenergy barriers times 178 in the millisecond range. The high electric fields required for erasure as a result of thelarge energy barriers device 72. Anisland 26 may be composed of a material of lower or adjusted energy barrier height, such as diamond-like compounds of silicon, carbon and oxygen, to provide desiredenergy barriers acceptable retention time 176 can be established, whether seconds or years, by varying the relative concentrations of Si, C and O, thereby varying the electron affinity χ for theislands 26. This then determines the height of theenergy barriers time 178 for a particular erase voltage. - FIG. 7 shows the concepts involved using rough order-of-magnitude estimates of the variations of storage and erasure times with barrier height. The same device structure can be used either as replacements for DRAMS or as replacements for hard disk drives. Only the composition of the
island 26 needs to be changed in order to change the retention time and the erasure characteristics. This may be done on one integrated circuit so that radically different types of memory functions are realized on one integrated circuit. - FIG. 8 is a simplified flowchart of a
process 180 for forming theislands 26 of FIGS. 1 and 2, and FIGS. 9A-9E are simplified cross-sectional views of theislands 26 as they are being formed using theprocess 180 of FIG. 8, in accordance with embodiments of the present invention. The process 180 (FIG. 8) begins in astep 182 with formation of voids or pores 202 (FIG. 9A) in a suitable silicon substrate or layer 98 (FIGS. 3C and 9A-9E). In one embodiment, the voids orpores 202 are formed by processes similar to those described in “Formation Mechanism of Porous Silicon Layers Obtained by Anodization of Monocrystalline n-type Silicon in HF Solutions” by V. Dubin, Surface Science 274 (1992), pp. 82-92. In one embodiment, a current density of between 5 and 40 mA/cm2 is employed together with 12-24% HF. In general, increasing ND (silicon donor concentration), HF concentration or anodization current density provideslarger pores 202 and may lead toreentrant pores 202.Pores 202 are readily and uniformly formed to have the desired characteristics when using simple and easily controlled processes. - In a
step 184, thesilicon 98 including interiors of thepores 202 is oxidized to provide a thin oxide layer 100 (FIG. 9B). In one embodiment, thesilicon 98 is oxidized to provide theoxide layer 100 to have a thickness of between 2.5 and ten nanometers. Theoxidation step 184 may be carried out using conventional oxidation techniques. In one embodiment, an inductively-coupled oxygen-argon mixed plasma is employed for oxidizing thesilicon 98, as described in “Low-Temperature Si Oxidation Using Inductively Coupled Oxygen-Argon Mixed Plasma” by M. Tabakomori et al., Jap. Jour. Appl. Phys.,Part 1, Vol. 36, No. 9A (September 1997), pp. 5409-5415. In another embodiment, electron cyclotron resonance nitrous oxide plasma is employed for oxidizing thesilicon 98, as described in “Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and its Application to Polycrystalline Silicon Thin Film Transistors,” J. Lee et al., Jour. Electrochem. Soc., Vol. 144, No. 9 (September 1997), pp. 3283-3287 and “Highly Reliable Polysilicon Oxide Grown by Electron Cyclotron Resonance Nitrous Oxide Plasma” by N. Lee et al., IEEE El. Dev. Lett., Vol. 18, No. 10 (October 1997), pp. 486-488. - In a
step 186, a conductive material 204 (FIG. 9C) is formed over the surface of thesilicon 98 and in thepores 202. In some embodiments,semiconductor material 204 is deposited over the surface of thesilicon 98 and in thepores 202. - Examples of
materials 204 that may be used in accordance with embodiments of the invention include the materials listed in Table I above. Thematerial 204 within thepores 202 forms theislands 26 and is chosen to have an electron affinity χ that, together with the thickness d/do and the electron affinity χ of theinsulator 100 filling thegaps - In some embodiments, silicon oxycarbide is employed as the
material 204 in thestep 186. A process for forming thin microcrystalline films of silicon oxycarbide is described in “transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques” by R. Martins et al., Solar Energy Materials and Solar Cells 41/42 (1996), pp. 493-517. A diluent/reaction gas (e.g., hydrogen) is introduced directly into a region where plasma ignition takes place. The mixed gases containing the species to be deposited are introduced close to the region where the growth process takes place, which is often a substrate heater. A bias grid is located between the plasma ignition and the growth regions, spatially separating the plasma and growth regions. - Deposition parameters for producing doped microcrystalline Six:Cy:Oz:H films may be defined by determining the hydrogen dilution rate and power density that lead to microcrystallization of the grown
film 204. The power density is typically less than 150 milliWatts per cm3 for hydrogen dilution rates of 90%+, when the substrate temperature is about 250° C. and the gas flow is about 150 sccm. The composition of the films may then be varied by changing the partial pressure of oxygen during film growth to provide the desired characteristics. - In some embodiments, SiC is employed as the
material 204 in thestep 186. SiC films may be fabricated by chemical vapor deposition, sputtering, laser ablation, evaporation, molecular beam epitaxy or ion implantation. Vacuum annealing of silicon substrates is another method that may be used to provide SiC layers having thicknesses ranging from 20 to 30 nanometers, as described in “Localized Epitaxial Growth of Hexagonal and Cubic SiC Films on Si by Vacuum Annealing” by Luo et al., Appl. Phys. Lett. 69(7) (1996), pp. 916-918. Prior to vacuum annealing, the substrates are degreased with acetone and isopropyl alcohol in an ultrasonic bath for fifteen minutes, followed by cleaning in a solution of H2SO4:H2O2 (3:1) for fifteen minutes. A five minute rinse in deionized water then precedes etching with a 5% HF solution. The substrates are blown dry using dry nitrogen and placed in a vacuum chamber. The chamber is pumped to a base pressure of 1-2×10−6 Torr. The substrate is heated to 750 to 800° C. for half an hour to grow the microcrystalline SiC film. - In some embodiments, silicon is employed as the
material 204 in thestep 186. Methods for depositing high quality polycrystalline films of silicon on silicon dioxide substrates are given in “Growth of Polycrystalline Silicon at low Temperature on Hydrogenated Microcrystalline Silicon (μc-Si:H) Seed Layer” by Parks et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp. 403-408, “Novel Plasma Control Method in PECVD for Preparing Microcrystalline Silicon” by Nishimiya et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp. 397-401 and “Low Temperature (450° C.) Poly-Si Thin Film Deposition on SiO2 and Glass Using a Microcrystalline-Si Seed Layer” by D. M. Wolfe et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 472 (1997), pp. 427-432. A process providing grain sizes of about 4 nm is described in “Amorphous and Microcrystalline Silicon Deposited by Low-Power Electron-Cyclotron Resonance Plasma-Enhanced Chemical-Vapor Deposition” by J. P. Conde et al., Jap. Jour. Of Appl. Phys., Part I, Vol. 36, No. 1A (June 1997), pp. 38-49. Deposition conditions favoring small grain sizes for microcrystalline silicon include high hydrogen dilution, low temperature, low deposition pressure and low source-to-substrate separation. - In a
step 188, the portion of thematerials 204 deposited in thestep 186 that are located on the silicon surface are effectively removed. In one embodiment, in thestep 188, the portion of thematerials 204 deposited in thestep 186 that are located on the surface of thesilicon body 98 are oxidized to provide a structure as illustrated in FIG. 9D. Thestep 188 proceeds until thematerial 204 on the surface is completely oxidized but does not proceed for long enough to oxidize all of the material 204 in thepores 202. As a result,isolated islands 26 ofsemiconductor material 204 surrounded bysilicon dioxide 100 are formed in thepores 202 in thesingle crystal silicon 98 forming thebody 82 of the device 80 (FIGS. 3A-C). - Significantly, the materials listed in Table I for use in the
islands 26 can be oxidized to formsilicon dioxide 208 or to form a volatile gas (CO2). As a result, theislands 26 may be isolated from each other by a simple oxidation process that may not require a photolithographic step. - In a
step 190, an optional gate oxide 210 (FIG. 9E) is formed on the silicon surface and on top of the material 204 deposited in thepores 202. In astep 192, the gate oxide is patterned using conventional techniques. Theprocess 180 then ends and further fabrication is carried out using conventional processing. An advantage of theprocess 180 is that it does not rely on very-fine-line lithography for formation of theislands 26. - Approaches using such fine line lithography are described in “A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel” by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and “Fabrication And Characterization of Room Temperature Silicon Single Electron Memory” by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843. These devices were fabricated using e-beam lithography and incorporate features having widths as narrow as 25 nanometers. Similarly, devices described in “Room Temperature Operation of Si Single-Electron-Memory with Self-Aligned Floating Dot Gate” (IEDM 1996), pp. 952-954, Appl. Phys. Lett. 70(13) (Mar. 31, 1997), pp. 1742-1744 and “Si Single Electron Tunneling Transistor With Nanoscale Floating Dot Stacked on a Coulomb Island by Self-Aligned Process,” Appl. Phys. Lett. 71(3) (Jul. 21, 1997), pp. 353-355, all by A. Nakajima et al., employ feature sizes as small as 30 nanometers and require much closer alignment between elements than 30 nanometers. Formation of such small feature sizes using electron beam lithography does not presently lend itself to mass production.
- It will be appreciated that other techniques for forming the islands26 (FIG. 3C) may be employed. For example, shallow implantation of relatively high doses (e.g., ca. 5-50×1014/cm2) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (September 1996), pp. 1553-1558. Performance of memories using nanocrystals in proximity to a channel is discussed in “Single Charge and Confinement Effects in Nano-Crystal Memories” by S. Tiwari et al., Appl. Phys. Lett. 69(9) (Aug. 26, 1996), pp. 1232-1234.
- FIG. 10 is a simplified block diagram of a portion of a
computer system 220 including thememory device 80 of FIGS. 3A-C, in accordance with embodiments of the present invention. Thecomputer system 220 includes acentral processing unit 222 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. Thecentral processing unit 222 is coupled via abus 224 to amemory 226, auser input interface 228, such as a keyboard or a mouse, and adisplay 230. Thememory 226 may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and read-write memory for temporary storage of data. Theprocessor 222 operates on data from thememory 226 in response to input data from theuser input interface 228 and displays results on thedisplay 230. Theprocessor 222 also stores data in the read-write portion of thememory 226. The integrated circuit 72 (FIG. 3A) is particularly useful when it is a memory integrated circuit in the read-write memory portion of thememory 226, because it may then allow thememory 226 to provide increased information storage capacity and/or density. - The embodiments of the present invention provide a compact, sensitive memory cell and permit very high storage capacity memories to be fabricated. Additionally, the inventive memory cell does not require high resolution lithography for fabrication of the islands that store charge.
- It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.
Claims (61)
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US09/943,726 US6452839B1 (en) | 1998-08-27 | 2001-08-29 | Method for erasing data from a single electron resistor memory |
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US09/943,726 Expired - Lifetime US6452839B1 (en) | 1998-08-27 | 2001-08-29 | Method for erasing data from a single electron resistor memory |
US09/944,258 Expired - Lifetime US6452831B2 (en) | 1998-08-27 | 2001-08-29 | Single electron resistor memory device and method |
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US10/123,580 Expired - Lifetime US6544846B2 (en) | 1998-08-27 | 2002-04-15 | Method of manufacturing a single electron resistor memory device |
US10/123,579 Expired - Lifetime US6607956B2 (en) | 1998-08-27 | 2002-04-15 | Method of manufacturing a single electron resistor memory device |
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Cited By (6)
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US6444546B1 (en) * | 1999-11-25 | 2002-09-03 | Electronics And Telecommunications Research Institute | Single electron device using ultra-thin metal film and method for fabricating the same |
US20080130356A1 (en) * | 2004-07-16 | 2008-06-05 | The University Of Manchester | Memory Device |
US7715229B2 (en) * | 2004-07-16 | 2010-05-11 | Nano Eprint Limited | Memory device |
US20080286082A1 (en) * | 2007-05-15 | 2008-11-20 | Sandisk Il Ltd. | Methods and systems for interrupted counting of items in countainers |
US8204169B2 (en) | 2007-05-15 | 2012-06-19 | Sandisk Il Ltd. | Methods and systems for interrupted counting of items in containers |
US8638902B2 (en) | 2007-05-15 | 2014-01-28 | Sandisk Il Ltd. | Methods for interrupted counting of particles in cells |
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US6607956B2 (en) | 2003-08-19 |
US20020021589A1 (en) | 2002-02-21 |
US6514820B2 (en) | 2003-02-04 |
US20020018373A1 (en) | 2002-02-14 |
US6141260A (en) | 2000-10-31 |
US6407426B1 (en) | 2002-06-18 |
US20020151173A1 (en) | 2002-10-17 |
US6452831B2 (en) | 2002-09-17 |
US6544846B2 (en) | 2003-04-08 |
US6452839B1 (en) | 2002-09-17 |
US20020151172A1 (en) | 2002-10-17 |
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