US20020022323A1 - Non-volatile semiconductor memory device and method of manufacturing the same - Google Patents
Non-volatile semiconductor memory device and method of manufacturing the same Download PDFInfo
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- US20020022323A1 US20020022323A1 US09/272,243 US27224399A US2002022323A1 US 20020022323 A1 US20020022323 A1 US 20020022323A1 US 27224399 A US27224399 A US 27224399A US 2002022323 A1 US2002022323 A1 US 2002022323A1
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- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- the present invention relates to a non-volatile semiconductor memory device for storing information by accumulation of an electric charge and a method of manufacturing thereof. More specifically, the present invention relates to a non-volatile semiconductor memory device in which a memory element is selectively activated by a field effect transistor and a method of manufacturing thereof.
- a flash memory As a non-volatile semiconductor memory device having memory elements provided with floating gates and control gates, a flash memory can be mentioned as an example.
- a variety of designs are available for flash memories, one of which is a device in which a memory element is selectively activated by a field effect transistor.
- a flash memory with such a configuration has been disclosed, for example, in Japanese Patent Application Laid-Open No. 6-275847. In the following, a method of manufacturing the flash memory disclosed in the Japanese Patent Application Laid-Open No. 6-275847 is described with reference to FIGS. 23 to 31 .
- a silicon oxide layer 202 as a tunnel oxide layer is grown. and then a polysilicon layer 204 as a floating gate is formed. Part of the polysilicon layer 204 that is positioned over an access transistor formation region 232 is selectively etched as shown in FIG. 24. and remaining part of the polysilicon layer 204 positioned over a memory element formation region 234 is left. This remaining part of the polysilicon layer 204 in hereinafter referred to as a polysilicon layer 204 a .
- an ONO-layer 206 is formed on the polysilicon layer 204 a . and a silicon oxide layer 208 as a gate oxide layer is formed over the access transistor formation region 232 . Subsequently, a polysilicon layer 210 is formed on the ONO-layer 206 and the silicon oxide layer 208 .
- a resist 212 is prepared on the polysilicon layer 210 which is then selectively etched by using the resist 212 as a mask, thereby forming a gate electrode 214 over the access transistor formation region 232 while leaving part of the polysilicon layer 210 that is positioned over the memory element formation region 234 .
- the remaining part of the polysilicon layer 210 over the memory element formation region 234 is hereinafter referred to as a polysilicon layer 210 a .
- This etching exposes the silicon oxide layer 208 on a principal surface 236 of the semiconductor substrate 200 , in the area between the gate electrode 214 and a floating gate to be formed in a later step.
- the resist 212 is removed and a resist 216 is prepared over the memory element formation region 234 and the access transistor formation region 232 .
- the resist 216 is patterned so that it provides a mask for forming a control gate.
- the resist 216 is patterned so that it covers the gate electrode 214 , while at the same time its edge 216 a does not overlap the polysilicon layers 204 a and 210 a
- the gate electrode 214 has to be covered by resist 216 because the gate electrode 214 is formed of a material identical to that of the control gate and the floating gate, i.e. polysilicon, and therefore has to be protected from being etched away during the etching step to form the control gate and the floating gate.
- the patterning is provided in such a way that the edge 216 a does not overlap the polysilicon layers 204 a and 210 a because when the polysilicon layers 204 a and 210 a are etched later to form the control gate and the floating gate, unnecessary polysilicon layers 204 a and 210 a are left on the principal surface of the semiconductor substrate 200 if the edge 216 a overlaps the polysilicon layers 204 a and 210 a . Consequently, the resist 216 is patterned while being the silicon oxide layer 208 exposed on a principal surface 236 of the semiconductor substrate 200 , in the area between the gate electrode 214 and a floating gate to be formed in a later step.
- the polysilicon layer 210 a is selectively etched by using the resist 216 as a mask to forma control gate 218 .
- the ONO-layer 206 is then selectively etched by using the resist 216 as a mask, as shown in FIG. 28. This etching removes the exposed portion of the silicon oxide layer 208 and exposes the principal surface 236 in the area between the gate electrode 214 and a floating gate to be formed in a later step.
- the polysilicon layer 204 a is selectively etched by using the resist 216 as a mask, thereby forming a floating gate 220 . Since the principal surface 236 is exposed. the principal surface 236 is also etched to unavoidably form a groove section 222 on the principal surface 236 . Subsequently, an ion implantation is provided on the principal surface of the semiconductor substrate 200 by using the resist 216 as a mask. thereby forming a source/drain 224 in the memory element formation region 234 as well as an impurity region 226 electrically connected to the source/drain 224 , in the groove section 222 .
- a silicon oxide layer 228 is grown on the principal surface of the semiconductor substrate 200 as shown in FIG. 30. followed by the formation of a contact hole 238 on the silicon oxide layer 228 . The that the source/drain 224 is exposed. As shown in FIG. 31, an aluminum wiring 230 is then provided on the silicon oxide layer 228 . The aluminum wiring 230 is also formed on the contact hole 238 and is electrically connected to the source/drain 224 .
- a memory element 242 is provided with the control gate 218 . the floating gate 220 , and the source/drain 224 , whereas an access transistor 244 is provided with the gate electrode 214 and the source/drain 240 .
- control gate 219 and the gate electrode 214 have conventionally been prepared in separate steps. Consequently, there is a need to allow for a margin for aligning a mask for forming the control gate 218 and a mask for forming the gate electrode 214 , which has caused an obstacle for reducing the space between the control gate 218 and the gate electrode 214 .
- an object of the present invention is to provide a non-volatile semiconductor memory device which can reduce the space between a control gate and a gate electrode and a method of manufacturing thereof.
- a method of manufacturing a non-volatile semiconductor memory device that comprises:
- a semiconductor substrate having a principal surface including a first region and a second region
- At least one memory element including a floating gate formed on the first region and a control gate formed on the floating gate;
- At least one access gate transistor for selectively activating the memory element comprising a gate electrode formed on the second region.
- This method comprises the steps of:
- control gate and the gate electrode are simultaneously formed, there is no need to allow for the margin for aligning the masks for forming the control gate and the gate electrode. Consequently, the present invention makes it possible to reduce the space between the control gate and the gate electrode.
- the control gate and the gate electrode can be simultaneously formed because the present invention allows the formation of the floating gate by using the masking layer formed on the control gate as a mask. Therefore, in the step of forming the first resist to cover the gate electrode, there is no need to form the first resist on the second conductive layer on the first region.
- the control gate and the floating gate have been formed by selectively etching the second and the first conductive layers by using the first resist as a mask.
- the serial steps from forming the masking layer up to simultaneously forming the control gate and gate electrode may comprise the steps of: forming a second resist on the masking layer; and selectively etching the masking layer and the second conductive layer by using the second resist as a mask to form the control gate and gate electrode simultaneously.
- the serial steps from forming the masking layer up to simultaneously forming the control gate and gate electrode may comprise the steps of; forming a third resist on the masking layer: selectively etching the masking layer by using the third resist as a mask; and selectively etching the second conductive layer by using the masking layer as a mask to form the control gate and gate electrode simultaneously.
- the masking layer may comprise an insulation layer.
- the masking layer also may comprise a silicon oxide layer.
- the masking layer may have a thickness from 200 to 300 nm.
- the non-volatile semiconductor memory device may be provided with a plurality of the memory elements and a plurality of the access gate transistors, each of the access gate transistors selectively activating only one of the memory elements.
- a non-volatile semiconductor memory device for storing information through the accumulation of an electric charge, comprising:
- a semiconductor substrate having a principal surface comprising a first region and a second region
- At least one memory element comprising a floating gate formed in the first region and a control gate formed on the floating gate;
- At least one access gate transistor comprising a gate electrode formed on the second region for selectively activating the memory element
- a first layer that is located on the control gate and has the same width as the control gate and a different etching rate from the floating gate;
- a second layer that is located on the gate electrode and has the same width as the gate electrode and the same composition as the first layer.
- the first layer may be smaller than the second layer in thickness.
- the memory element may comprise a first source/drain formed in the first region, and a second source/drain that is formed in the first region apart from the first source/drain, the floating gate and control gate being located between the first source/drain and second source/drain;
- the access gate transistor may comprise a third source/drain which is formed in the second region and a fourth source/drain that is formed in the second region apart from the third source/drain, the gate electrode being located between the third source/drain and fourth source/drain;
- a groove section may be unavoidably formed on the principal surface in the area between the floating gate and gate electrode; and an impurity region for electrically connecting the second source/drain to the third source/drain may be formed in the semiconductor substrate to cover the groove section.
- the impurity concentration of the impurity region may be higher than the impurity concentration of each of the first source/drain and fourth source/drain.
- Each of the first and second layers may comprise an insulation layer.
- Bach of the first and second layers may comprise a silicon oxide layer.
- the first layer may be 80 to 200 nm in thickness
- the second layer may be 200 to 300 nm in thickness.
- the non-volatile semiconductor memory device may be provided with a plurality of the memory elements and a plurality of the access transistors, each of the access gate transistors selectively activating only one of the memory elements.
- FIG. 1 is a cross-sectional view of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 2 is a partial plan view of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device Of the present invention.
- FIG. 3 is a schematic diagram of a memory cell of the flash memory manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 4 is a schematic cross-sectional view of a memory cell of the flash memory manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 5 is a schematic diagram of a memory cell array of the flash memories manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 6 is a partial cross-sectional view of the device to illustrate the first step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 7 is a partial cross-sectional view of the device to illustrate the second step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 8 is a partial cross-sectional view of the device to illustrate the third step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 9 is a partial cross-sectional view of the device to illustrate the fourth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 10 is a partial cross-sectional view of the device to illustrate the fifth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 11 is a partial cross-sectional view of the device to illustrate the sixth stop of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 12 is a partial cross-sectional view of the device to illustrate the seventh stop of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 13 is a partial cross-sectional view of the device to illustrate the eighth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 14 is a partial cross-sectional view of the device to illustrate the ninth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 15 is a partial cross-sectional view of the device to illustrate the tenth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 16 is a partial cross-sectional view of the device to illustrate the first step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 17 is a partial cross-sectional view of the device to illustrate the second step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 10 is a partial cross-sectional view of the device to illustrate the third step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 19 is a partial cross-sectional view of the device to illustrate the fourth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 20 is a partial cross-sectional view of the device to illustrate the fifth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 21 is a partial cross-sectional view of the device to illustrate the sixth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 22 is a partial cross-sectional view of the device to illustrate the seventh step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 23 is a partial cross-sectional view of the device to illustrate the first step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 24 is a partial cross-sectional view of the device to illustrate the second step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 25 is a partial cross-sectional view of the device to illustrate the third step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 26 is a partial cross-sectional view of the device to illustrate the fourth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 27 is a partial cross-sectional view of the device to illustrate the fifth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 28 is a partial cross-sectional view of the device to illustrate the sixth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 29 is a partial cross-sectional view of the device to illustrate the seventh step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 30 is a partial cross-sectional view of the device to illustrate the eighth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 31 is a partial cross-sectional view of the device to illustrate the ninth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- each of the embodiment examples described below is an application of the present invention to a non-volatile semiconductor memory device provided with a plurality of memory elements and a plurality of access transistors for selectively activating the memory elements, in such a manner that each access transistor selectively activates only one memory element.
- the present invention is not limited to those described below but can be equally well applied to non-volatile semiconductor memory devices wherein memory elements are selectively activated by access transistors of types such as NOR, NAND, or DINOR, for example.
- FIG. 3 is a schematic view of a memory cell 400 of a flash memory of the above type.
- the memory cell 400 has an access transistor 401 and a memory transistor 402 which is a memory element.
- the access transistor 401 has a gate 401 A and the memory transistor 402 has a floating gate 403 and a control gate 404 .
- the access transistor 401 is an N-channel MOSFET with a threshold voltage of approximately 0.7 V.
- Programming of the memory cell 400 by channel hot electron is achieved by simultaneously applying a high positive programming voltage V pp .
- V pp a high positive programming voltage
- 5 to 12 V may be applied to the gate 401 A of the access transistor 401 , and 12 V to the control gate 404 of the memory transistor 402 , while holding a source 408 of the memory transistor 402 at a ground potential V gp , and applying a positive programming pulse to a drain 406 of the access transistor 401 .
- a programming pulse of about 5 V can be applied for 100 microseconds, for example.
- a drain 407 of the memory transistor 402 (which is also the source of the access transistor 401 ) has a high-concentration doping region 510 to the substrate.
- This ion implantation to the drain enhances the electric field in a channel region 511 close to the drain 407 . thereby accelerating the electrons and generating a distribution of high energy electrons which are energetic enough to overcome the potential energy barrier and to transfer through a thin tunnel layer and into the floating gate 403 (e.g. for hot electron injection).
- This ion implantation highly doping the drain 407 can multiply the speed of programming.
- the access transistor 401 uses a smaller fraction of the applied drain pulse voltage, since the width of the access transistor 401 is typically within the range of 1.0 to 5.0 ⁇ m, compared with the 0.25 to 1.5 ⁇ m of the memory transistor 402 .
- Erasure of the memory cell 400 is achieved by applying 5 V to the source 408 of the memory transistor 402 while holding the control gate 404 at ⁇ 7 V.
- a high electric field is generated in a tunnel oxide layer 405 (shown in Pig. 4 ), thereby allowing the electrons collected in the floating gate 403 to overcome the potential energy barrier and tunnel (by Povler-Nordheim tunneling, for example) through the tunnel oxide layer 405 to the source 408 of the memory transistor 402 .
- a voltage of 5 to 12 V is applied to the gate 401 A and the drain 406 is left floating.
- the source 408 of the memory transistor 402 is also formed by high-concentration doping 512 of the substrate.
- This high-concentration doping increases the dielectric breakdown of the junction, thereby significantly accelerating the transfer of electrons from the floating gate during the erasure.
- the memory transistor 402 erases during the erasure operation to the point at which its threshold voltage is negative.
- the control gate 404 cannot be turned off by the control gate 404 .
- the access transistor 401 prevents this overerasure from affecting cell performance. More specifically, the access transistor 401 is not controlled by the state of the floating gate. so the threshold voltage of the access transistor 401 remains at approximately 0.7 V.
- Various operating conditions can be set, other than these described above for programming and erasure operations.
- the conditions described below can also be set, for example, when programming and erasure are both provided by Fowler-Nordheim tunneling.
- Programming conditions can be: ⁇ 8 V at the control gate, the source in floating, 8 V at the drain, and 8 V at the gate of the access transistor.
- Erasure conditions can be: 8 V at the control gate, ⁇ 8 V at the source, the drain in floating, and 8 V at the gate of the access transistor.
- FIG. 5 A schematic view of a memory array 600 which comprises memory cells 400 A to 400 D is shown in FIG. 5. Each of these memory cells is identical to the memory cell 400 .
- the drains 406 of the access transistors 401 of the cells 400 A and 400 B are coupled to a metal drain bit line 631 , and the sources 408 of the memory transistors 402 of these cells 400 A and 400 B are coupled to a metal source bit line 630 .
- the gates 401 A of the access transistors 401 of the memory cells 400 A and 400 D are coupled to a word line 520 , and the control gates 404 of the memory cells 400 A and 400 D are coupled to a control line 521
- the reading of the memory cell 400 A is accomplished by applying a standard voltage V cc (usually 5 V) to the gate 401 A via the word line 520 as well as to the control gate 404 via the control line 521 , while simultaneously sensing the read current flowing through the memory cell 400 A by a conventional sense amplifier (not shown in the figure) that is connected to the drain bit line 631 . If the memory cell 400 A has been erased (i.e., if there is a zero charge or net positive charge on the floating gate 403 ), both the access transistor 401 and the memory transistor 402 are turned on, allowing a current to flow through the memory cell 400 A which can be sensed by the sense amplifier.
- V cc usually 5 V
- the threshold voltage of the memory transistor 402 rises above the supply voltage V cc , preventing current from flowing through the memory cell 400 A.
- the sense amplifier which receives the voltage from the drain bit line generates a feedback voltage to the source bit line 630 , which increases the voltage on the source bit line 630 during a read operation. This slows down the voltage drop on the drain bit line 631 .
- the present invention significantly reduces the time required for the bit lines to recover their original state so that they can perform sensing during the next logic state cycle, in comparison with conventional memory cell arrays.
- the main limitation to scaling of the memory transistor 402 is the punch-through requirement.
- Capacitive coupling between the drain 407 and the floating gate 403 typically causes the memory transistor 402 to be turned on by the coupling to the drain 407 .
- This capacitive coupling limits the scalability of the channel length of the channel region 511 (see FIG. 4) and thus limits the improvement in programming speed that is necessary for the 5-volt programming capability. More specifically. capacitive coupling from the drain 407 to the floating gate 403 degrades the punch-through margin of the memory transistor 402 , and limits the capability of the memory transistor 402 to handle the drain voltage.
- the capacitive coupling effect does not scale with the gate line width of the memory transistor 402 because of the strong effect of fringing capacitance.
- the memory cell of the present invention solves this scaling problem by the inclusion of the access transistor 401 within the memory cell 400 . Since this memory cell eliminates punch through of the memory transistor 402 in programming mode, the channel length of the channel region 511 can be scaled. This scalability means that the channel length can be reduced, which significantly increases the programming speed of the memory cell in comparison with the prior art. Moreover, the doping to the drain 407 enables the memory cell 400 to achieve a full 5 -volt programming capability.
- FIG. 1 is a cross-sectional view of a portion of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- the principal surface of a silicon substrate 10 which is an example of a semiconductor substrate, is divided into a first region 11 on which a memory cell 15 exemplifying the memory element is formed. and a second region 13 on which an access gate transistor 17 is formed.
- a silicon oxide layer 12 as a tunnel insulation layer, on which a floating gate 88 , an ONO-layer 16 as a dielectric layer on the floating gate 88 , and a control gate 84 are formed on the ONO-layer.
- a silicon oxide layer 76 having a thickness of 80 to 200 nm is formed as an example of the masking layer.
- a source/drain regions 96 and 97 are formed separately and in opposite positions across the control gate 84 and the floating gate 88 .
- a gate oxide layer 20 as a gate insulation layer. on which a gate electrode 82 is formed.
- a silicon oxide layer 76 having a thickness of 200 to 300 nm is formed.
- source/drain regions 99 and 100 are formed separately and in opposite positions across the gate electrode 82 .
- a groove section 90 is unavoidably formed. Over the area of the groove section 90 , N + type regions 94 and 98 are formed in such a way that the N + type regions 94 and 98 overlap each other at the groove section 90 , with the N + type region 94 being formed in a deeper position than the N + type region 98 in the silicon substrate 10 .
- Part of the N + type regions 94 and 98 positioned in the first region 11 constitute the source/drain 97
- part of the N + type region 98 positioned in the second region 13 constitutes the source/drain 99 .
- the impurity region comprising the N + type regions 94 and 98 has a higher impurity concentration than that of the source/drain regions 96 , 99 , and 100 .
- a silicon oxide layer 44 is formed so that it covers the memory cell 15 and the access gate transistor 17 .
- a contact hole 46 a to expose source/drain 96 is formed on the silicon oxide layer 44 .
- a contact hole 46 b to expose the source/drain 100 are formed on the silicon oxide layer 44 .
- aluminum wiring layers 48 a and 48 b are provided over the silicon oxide layer 44 .
- the aluminum wiring layer 48 a is also formed within the contact hole 46 a and is electrically connected with the source/drain 96 .
- the aluminum wiring layer 48 b is also formed within the contact hole 46 b and is electrically connected to the source/drain 100 .
- FIG. 2 is a plan view of the non-volatile semiconductor memory device shown in FIG. 5 at the segment indicated as 400 A
- FIG. 1 is a cross-sectional view taken along the A-A line in the direction as indicated by the arrows.
- the illustration shows that the control gate 37 , aluminum wiring layer 48 a , control gate 84 , groove section 90 , gate electrode 82 , and aluminum wiring layer 48 b are formed with vertical spaces provided between them.
- the control gate 84 and the gate electrode 82 correspond respectively to the control gate 404 and the gate electrode 401 A shown in FIG. 5.
- a silicon oxide layer 12 as the tunnel insulation layer having a thickness of 7 to 10 nm is grown on the principal surface of the silicon substrate 10 by means of a thermal oxidation method, for example.
- a polysilicon layer 14 having a thickness of 100 to 200 nm, exemplifying the first conductive layer, is then grown over the silicon oxide layer 12 by means of a CVD method, for example.
- the polysilicon layer 14 over the area of a second region 13 is selectively removed by a photo-etching technique, for example. Then an ONO-layer 16 is grown on the principal surface of the silicon substrate 10 to cover the polysilicon layer 14 on the first region 11 the oxide portions of the ONO layer 16 are formed for example by a CVD method or a thermal oxidation method, and the nitride portion is formed for example by a CVD method.
- a resist 18 is formed on the principal surface of the silicon substrate 10 .
- the resist 18 over the area of the second region 13 is then removed.
- the ONO-layer 16 and silicon oxide layer 12 over the area of the second region 13 are etched to expose the 20 principal surface of the silicon substrate 10 .
- a gate oxide layer 20 having a thickness of 5 to 20 nm is grown on the second region 13 by a thermal oxidation method, for example.
- a polysilicon layer 24 having a thickness of 200 to 400 nm exemplifying the second conductive layer is grown over the entire principal surface or the silicon substrate 10 by means of a CVD method, for example.
- the second conductive layer include a laminated structure of a polysilicon layer having a thickness of 80 to 200 nm and a layer of silicide such as WSi 2 , MoSi 2 . CoSi 2 , TiSi 2 or other materials which is grown on the polysilicon layer to a thickness of 80 to 200 nm.
- a silicon oxide layer 76 having a thickness of 200 to 300 nm is formed on the polysilicon layer 24 by using, for example, a CVD method.
- the silicon oxide layer 76 is an example of the masking layer.
- a resist 80 as the second resist is prepared on the silicon oxide layer 76 and patterned for a control gate and a gate electrode.
- the silicon oxide layer 76 and the polysilicon layer 24 are selectively etched in succession by using the resist 80 as a mask to form a control gate 84 and a gate electrode 82 simultaneously, with the resist 80 being removed afterward.
- a resist 86 is prepared over the principal surface of the silicon substrate 10 , and then patterned to cover the gate electrode 82 , as shown in FIG. 12, The resist 86 thus prepared is the first resist.
- the ONO-layer 16 is selectively etched by using as a mask the silicon oxide layer 76 and the resist 86 on the control gate 84 , to leave a portion of the ONO-layer 16 positioned underneath the control gate 84 .
- the silicon oxide layer 20 on the principal surface of the silicon substrate 10 is also etched at the position between the floating gate and the gate electrode to expose the principal surface of the silicon substrate 10 .
- a floating gate 88 is then formed by selectively etching the polysilicon layer 14 .
- the exposed portion of the silicon substrate 10 at the principal surface is also etched to form a groove section 90 having a depth of 100 to 300 nm in the silicon substrate.
- the silicon oxide layer 76 on the control gate 84 is used as a mask for selectively etching the ONO-layer 16 and the polysilicon layer 14 . Since the above etching removes a portion of the silicon oxide layer 76 on the control gate 84 , the thickness of the silicon oxide layer 76 on the control gate 84 becomes smaller than that of the silicon oxide layer 76 on the gate electrode 82 .
- a resist 92 is formed over the principal surface of the silicon substrate 10 .
- the resist 92 is then patterned to cover the first region 11 on which a source/drain 96 is formed while its edge 92 a is positioned on the control gate 84 and also to cover the second region 13 on which a source/drain 100 is formed while its edge 92 b is positioned between the gate electrode 82 and the groove section 90 .
- a phosphorus ion implantation is provided over an area covering the groove section 90 on the principal surface of the silicon substrate 10 , under conditions of energy of 40 to 120 KeV and a dosage of 1E14/cm 2 to 6E15/cm 2 .
- a phosphorus or arsenic ion implantation is then performed under conditions of 30 to 80 Kev and 1E15/cm 2 to 6E15/cm 2 .
- a thermal treatment is provided on the diffused ions to form an N + type region 94 , having a thickness of 200 to 600 nm with an impurity concentration of 1E18/cm 3 to 1E21/cm 3 .
- the thermal treatment for forming the N + type region 94 is performed under an N 2 or N 2 /O 2 atmosphere for 30 to 180 minutes at 900 to 950° C. With the above-mentioned ion implantations and thermal treatment, the N + type region 94 is formed on the principal surface of the silicon substrate 10 so that it covers the groove section 90 .
- a phosphorus ion implantation is then provided over the principal surface of the silicon substrate 10 by using as masks the silicon oxide layer 76 on the control gate 84 and the silicon oxide layer 76 on the gate electrode 82 , under conditions of an energy of 40 to 120 KeV and a dosage of 5E12/cm 2 to 5E14/cm 2 .
- a phosphorus or arsenic ion implantation is then performed under conditions of 30 to 80 KeV and 1E15/cm 2 to 6E15/cm 2 .
- the source/drain 96 , an N + type region 98 , and the source/drain 100 are formed.
- the N + type region 98 has a thickness of 100 to 400 nm and an impurity concentration of 1E17/cm 3 to 1E21/cm 3 .
- a silicon oxide layer 44 as an interlayer insulation layer is formed over the entire principal surface of the silicon substrate 10 by a CVD method, for example.
- a PSG layer, an SOG layer, or a BPSG layer can be used in place of the silicon oxide layer.
- the interlayer insulation layer can also be of a single layer of PSG, SOG, or BPSG, or of a multi-layered structure combining a silicon oxide layer, a PSG layer, a SOG layer, or a BPSG layer.
- the silicon oxide layer 44 is selectively etched to form a contact hole 46 a to expose the source/drain 96 , as well as a contact hole 46 b to expose the source/drain 100 .
- an aluminum layer is grown over the silicon oxide layer 44 by means of sputtering, for example, and then aluminum wiring layers 48 a and 48 b are formed by providing a patterning on the aluminum layer. Note that aluminum alloy wiring layer comprising aluminum and other metals such as copper could also be used in place of the aluminum wiring layer.
- control gate 84 and the gate electrode 82 are simultaneously formed, there is no need to consider the margin for aligning the masks for forming the control gate 84 and the gate electrode 82 . Consequently, the space between the control gate 84 and the gate electrode 82 can be reduced, thereby contributing to microminiaturization of the non-volatile semiconductor memory device.
- the impurity region comprising the N + type regions 94 and 98 in the groove section 90 are formed by the two ion implantations described with reference to FIG. 14 and FIG. 15.
- the source/drain regions 96 , 99 , and 100 are formed by the ion implantation described with reference to FIG. 15, under the conditions for depth and concentration of impurities required for these source/drain regions.
- the present embodiment allows the formation of the source/drain regions 96 , 99 , and 100 with the necessary depth and concentration of impurities while lowering the diffusion resistance of the impurity region at the groove section 90 .
- edge 92 a of the resist 92 is not positioned between the control gate 84 and the groove section 90 , there is no need to Consider the mask alignment margin for the area between the control gate and the groove section, enabling shortening the space between the control gate and the groove section, thereby achieving a high cell density and a high degree of integration for the non-volatile semiconductor memory device.
- the second embodiment of the present invention is described below.
- the fabrication steps up to the formation of the polysilicon layer 24 are performed as in the first embodiment.
- a silicon oxide layer 77 having a thickness of 200 to 300 nm is grown by means of a CVD method, for example.
- This silicon oxide layer 77 exemplifies the masking layer.
- a resist 81 as the third resist is formed on the silicon oxide layer 77 and provided with a desired pattern Referring to FIG. 17, by using the resist 81 as a mask, the silicon oxide layer 77 is first selectively etched. After removing the resist 81 as shown in FIG. 18, the polysilicon layer 24 is selectively etched by using the silicon oxide layer 77 as a mask to simultaneously form a control gate 104 and a gate electrode 102 .
- a resist 106 is formed on the principal surface of the silicon substrate 10 and patterned to cover the gate electrode 102 .
- the above resist corresponds to the first resist.
- the ONO-layer 16 and the polysilicon layer 14 are selectively etched in succession to form a floating gate 110 .
- a groove section 108 is formed on the principal surface of the silicon substrate 10 in the area between the floating gate 110 and the gate electrode 102 , in the same unavoidable manner as described in the first embodiment.
- the silicon oxide layer 77 formed on the control gate 104 is used as a mask for selectively etching the ONO-layer 16 and the polysilicon layer 14 . Since the above etching removes a portion of the silicon oxide layer 77 . the thickness of the silicon oxide layer 77 on the control gate 104 becomes smaller than that of the silicon oxide layer 77 on the gate electrode 102 , Referring to FIG. 21. a resist 92 is formed on the principal surface of the silicon substrate 10 .
- the resist 92 is patterned so that the resist 92 covers the first region 11 on which the source/drain 96 is formed while its edge 92 a is positioned on the control gate 104 , and also covers the second region 13 on which the source/drain 100 is formed while its edge 92 b is positioned between the gate electrode 102 and the groove section 108 .
- the first ion implantation is performed on the silicon substrate 10 , followed by a thermal treatment to form an N+ type region 94 covering the groove section 108 .
- the conditions for the above ion implantation and the thermal treatment are the same as in the first embodiment.
- a second ion implantation is performed on the principal surface of the silicon substrate 10 by using as masks the silicon oxide layer 77 on the control gate 104 and also the silicon oxide layer 77 on the gate electrode 102 .
- source/drain regions 96 and 100 as well as an N + type region 98 covering the groove section 108 are formed.
- the conditions for the ion implantation are the same as in the first embodiment.
- Part of the N type regions 94 and 98 located in the first region 11 constitute the source/drain 97 .
- Part of the N + type regions 98 located in the second region 13 constitutes the source/drain 99 .
- the rest of the fabrication steps are the same as in the first embodiment.
- this embodiment forms the control gate 104 and the gate electrode 102 by using the silicon oxide layer 77 as a mask. Consequently, the control gate and the gate electrode can be formed with a more accurate shape than a method of forming the same by using a resist as the mask.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a non-volatile semiconductor memory device for storing information by accumulation of an electric charge and a method of manufacturing thereof. More specifically, the present invention relates to a non-volatile semiconductor memory device in which a memory element is selectively activated by a field effect transistor and a method of manufacturing thereof.
- 2. Description of the Prior Art
- As a non-volatile semiconductor memory device having memory elements provided with floating gates and control gates, a flash memory can be mentioned as an example. A variety of designs are available for flash memories, one of which is a device in which a memory element is selectively activated by a field effect transistor. A flash memory with such a configuration has been disclosed, for example, in Japanese Patent Application Laid-Open No. 6-275847. In the following, a method of manufacturing the flash memory disclosed in the Japanese Patent Application Laid-Open No. 6-275847 is described with reference to FIGS.23 to 31.
- As shown in FIG. 23, on a principal surface of a
semiconductor substrate 200, asilicon oxide layer 202 as a tunnel oxide layer is grown. and then apolysilicon layer 204 as a floating gate is formed. Part of thepolysilicon layer 204 that is positioned over an accesstransistor formation region 232 is selectively etched as shown in FIG. 24. and remaining part of thepolysilicon layer 204 positioned over a memoryelement formation region 234 is left. This remaining part of thepolysilicon layer 204 in hereinafter referred to as apolysilicon layer 204 a. As shown in FIG. 25, an ONO-layer 206 is formed on thepolysilicon layer 204 a. and asilicon oxide layer 208 as a gate oxide layer is formed over the accesstransistor formation region 232. Subsequently, apolysilicon layer 210 is formed on the ONO-layer 206 and thesilicon oxide layer 208. - As shown in FIG. 26, a resist212 is prepared on the
polysilicon layer 210 which is then selectively etched by using the resist 212 as a mask, thereby forming agate electrode 214 over the accesstransistor formation region 232 while leaving part of thepolysilicon layer 210 that is positioned over the memoryelement formation region 234. The remaining part of thepolysilicon layer 210 over the memoryelement formation region 234 is hereinafter referred to as apolysilicon layer 210 a. This etching exposes thesilicon oxide layer 208 on aprincipal surface 236 of thesemiconductor substrate 200, in the area between thegate electrode 214 and a floating gate to be formed in a later step. Next, as shown in FIG. 27, the resist 212 is removed and a resist 216 is prepared over the memoryelement formation region 234 and the accesstransistor formation region 232. The resist 216 is patterned so that it provides a mask for forming a control gate. - Note that the resist216 is patterned so that it covers the
gate electrode 214, while at the same time its edge 216 a does not overlap the polysilicon layers 204 a and 210 a Thegate electrode 214 has to be covered by resist 216 because thegate electrode 214 is formed of a material identical to that of the control gate and the floating gate, i.e. polysilicon, and therefore has to be protected from being etched away during the etching step to form the control gate and the floating gate. The patterning is provided in such a way that the edge 216 a does not overlap the polysilicon layers 204 a and 210 a because when the polysilicon layers 204 a and 210 a are etched later to form the control gate and the floating gate, unnecessary polysilicon layers 204 a and 210 a are left on the principal surface of thesemiconductor substrate 200 if the edge 216 a overlaps the polysilicon layers 204 a and 210 a. Consequently, the resist 216 is patterned while being thesilicon oxide layer 208 exposed on aprincipal surface 236 of thesemiconductor substrate 200, in the area between thegate electrode 214 and a floating gate to be formed in a later step. - The
polysilicon layer 210 a is selectively etched by using the resist 216 as a mask to formacontrol gate 218. The ONO-layer 206 is then selectively etched by using the resist 216 as a mask, as shown in FIG. 28. This etching removes the exposed portion of thesilicon oxide layer 208 and exposes theprincipal surface 236 in the area between thegate electrode 214 and a floating gate to be formed in a later step. - As shown in Pig.29, the
polysilicon layer 204 a is selectively etched by using the resist 216 as a mask, thereby forming a floatinggate 220. Since theprincipal surface 236 is exposed. theprincipal surface 236 is also etched to unavoidably form agroove section 222 on theprincipal surface 236. Subsequently, an ion implantation is provided on the principal surface of thesemiconductor substrate 200 by using theresist 216 as a mask. thereby forming a source/drain 224 in the memoryelement formation region 234 as well as animpurity region 226 electrically connected to the source/drain 224, in thegroove section 222. - A
silicon oxide layer 228 is grown on the principal surface of thesemiconductor substrate 200 as shown in FIG. 30. followed by the formation of acontact hole 238 on thesilicon oxide layer 228. The that the source/drain 224 is exposed. As shown in FIG. 31, analuminum wiring 230 is then provided on thesilicon oxide layer 228. Thealuminum wiring 230 is also formed on thecontact hole 238 and is electrically connected to the source/drain 224. Amemory element 242 is provided with thecontrol gate 218. thefloating gate 220, and the source/drain 224, whereas anaccess transistor 244 is provided with thegate electrode 214 and the source/drain 240. - As described above, the control gate219 and the
gate electrode 214 have conventionally been prepared in separate steps. Consequently, there is a need to allow for a margin for aligning a mask for forming thecontrol gate 218 and a mask for forming thegate electrode 214, which has caused an obstacle for reducing the space between thecontrol gate 218 and thegate electrode 214. - The present invention has been made to eliminate the above-described problems with the prior art. Accordingly, an object of the present invention is to provide a non-volatile semiconductor memory device which can reduce the space between a control gate and a gate electrode and a method of manufacturing thereof.
- According to one aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device that comprises:
- a semiconductor substrate having a principal surface including a first region and a second region;
- at least one memory element including a floating gate formed on the first region and a control gate formed on the floating gate; and
- at least one access gate transistor for selectively activating the memory element, comprising a gate electrode formed on the second region.
- This method comprises the steps of:
- forming a tunnel insulation layer on the first region;
- forming on the tunnel insulation layer a first conductive layer that functions as the floating gate;
- forming a dielectric layer on the first conductive layer;
- forming a gate insulation layer on the second region:
- forming a second conductive layer on the dielectric layer and gate insulation layer;
- forming on the second conductive layer a masking layer that has a different etching rate from the first conductive layer and functions as a mask when the first conductive layer is selectively etched;
- selectively etching the masking layer and second conductive layer to simultaneously form the control gate and gate electrode, while leaving the masking layer on the control gate;
- forming a first resist to cover the gate electrode; and
- selectively etching the first conductive layer by using the masking layer on the control gate as well as the first resist as masks to form the floating gate.
- In the method of manufacturing a non-volatile semiconductor memory device according to the present invention. since the control gate and the gate electrode are simultaneously formed, there is no need to allow for the margin for aligning the masks for forming the control gate and the gate electrode. Consequently, the present invention makes it possible to reduce the space between the control gate and the gate electrode. The control gate and the gate electrode can be simultaneously formed because the present invention allows the formation of the floating gate by using the masking layer formed on the control gate as a mask. Therefore, in the step of forming the first resist to cover the gate electrode, there is no need to form the first resist on the second conductive layer on the first region. In the prior art method, by contrast, the control gate and the floating gate have been formed by selectively etching the second and the first conductive layers by using the first resist as a mask.
- The serial steps from forming the masking layer up to simultaneously forming the control gate and gate electrode may comprise the steps of: forming a second resist on the masking layer; and selectively etching the masking layer and the second conductive layer by using the second resist as a mask to form the control gate and gate electrode simultaneously.
- The serial steps from forming the masking layer up to simultaneously forming the control gate and gate electrode may comprise the steps of; forming a third resist on the masking layer: selectively etching the masking layer by using the third resist as a mask; and selectively etching the second conductive layer by using the masking layer as a mask to form the control gate and gate electrode simultaneously.
- The masking layer may comprise an insulation layer. The masking layer also may comprise a silicon oxide layer. The masking layer may have a thickness from 200 to 300 nm.
- The non-volatile semiconductor memory device may be provided with a plurality of the memory elements and a plurality of the access gate transistors, each of the access gate transistors selectively activating only one of the memory elements.
- According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device for storing information through the accumulation of an electric charge, comprising:
- a semiconductor substrate having a principal surface comprising a first region and a second region;
- at least one memory element comprising a floating gate formed in the first region and a control gate formed on the floating gate;
- at least one access gate transistor comprising a gate electrode formed on the second region for selectively activating the memory element;
- a first layer that is located on the control gate and has the same width as the control gate and a different etching rate from the floating gate; and
- a second layer that is located on the gate electrode and has the same width as the gate electrode and the same composition as the first layer.
- The first layer may be smaller than the second layer in thickness.
- The memory element may comprise a first source/drain formed in the first region, and a second source/drain that is formed in the first region apart from the first source/drain, the floating gate and control gate being located between the first source/drain and second source/drain; the access gate transistor may comprise a third source/drain which is formed in the second region and a fourth source/drain that is formed in the second region apart from the third source/drain, the gate electrode being located between the third source/drain and fourth source/drain; a groove section may be unavoidably formed on the principal surface in the area between the floating gate and gate electrode; and an impurity region for electrically connecting the second source/drain to the third source/drain may be formed in the semiconductor substrate to cover the groove section.
- The impurity concentration of the impurity region may be higher than the impurity concentration of each of the first source/drain and fourth source/drain.
- Each of the first and second layers may comprise an insulation layer.
- Bach of the first and second layers may comprise a silicon oxide layer.
- The first layer may be 80 to 200 nm in thickness, and the second layer may be 200 to 300 nm in thickness.
- The non-volatile semiconductor memory device may be provided with a plurality of the memory elements and a plurality of the access transistors, each of the access gate transistors selectively activating only one of the memory elements.
- Note that when the word “on” is used to explain the positional relationship between two layers of the device in the present application, there may exist other layers between those two layers.
- FIG. 1 is a cross-sectional view of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 2 is a partial plan view of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device Of the present invention.
- FIG. 3 is a schematic diagram of a memory cell of the flash memory manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 4 is a schematic cross-sectional view of a memory cell of the flash memory manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 5 is a schematic diagram of a memory cell array of the flash memories manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 6 is a partial cross-sectional view of the device to illustrate the first step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 7 is a partial cross-sectional view of the device to illustrate the second step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 8 is a partial cross-sectional view of the device to illustrate the third step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 9 is a partial cross-sectional view of the device to illustrate the fourth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 10 is a partial cross-sectional view of the device to illustrate the fifth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 11 is a partial cross-sectional view of the device to illustrate the sixth stop of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 12 is a partial cross-sectional view of the device to illustrate the seventh stop of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 13 is a partial cross-sectional view of the device to illustrate the eighth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 14 is a partial cross-sectional view of the device to illustrate the ninth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 15 is a partial cross-sectional view of the device to illustrate the tenth step of the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 16 is a partial cross-sectional view of the device to illustrate the first step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 17 is a partial cross-sectional view of the device to illustrate the second step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 10 is a partial cross-sectional view of the device to illustrate the third step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 19 is a partial cross-sectional view of the device to illustrate the fourth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 20 is a partial cross-sectional view of the device to illustrate the fifth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 21 is a partial cross-sectional view of the device to illustrate the sixth step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 22 is a partial cross-sectional view of the device to illustrate the seventh step of the second embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention.
- FIG. 23 is a partial cross-sectional view of the device to illustrate the first step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 24 is a partial cross-sectional view of the device to illustrate the second step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 25 is a partial cross-sectional view of the device to illustrate the third step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 26 is a partial cross-sectional view of the device to illustrate the fourth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 27 is a partial cross-sectional view of the device to illustrate the fifth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 28 is a partial cross-sectional view of the device to illustrate the sixth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 29 is a partial cross-sectional view of the device to illustrate the seventh step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 30 is a partial cross-sectional view of the device to illustrate the eighth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- FIG. 31 is a partial cross-sectional view of the device to illustrate the ninth step of a conventional method of manufacturing a non-volatile semiconductor memory device.
- Each of the embodiment examples described below is an application of the present invention to a non-volatile semiconductor memory device provided with a plurality of memory elements and a plurality of access transistors for selectively activating the memory elements, in such a manner that each access transistor selectively activates only one memory element. However, the present invention is not limited to those described below but can be equally well applied to non-volatile semiconductor memory devices wherein memory elements are selectively activated by access transistors of types such as NOR, NAND, or DINOR, for example.
- Referring to FIGS. 3, 4, and5, descriptions are first given on a non-volatile semiconductor memory device provided with a plurality of memory elements and a plurality of access transistors for selectively activating the memory elements, in such a manner that each access transistor selectively activates only one memory element. FIG. 3 is a schematic view of a
memory cell 400 of a flash memory of the above type. Thememory cell 400 has anaccess transistor 401 and amemory transistor 402 which is a memory element. Theaccess transistor 401 has agate 401A and thememory transistor 402 has a floatinggate 403 and acontrol gate 404. Theaccess transistor 401 is an N-channel MOSFET with a threshold voltage of approximately 0.7 V. - Programming of the
memory cell 400 by channel hot electron is achieved by simultaneously applying a high positive programming voltage Vpp. For example, 5 to 12 V may be applied to thegate 401A of theaccess transistor 401, and 12 V to thecontrol gate 404 of thememory transistor 402, while holding asource 408 of thememory transistor 402 at a ground potential Vgp, and applying a positive programming pulse to adrain 406 of theaccess transistor 401. A programming pulse of about 5 V can be applied for 100 microseconds, for example. Referring to FIG. 4. adrain 407 of the memory transistor 402 (which is also the source of the access transistor 401) has a high-concentration doping region 510 to the substrate. This ion implantation to the drain enhances the electric field in achannel region 511 close to thedrain 407. thereby accelerating the electrons and generating a distribution of high energy electrons which are energetic enough to overcome the potential energy barrier and to transfer through a thin tunnel layer and into the floating gate 403 (e.g. for hot electron injection). This ion implantation highly doping thedrain 407 can multiply the speed of programming. Note that theaccess transistor 401 uses a smaller fraction of the applied drain pulse voltage, since the width of theaccess transistor 401 is typically within the range of 1.0 to 5.0 μm, compared with the 0.25 to 1.5 μm of thememory transistor 402. - Erasure of the
memory cell 400 is achieved by applying 5 V to thesource 408 of thememory transistor 402 while holding thecontrol gate 404 at −7 V. A high electric field is generated in a tunnel oxide layer 405 (shown in Pig. 4), thereby allowing the electrons collected in the floatinggate 403 to overcome the potential energy barrier and tunnel (by Povler-Nordheim tunneling, for example) through thetunnel oxide layer 405 to thesource 408 of thememory transistor 402. During the erasure, A voltage of 5 to 12 V is applied to thegate 401A and thedrain 406 is left floating. - The
source 408 of thememory transistor 402 is also formed by high-concentration doping 512 of the substrate. This high-concentration doping increases the dielectric breakdown of the junction, thereby significantly accelerating the transfer of electrons from the floating gate during the erasure. In this manner, thememory transistor 402 erases during the erasure operation to the point at which its threshold voltage is negative. Thus thememory transistor 402 cannot be turned off by thecontrol gate 404. However, theaccess transistor 401 prevents this overerasure from affecting cell performance. More specifically, theaccess transistor 401 is not controlled by the state of the floating gate. so the threshold voltage of theaccess transistor 401 remains at approximately 0.7 V. - Various operating conditions can be set, other than these described above for programming and erasure operations. The conditions described below can also be set, for example, when programming and erasure are both provided by Fowler-Nordheim tunneling. Programming conditions can be: −8 V at the control gate, the source in floating, 8 V at the drain, and 8 V at the gate of the access transistor. Erasure conditions can be: 8 V at the control gate, −8 V at the source, the drain in floating, and 8 V at the gate of the access transistor.
- A schematic view of a
memory array 600 which comprisesmemory cells 400A to 400D is shown in FIG. 5. Each of these memory cells is identical to thememory cell 400. Thedrains 406 of theaccess transistors 401 of thecells drain bit line 631, and thesources 408 of thememory transistors 402 of thesecells line 630. Thegates 401A of theaccess transistors 401 of thememory cells word line 520, and thecontrol gates 404 of thememory cells control line 521 - Referring to FIG. 5. the reading of the
memory cell 400A, for example, is accomplished by applying a standard voltage Vcc (usually 5 V) to thegate 401A via theword line 520 as well as to thecontrol gate 404 via thecontrol line 521, while simultaneously sensing the read current flowing through thememory cell 400A by a conventional sense amplifier (not shown in the figure) that is connected to thedrain bit line 631. If thememory cell 400A has been erased (i.e., if there is a zero charge or net positive charge on the floating gate 403), both theaccess transistor 401 and thememory transistor 402 are turned on, allowing a current to flow through thememory cell 400A which can be sensed by the sense amplifier. If thememory cell 400A is programmed (i.e., if there a net negative charge on the floating gate 403). the threshold voltage of thememory transistor 402 rises above the supply voltage Vcc, preventing current from flowing through thememory cell 400A. - In this configuration, the sense amplifier which receives the voltage from the drain bit line generates a feedback voltage to the
source bit line 630, which increases the voltage on thesource bit line 630 during a read operation. This slows down the voltage drop on thedrain bit line 631. Thus, the present invention significantly reduces the time required for the bit lines to recover their original state so that they can perform sensing during the next logic state cycle, in comparison with conventional memory cell arrays. - The main limitation to scaling of the
memory transistor 402 is the punch-through requirement. Capacitive coupling between thedrain 407 and the floatinggate 403 typically causes thememory transistor 402 to be turned on by the coupling to thedrain 407. This capacitive coupling limits the scalability of the channel length of the channel region 511 (see FIG. 4) and thus limits the improvement in programming speed that is necessary for the 5-volt programming capability. More specifically. capacitive coupling from thedrain 407 to the floatinggate 403 degrades the punch-through margin of thememory transistor 402, and limits the capability of thememory transistor 402 to handle the drain voltage. The capacitive coupling effect does not scale with the gate line width of thememory transistor 402 because of the strong effect of fringing capacitance. which is the capacitance other than parallel-plate capacitance. Therefore, the effect of this drain coupling becomes more dominant for smaller geometries and poses a serious limitation to the scaling of conventional EEPROM and flash memories that do not have access gates. Note that the programming speed increases exponentially with the reciprocal of the effective channel length. - The memory cell of the present invention solves this scaling problem by the inclusion of the
access transistor 401 within thememory cell 400. Since this memory cell eliminates punch through of thememory transistor 402 in programming mode, the channel length of thechannel region 511 can be scaled. This scalability means that the channel length can be reduced, which significantly increases the programming speed of the memory cell in comparison with the prior art. Moreover, the doping to thedrain 407 enables thememory cell 400 to achieve a full 5-volt programming capability. - First Embodiment
- FIG. 1 is a cross-sectional view of a portion of a non-volatile semiconductor memory device manufactured by the first embodiment of the method of manufacturing a non-volatile semiconductor memory device of the present invention. The principal surface of a
silicon substrate 10, which is an example of a semiconductor substrate, is divided into afirst region 11 on which amemory cell 15 exemplifying the memory element is formed. and asecond region 13 on which anaccess gate transistor 17 is formed. On thefirst region 11 is formed asilicon oxide layer 12 as a tunnel insulation layer, on which a floatinggate 88, an ONO-layer 16 as a dielectric layer on the floatinggate 88, and acontrol gate 84 are formed on the ONO-layer. On thecontrol gate 84, asilicon oxide layer 76 having a thickness of 80 to 200 nm is formed as an example of the masking layer. Within thefirst region 11, a source/drain regions control gate 84 and the floatinggate 88. - Over the
second region 13 is formed agate oxide layer 20 as a gate insulation layer. on which agate electrode 82 is formed. On thegate electrode 82, asilicon oxide layer 76 having a thickness of 200 to 300 nm is formed. Within thesecond region 13, source/drain regions gate electrode 82. - On the principal surface of the
silicon substrate 10 in the area between the floatinggate 88 and thegate electrode 82. agroove section 90 is unavoidably formed. Over the area of thegroove section 90, N+ type regions 94 and 98 are formed in such a way that the N+ type regions 94 and 98 overlap each other at thegroove section 90, with the N+ type region 94 being formed in a deeper position than the N+ type region 98 in thesilicon substrate 10. Part of the N+ type regions 94 and 98 positioned in thefirst region 11 constitute the source/drain 97, whereas part of the N+ type region 98 positioned in thesecond region 13 constitutes the source/drain 99. The impurity region comprising the N+ type regions 94 and 98 has a higher impurity concentration than that of the source/drain regions - On the principal surface of the
silicon substrate 10, asilicon oxide layer 44 is formed so that it covers thememory cell 15 and theaccess gate transistor 17. On thesilicon oxide layer 44, a contact hole 46 a to expose source/drain 96, and acontact hole 46 b to expose the source/drain 100 are formed. Over thesilicon oxide layer 44, aluminum wiring layers 48 a and 48 b are provided. Thealuminum wiring layer 48 a is also formed within the contact hole 46 a and is electrically connected with the source/drain 96. Similarly. thealuminum wiring layer 48 b is also formed within thecontact hole 46 b and is electrically connected to the source/drain 100. - FIG. 2 is a plan view of the non-volatile semiconductor memory device shown in FIG. 5 at the segment indicated as400A, and FIG. 1 is a cross-sectional view taken along the A-A line in the direction as indicated by the arrows. The illustration shows that the
control gate 37,aluminum wiring layer 48 a,control gate 84,groove section 90,gate electrode 82, andaluminum wiring layer 48 b are formed with vertical spaces provided between them. Thecontrol gate 84 and thegate electrode 82 correspond respectively to thecontrol gate 404 and thegate electrode 401A shown in FIG. 5. - The first embodiment of the method of manufacturing the non-volatile semiconductor memory device according to the present invention is described below. As shown in FIG. 6, a
silicon oxide layer 12 as the tunnel insulation layer having a thickness of 7 to 10 nm is grown on the principal surface of thesilicon substrate 10 by means of a thermal oxidation method, for example. Apolysilicon layer 14 having a thickness of 100 to 200 nm, exemplifying the first conductive layer, is then grown over thesilicon oxide layer 12 by means of a CVD method, for example. - As shown in FIG. 8, the
polysilicon layer 14 over the area of asecond region 13 is selectively removed by a photo-etching technique, for example. Then an ONO-layer 16 is grown on the principal surface of thesilicon substrate 10 to cover thepolysilicon layer 14 on thefirst region 11 the oxide portions of theONO layer 16 are formed for example by a CVD method or a thermal oxidation method, and the nitride portion is formed for example by a CVD method. - As shown in FIG. 8, a resist18 is formed on the principal surface of the
silicon substrate 10. The resist 18 over the area of thesecond region 13 is then removed. By using the resist 18 as a mask, the ONO-layer 16 andsilicon oxide layer 12 over the area of thesecond region 13 are etched to expose the 20 principal surface of thesilicon substrate 10. As shown in FIG. 9, agate oxide layer 20 having a thickness of 5 to 20 nm is grown on thesecond region 13 by a thermal oxidation method, for example. - As shown in FIG. 10, a
polysilicon layer 24 having a thickness of 200 to 400 nm exemplifying the second conductive layer is grown over the entire principal surface or thesilicon substrate 10 by means of a CVD method, for example. Note here that other examples of the second conductive layer include a laminated structure of a polysilicon layer having a thickness of 80 to 200 nm and a layer of silicide such as WSi2, MoSi2. CoSi2, TiSi2 or other materials which is grown on the polysilicon layer to a thickness of 80 to 200 nm. Subsequently, asilicon oxide layer 76 having a thickness of 200 to 300 nm is formed on thepolysilicon layer 24 by using, for example, a CVD method. Thesilicon oxide layer 76 is an example of the masking layer. Then a resist 80 as the second resist is prepared on thesilicon oxide layer 76 and patterned for a control gate and a gate electrode. - As shown in FIG. 11. the
silicon oxide layer 76 and thepolysilicon layer 24 are selectively etched in succession by using the resist 80 as a mask to form acontrol gate 84 and agate electrode 82 simultaneously, with the resist 80 being removed afterward. - Subsequently, a resist86 is prepared over the principal surface of the
silicon substrate 10, and then patterned to cover thegate electrode 82, as shown in FIG. 12, The resist 86 thus prepared is the first resist. - As shown in FIG. 13, the ONO-
layer 16 is selectively etched by using as a mask thesilicon oxide layer 76 and the resist 86 on thecontrol gate 84, to leave a portion of the ONO-layer 16 positioned underneath thecontrol gate 84. By the selective etching of the ONO-layer 16 in the above, thesilicon oxide layer 20 on the principal surface of thesilicon substrate 10 is also etched at the position between the floating gate and the gate electrode to expose the principal surface of thesilicon substrate 10. A floatinggate 88 is then formed by selectively etching thepolysilicon layer 14. By the above etching, the exposed portion of thesilicon substrate 10 at the principal surface is also etched to form agroove section 90 having a depth of 100 to 300 nm in the silicon substrate. - As described in the step shown in FIG. 13, the
silicon oxide layer 76 on thecontrol gate 84 is used as a mask for selectively etching the ONO-layer 16 and thepolysilicon layer 14. Since the above etching removes a portion of thesilicon oxide layer 76 on thecontrol gate 84, the thickness of thesilicon oxide layer 76 on thecontrol gate 84 becomes smaller than that of thesilicon oxide layer 76 on thegate electrode 82. - Referring to FIG. 14. a resist92 is formed over the principal surface of the
silicon substrate 10. The resist 92 is then patterned to cover thefirst region 11 on which a source/drain 96 is formed while its edge 92 a is positioned on thecontrol gate 84 and also to cover thesecond region 13 on which a source/drain 100 is formed while itsedge 92 b is positioned between thegate electrode 82 and thegroove section 90. - By using the resist92 as a mask, a phosphorus ion implantation is provided over an area covering the
groove section 90 on the principal surface of thesilicon substrate 10, under conditions of energy of 40 to 120 KeV and a dosage of 1E14/cm2 to 6E15/cm2. A phosphorus or arsenic ion implantation is then performed under conditions of 30 to 80 Kev and 1E15/cm2 to 6E15/cm2. After these ion implantations, a thermal treatment is provided on the diffused ions to form an N+ type region 94, having a thickness of 200 to 600 nm with an impurity concentration of 1E18/cm3 to 1E21/cm3. The thermal treatment for forming the N+ type region 94 is performed under an N2 or N2/O2 atmosphere for 30 to 180 minutes at 900 to 950° C. With the above-mentioned ion implantations and thermal treatment, the N+ type region 94 is formed on the principal surface of thesilicon substrate 10 so that it covers thegroove section 90. - As shown in FIG. 15, a phosphorus ion implantation is then provided over the principal surface of the
silicon substrate 10 by using as masks thesilicon oxide layer 76 on thecontrol gate 84 and thesilicon oxide layer 76 on thegate electrode 82, under conditions of an energy of 40 to 120 KeV and a dosage of 5E12/cm2 to 5E14/cm2. A phosphorus or arsenic ion implantation is then performed under conditions of 30 to 80 KeV and 1E15/cm2 to 6E15/cm2. After these ion implantations and a thermal treatment, the source/drain 96, an N+ type region 98, and the source/drain 100 are formed. The N+ type region 98 has a thickness of 100 to 400 nm and an impurity concentration of 1E17/cm3 to 1E21/cm3. - Referring to FIG. 1, a
silicon oxide layer 44 as an interlayer insulation layer is formed over the entire principal surface of thesilicon substrate 10 by a CVD method, for example. As the interlayer insulation layer. a PSG layer, an SOG layer, or a BPSG layer can be used in place of the silicon oxide layer. The interlayer insulation layer can also be of a single layer of PSG, SOG, or BPSG, or of a multi-layered structure combining a silicon oxide layer, a PSG layer, a SOG layer, or a BPSG layer. Next, by using an appropriately patterned resist, thesilicon oxide layer 44 is selectively etched to form a contact hole 46 a to expose the source/drain 96, as well as acontact hole 46 b to expose the source/drain 100. Subsequently, an aluminum layer is grown over thesilicon oxide layer 44 by means of sputtering, for example, and then aluminum wiring layers 48 a and 48 b are formed by providing a patterning on the aluminum layer. Note that aluminum alloy wiring layer comprising aluminum and other metals such as copper could also be used in place of the aluminum wiring layer. - In the present embodiment, as shown in FIG. 11, since the
control gate 84 and thegate electrode 82 are simultaneously formed, there is no need to consider the margin for aligning the masks for forming thecontrol gate 84 and thegate electrode 82. Consequently, the space between thecontrol gate 84 and thegate electrode 82 can be reduced, thereby contributing to microminiaturization of the non-volatile semiconductor memory device. - Furthermore, in the present embodiment, the impurity region comprising the N+ type regions 94 and 98 in the
groove section 90 are formed by the two ion implantations described with reference to FIG. 14 and FIG. 15. Meanwhile, the source/drain regions drain regions groove section 90. Moreover, since the edge 92 a of the resist 92 is not positioned between thecontrol gate 84 and thegroove section 90, there is no need to Consider the mask alignment margin for the area between the control gate and the groove section, enabling shortening the space between the control gate and the groove section, thereby achieving a high cell density and a high degree of integration for the non-volatile semiconductor memory device. - Second Embodiment
- The second embodiment of the present invention is described below. Referring to FIG. 16, the fabrication steps up to the formation of the
polysilicon layer 24 are performed as in the first embodiment. On thepolysilicon layer 24, asilicon oxide layer 77 having a thickness of 200 to 300 nm is grown by means of a CVD method, for example. Thissilicon oxide layer 77 exemplifies the masking layer. A resist 81 as the third resist is formed on thesilicon oxide layer 77 and provided with a desired pattern Referring to FIG. 17, by using the resist 81 as a mask, thesilicon oxide layer 77 is first selectively etched. After removing the resist 81 as shown in FIG. 18, thepolysilicon layer 24 is selectively etched by using thesilicon oxide layer 77 as a mask to simultaneously form acontrol gate 104 and agate electrode 102. - As shown in FIG. 19, a resist106 is formed on the principal surface of the
silicon substrate 10 and patterned to cover thegate electrode 102. The above resist corresponds to the first resist. Referring to FIG. 20. by using thesilicon oxide layer 77 on thecontrol gate 104 and the resist 106 as masks, the ONO-layer 16 and thepolysilicon layer 14 are selectively etched in succession to form a floatinggate 110. In this step, agroove section 108 is formed on the principal surface of thesilicon substrate 10 in the area between the floatinggate 110 and thegate electrode 102, in the same unavoidable manner as described in the first embodiment. - As described in the step shown in FIG. 20, the
silicon oxide layer 77 formed on thecontrol gate 104 is used as a mask for selectively etching the ONO-layer 16 and thepolysilicon layer 14. Since the above etching removes a portion of thesilicon oxide layer 77. the thickness of thesilicon oxide layer 77 on thecontrol gate 104 becomes smaller than that of thesilicon oxide layer 77 on thegate electrode 102, Referring to FIG. 21. a resist 92 is formed on the principal surface of thesilicon substrate 10. The resist 92 is patterned so that the resist 92 covers thefirst region 11 on which the source/drain 96 is formed while its edge 92 a is positioned on thecontrol gate 104, and also covers thesecond region 13 on which the source/drain 100 is formed while itsedge 92 b is positioned between thegate electrode 102 and thegroove section 108. By using the resist 92 as a mask, the first ion implantation is performed on thesilicon substrate 10, followed by a thermal treatment to form anN+ type region 94 covering thegroove section 108. The conditions for the above ion implantation and the thermal treatment are the same as in the first embodiment. - Next, referring to FIG. 22, a second ion implantation is performed on the principal surface of the
silicon substrate 10 by using as masks thesilicon oxide layer 77 on thecontrol gate 104 and also thesilicon oxide layer 77 on thegate electrode 102. After a subsequent thermal treatment, source/drain regions groove section 108 are formed. The conditions for the ion implantation are the same as in the first embodiment. Part of theN type regions first region 11 constitute the source/drain 97. Part of the N+ type regions 98 located in thesecond region 13 constitutes the source/drain 99. The rest of the fabrication steps are the same as in the first embodiment. - In addition to the same effects as described for the first embodiment, the present embodiment has the following effect. As shown in FIG. 18, this embodiment forms the
control gate 104 and thegate electrode 102 by using thesilicon oxide layer 77 as a mask. Consequently, the control gate and the gate electrode can be formed with a more accurate shape than a method of forming the same by using a resist as the mask.
Claims (15)
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US6645814B1 (en) * | 2002-06-24 | 2003-11-11 | Micron Technology, Inc. | Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array |
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JP2002100689A (en) * | 2000-09-22 | 2002-04-05 | Toshiba Corp | Nonvolatile semiconductor memory device |
US6759298B2 (en) * | 2002-06-24 | 2004-07-06 | Micron Technology, Inc. | Methods of forming an array of flash field effect transistors and circuitry peripheral to such array |
KR100539276B1 (en) * | 2003-04-02 | 2005-12-27 | 삼성전자주식회사 | Semiconductor device having a gate line and Method of manufacturing the same |
US7256090B2 (en) * | 2003-12-31 | 2007-08-14 | Dongbu Electronics Co., Ltd. | Method for fabricating semiconductor device |
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IT1191755B (en) * | 1986-04-29 | 1988-03-23 | Sgs Microelettronica Spa | MANUFACTURING PROCESS FOR EPROM CELLS WITH DIELECTRIC OXIDE-NITRIDE-OXIDE |
US4775642A (en) * | 1987-02-02 | 1988-10-04 | Motorola, Inc. | Modified source/drain implants in a double-poly non-volatile memory process |
FR2625608B1 (en) * | 1988-01-04 | 1990-06-15 | Sgs Thomson Microelectronics | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING ELEMENTS WITH TWO GRID LEVELS |
JPH06275847A (en) | 1993-03-24 | 1994-09-30 | Sony Corp | Semiconductor device having floating gate and its manufacture |
JP2536413B2 (en) * | 1993-06-28 | 1996-09-18 | 日本電気株式会社 | Method for manufacturing semiconductor integrated circuit device |
KR0161402B1 (en) * | 1995-03-22 | 1998-12-01 | 김광호 | Method of manufacturing non-volatile memory |
JP2734433B2 (en) * | 1995-10-31 | 1998-03-30 | 日本電気株式会社 | Manufacturing method of nonvolatile semiconductor memory device |
JPH10154802A (en) * | 1996-11-22 | 1998-06-09 | Toshiba Corp | Manufacture of nonvolatile semiconductor memory |
US6083791A (en) * | 1997-12-15 | 2000-07-04 | National Semiconductor Corporation | Self-aligned stacked gate etch process for fabricating a two-transistor EEPROM cell |
-
1999
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US6645814B1 (en) * | 2002-06-24 | 2003-11-11 | Micron Technology, Inc. | Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array |
US6746921B2 (en) | 2002-06-24 | 2004-06-08 | Micron Technology, Inc. | Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array |
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