US20020017951A1

US20020017951A1 - Preamplification circuit

Info

Publication number: US20020017951A1
Application number: US09/852,738
Authority: US
Inventors: Tsuneo Kikuchi; Yuichi Sato
Original assignee: Individual
Current assignee: NEC Corp; Regions Bank
Priority date: 2000-05-12
Filing date: 2001-05-11
Publication date: 2002-02-14
Anticipated expiration: 2021-05-11
Also published as: JP2001320253A; US6404282B2

Abstract

According to a level of an input signal, first switching means performs control in such a way that only a first feedback resistor or the first and second feedback resistors become feedback resistors connected to amplifying means, and thereby allows the amplifying means to keep linearity without saturating even when the level of the input signal changes. Furthermore, when the input signal has a higher level than a predetermined threshold, a phase compensation capacitor is charged under the control of second switching means for phase compensation of the amplifying means. However, even when the input signal has a lower level than the predetermined threshold, the phase compensation capacitor is charged at predetermined timing under the control of third switching means, preventing a high current from being pulled into the amplifying means when the input signal changes from a lower level than the predetermined threshold to a higher level than the predetermined threshold, thereby reducing noise applied to an output signal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a preamplification circuit that controls large signal inputs.

2. Description of the Related Art

FIG. 1 is a circuit diagram showing a configuration example of a conventional preamplification circuit.

As shown in FIG. 1, this conventional example comprises

inverse amplifier

1 for amplifying and outputting a preamp input signal, buffer circuit 2 for buffering and outputting the signal outputted from inverse amplifier 1,

feedback resistors

3 and 4 connected in parallel to each other between the input terminal of inverse amplifier 1 and the output terminal of buffer circuit 2 for changing the gain of inverse amplifier 1, phase compensation capacitor 7 connected between the input terminal and output terminal of inverse amplifier 1 for compensating the phase of inverse amplifier 1, FET switch 5 for switchng the connection between feedback resistor 4 and inverse amplifier 1, buffer circuit 2 based on a gain switching signal supplied and FET switch 6 for switching between charge/discharge of phase compensation capacitor 7 based on the gain switching signal. The signal outputted from buffer circuit 2 is outputted as a preamp output signal (see Japanese Patent Laid-Open No. 1997-8563).

In the preamplification circuit in the above described configuration, the gain switching signal is fixed to LOW while the preamp input signal stays at a low level, which keeps

OFF FET switch

5. As a result, feedback resistor 3 is the only feedback resistor to control the gain of inverse amplifier 1. Furthermore, FET switch 6 is turned OFF, and therefore phase compensation capacitor 7 is left open and discharged, and phase compensation is not performed using phase compensation capacitor 7 for inverse amplifier 1.

On the other hand, while the preamp input signal stays at a high level, the gain switching signal is HIGH, which turns ON

FET switch

5. In this way,

feedback resistors

3 and 4 function as the feedback resistors to control the gain of inverse amplifier 1. As a result, the gain of inverse amplifier 1 becomes smaller than when the preamp input signal stays at a low level. Furthermore, FET switch 6 turns ON, which causes phase compensation capacitor 7 to be charged with the preamp input signal, and in this way, phase compensation is performed for inverse amplifier 1.

In the conventional preamplification circuit above, charging to

phase compensation capacitor

7 starts when the gain switching signal changes from LOW to HIGH.

As shown in FIG. 2, in this conventional example, charging to

phase compensation capacitor

7 starts at the timing at which the preamp input signal changes from a low level signal to a high level signal and the gain switching signal changes from LOW to HIGH. However, if input of the low level signal persists long time, the amount of discharge of phase compensation capacitor 7 increases, and then when the preamp input signal becomes a high level signal and the gain switching signal becomes HIGH, a high current is pulled into inverse amplifier 1. This introduces large noise to the preamp output signal, causing a problem of adversely affecting the circuits that follow.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a preamplification circuit capable of reducing noise applied to a preamp output signal when the preamp input signal changes from a low level signal to a high level signal.

In the present invention, when an input signal having a lower level than a predetermined threshold is supplied, first switching means performs control in such a way that the first feedback resistor is the only feedback resistor connected to amplifying means and the gain of the amplifying means is controlled only by the first feedback resistor. Then, when the input signal has a higher level than the predetermined threshold, the first switching means performs control in such a way that the feedback resistors connected to the amplifying means become the first and second feedback resistors connected in parallel to each other, thereby the gain of the amplifying means is controlled by the resistance value of the first and second feedback resistors connected in parallel. This allows the amplifying means to keep linearity without saturating even when the input signal changes from a lower level than the predetermined threshold to a higher level than the predetermined threshold.

Here, when an input signal having a higher level than the predetermined threshold is supplied, the phase compensation capacitor is charged under the control of the second switching means for phase compensation of the amplifying means. However, even when the input signal has a lower level than the predetermined threshold, the phase compensation capacitor is charged at predetermined timing under the control of third switching means, preventing a high current from being pulled into the amplifying means when the input signal changes from a lower level than the predetermined threshold to a higher level than the predetermined threshold, thus reducing noise applied to the output signal.

The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration example of a conventional preamplification circuit; [0014]
FIG. 2 is a timing chart to explain an operation of the preamplification circuit shown in FIG. 1; [0015]
FIG. 3 is a circuit diagram showing a first embodiment of the preamplification circuit of the present invention; [0016]
FIG. 4 is a timing chart to explain an operation of the preamplification circuit shown in FIG. 3; and [0017]
FIG. 5 is a circuit diagram showing a second embodiment of the preamplification circuit of the present invention.[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(First Embodiment) [0019]
As shown in FIG. 3, this embodiment comprises [0020] inverse amplifier 1 for amplifying and outputting a preamp input signal, buffer circuit 2 for buffering and outputting the signal outputted from inverse amplifier 1, first and second feedback resistors 3 and 4 connected in parallel to each other between the input terminal of inverse amplifier 1 and the output terminal of buffer circuit 2 for changing the gain of inverse amplifier 1, phase compensation capacitor 7 connected between the input terminal and output terminal of inverse amplifier 1 for compensating the phase of inverse amplifier 1, FET switch 5 as first switching means for switching the connection between the feedback resistor 4 and inverse amplifier 1, buffer circuit 2 based on a gain switching signal supplied, FET switch 6 as second switching means for switching between charge/discharge of phase compensation capacitor 7 based on the gain switching signal or a reset signal and an OR gate 8 as third switching means, whose input terminal is supplied the gain switching signal and the reset signal and output terminal is connected to the gate of FET switch 6. A signal outputted from buffer circuit 2 is outputted as a preamp output signal. The resistance values of feedback resistors 3 and 4 have a relationship: (a resistance value of the feedback resistor 3)>>(a resistance value of the feedback resistor 4)
The operation of the preamplification circuit in the above configuration will be explained with reference to FIG. 4. [0021]
When a preamp input signal having a lower level than a predetermined threshold is supplied, the gain switching signal is fixed to LOW, which keeps [0022] OFF FET switch 5. As a result, feedback resistor 3 is the only feedback resistor to control the gain of inverse amplifier 1 and the signal amplified with this gain is outputted as a preamp output signal.
Here, when the preamp input signal is supplied, the reset signal becomes HIGH for every data supplied and then the data is supplied. [0023]
For this reason, even when the gain switching signal is LOW, the HIGH level of the reset signal is transmitted to the gate of [0024] FET switch 6 via OR gate 8 and FET switch 6 turns ON every time the reset signal becomes HIGH.
This causes [0025] phase compensation capacitor 7 to be charged every time the preamp input signal is supplied even when the gain switching signal is LOW, which means that the amount of discharge of phase compensation capacitor 7 will no longer increase.
Then, when the preamp input signal has a higher level than the predetermined threshold, the gain switching signal becomes HIGH, which turns ON [0026] FET switch 5. Thus, the gain of inverse amplifier 1 is controlled by feedback resistors 3 and 4 and the signal amplified with the gain is outputted as the preamp output signal. That is, the gain of inverse amplifier 1 becomes smaller than when the preamp input signal has a lower level than the predetermined threshold. As a result, inverse amplifier 1 keeps linearity without saturating.
Furthermore, the HIGH level of the gain switching signal is transmitted to the gate of [0027] FET switch 6 via OR gate 8, which turns ON FET switch 6 causing phase compensation capacitor 7 to be charged. This allows the phase of inverse amplifier 1 to be compensated. Here, even when the gain switching signal is LOW, phase compensation capacitor 7 is charged by the HIGH level of the reset signal every time the preamp input signal is supplied, preventing any high current from being pulled into inverse amplifier 1 and preventing noise from applying to the preamp output signal.
In this embodiment, [0028] FET switches 5 and 6 are used as the first and second switching means, but the present invention is not limited to this and other switches can also be used.
(Second Embodiment) [0029]
As shown in FIG. 5, this embodiment comprises [0030] inverse amplifier 1 for amplifying and outputting a preamp input signal, buffer circuit 2 for buffering and outputting the signal outputted from inverse amplifier 1, first and second feedback resistors 3 and 4 connected in parallel to each other between the input terminal of inverse amplifier 1 and the output terminal of buffer circuit 2 for changing the gain of inverse amplifier 1, phase compensation capacitor 7 connected between the input terminal and output terminal of inverse amplifier 1 for compensating the phase of inverse amplifier 1, FET switch 5 as first switching means for switching the connection between the feedback resistor 4 and inverse amplifier 1, buffer circuit 2 based on a gain switching signal supplied, FET switch 6 as second switching means for switching between charge/discharge of phase compensation capacitor 7 based on the gain switching signal and an FET switch 9 as third switching means for switching between charge/discharge of phase compensation capacitor 7 based on a reset signal that becomes HIGH every time a preamp input signal is supplied. A signal outputted from buffer circuit 2 is outputted as a preamp output signal. The resistance values of feedback resistors 3 and 4 have a relationship: (a resistance value of the feedback resistor 3)>>(a resistance value of the feedback resistor 4)
The operation of the preamplification circuit in the above configuration will be explained below. [0031]
When a preamp input signal having a lower level than a predetermined threshold is supplied, the gain switching signal is fixed to LOW, which keeps [0032] OFF FET switch 5. As a result, feedback resistor 3 is the only feedback resistor to control the gain of inverse amplifier 1 and the signal amplified with this gain is outputted as a preamp output signal.
Here, when the preamp input signal is supplied, the reset signal becomes HIGH for every data supplied and then the data is supplied. [0033]
For this reason, even when the gain switching signal is LOW, the HIGH level of the reset signal is transmitted to the gate of [0034] FET switch 9 and FET switch 9 turns ON every time the reset signal becomes HIGH.
This causes [0035] phase compensation capacitor 7 to be charged every time the preamp input signal is supplied even when the gain switching signal is LOW, which means that the amount of discharge of phase compensation capacitor 7 will no longer increase.
Then, when the preamp input signal has a higher level than the predetermined threshold, the gain switching signal becomes HIGH, which turns ON [0036] FET switch 5. Thus, the gain of inverse amplifier 1 is controlled by feedback resistors 3 and 4 and the signal amplified with the gain is outputted as the preamp output signal. That is, the gain of inverse amplifier 1 becomes smaller than when the preamp input signal has a lower level than the predetermined threshold. As a result, inverse amplifier 1 keeps linearity without saturating.
Furthermore, the HIGH level of the gain switching signal is transmitted to the gate of [0037] FET switch 6, which turns ON FET switch 6 causing phase compensation capacitor 7 to be charged. This allows the phase of inverse amplifier 1 to be compensated. Here, even when the gain switching signal is LOW, phase compensation capacitor 7 is charged by the HIGH level of the reset signal every time the preamp input signal is supplied, preventing any high current from being pulled into inverse amplifier 1 and preventing noise from applying to the preamp output signal.
In this embodiment, FET switches [0038] 5, 6 and 9 are used as the first to third switching means, but the present invention is not limited to this and other switches can also be used.
While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the sprit or scope of the following claims. [0039]

Claims

What is claimed is:

1. A preamplification circuit, comprising:

amplifying means for amplifying and outputting an input signal;

first and second feedback resistors connected in parallel to each other between an input terminal and an output terminal of said amplifying means;

first switching means for switching a connection between said amplifying means and said second feedback resistor;

a phase compensation capacitor for compensating a phase of said amplifying means;

second switching means for changing said phase compensation capacitor when said input signal has a higher level than a predetermined threshold; and

third switching means for charging said phase compensation capacitor at predetermined timing,

wherein a gain of said amplifying means is switched by using said first and second feedback resistors or only said first feedback resistor as the feedback resistor connected to said amplifying means by the switching of said first switching means.

2. The preamplification circuit according to claim 1, wherein said third switching means charges said phase compensation capacitor based on a reset signal supplied every time said input signal is supplied.

3. The preamplification circuit according to claim 2, wherein said first and second switching means are FET switches.

4. The preamplification circuit according to claim 2, wherein said third switching means is an OR gate that controls said second switching means so that said phase compensation capacitor is charged in the case where either said reset signal is supplied or a gain switching signal that controls said second switching means when said input signal has a higher level than a predetermined threshold.

5. The preamplification circuit according to claim 3, wherein said third switching means is an OR gate that controls said second switching means so that said phase compensation capacitor is charged in the case where either said reset signal is supplied or a gain switching signal that controls said second switching means when said input signal has a higher level than a predetermined threshold.

6. The preamplification circuit according to claim 2, wherein said third switching means is an FET switch.

7. The preamplification circuit according to claim 3, wherein said third switching means is an FET switch.

8. The preamplification circuit according to claim 1, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

9. The preamplification circuit according to claim 2, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

10. The preamplification circuit according to claim 3, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

11. The preamplification circuit according to claim 4, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

12. The preamplification circuit according to claim 5, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

13. The preamplification circuit according to claim 6, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.

14. The preamplification circuit according to claim 7, wherein a resistance value of said first feedback resistor is larger than a resistance value of said second feedback resistor.