JPS6085613A - Preamplifier - Google Patents

Abstract

PURPOSE:To attain the titled preamplifier suitable for large scale circuit integration by constituting an amplifier circuit of a modulation signal with an operational amplifier, an input/output capacitor pair of set the gain of the operational amlifier and a short-circuit switch for initial setting so as to attain high accuracy of signal amplification to the gain setting in response to a wide range of signal level. CONSTITUTION:A timing (c) is set during time t1-T2 prior to timings a, b, switches 22-29 are turned on so as to apply initial setting to capacitors 81-84 and 87-90, that is, to discharge an electric charge stored in the capacitors due to leakage, thereby eliminating the effect of a leakage current. A polarity switching circuit 100 sets the timing (a) during time t2-t3 succeedingly, the timing (b) is set during t3-t4, the polarity of an input signal is inverted alternately at the two time sections, the input signal is modulated into a high frequency signal near the frequency of the timings a, b and the result is inputted to an amplifier 101. The gain of the amplifier circuit 101 is a product of the gain of the 1st amplifier stage comprising two non-inverting amplifiers and the 2nd amplifier stage comprising a differential amplifier.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a preamplifier for amplifying a wide range of signal levels. Regarding suitable preamplifiers. [Background of the Invention] Normally, when dealing with a wide range of input ranges for a wide variety of sensors, it is common to install 1x preamplifiers. In this case, the preamplifier must have a gain that can be set arbitrarily, a very high input impedance, and can perform highly accurate signal amplification. A preamplifier with such characteristics
In order to implement LsI, it is necessary to have a circuit configuration suitable for LSI technology. An example of a circuit to deal with these problems is shown in FIG. A polarity conversion circuit 100 that switches and modulates the polarity of the input signal using a switch 2.0.21, and monolithic capacitors 81 to 8 that are relatively easy to achieve accuracy on an LSI for gain setting.
4, 87 to 90 are all used, switches 22 to 27 are provided to set the initial value of each capacitor, and the modulation signal is set to the first
and an amplifier circuit l that performs amplification r with a two-stage configuration of a second amplification stage.
O1, a sample hold circuit 102 that holds the output signal of the amplifier circuit 101 at the timing of the switch 6υQ, and this holding type EE: a rectifier type switch that demodulates in synchronization with the polarity of the input signal using all the switches 61 and 62 and the capacitor 71. Consisting of a capacitor circuit 103 and a current-voltage conversion circuit 104 that smoothes the charging and discharging current of the capacitor 71 and converts it into a heavy voltage, the valley switches 20 to 27.60
~63 are the timing signals a, h''''C''C in Fig. 2
Operation Note that the timing signals a to h in FIG. 2 correspond to the symbols of the contacts in FIG. 1, and indicate that the corresponding contact is connected to the movable piece when the timing signal is on. Due to this circuit operation, as shown in FIG. 2, the input signal has a voltage waveform of k at the output of the amplifier circuit 101, the output of the 11-sample hold circuit 102, and the j1 current-voltage conversion circuit 104. If these waveforms look like solid lines, it means that a signal that does not correspond to the input signal is obtained, and if the waveforms look like dotted lines,
This shows that a signal corresponding to the input signal is obtained. In other words, distortion occurs in signal amplification. In this way, the reason why the waveform does not look like the dotted line is that in the amplifier circuit 101, when the signal amplification (C advance timing signal C is on (when both timing signals a and b are off), the initial value setting switches 22 to 27 As a result, the output of the amplifier circuit is initially set to 1 and 0 as shown in i in Fig. 2. However, when switching to signal amplification, the output of the initial value setting switch and the capacitor 81 without an initial value setting switch are set. ,82°8
As a result of the charge being accumulated at 7.88, an offset occurs as an amplifier circuit. The input/output relational expression of the amplifier circuit in this state is that the voltages applied to input terminals 1 and 2 are V, V2,
, the voltage obtained at terminal i is Vo, the capacitor 81.82
The capacitance of is Cm, the capacitance of capacitor 83.84'kc,
, the capacitance of the capacitor 8788 (Il-C5, the capacitance kct of the capacitor 89.90, the difference numerator of the amount accumulated in the capacitor 81.82 and resulting in an offset Va t
t + + capacitors 87 and 88 respectively, and the offset becomes the fit) difference (ll-vo, t2 torque, ...... (2). In other words, the first term is The term in which the input signal V2-■ is amplified by the set gain, the second and third terms are off-cellar)
Vott, +t is the term amplified by the set gain. now,
Considering the case where there is a negative offset, the input signal is amplified at the center of the negative offset (k) from equation (I). On the other hand, since it has a custom input/output like the general amplifier circuit Vi, No. 3178I, it has a negative offset
When an input signal 'Tf V H is applied to the amplifier circuit, the output V. The positive amplitude is amplified in the linear region, but the negative amplitude is amplified from the linear to the saturation region, resulting in a distorted nonlinear waveform V. Therefore, it becomes impossible to obtain an output corresponding to the input with high precision in the linear region. As can be seen from equation (1), this tendency is true as the gain of the amplifier circuit increases. That is, the closer the level of the input signal and the offset are, the more serious the problem becomes. In this case, the capacitor specified by the amplifier circuit is charged and discharged due to leakage, etc.
The initial setting switch is provided to prevent drift i from occurring during signal amplification and causing the amplification circuit to deviate from its operating range.
This causes an excessive amount of off-cellarity to occur, and as a result, it becomes difficult for the amplifier circuit to operate in the linear region, which prevents the amplifier circuit from achieving highly accurate signal amplification. [Object of the Invention] An object of the present invention is to provide a preamplifier which is capable of highly accurate signal amplification with respect to output settings corresponding to a wide range of signal levels and is suitable for LSI implementation. [Summary of the Invention] The present invention provides a polarity switching circuit that periodically switches the polarity of an input signal, an amplifier circuit that fully amplifies the output signal of the polarity switching circuit, and a sample hold circuit that holds the output voltage of the amplifier circuit. In a device amplifier consisting of a rectifying switched capacitor circuit that rectifies the output voltage of this sample and hold circuit while inverting the polarity of the charge transmitted to the capacitor in synchronization with the switching period of the polarity switching circuit. The circuit consists of an operational amplifier, an input and feedback capacitor for variable gain setting, one of the capacitor pairs, and a discharge switch for initial value setting provided at the terminal to which all output signals of the polarity switching circuit are applied at the input of the operational amplifier. A switch is provided on the other of the pair of capacitors of the operational amplifier to eliminate the influence of the discharge switch for setting the initial value,
Should it operate at the same timing as the discharge switch for initial value setting? Features. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 4 shows an embodiment of the present invention, and FIG. 5 is an operation time chart thereof. In FIG. 4, the polarity switching disconnection io
The amplifier circuit 101 includes a capacitor 81, 83 and an operational amplifier l.
A positive phase amplifier consisting of capacitors 82 and 84 and operational amplifier 11, a differential amplifier consisting of capacitors 87 to 90 and operational amplifier 12, and an initial phase amplifier of each capacitor. Value setting switch 22~
27 and a switch 28.29 of a capacitor 81.82. The sample and hold circuit 102 is composed of a switch 60, a capacitor 70, and an operational amplifier 13, and the rectifying switched capacitor circuit 103 is composed of two-make switches 61 and 62 and a capacitor 71.
Further, the current-voltage conversion circuit 104 includes a capacitor 72, a resistor 73, and an operational amplifier 14. Each of the above-mentioned switches is actually realized by a switching element such as a MOS (MOS) synristor. The operating sound of the above circuit will be explained using the time chart shown in FIG. The timing signals a to h in FIG. 5 correspond to the symbols of the contacts of each switch 20 to 29 and 60 to 62 in FIG. 4, and indicate that the corresponding contact is connected to the movable piece when the timing signal is on. [There are 7. The frequency of the timing signals a and b (having the same period) of the polarity switching switches 20 and 21 is the same as that of the input signal (not shown).
．． sufficiently higher than the highest frequency component of (applied between 2),
It is assumed that by this switching, the input signal is shifted to a high frequency band near the frequencies of the timing signals a and b without distortion. Therefore, in the range of the horizontal axis (time axis) in FIG. 6, the input signal can be considered to be approximately direct current. Therefore, first, prior to timings a and b (timing signals are simply abbreviated as timings. The same applies hereinafter), the switch 22 is turned on between timing Cf and time t1 to t2.
~29 is turned on and capacitors 81~84.87~90
In other words, the current accumulated in the capacitor due to leakage etc. is discharged to remove the influence of the leakage current. During this period from t to t2, timings a and b are both off. Subsequently, in the polarity switching circuit 100, the timing a'ff is on from time t2 to t8, and the timing b is fully on from 13 to 1°, and the polarity of the input signal is alternately inverted during these two time periods. The signal is modulated into a high frequency signal near the frequencies of timings a and b, and is input to the amplifier circuit 101. Therefore, the input impedance seen from the input signal side is
It is equal to the input impedance of operational amplifier 10.11, which is MOS) transistor gold operational amplifier 10°11
If used for the first stage, it can be set to a sufficiently large value. The gain of the tqq width circuit 101 is the sum of the gains of a first amplification stage made up of two positive-phase amplifiers and a second amplification stage made up of a differential amplifier. The gain of the amplifier in the first amplification stage, 01, is expressed as follows, where the capacitance of the input capacitor 81.82 is r-1, and the capacitance of the feedback capacitor 83.84 is 07, and the gain of the second amplification stage is 02 &. Capacity Iff of input capacitor 87.88 Basin Cl % If the capacitance of feedback capacitor 89.90 is Cf, it is expressed as follows, so the gain G of the amplifier circuit 101 is as follows. Therefore, in the amplifier circuit 101 as a whole, the modulated high frequency signal is amplified by a factor of 2G and output. Then, this output waveform i becomes almost inverted in polarity during the ON periods of timings a and b (as mentioned above, there is almost no change in the input signal within the range shown in Figure 5), and at timing C, becomes 0. Next, this output voltage i is sampled at timing d and held in the sample hold circuit 102. Timing d is time tI in FIG. 5 when timings a and b are off.
+ 13 r If it is turned on just before '4..., the value indicated by the circle on waveform i will be sampled, so
The output of the sample and hold circuit 102 has a waveform shown in FIG. The rectifying switched capacitor circuit 103 operates at the timing C+ f+ -g*h shown in FIG. Of these, timings e and f are always turned on with opposite phases to each other,
The same applies to timings g and h. However, the timing
, h have opposite phases when timing a is on and when timing b is on. Then, while timing a is on, timings e and h are in phase, and timing f1g is in phase, so that the charges sampled and accumulated in the capacitor 71 by input signal i when timings e and h are on are the same at the following timing f1g. , are applied to the current-voltage conversion circuit 104 with polarity opposite to that of the input signal i. Also, while timing b is on, timing e1g is in phase, timing f and h
are in phase, so the switched capacitor circuit 103 in this case is equivalent to a normal resistor, as is well known, and a sampled signal with the same polarity as the input signal 1 is applied to the current-voltage conversion circuit 104. be done. Therefore, the output of the current-voltage conversion circuit 104 is a demodulated signal modulated at timings a and b by the polarity switching circuit 100 and amplified by the amplifier circuit 101, and a desired output signal is obtained. Here, the current-voltage conversion circuit 104 has a capacitor 72 and a resistor 73 inserted in its feedback loop, and converts the output current of the capacitor 71 into an XF-slip so that it can be used as a voltage. That is, the output current 'f of the capacitor 71: 1. e. Switched capacitor frequency 'f: f, cosonator 7
The capacitance of 2 is Ct, the resistance is 73 gold RL, and C1R4>'
1/f, in the current-voltage conversion circuit 104, Iga"
It is converted into a voltage Rt. According to this method, the switches 22 to 27 are charged and discharged by each of the capacitors 81 to 84 and 87 to 90 that determine the gain of the amplifier circuit 101, and the switches 22 to 27 are used to prevent the amplifier circuit 101 from deviating from the linear operating region. In addition, since the capacitors 81 and 82 are also provided with switches 28 and 29i, the initial value setting can be made completely stable during the period of timing C and at the time of switching (when switches 22 to 29 are turned off). . In other words, the charges accumulated in the capacitors 81 and 82 due to the influence from the initial value switch are reduced by the switches 28 and 29.
By reducing the influence of offset on the amplifier circuit, the output amplification of the amplifier circuit 101 can operate in a linear region. In addition, in the above explanation, the on periods of the timing signals c-11 shown in FIG. 5 tend to overlap,
It's actually better to avoid duplication. Also, since the sample and hold circuit 102i is used, the timing g
, h are switched according to the timings a and b as described in FIG.
This is extremely advantageous in terms of design since it can be selected independently of the However, if timings a and b and timings C to 11 are completely synchronized, the sample hold circuit +02'
can be omitted. However, the above-mentioned current-voltage conversion circuit 104 can also be omitted if the current output is used as the IF signal. Further, although the output modulation signal of the amplifier circuit 101 is demodulated (rectified) by the sample hold circuit 102 and the switched capacitor 103, it can be realized by other circuits.゛ According to the above embodiment, by removing the top of the offset in the second term of equation (1) that most affects the output, the initial value setting switch of the gain setting capacitor of the first amplification stage of the amplifier circuit can be adjusted. It is possible to effectively eliminate the influence of An embodiment of the amplification circuit 101 shown in FIG. 4, which is intended to achieve even more accurate signal amplification, will be described below. FIG. 6 shows another embodiment of the amplifier circuit 101 shown in FIG. 4, which differs from the amplifier circuit 101 shown in FIG. are different. In this case, since the influence of the switch on the capacitor can be removed even in the second amplification stage of the amplifier circuit, the output amplitude can be controlled within the linear region even in high-gain signal amplification. That is, in FIG. 6, the influence of the offset in the second and third terms of equation (1) is reduced. Next, FIG. 8 shows, as another embodiment of the present invention,
Another basic form of the amplifier circuit 101 is shown. Usually, L.S.
The capacitor line on I, as shown in the equal circuit in Figure 7,
This is a structure in which a parasitic capacitance 219 is added. Therefore, in this embodiment, the ground side of the input capacitors 81 and 82 for setting the gain of the first amplification stage of the amplifier circuit shown in FIG. 4 is connected to the parasitic capacitor 99.
f! The structure is such that it is grounded through C. Even in this configuration, the gain of the amplifier circuit is expressed similarly to equation (3), indicating that parasitic capacitance does not affect the gain. By providing the second amplification stage at both ends of the input capacitor, the output of the amplification circuit can operate in the linear region as in FIG. 6. Although the explanation has been given so far with a constant gain, a circuit configuration in which variable gain can be set can also be realized in FIGS. 4, 6, 8, etc. In the figure, 105 and 106 are input terminals of the amplifier circuit, and 10
7 is the output terminal of the amplifier circuit, 30.31 is the switch, 21
8 is the regular capacity. [Effects of the Invention] According to the present invention, since the influence of the initial value setting switch of the gain setting capacitor can be removed, highly accurate signal amplification in the linear region is possible, and the preamplifier is suitable for T and SI. can be realized.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional preamplifier, Figure 2 is an operation time chart of the circuit in Figure 1, Figure 3 is an input/output characteristic diagram of a general preamplifier, and Figure 4 is a diagram of the circuit of the present invention. A circuit diagram of one embodiment of the preamplifier, FIG. 5 is an operation time chart of the embodiment of FIG. 4, and FIGS. 6 and 8 are circuit diagrams of other embodiments of the amplifier circuit of FIG. 4, respectively. Fig. 7 is an equivalent circuit diagram of a monolithic capacitor.
--1111 Takuq product

Claims (1)

[Claims] 1. A polarity switching circuit for converting an input signal into a modulation signal by switching the polarity of the input signal using a switching timing signal that changes the polarity of the input signal at all cycles; an amplification circuit for the modulation signal; and an output modulation circuit for the amplification circuit. In a preamplifier consisting of a signal demodulation circuit, the amplification circuit includes an operational amplifier and a gain of the operational amplifier. A preamplifier comprising a pair of input and feedback capacitors for setting, and a short-circuit switch for initial value setting provided at both of the capacitor pair and at a terminal to which the modulation signal of the operational amplifier is applied. . 2. The demodulation circuit includes a sample and hold circuit that holds the output modulation signal of the amplifier circuit, and an output signal of this sample and hold circuit. 2. The preamplifier according to claim 1, further comprising a switched capacitor circuit that performs demodulation by controlling the timing and polarity of charging and discharging a capacitor.