US20020016045A1 - Method for forming capacitor of semiconductor device - Google Patents

Method for forming capacitor of semiconductor device Download PDF

Info

Publication number
US20020016045A1
US20020016045A1 US09/867,658 US86765801A US2002016045A1 US 20020016045 A1 US20020016045 A1 US 20020016045A1 US 86765801 A US86765801 A US 86765801A US 2002016045 A1 US2002016045 A1 US 2002016045A1
Authority
US
United States
Prior art keywords
film
forming
lower electrode
lpcvd
ranging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/867,658
Other versions
US6410381B2 (en
Inventor
Kyong Min Kim
Kyung Cheol Jeong
Han Sang Song
Dong Jun Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEONG, KYUNG CHEOL, KIM, DONG JUN, KIM, KYONG MIN, SONG, HAN SANG
Publication of US20020016045A1 publication Critical patent/US20020016045A1/en
Application granted granted Critical
Publication of US6410381B2 publication Critical patent/US6410381B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Memories (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device which can increase a capacitance and prevent a leakage current at the same time. The method includes the steps of depositing a cap oxide film on a semiconductor substrate, patterning the cap oxide film to expose a capacitor region of the semiconductor substrate, consecutively depositing an Ru film for a lower electrode on the patterned cap oxide film and the semiconductor substrate in in-situ according to a low pressure chemical vapor deposition(LPCVD) and a plasma enhanced chemical vapor deposition(PECVD), forming a cylindrical lower electrode, by performing a chemical mechanical polishing process on the Ru film and removing the cap oxide film, forming an amorphous TaON film having a high dielectric constant on the lower electrode, crystallizing the amorphous TaON film according to a thermal treatment, and forming a metal film for an upper electrode on the crystallized TaON film.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims priority from Korean Patent Application No. 2000-30090, filed Jun. 1, 2000, the entirety of which is incorporated herein by reference. [0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to a method for forming a capacitor of a semiconductor device, and in particular to an improved method for forming a capacitor of a semiconductor device which can increase a capacitance and prevent a leakage current at the same time. [0003]
  • 2. Description of the Background Art [0004]
  • The capacitance of a capacitor used as a data storage unit in the semiconductor device is dependent upon the area of the electrode, the gap between the electrodes and a dielectric constant of a dielectric film inserted between the electrodes. However, semiconductor devices have become highly integrated. Accordingly, the capacitor formation region of the semiconductor device has decreased, and thus the area of the electrode of the capacitor has also decreased, thereby reducing the capacitance of the capacitor. [0005]
  • Therefore, in a capacitor having a structure of metal film—dielectric film—metal film (MIM), an Ru film is deposited as a lower electrode, a TaON film having a high dielectric constant is deposited thereon, and a metal film is deposited on the dielectric film, thereby maximizing the capacitance of the TaON capacitor. [0006]
  • FIGS. 1 and 2 are cross-sectional diagrams illustrating sequential steps of a conventional method for forming a capacitor of a semiconductor device. [0007]
  • As illustrated in FIG. 1, a semiconductor substrate(not shown) including a MOSFET is provided. Here, a [0008] polysilicon film 5 for a plug and a barrier metal film 6 consisting of a Ti/TiN film are sequentially stacked on an interlayer insulation film 4 having a contact hole(not shown) exposing one of the junction regions of the MOSFET(not shown).
  • A cap oxide film [0009] 7 is deposited on the semiconductor substrate 2 in order to form a cylindrical capacitor.
  • Thereafter, the cap oxide film [0010] 7 is patterned to define a capacitor region and expose the interlayer insulation film 4 and the barrier metal film 6.
  • An [0011] Ru film 8 for a lower electrode is deposited over the patterned cap oxide film 7 a. When the metal film is used as the lower electrode, a leakage current property may be improved according to quality of the lower electrode.
  • In addition, the [0012] Ru film 8 may be deposited as the lower electrode according a chemical vapor deposition (CVD), a physical vapor deposition (PVD), a low pressure chemical vapor deposition (LPCVD) and a plasma enhanced chemical vapor deposition (PECVD).
  • When the Ru [0013] film 8 is deposited according to the CVD, a deposition rate of the Ru film 8 is slow on the cap oxide film 7 a, and the surface of the Ru film 8 is inferior. It is thus difficult to apply the CVD to the actual process.
  • On the other hand, when the Ru [0014] film 8 is deposited according to the PECVD, the quality of the film is superior, but a step coverage, namely a deposition state is inferior. Accordingly, the PECVD is not suitable for the method for forming the capacitor.
  • When the Ru [0015] film 8 is deposited according to the LPCVD, the step coverage is superior, but the quality of the film is reduced, as compared with the PECVD.
  • As a result, the [0016] Ru film 8 is deposited according to the PVD, and re-deposited according to the CVD, thereby improving the deposition rate and quality of the Ru film 8.
  • Referring to FIG. 2, a chemical mechanical polishing process is performed on the [0017] Ru film 8 for the lower electrode, and the cap oxide film 7 a is removed, thereby forming an Ru film 8 a which is a cylindrical lower electrode. A TaON film 9 having a high dielectric constant is formed on the cylindrical Ru film 8 a, and an upper electrode 10 is formed on the TaON film 9, thereby forming the capacitor of the semiconductor device.
  • However, the conventional method for forming the capacitor of the semiconductor device has the following disadvantages. [0018]
  • When the Ru film is deposited as the lower electrode, the deposition rate and quality of the Ru film can be improved by depositing the Ru film according to the PVD, and re-depositing the Ru film according to the CVD. However, such a deposition process cannot be performed in in-situ, and thus an impurity may be put on the wafer surface during a transfer from one chamber to another chamber. [0019]
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention provides a method for forming a capacitor of a semiconductor device which can improve a film quality of a lower electrode. [0020]
  • Additionally, the present invention provides a method for forming a capacitor of a semiconductor device which can obtain a high capacitance and a low leakage current at the same time. [0021]
  • The present invention thus provides a method for forming a capacitor of a semiconductor device, including the steps of depositing a cap oxide film on a semiconductor substrate; patterning the cap oxide film to expose a capacitor region of the semiconductor substrate; consecutively depositing an Ru film for a lower electrode on the patterned cap oxide film and the semiconductor substrate in in-situ according to a low pressure chemical vapor deposition and a plasma enhanced chemical vapor deposition; forming a cylindrical lower electrode, by performing a chemical mechanical polishing process on the Ru film and removing the cap oxide film; forming an amorphous TaON film on the lower electrode; crystallizing the amorphous TaON film according to a thermal treatment; and forming a metal film for an upper electrode on the crystallized TaON film. [0022]
  • In addition, there is provided a method for forming a capacitor of a semiconductor device, including the steps of depositing a cap oxide film on a semiconductor substrate; patterning the cap oxide film to expose a capacitor region of the semiconductor substrate; consecutively depositing an Ru film for a lower electrode on the patterned cap oxide film and the semiconductor substrate in in-situ according to a low pressure chemical vapor deposition and a plasma enhanced chemical vapor deposition; forming a cylindrical lower electrode, by performing a chemical mechanical polishing process on the Ru film and removing the cap oxide film; forming an amorphous TaON film on the lower electrode; performing a plasma treatment on the amorphous TaON film; crystallizing the amorphous TaON film according to a thermal treatment such as an RTP; and forming a metal film for an upper electrode on the crystallized TaON film.[0023]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: [0024]
  • FIGS. 1 and 2 are cross-sectional diagrams illustrating sequential steps of a conventional method for forming a capacitor of a semiconductor device; and [0025]
  • FIGS. 3, 4, [0026] 5, and 6 are cross-sectional diagrams illustrating sequential steps of a method for forming a capacitor of a semiconductor device in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A method for forming a capacitor of a semiconductor device in accordance with the present invention will now be described in detail with reference to the accompanying drawings. [0027]
  • FIGS. 3, 4, [0028] 5, and 6 are cross-sectional diagrams illustrating sequential steps of a method for forming the capacitor of the semiconductor device in accordance with the present invention.
  • As illustrated in FIG. 3, an [0029] interlayer insulation film 14 having a contact hole (not shown) exposing one of the junction regions is formed on a semiconductor substrate(not shown) having a MOSFET (not shown).
  • A [0030] plug polysilicon film 15 is formed on the contact hole(not shown) of the interlayer insulation film 14. The surface of the polysilicon film 15 is etched according to an etch back process using an HF solution and a buffer oxide etching agent, thereby removing a natural oxide film.
  • Thereafter, a [0031] barrier metal film 16 consisting of a Ti/TiN film is formed on the etched polysilicon film 15, thereby filling up the contact hole(not shown). A chemical mechanical polishing process is performed thereon until the interlayer insulation film 14 is exposed. A cap oxide film 17 is deposited on a resultant material(A).
  • A patterned [0032] cap oxide film 17 a is formed to define a presumed cylindrical capacitor region and to expose the interlayer insulation film 14 and the barrier metal film 16.
  • As depicted in FIG. 4, an [0033] Ru film 18 for a lower electrode is deposited on the patterned cap oxide film 17 a. Here, the Ru film 18 is consecutively deposited according to a two-step deposition method. That is, the Ru film 18 is deposited according to a low pressure chemical vapor deposition (LPCVD), and re-deposited in in-situ according to a plasma enhanced chemical vapor deposition (PECVD).
  • In the LPCVD, the [0034] Ru film 18 is partially deposited by forming tris 2,4-octanedionato Ru in a vapor state, and maintaining a temperature of the semiconductor substrate at 200 to 350° C., a flow rate of O2 reaction gas at a few tens to a few hundreds standard cubic centimeters per minute (sccm), and a pressure of a reactor at a few mTorr to a few Torr.
  • Thereafter, the [0035] Ru film 18 is partially deposited in in-situ according to the PECVD using plasma. Here, an RF power ranges from 100 to 300W, a sub heater applies the power to a ground, and a shower head applies the power to an electrode.
  • As shown in FIG. 5, the chemical mechanical polishing process is performed on the [0036] Ru film 18 for the lower electrode, and the cap oxide film is removed, thereby forming a cylindrical lower electrode 18 a.
  • An [0037] amorphous TaON film 19 having a high dielectric constant is formed on the cylindrical lower electrode 18 a. Here, the amorphous TaON film 19 is formed according to a chemical vapor deposition, for example the LPCVD. Here, Ta(OC2H5)5 is formed in a vapor state in a vaporizer having a temperature of 170 to 190° C., and NH3 having a flow rate of 10 to 1000 sccm is reacted with chemical Ta vapor in an LPCVD chamber maintaining a pressure of 0.1 to 1.2 Torr and a temperature of 300 to 400° C., and receiving NH3 gas.
  • Thereafter, N[0038] 2O plasma or UV/O3 treatment is carried out at 300 to 500° C. by considering an electric property of the capacitor.
  • Referring to FIG. 6, an rapid thermal process (RTP) process is performed on the [0039] amorphous TaON film 19 at 500 to 650° C. by using N2 gas and O2, thereby forming a crystallized TaON film 19 a. Preferably, an Ru film or TiN film is deposited on the TaON film 19 a as an upper electrode 20, and thus formation of the capacitor is finished.
  • As discussed earlier, the Ru film is consecutively deposited according to a two-step deposition method. That is, the Ru film is deposited according to the LPCVD, and re-deposited in in-situ according to the PECVD using plasma. [0040]
  • Accordingly, a deposition rate and quality of the Ru film are improved, thereby obtaining a high capacitance and a low leakage current at the same time. [0041]
  • As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims. [0042]

Claims (19)

What is claimed is:
1. A method of forming a capacitor of a semiconductor device, comprising:
providing a semiconducotor substrate;
forming a lower electrode on the semiconductor substrate, said lower electrode comprising an Ru film formed in-situ, said in-situ forming comprising in sequential order a low pressure chemical vapor deposition (LPCVD) and a plasma enhanced chemical vapor deposition (PECVD);
forming an amorphous TaON film on the lower electrode;
crystallizing the amorphous TaON film, said crystallizing comprising a thermal treatment; and
forming an upper electrode on the crystallized TaON film.
2. The method according to claim 1, wherein forming the Ru film comprises partial deposition using LPCVD and partial deposition using PECVD.
3. The method according to claim 2, wherein the partial deposition using LPCVD comprises forming tris 2,4-octanedionato Ru in a vapor state; and maintaining the semiconductor substrate at a temperature ranging from 200 to 350° C., an O2 reaction gas flow rate ranging from 20 to less than 1,000 sccm, and a reactor pressure ranging from 2 mTorr to less than 1,000 Torr.
4. The method according to claim 3, wherein the partial deposition using PECVD comprises maintaining an RF power ranging from 100 to 300 W applied between a ground of a sub heater and an electrode of a shower head.
5. The method according to claim 1, wherein the LPCVD comprises forming vapor comprising Ta by vaporizing Ta(OC2H5)5 in a vaporizer having a temperature ranging from 170 to 190° C., and reacting NH3 gas having a flow rate ranging from 10 to 1000 sccm with the vapor comprising Ta in an LPCVD chamber at a pressure ranging from 0.1 to 1.2 Torr and a temperature ranging from 300 to 400° C.
6. The method according to claim 1, further comprising, prior to said crystallizing, performing a treatment chosen from N2O plasma and UV/O3 treatments at a temperature ranging from 300 to 500° C.
7. The method according to claim 1, wherein said crystallizing comprises performing a rapid thermal process (RTP) process on the amorphous TaON film at a temperature ranging from 500 to 650° C. and using at least one of N2 and O2 gases.
8. The method according to claim 1, wherein said upper electrode comprises at least one of an Ru film and a TiN film deposited on the crystallized TaON film.
9. A method of forming a capacitor of a semiconductor device, comprising:
providing a semiconductor substrate;
forming a lower electrode on the semiconductor substrate, said lower electrode comprising an Ru film formed in-situ, said in-situ forming comprising in sequential order a low pressure chemical vapor deposition (LPCVD) and a plasma enhanced chemical vapor deposition (PECVD);
forming an amorphous TaON film on the lower electrode;
performing a plasma treatment on the amorphous TaON film;
crystallizing the amorphous TaON film, said crystallizing comprising a thermal treatment; and
forming an upper electrode comprising a metal film on the crystallized TaON film.
10. The method according to claim 9, wherein forming the Ru film comprises partial deposition using LPCVD and partial deposition using PECVD.
11. The method according to claim 10, wherein the partial deposition using LPCVD comprises forming tris 2,4-octanedionato Ru in a vapor state; and maintaining the semiconductor substrate at a temperature ranging from 200 to 350° C., a O2 reaction gas flow rate ranging from 20 to less than 1,000 sccm, and a reactor pressure ranging from 2 mTorr to less than 1,000 Torr.
12. The method according to claim 11, wherein the partial deposition using PECVD comprises maintaining an RF power ranging from 100 to 300W applied between a ground of a sub heater and an electrode of a shower head.
13. The method according to claim 9, wherein the LPCVD comprises forming vapor comprising Ta by vaporizing Ta(OC2H5)5 in a vaporizer having a temperature ranging from 170 to 190° C., and reacting NH3 gas having a flow rate ranging from 10 to 1000 sccm with the vapor comprising Ta in an LPCVD chamber at a pressure ranging from 0.1 to 1.2 Torr and a temperature ranging from 300 to 400° C.
14. The method according to claim 9, wherein the plasma treatment for the amorphous TaON film comprises at least one of an N2O plasma and a UV/O3 treatment at a temperature ranging from 300 to 500° C.
15. The method according to claim 9, wherein said crystallizing comprises a rapid thermal process (RTP) process at a temperature ranging from 500 to 650° C. using N2 gas and O2.
16. The method according to claim 9, wherein said upper electrode comprises at least one of an Ru film and a TiN film deposited on the crystallized TaON film.
17. The method according to claim 9, wherein said lower electrode is a cylindrical shape.
18. A method of forming a capacitator of a semiconductor device, comprising:
providing a semiconductor substrate;
forming a lower electrode on the semiconductor substrate, said lower electrode comprising an Ru film formed in-situ, said in-situ forming comprising in sequential order a low pressure chemical capor deposition (LPCVD) and a plasma enhanced chemical vapor deposition (PECVD);
forming an amorphous TaON film on the lower electrode;
performing a plasma treatment on the amorphous TaON film, said performing a plasma treatment comprising at least one of an N2O plasma and a UV/O3 treatment at a temperature ranging from 300 to 500° C.;
crystallizing the amorphous TaON film, said crystallizing comprising a thermal treatment; and
forming an upper electrode comprising a metal film on the crystallized TaON film, said upper electrode comprising at least one of an Ru film and a TiN film.
19. The method according to claim 18, wherein said crystallizing comprises ad rapid thermal process (RTP) at a temperature ranging from 500 to 600° C. using N2 gas and O2.
US09/867,658 2000-06-01 2001-05-31 Method for forming capacitor of semiconductor device Expired - Fee Related US6410381B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020000030090A KR100587048B1 (en) 2000-06-01 2000-06-01 Method for manu facturing capa citor in semiconductor memory divice
KR2000-30090 2000-06-01

Publications (2)

Publication Number Publication Date
US20020016045A1 true US20020016045A1 (en) 2002-02-07
US6410381B2 US6410381B2 (en) 2002-06-25

Family

ID=19671014

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/867,658 Expired - Fee Related US6410381B2 (en) 2000-06-01 2001-05-31 Method for forming capacitor of semiconductor device

Country Status (3)

Country Link
US (1) US6410381B2 (en)
JP (1) JP4399845B2 (en)
KR (1) KR100587048B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150194601A1 (en) * 2014-01-04 2015-07-09 Sony Corporation Interfacial cap for electrode contacts in memory cell arrays
US20160197136A1 (en) * 2015-01-06 2016-07-07 Se Hoon Oh Semiconductor devices including capacitors and methods for manufacturing the same

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618682B1 (en) * 2000-06-01 2006-09-06 주식회사 하이닉스반도체 Method for manufacturing capacitor in semiconductor memory divice
KR100587047B1 (en) * 2000-06-01 2006-06-07 주식회사 하이닉스반도체 Method for manufacturing capac itor in semiconductor memory divice
KR100464938B1 (en) * 2000-12-22 2005-01-05 주식회사 하이닉스반도체 A method for forming capacitor using polysilicon plug structure in semiconductor device
KR100418580B1 (en) * 2001-06-12 2004-02-21 주식회사 하이닉스반도체 Method of forming a capacitor of a semiconductor device
KR100417859B1 (en) * 2001-09-13 2004-02-05 주식회사 하이닉스반도체 mehtod for fabricating capacitor
KR100417860B1 (en) * 2001-09-13 2004-02-05 주식회사 하이닉스반도체 mehtod for fabricating capacitor
KR100440073B1 (en) * 2001-12-10 2004-07-14 주식회사 하이닉스반도체 A method for forming a capacitor of a semiconductor device
KR100408725B1 (en) * 2001-12-10 2003-12-11 주식회사 하이닉스반도체 A method for forming a capacitor of a semiconductor device
KR100450470B1 (en) * 2001-12-20 2004-10-01 주성엔지니어링(주) Ru thin film forming method using plasma enhanced process
KR100478480B1 (en) * 2002-07-30 2005-03-28 동부아남반도체 주식회사 Semiconductor device and fabrication method of thereof
KR20050070939A (en) * 2003-12-31 2005-07-07 동부아남반도체 주식회사 Capacitor of semiconductor device and its fabricating method
KR100668957B1 (en) * 2003-12-31 2007-01-12 동부일렉트로닉스 주식회사 Method for fabricating MIM capacitor
KR100669655B1 (en) * 2003-12-31 2007-01-15 동부일렉트로닉스 주식회사 Capacitor of semiconductor device and its fabricating method
KR100613281B1 (en) * 2004-06-07 2006-08-22 동부일렉트로닉스 주식회사 Fabrication method of thin film capacitor
US8319313B1 (en) 2004-10-26 2012-11-27 Marvell Israel (M.I.S.L) Ltd. Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds
US7456655B1 (en) 2005-05-16 2008-11-25 Marvell Israel (Misl) Ltd. System and process for overcoming wire-bond originated cross-talk

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5840897A (en) * 1990-07-06 1998-11-24 Advanced Technology Materials, Inc. Metal complex source reagents for chemical vapor deposition
JP3319138B2 (en) * 1994-03-17 2002-08-26 ソニー株式会社 Method of forming high dielectric film containing tantalum
KR950034588A (en) * 1994-03-17 1995-12-28 오가 노리오 Tantalum high dielectric material and formation method of high dielectric film and semiconductor device
CN1054702C (en) * 1995-06-26 2000-07-19 现代电子产业株式会社 Method for producing semiconductor device capacitor
KR100330572B1 (en) * 1995-06-30 2002-11-23 주식회사 하이닉스반도체 Method for forming capacitor in semiconductor device
KR0159013B1 (en) * 1995-06-26 1998-12-01 김주용 Capacitor fabrication method of semiconductor device
KR970030818A (en) * 1995-11-06 1997-06-26 김주용 Capacitor Manufacturing Method of Semiconductor Device
US5879985A (en) * 1997-03-26 1999-03-09 International Business Machines Corporation Crown capacitor using a tapered etch of a damascene lower electrode
GB2326279B (en) * 1997-06-11 2002-07-31 Hyundai Electronics Ind Method of forming a capacitor of a semiconductor device
JPH1174487A (en) * 1997-06-30 1999-03-16 Fujitsu Ltd Semiconductor device and manufacture thereof
JP3112073B2 (en) * 1997-11-13 2000-11-27 日本電気株式会社 Method for manufacturing semiconductor device
JPH11354751A (en) * 1998-06-04 1999-12-24 Toshiba Corp Semiconductor device, its manufacture, and semiconductor manufacturing device
JP2000058529A (en) * 1998-08-12 2000-02-25 Hitachi Electron Eng Co Ltd Chemical vapor deposition device and manufacture of semiconductor device
KR100389913B1 (en) * 1999-12-23 2003-07-04 삼성전자주식회사 Forming method of Ru film using chemical vapor deposition with changing process conditions and Ru film formed thereby
KR100367404B1 (en) * 1999-12-31 2003-01-10 주식회사 하이닉스반도체 Method of forming capacitor with multi-layered TaON dielectic layer
KR100415516B1 (en) * 2000-06-28 2004-01-31 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
KR100414948B1 (en) * 2000-06-30 2004-01-14 주식회사 하이닉스반도체 Method of forming a capacitor in a semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150194601A1 (en) * 2014-01-04 2015-07-09 Sony Corporation Interfacial cap for electrode contacts in memory cell arrays
US9306162B2 (en) * 2014-01-04 2016-04-05 Sony Corporation Interfacial cap for electrode contacts in memory cell arrays
US20160197136A1 (en) * 2015-01-06 2016-07-07 Se Hoon Oh Semiconductor devices including capacitors and methods for manufacturing the same
US9923047B2 (en) * 2015-01-06 2018-03-20 Samsung Electronics Co., Ltd. Method for manufacturing a capacitor for semiconductor devices

Also Published As

Publication number Publication date
US6410381B2 (en) 2002-06-25
KR20010108994A (en) 2001-12-08
KR100587048B1 (en) 2006-06-07
JP2002057224A (en) 2002-02-22
JP4399845B2 (en) 2010-01-20

Similar Documents

Publication Publication Date Title
US6410381B2 (en) Method for forming capacitor of semiconductor device
US6673668B2 (en) Method of forming capacitor of a semiconductor memory device
US6767806B2 (en) Method of forming a patterned substantially crystalline ta2o5 comprising material, and method of forming a capacitor having a capacitor dielectric region comprising substantially crystalline ta2o5 comprising material
US20040125541A1 (en) Capacitor having oxygen diffusion barrier and method for fabricating the same
US6607963B2 (en) Method for forming capacitor of semiconductor device
US6319765B1 (en) Method for fabricating a memory device with a high dielectric capacitor
US6777740B2 (en) Capacitor for semiconductor memory device and method of manufacturing the same
US6365487B2 (en) Method of manufacturing a capacitor in a semiconductor device
US6835658B2 (en) Method of fabricating capacitor with hafnium
US20020011620A1 (en) Capacitor having a TaON dielectric film in a semiconductor device and a method for manufacturing the same
US6635524B2 (en) Method for fabricating capacitor of semiconductor memory device
US6372667B1 (en) Method of manufacturing a capacitor for semiconductor memory devices
KR100671604B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR100379528B1 (en) Capacitor and method for fabricating the same
US6306666B1 (en) Method for fabricating ferroelectric memory device
KR100353540B1 (en) Method for manufacturing capacitor in semiconductor device
US6762090B2 (en) Method for fabricating a capacitor
KR100424715B1 (en) Method of manufacturing capacitor in semiconductor device
KR100559720B1 (en) Method of manufacturing a capacitor in a semiconductor device
US6716717B2 (en) Method for fabricating capacitor of semiconductor device
KR100587047B1 (en) Method for manufacturing capac itor in semiconductor memory divice
KR100440777B1 (en) Method of manufacturing capacitor in semiconductor device
KR20020052846A (en) Method for fabricating semiconductor device
KR20050122072A (en) Method of manufacturing capacitor for semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, KYONG MIN;JEONG, KYUNG CHEOL;SONG, HAN SANG;AND OTHERS;REEL/FRAME:012203/0683

Effective date: 20010904

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140625