US20020013879A1 - Flash memory array access method and device - Google Patents
Flash memory array access method and device Download PDFInfo
- Publication number
- US20020013879A1 US20020013879A1 US09/271,444 US27144499A US2002013879A1 US 20020013879 A1 US20020013879 A1 US 20020013879A1 US 27144499 A US27144499 A US 27144499A US 2002013879 A1 US2002013879 A1 US 2002013879A1
- Authority
- US
- United States
- Prior art keywords
- block
- conversion information
- logical address
- memory array
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
Definitions
- the present invention is directed to flash memory array access method and device, and in particular to an improved flash memory array access method and device capable of reducing a search time between a logical address from a host and a physical address and improving an access time of the memory.
- Modern computer systems or digital systems utilize a memory such as a hard disk.
- the hard disk is heavy in weight, has large capacity and consumes a significant amount of electricity.
- a flash electrically erasable programmable read only memory EEPROM has been popularly used as a memory device capable of overcoming the aforementioned disadvantages.
- the flash EEPROM is reprogrammable, and thus it can be used for updating software connected with system operation.
- the flash EEPROM is only reprogrammable after its entire memory array is erased. That is, the flash EEPROM cannot be reprogrammed before being erased.
- the flash EEPROM is erased by simultaneously applying a high voltage to source terminals of all transistors (cells) used in the memory.
- the time to perform this erasure is relatively long. Therefore, in order to efficiently perform an erase operation, the memory array is divided into a plurality of blocks, and then memory elements in a corresponding block can be separately erased.
- the respective blocks include at least two or more sectors that are also managed by the host. Each sector has a user region and an overhead region. The overhead region serves to store the erase frequency information such as an erase cycle frequency.
- FIG. 1 is a schematic block diagram illustrating how a memory array constituted by using a conventional flash EEPROM is utilized.
- the memory array 1 of the conventional flash EEPROM receives a logic address from the host (not illustrated) and generates the physical address corresponding to the logical address.
- a control unit 2 accessing the memory array 1 and providing a data to the host is used.
- the control unit 2 includes: an address conversion block 3 , which stores a lookup table determining the relationship between the logical address and the physical address, a first database listing the amount of free space in each block of the memory array 1 and the total amount of free space, and a second database listing the amount of invalid data in each block and the total amount of invalid data; and a memory control unit 4 providing the received physical address to the memory array 1 and further providing or receiving a data or table information to or from the memory array 1 .
- an address conversion block 3 which stores a lookup table determining the relationship between the logical address and the physical address
- a first database listing the amount of free space in each block of the memory array 1 and the total amount of free space
- a second database listing the amount of invalid data in each block and the total amount of invalid data
- a memory control unit 4 providing the received physical address to the memory array 1 and further providing or receiving a data or table information to or from the memory array 1 .
- the previously-stored block containing that data is not erased, but the data is sequentially stored in a vacant space in the memory array.
- the previously-stored data is managed as invalid data, the block containing the data is erased afterward, and thus it is necessary to determine the relationship between the logical address managed by the host and the physical address.
- the address conversion block 3 is utilized for such a process.
- the memory control unit 4 serves to control read and output, write or erase operations of the information connected with the sectors in the blocks where the physical address is designated.
- the plurality of blocks (not illustrated) composing the memory array 1 respectively include a separate region having the table information as in the lookup table stored by the address conversion block 3 .
- the read and output operation is started when the control unit 2 illustrated in FIG. 1 receives the logical address from the host.
- a microprocessor (not illustrated) of the control unit 2 refers to the lookup table of the address conversion block 3 and obtains the physical address pursuant to the relationship between the logical address and the physical address. If there is a corresponding physical address, a valid data included in the physical sector is outputted to the host by using the physical address.
- the write operation will now be explained.
- the host provides the logical address to the control unit 2 illustrated in FIG. 1, as in the read and output operation.
- the corresponding physical address is firstly obtained by referring to the lookup table.
- the lookup table information that corresponds to the provided logical address is invalidated, the first and second databases are updated, and whether a sector which is not presently used in the lookup table exists is determined (i.e., a physical address with no associated logical address).
- a sector which is not presently used in the lookup table exists is determined (i.e., a physical address with no associated logical address).
- the data transmitted from the host is written in a physical position of the corresponding sector.
- the data can be read afterward by updating the lookup table for the sector.
- the lookup table information that corresponds to the provided logical address is still invalidated and the first and second databases updated. However, the remainder of the write operation is carried out after the erase operation.
- the erase operation will now be explained.
- the block that does not have valid data or has the least amount of valid data is selected using the second database. Selection of the block for erasure can also depend on the number of erasures each block has undergone such as described in U.S. Pat. No. 5,341,339.
- the erase operation is performed on the block that will be erased, and then the remainder of the write operation is carried out.
- the erase operation is performed by applying, for example, a voltage of 12V to a source of a floating-gate field-effect transistor composing the memory cell.
- the valid data is transmitted to a portion of the memory array 1 set aside for dealing with part of the erase operation. Then, the corresponding lookup table and table information are amended and the erase operation is carried out. Subsequently, the remainder of the write operation takes place.
- the lookup table is very important in using the memory in the conventional art.
- the conventional method has a disadvantage in that it takes relatively long time to carry out the read and output operation or to search the lookup table for obtaining the physical address of the sector that the host will access.
- the method and device for accessing a flash memory array accesses a flash memory array divided into a plurality of blocks. Each block includes logical address to physical address conversion information for that block. After determining to which block a received logical address corresponds, the method and device obtain the conversion information for that block, store the obtained conversion information, and then perform a memory access operation based on the received logical address and the stored conversion information. In this manner, only conversion information for a block is searched to perform a memory access operation, instead of conversion information for the entire flash memory array as in the conventional art.
- the present invention provides an improved high-speed flash EEPROM access method and device capable of processing data at high-speed.
- FIG. 1 is a constitutional block diagram of a conventional flash memory array access device
- FIG. 2 is a constitutional block diagram of a flash memory array access device in accordance with the present invention.
- FIG. 3 is a schematic diagram illustrating a memory array divided into a plurality of operation blocks in accordance with the present invention
- FIG. 4 is a constitutional diagram of a single operation block illustrated in FIG. 3;
- FIG. 5 is a constitutional diagram of a single block illustrated in FIG. 4.
- FIG. 6 is a constitutional diagram of a single lookup table illustrated in FIG. 5.
- the memory array having the flash memory cells is divided into a plurality of blocks pursuant to an erase characteristic of a flash EEPROM device.
- the blocks demanding an erase operation can be erased, and thus all the blocks are not erased.
- the flash memory array 11 includes a plurality of operation blocks OB 0 -OB n .
- Each block has an identical constitution, and thus the constitution of a first operation block OB 1 will now be described.
- FIG. 4 The constitution of the operation block in accordance with the present invention is illustrated in FIG. 4.
- the respective operation blocks each have a lookup table giving the relationship between a logical address and a physical address for each data in the operation block and indicating whether the data is valid or invalid.
- the first operation block OB 1 has the lookup table LT 1 .
- each operation block OB 0 -OB n has a lookup table, there are provided ‘n’ lookup tables. Based on the aforementioned constitution, each lookup table is searched in operation block units in the present invention. Consequently, the processing speed is remarkably improved, as compared with searching a physical address by using a single lookup table for a flash memory having a large capacity.
- New data is sequentially written in a vacant block. Updated data is also written in a vacant block and the corresponding previously-stored is managed as invalid data. Furthermore, the operation blocks are divided into a plurality of erase blocks EB 0 -EB n , as illustrated in FIG. 4. Each erase block EB 0 -EB n is independently erasable, and has a plurality of sectors S 0 -S k , as shown in FIG. 5. The respective sector addresses are managed by the respective lookup table.
- the lookup table will now be described with reference to FIG. 6.
- Each operation block has an identical constitution, accordingly only a first lookup table LT 1 assigned to the first operation block OB 1 will be described with reference to FIG. 6.
- the lookup table maintains the logical address that corresponds to the physical address for a sector and indicates the validity of data stored in the sector. A corresponding sector illustrated in FIG. 5 is accessed by the searched physical address.
- control unit 16 serves to generate the physical address pursuant to the logical address from the host, read and output a data in the memory array 11 , carry out a write operation on the memory array 11 , or carry out an erase operation of a memory element.
- the control unit 16 includes: an operation group select unit 13 receiving the logical address from the host and selecting the corresponding operation block; first and second buffers 14 and 15 temporarily storing a look-up table; and a memory control unit 12 carrying out a control function such as managing the lookup table for the flash memory, generating the physical address, and performing the read, output, write, and erase operations.
- the operation group select unit 13 serves to select one of the plurality of operation blocks in the memory array 11 based on the logical address.
- a constant divider or a comparator can be used in accordance with a preferred embodiment of the present invention to determine the operation block as described in detail below.
- a different embodiment can be carried out by those skilled in this field, based on the following description; however, such embodiments are all included in the present invention.
- the flash memory array 11 is represented by a decimal system, and, for example, has addresses from 0 to 1000 divided into 10 operation blocks of 100 addresses each.
- a number of the operation block including the logical address becomes ‘2’.
- the operation group select unit 13 is embodied by the constant divider, a value obtained by dividing the host logical address by 100 can be used as the number of the operation group block, and the value is inputted to the memory control unit 12 .
- the number of the operation group can be designated by comparing in which range of the compared reference values, for instance, 0-99, 100-299, . . . 900-999, an inputted host logical address exists. Accordingly, in a preferred embodiment of the present invention, some correlation exists between the logical address and the physical structure of the memory array 11 .
- the memory control unit 12 is provided with the number of the operation group block and selects the second operation block OB 2 corresponding to the value ‘2’ in the above-described example among the operation blocks illustrated in FIG. 3.
- the memory control unit 12 is provided with a microprocessor (not shown), and a read-only memory ROM (not shown) storing predetermined software for controlling every operation in accordance with the present invention.
- the memory control unit 12 controls memory operations pursuant to an external order such as the write operation or the read and output operation.
- the logical address is transmitted to the memory control unit 12 from the host with a read and output order, and then a predetermined process according to the present invention is performed. At this time, the logical address is also transmitted to the operation group select unit 13 . As described above, the number of the operation block having the transmitted logical address is outputted from the operation group select unit 13 .
- the memory control unit 12 then accesses the operation block indicated by the operation group select unit 13 and stores the look-up table thereof in the first buffer 14 . For instance, if the operation group select unit 13 indicates the first operation block OB 1 , the memory control unit 12 accesses the first operation block OB 1 and temporarily stores the first look-up table LT 1 in the first buffer 14 . Then, the memory control unit 12 confirms whether the first operation block OB 1 includes the logical address matching the logical address transmitted from the host using the first lookup table LT 1 .
- the memory control unit 12 In case the logical address from the host is not in the first lookup table LT 1 , the memory control unit 12 outputs a ‘no sector’ signal to the host.
- the search range of the lookup table is similar to the size of the selected operation block in the above-described operation, and therefore it is not necessary to utilize the information of all blocks, unlike in the conventional method. Accordingly, the search time can be remarkably reduced.
- the logical address is transmitted to the memory control unit 12 from the host with a write order, and then a predetermined process according to the present invention is performed.
- the logical address is also transmitted to the operation group select unit 13 .
- the number of the operation block including the logical address is outputted from the operation group select unit 13 .
- the memory control unit 12 then accesses the operation block indicated by the operation group select unit 13 and stores the look-up table thereof in the first buffer 14 . For instance, if the operation group select unit 13 indicates the first operation block OB 1 , the memory control unit 12 accesses the first operation block OB 1 and temporarily stores the first look-up table LT 1 in the first buffer 14 . Then, the memory control unit 12 confirms whether the first operation block OB 1 includes a logical address matching the logical address transmitted from the host using the first lookup table LT 1 .
- the corresponding information in the first lookup table LT 1 is no longer usable, and thus that information must be invalidated. Then, a vacant or unused sector (i.e., a sector not being used in the first lookup table LT 1 ) is searched for using the first look-up table LT 1 . If the identical logical address from the host is not found in the first lookup table LT 1 , a vacant sector (i.e., a sector with no associated logical address) is also searched for using the first look-up table LT 1 .
- the data transmitted from the host is written in the unused sector by referring to the physical address of the sector given in the first look-up table LT 1 .
- a relationship between the physical address of the sector and the logical address is formed, and thus the presently-used lookup table LT 1 in the first buffer 14 is updated.
- the memory control unit 12 re-stores the updated contents of the first lookup table LT 1 in the first operation block to use afterward.
- the erase operation is conducted when a vacant sector cannot be located in which to write new data.
- the memory control unit 12 first searches the first lookup table LT 1 for an erase block that does not include any valid data. If such an erase block is located, the memory control unit 12 causes the memory array 11 to erase this erase block, and store the new data in one or more sectors of the erased erase block. Furthermore, the memory control unit 12 updates the first lookup table LT 1 based on the foregoing changes to the erase block, and restores the first lookup table LT 1 in the first operation block OB 1 .
- the memory control unit 12 If the memory control unit 12 does not locate an erase block including no valid data, the memory control unit 12 then searches for the erase block having the least amount of valid data. Any valid data in the located erase block is then transferred from the erase block to a set of sectors within the memory array 11 that serve temporary storage for such operations. The memory control unit 12 then causes the memory array 11 to erase the chosen erase block, restore the valid data transferred to the temporary sectors, and store the new data. The memory control 12 then updates the first lookup table LT 1 based on the foregoing changes, and restores the first lookup table LT 1 in the first operation block OB 1 .
- the operation blocks can further include separate regions capable of having the information required for such a process. For example, a sector can have an user region and an overhead region, and the erase operation can be carried out in the entire memory array 11 by using the overhead information.
- the method and device of the present invention can also process data in a pipe line method for efficient high-speed processing. This pipeline operation will now described.
- the pipe line method processes data in parallel.
- a second buffer 15 is employed in addition to the first buffer 14 .
- the operation connected with one lookup table is performed, and the next operation can only be carried out once the first buffer 14 is no longer in use.
- the second buffer 15 allows temporary storage of the next lookup table for the next operation when a lookup table of a current operation is stored in the first buffer 14 . Accordingly, the lookup table associated with successive operations are alternately stored in the first and second buffers 14 and 15 . This allows substantially parallel performance of two operations according to the method of the present invention.
- the buffer used in the present invention is optional.
- the memory control unit 12 has a random access memory RAM which can be used instead.
- the buffer serves to improve the processing speed.
- the addresses in a restricted range are searched by using one of a plurality of lookup tables. This results in a more efficient high-speed process.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention is directed to flash memory array access method and device, and in particular to an improved flash memory array access method and device capable of reducing a search time between a logical address from a host and a physical address and improving an access time of the memory.
- 2. Description of the Background Art
- Modern computer systems or digital systems utilize a memory such as a hard disk. However, the hard disk is heavy in weight, has large capacity and consumes a significant amount of electricity. Recently, a flash electrically erasable programmable read only memory EEPROM has been popularly used as a memory device capable of overcoming the aforementioned disadvantages. In addition, the flash EEPROM is reprogrammable, and thus it can be used for updating software connected with system operation.
- However, unlike an EEPROM, the flash EEPROM is only reprogrammable after its entire memory array is erased. That is, the flash EEPROM cannot be reprogrammed before being erased.
- The flash EEPROM is erased by simultaneously applying a high voltage to source terminals of all transistors (cells) used in the memory. However, the time to perform this erasure is relatively long. Therefore, in order to efficiently perform an erase operation, the memory array is divided into a plurality of blocks, and then memory elements in a corresponding block can be separately erased. The respective blocks include at least two or more sectors that are also managed by the host. Each sector has a user region and an overhead region. The overhead region serves to store the erase frequency information such as an erase cycle frequency.
- For example, U.S. Pat. No. 5,341,339 entitled “METHOD FOR WEAR LEVELING IN A FLASH EEPROM MEMORY” to Wells, hereby incorporated by reference in its entirety, is related to a flash EEPROM. In this patent, in order to solve a problem that some memory elements are more frequently erased than the other memory elements and finally become unusable, there is provided a method of equally erasing memory cells by using the erase frequency information. Furthermore, there is described a method of using a lookup table to know the relationship between the physical address and the logical address managed by the host in writing data to a memory array divided into blocks. FIG. 1 is a schematic block diagram illustrating how a memory array constituted by using a conventional flash EEPROM is utilized.
- In order to access the
memory array 1, thememory array 1 of the conventional flash EEPROM receives a logic address from the host (not illustrated) and generates the physical address corresponding to the logical address. Here, acontrol unit 2 accessing thememory array 1 and providing a data to the host is used. Thecontrol unit 2 includes: anaddress conversion block 3, which stores a lookup table determining the relationship between the logical address and the physical address, a first database listing the amount of free space in each block of thememory array 1 and the total amount of free space, and a second database listing the amount of invalid data in each block and the total amount of invalid data; and amemory control unit 4 providing the received physical address to thememory array 1 and further providing or receiving a data or table information to or from thememory array 1. - In the case that there is a data that will updated, the previously-stored block containing that data is not erased, but the data is sequentially stored in a vacant space in the memory array. The previously-stored data is managed as invalid data, the block containing the data is erased afterward, and thus it is necessary to determine the relationship between the logical address managed by the host and the physical address. The
address conversion block 3 is utilized for such a process. Accordingly, thememory control unit 4 serves to control read and output, write or erase operations of the information connected with the sectors in the blocks where the physical address is designated. The plurality of blocks (not illustrated) composing thememory array 1 respectively include a separate region having the table information as in the lookup table stored by theaddress conversion block 3. - The data read and output operation from the
memory array 1 will now be described. - The read and output operation is started when the
control unit 2 illustrated in FIG. 1 receives the logical address from the host. Here, in order to carry out a series of processes, a microprocessor (not illustrated) of thecontrol unit 2 refers to the lookup table of theaddress conversion block 3 and obtains the physical address pursuant to the relationship between the logical address and the physical address. If there is a corresponding physical address, a valid data included in the physical sector is outputted to the host by using the physical address. - The write operation will now be explained. The host provides the logical address to the
control unit 2 illustrated in FIG. 1, as in the read and output operation. At this time, the corresponding physical address is firstly obtained by referring to the lookup table. The lookup table information that corresponds to the provided logical address is invalidated, the first and second databases are updated, and whether a sector which is not presently used in the lookup table exists is determined (i.e., a physical address with no associated logical address). In case there is a vacant usable sector, the data transmitted from the host is written in a physical position of the corresponding sector. The data can be read afterward by updating the lookup table for the sector. In the case that a usable sector does not exist, the lookup table information that corresponds to the provided logical address is still invalidated and the first and second databases updated. However, the remainder of the write operation is carried out after the erase operation. - The erase operation will now be explained. The block that does not have valid data or has the least amount of valid data is selected using the second database. Selection of the block for erasure can also depend on the number of erasures each block has undergone such as described in U.S. Pat. No. 5,341,339.
- In regard to the block that does not include the valid data, a portion of the lookup table connected with the block and the table information in the
memory array 1 are amended, the erase operation is performed on the block that will be erased, and then the remainder of the write operation is carried out. The erase operation is performed by applying, for example, a voltage of 12V to a source of a floating-gate field-effect transistor composing the memory cell. - In the case the block that will be erased includes valid data, the valid data is transmitted to a portion of the
memory array 1 set aside for dealing with part of the erase operation. Then, the corresponding lookup table and table information are amended and the erase operation is carried out. Subsequently, the remainder of the write operation takes place. - As described so far, the lookup table is very important in using the memory in the conventional art. However, the conventional method has a disadvantage in that it takes relatively long time to carry out the read and output operation or to search the lookup table for obtaining the physical address of the sector that the host will access.
- Also, when the write operation is performed, the lookup table for invalidating a previously-written sector must be searched, which requires a considerable amount of time.
- The method and device for accessing a flash memory array accesses a flash memory array divided into a plurality of blocks. Each block includes logical address to physical address conversion information for that block. After determining to which block a received logical address corresponds, the method and device obtain the conversion information for that block, store the obtained conversion information, and then perform a memory access operation based on the received logical address and the stored conversion information. In this manner, only conversion information for a block is searched to perform a memory access operation, instead of conversion information for the entire flash memory array as in the conventional art.
- Accordingly, the present invention provides an improved high-speed flash EEPROM access method and device capable of processing data at high-speed.
- The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:
- FIG. 1 is a constitutional block diagram of a conventional flash memory array access device;
- FIG. 2 is a constitutional block diagram of a flash memory array access device in accordance with the present invention;
- FIG. 3 is a schematic diagram illustrating a memory array divided into a plurality of operation blocks in accordance with the present invention;
- FIG. 4 is a constitutional diagram of a single operation block illustrated in FIG. 3;
- FIG. 5 is a constitutional diagram of a single block illustrated in FIG. 4; and
- FIG. 6 is a constitutional diagram of a single lookup table illustrated in FIG. 5.
- A flash memory array access method and device in accordance with a preferred embodiment of the present invention will now be described with reference to the accompanying drawings.
- First, the constitution of a memory array composed of flash memory cells will now be explained with reference to FIG. 3. The memory array having the flash memory cells is divided into a plurality of blocks pursuant to an erase characteristic of a flash EEPROM device. The blocks demanding an erase operation can be erased, and thus all the blocks are not erased.
- As illustrated in FIG. 3, the
flash memory array 11 includes a plurality of operation blocks OB0-OBn. Each block has an identical constitution, and thus the constitution of a first operation block OB1 will now be described. - The constitution of the operation block in accordance with the present invention is illustrated in FIG. 4. In the present invention, there are provided a plurality of lookup tables determining a relationship between a logical address and a physical address. That is, as shown in FIG. 4, the respective operation blocks each have a lookup table giving the relationship between a logical address and a physical address for each data in the operation block and indicating whether the data is valid or invalid. In this case, the first operation block OB1 has the lookup table LT1. As each operation block OB0-OBn has a lookup table, there are provided ‘n’ lookup tables. Based on the aforementioned constitution, each lookup table is searched in operation block units in the present invention. Consequently, the processing speed is remarkably improved, as compared with searching a physical address by using a single lookup table for a flash memory having a large capacity.
- New data is sequentially written in a vacant block. Updated data is also written in a vacant block and the corresponding previously-stored is managed as invalid data. Furthermore, the operation blocks are divided into a plurality of erase blocks EB0-EBn, as illustrated in FIG. 4. Each erase block EB0-EBn is independently erasable, and has a plurality of sectors S0-Sk, as shown in FIG. 5. The respective sector addresses are managed by the respective lookup table.
- The lookup table will now be described with reference to FIG. 6. Each operation block has an identical constitution, accordingly only a first lookup table LT1 assigned to the first operation block OB1 will be described with reference to FIG. 6. For example, the lookup table maintains the logical address that corresponds to the physical address for a sector and indicates the validity of data stored in the sector. A corresponding sector illustrated in FIG. 5 is accessed by the searched physical address.
- As illustrated in FIG. 2, the
control unit 16 according to the present invention serves to generate the physical address pursuant to the logical address from the host, read and output a data in thememory array 11, carry out a write operation on thememory array 11, or carry out an erase operation of a memory element. - The
control unit 16 includes: an operation groupselect unit 13 receiving the logical address from the host and selecting the corresponding operation block; first andsecond buffers memory control unit 12 carrying out a control function such as managing the lookup table for the flash memory, generating the physical address, and performing the read, output, write, and erase operations. - When a data in the
memory array 11 is read and outputted to the host (not illustrated) or a data is written in thememory array 11, a logical and easily-usable address is used. Such a logical address is inputted to the operation groupselect unit 13 of thecontrol unit 16. - The operation group
select unit 13 serves to select one of the plurality of operation blocks in thememory array 11 based on the logical address. Here, a constant divider or a comparator can be used in accordance with a preferred embodiment of the present invention to determine the operation block as described in detail below. A different embodiment can be carried out by those skilled in this field, based on the following description; however, such embodiments are all included in the present invention. - For instance, it is assumed that the
flash memory array 11 is represented by a decimal system, and, for example, has addresses from 0 to 1000 divided into 10 operation blocks of 100 addresses each. Here, when the logical address, ‘250’ is given from the host, a number of the operation block including the logical address becomes ‘2’. This shows the constant divider can be employed. In the case that the operation groupselect unit 13 is embodied by the constant divider, a value obtained by dividing the host logical address by 100 can be used as the number of the operation group block, and the value is inputted to thememory control unit 12. On the other hand, when the operation groupselect unit 13 is embodied by the comparator, the number of the operation group can be designated by comparing in which range of the compared reference values, for instance, 0-99, 100-299, . . . 900-999, an inputted host logical address exists. Accordingly, in a preferred embodiment of the present invention, some correlation exists between the logical address and the physical structure of thememory array 11. - The
memory control unit 12 is provided with the number of the operation group block and selects the second operation block OB2 corresponding to the value ‘2’ in the above-described example among the operation blocks illustrated in FIG. 3. - It is preferred that the
memory control unit 12 is provided with a microprocessor (not shown), and a read-only memory ROM (not shown) storing predetermined software for controlling every operation in accordance with the present invention. Thememory control unit 12 controls memory operations pursuant to an external order such as the write operation or the read and output operation. - First, the read and output operation of the present invention will now be explained.
- The logical address is transmitted to the
memory control unit 12 from the host with a read and output order, and then a predetermined process according to the present invention is performed. At this time, the logical address is also transmitted to the operation groupselect unit 13. As described above, the number of the operation block having the transmitted logical address is outputted from the operation groupselect unit 13. Thememory control unit 12 then accesses the operation block indicated by the operation groupselect unit 13 and stores the look-up table thereof in thefirst buffer 14. For instance, if the operation groupselect unit 13 indicates the first operation block OB1, thememory control unit 12 accesses the first operation block OB1 and temporarily stores the first look-up table LT1 in thefirst buffer 14. Then, thememory control unit 12 confirms whether the first operation block OB1 includes the logical address matching the logical address transmitted from the host using the first lookup table LT1. - In case the identical logical address exists in the first lookup table LT1, a corresponding sector is found by using the physical address corresponding to the logical address given in the look-up table LT1. Accordingly, the
memory control unit 12 can provide data to the host by accessing the sector having this physical address. - In case the logical address from the host is not in the first lookup table LT1, the
memory control unit 12 outputs a ‘no sector’ signal to the host. - While the details of the read and output operation have been described with respect to the first operation block OB1, it will be understood by those skilled in the art that this operation applies to each operation block.
- The search range of the lookup table is similar to the size of the selected operation block in the above-described operation, and therefore it is not necessary to utilize the information of all blocks, unlike in the conventional method. Accordingly, the search time can be remarkably reduced.
- The data write operation of the present invention will now be described.
- The logical address is transmitted to the
memory control unit 12 from the host with a write order, and then a predetermined process according to the present invention is performed. Here, the logical address is also transmitted to the operation groupselect unit 13. As described above, the number of the operation block including the logical address is outputted from the operation groupselect unit 13. Thememory control unit 12 then accesses the operation block indicated by the operation groupselect unit 13 and stores the look-up table thereof in thefirst buffer 14. For instance, if the operation groupselect unit 13 indicates the first operation block OB1, thememory control unit 12 accesses the first operation block OB1 and temporarily stores the first look-up table LT1 in thefirst buffer 14. Then, thememory control unit 12 confirms whether the first operation block OB1 includes a logical address matching the logical address transmitted from the host using the first lookup table LT1. - In case the identical logical address exists in the first lookup table LT1, the corresponding information in the first lookup table LT1 is no longer usable, and thus that information must be invalidated. Then, a vacant or unused sector (i.e., a sector not being used in the first lookup table LT1) is searched for using the first look-up table LT1. If the identical logical address from the host is not found in the first lookup table LT1, a vacant sector (i.e., a sector with no associated logical address) is also searched for using the first look-up table LT1.
- If an unused sector is located from the first lookup table LT1, the data transmitted from the host is written in the unused sector by referring to the physical address of the sector given in the first look-up table LT1. At this time, a relationship between the physical address of the sector and the logical address is formed, and thus the presently-used lookup table LT1 in the
first buffer 14 is updated. Thememory control unit 12 re-stores the updated contents of the first lookup table LT1 in the first operation block to use afterward. - In the case that an unused sector does not exist, a data is newly written in the vacant sector after carrying out the erase operation as described in detail below.
- While the details of the write operation have been described with respect to the first operation block OB1, it will be understood by those skilled in the art that this operation applies to each operation block.
- The erase operation of the present invention will now be described.
- As discussed briefly above, the erase operation is conducted when a vacant sector cannot be located in which to write new data. Continuing with the example above, if the first lookup table LT1 does not indicate a vacant sector exists for storing newly received data, then the erase operation is performed. In performing the erase operation, the
memory control unit 12 first searches the first lookup table LT1 for an erase block that does not include any valid data. If such an erase block is located, thememory control unit 12 causes thememory array 11 to erase this erase block, and store the new data in one or more sectors of the erased erase block. Furthermore, thememory control unit 12 updates the first lookup table LT1 based on the foregoing changes to the erase block, and restores the first lookup table LT1 in the first operation block OB1. - If the
memory control unit 12 does not locate an erase block including no valid data, thememory control unit 12 then searches for the erase block having the least amount of valid data. Any valid data in the located erase block is then transferred from the erase block to a set of sectors within thememory array 11 that serve temporary storage for such operations. Thememory control unit 12 then causes thememory array 11 to erase the chosen erase block, restore the valid data transferred to the temporary sectors, and store the new data. Thememory control 12 then updates the first lookup table LT1 based on the foregoing changes, and restores the first lookup table LT1 in the first operation block OB1. - While the details of the erase operation having been described with respect to the first operation block OB1, it will be understood by those skilled in the art that this operation applies to each operation block.
- Other conventional preferred processing methods connected with the above-described erase operation can be further included. However, it must be noted that such a combination is also included in the present invention. For instance, selection of the erase block for erasure can also depend on the number of erasures as described U.S. Pat. Nos. 5,341,339 and 5,568,423, both of which are hereby incorporated by reference in their entirety. Therefore, in order to process data by further including the added conventional methods, the operation blocks can further include separate regions capable of having the information required for such a process. For example, a sector can have an user region and an overhead region, and the erase operation can be carried out in the
entire memory array 11 by using the overhead information. - The method and device of the present invention can also process data in a pipe line method for efficient high-speed processing. This pipeline operation will now described.
- The pipe line method processes data in parallel. As illustrated in FIG. 2, a
second buffer 15 is employed in addition to thefirst buffer 14. When only thefirst buffer 14 is used, the operation connected with one lookup table is performed, and the next operation can only be carried out once thefirst buffer 14 is no longer in use. However, thesecond buffer 15 allows temporary storage of the next lookup table for the next operation when a lookup table of a current operation is stored in thefirst buffer 14. Accordingly, the lookup table associated with successive operations are alternately stored in the first andsecond buffers - The buffer used in the present invention is optional. In general, the
memory control unit 12 has a random access memory RAM which can be used instead. In the present invention, the buffer serves to improve the processing speed. - In accordance with the present invention, the addresses in a restricted range are searched by using one of a plurality of lookup tables. This results in a more efficient high-speed process.
- As the present invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims (26)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980009219A KR100319598B1 (en) | 1998-03-18 | 1998-03-18 | Flash memory array access method and device |
KR9219/1998 | 1998-03-18 | ||
KR98/9219 | 1998-03-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020013879A1 true US20020013879A1 (en) | 2002-01-31 |
US6374324B2 US6374324B2 (en) | 2002-04-16 |
Family
ID=19534992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/271,444 Expired - Lifetime US6374324B2 (en) | 1998-03-18 | 1999-03-18 | Flash memory array access method and device |
Country Status (4)
Country | Link |
---|---|
US (1) | US6374324B2 (en) |
JP (1) | JPH11297078A (en) |
KR (1) | KR100319598B1 (en) |
DE (1) | DE19845295A1 (en) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030041210A1 (en) * | 2001-08-24 | 2003-02-27 | Micron Technology, Inc. | Erase block management |
US20040093459A1 (en) * | 1999-08-19 | 2004-05-13 | Murata Manufacturing Co., Ltd. | Data processing device |
US20040221130A1 (en) * | 2003-05-02 | 2004-11-04 | Lai Jui Yang | Method and device for a accessing non-volatile memory by PC and X-BOX |
US20050055525A1 (en) * | 2003-09-08 | 2005-03-10 | Eric Chuang | Method and related apparatus for clearing data in a memory |
US20050144418A1 (en) * | 2003-12-26 | 2005-06-30 | Kenzo Kita | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US20050144421A1 (en) * | 2003-12-26 | 2005-06-30 | Samsung Electronics Co., Ltd. | Data management device and method for flash memory |
US20050154818A1 (en) * | 2004-01-13 | 2005-07-14 | Ping Chen | Method of accessing a nonvolatile memory |
US20060026340A1 (en) * | 2004-07-27 | 2006-02-02 | Takafumi Ito | Memory card, card controller mounted on the memory card, and device for processing the memory card |
US20070033330A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Reclaiming Data Storage Capacity in Flash Memory Systems |
US20070033331A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | NonVolatile Memory With Block Management |
US20070033332A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Methods of Managing Blocks in NonVolatile Memory |
US20070118698A1 (en) * | 2005-11-18 | 2007-05-24 | Lafrese Lee C | Priority scheme for transmitting blocks of data |
US20070150654A1 (en) * | 2005-12-27 | 2007-06-28 | Samsung Electronics Co., Ltd. | Storage apparatus using non-volatile memory as cache and method of managing the same |
US20070276987A1 (en) * | 2004-02-26 | 2007-11-29 | Super Talent Electronics, Inc. | Source and Shadow Wear-Leveling Method and Apparatus |
US20080229428A1 (en) * | 2005-03-07 | 2008-09-18 | Noam Camiel | System and Method For a Dynamic Policies Enforced File System For a Data Storage Device |
WO2009045010A2 (en) * | 2007-10-02 | 2009-04-09 | Huone Inc. | Flash memory mapping management method |
US20090164745A1 (en) * | 2007-12-21 | 2009-06-25 | Alan Sinclair | System and Method for Controlling an Amount of Unprogrammed Capacity in Memory Blocks of a Mass Storage System |
US20100268869A1 (en) * | 2009-04-20 | 2010-10-21 | Samsung Electronics Co., Ltd. | Memory system comprising nonvolatile memory device and controller |
USRE42263E1 (en) * | 2001-03-22 | 2011-03-29 | Panasonic Corporation | Address conversion unit for memory device |
US20120324159A1 (en) * | 2000-06-30 | 2012-12-20 | Emc Corporation | Method and apparatus for implementing high-performance, scaleable data processing and storage systems |
CN110806985A (en) * | 2008-11-06 | 2020-02-18 | 慧荣科技(深圳)有限公司 | Method for managing a memory device and related memory device |
CN113110797A (en) * | 2020-01-10 | 2021-07-13 | 祥硕科技股份有限公司 | Data storage system, data storage device and management method thereof |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7190617B1 (en) * | 1989-04-13 | 2007-03-13 | Sandisk Corporation | Flash EEprom system |
US6347051B2 (en) * | 1991-11-26 | 2002-02-12 | Hitachi, Ltd. | Storage device employing a flash memory |
JP3942807B2 (en) * | 2000-06-06 | 2007-07-11 | 株式会社ルネサステクノロジ | Semiconductor memory device with block alignment function |
KR100437609B1 (en) * | 2001-09-20 | 2004-06-30 | 주식회사 하이닉스반도체 | Method for address translation of semiconductor memory device and apparatus the same |
KR20030062070A (en) * | 2002-01-16 | 2003-07-23 | 한국전자통신연구원 | Apparatus and method for controlling an access of a flash memory |
US6732222B1 (en) * | 2002-02-01 | 2004-05-04 | Silicon Motion, Inc. | Method for performing flash memory file management |
KR100439507B1 (en) * | 2002-03-18 | 2004-07-09 | 삼성전기주식회사 | Data operating method in flash memory card system of high-capacity |
KR100479170B1 (en) * | 2002-06-14 | 2005-03-28 | 주식회사 포인칩스 | Access control device for memory and method thereof |
JP2005108304A (en) * | 2003-09-29 | 2005-04-21 | Toshiba Corp | Semiconductor memory and its control method |
US20050204115A1 (en) * | 2004-01-30 | 2005-09-15 | Kiminori Matsuno | Semiconductor memory device, memory controller and data recording method |
TWI249670B (en) | 2004-04-29 | 2006-02-21 | Mediatek Inc | System and method capable of sequentially writing a flash memory |
KR100643288B1 (en) * | 2004-11-16 | 2006-11-10 | 삼성전자주식회사 | Data processing device and method for flash memory |
KR100643287B1 (en) * | 2004-11-19 | 2006-11-10 | 삼성전자주식회사 | Data processing device and method for flash memory |
US7457909B2 (en) * | 2005-01-14 | 2008-11-25 | Angelo Di Sena | Controlling operation of flash memories |
KR100739760B1 (en) * | 2005-11-23 | 2007-07-13 | 삼성전자주식회사 | System and method for providing information on usage of computer memory |
KR100781517B1 (en) | 2006-02-16 | 2007-12-03 | 삼성전자주식회사 | Mapping table managing apparatus and method for nonvolatile memory |
KR100843133B1 (en) | 2006-09-20 | 2008-07-02 | 삼성전자주식회사 | Apparatus and method for reorganization of Mapping information in flash memory |
KR100817087B1 (en) * | 2007-02-13 | 2008-03-27 | 삼성전자주식회사 | Method for operating buffer cache of storage device including flash memory |
KR100857761B1 (en) * | 2007-06-14 | 2008-09-10 | 삼성전자주식회사 | Memory system performing wear levelling and write method thereof |
WO2011007511A1 (en) * | 2009-07-16 | 2011-01-20 | パナソニック株式会社 | Memory controller, nonvolatile storage device, accessing device, and nonvolatile storage system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5430859A (en) * | 1991-07-26 | 1995-07-04 | Sundisk Corporation | Solid state memory system including plural memory chips and a serialized bus |
JPH05233426A (en) * | 1992-02-20 | 1993-09-10 | Fujitsu Ltd | Flash memory using method |
JP3641280B2 (en) | 1992-10-30 | 2005-04-20 | インテル・コーポレーション | Method for determining blocks to be cleaned up in a flash EEPROM array |
US5455934A (en) * | 1993-03-23 | 1995-10-03 | Eclipse Technologies, Inc. | Fault tolerant hard disk array controller |
JPH08137634A (en) * | 1994-11-09 | 1996-05-31 | Mitsubishi Electric Corp | Flash disk card |
US5568423A (en) | 1995-04-14 | 1996-10-22 | Unisys Corporation | Flash memory wear leveling system providing immediate direct access to microprocessor |
US5907856A (en) * | 1995-07-31 | 1999-05-25 | Lexar Media, Inc. | Moving sectors within a block of information in a flash memory mass storage architecture |
KR100359414B1 (en) * | 1996-01-25 | 2003-01-24 | 동경 엘렉트론 디바이스 주식회사 | Data reading method and memory controlling apparatus |
US5943692A (en) * | 1997-04-30 | 1999-08-24 | International Business Machines Corporation | Mobile client computer system with flash memory management utilizing a virtual address map and variable length data |
-
1998
- 1998-03-18 KR KR1019980009219A patent/KR100319598B1/en not_active IP Right Cessation
- 1998-10-01 DE DE19845295A patent/DE19845295A1/en not_active Withdrawn
- 1998-10-19 JP JP29654498A patent/JPH11297078A/en active Pending
-
1999
- 1999-03-18 US US09/271,444 patent/US6374324B2/en not_active Expired - Lifetime
Cited By (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040093459A1 (en) * | 1999-08-19 | 2004-05-13 | Murata Manufacturing Co., Ltd. | Data processing device |
US20120324159A1 (en) * | 2000-06-30 | 2012-12-20 | Emc Corporation | Method and apparatus for implementing high-performance, scaleable data processing and storage systems |
USRE42263E1 (en) * | 2001-03-22 | 2011-03-29 | Panasonic Corporation | Address conversion unit for memory device |
US8433846B2 (en) | 2001-08-24 | 2013-04-30 | Micron Technology, Inc. | Methods and apparatus reading erase block management data in subsets of sectors having user data and control data sections |
US7454558B2 (en) | 2001-08-24 | 2008-11-18 | Micron Technology, Inc. | Non-volatile memory with erase block state indication in data section |
US20090125670A1 (en) * | 2001-08-24 | 2009-05-14 | Micron Technology, Inc. | Erase block management |
US20030041210A1 (en) * | 2001-08-24 | 2003-02-27 | Micron Technology, Inc. | Erase block management |
US6948026B2 (en) * | 2001-08-24 | 2005-09-20 | Micron Technology, Inc. | Erase block management |
US20050273551A1 (en) * | 2001-08-24 | 2005-12-08 | Micron Technology, Inc. | Erase block management |
US8112573B2 (en) | 2001-08-24 | 2012-02-07 | Micron Technology, Inc. | Non-volatile memory with erase block state indication in a subset of sectors of erase block |
US20040221130A1 (en) * | 2003-05-02 | 2004-11-04 | Lai Jui Yang | Method and device for a accessing non-volatile memory by PC and X-BOX |
US20050055525A1 (en) * | 2003-09-08 | 2005-03-10 | Eric Chuang | Method and related apparatus for clearing data in a memory |
US7124269B2 (en) * | 2003-09-08 | 2006-10-17 | Via Technologies Inc. | Memory controller including data clearing module |
US20050144421A1 (en) * | 2003-12-26 | 2005-06-30 | Samsung Electronics Co., Ltd. | Data management device and method for flash memory |
US7779226B2 (en) * | 2003-12-26 | 2010-08-17 | Tdk Corporation | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US20070260845A1 (en) * | 2003-12-26 | 2007-11-08 | Tdk Corporation | Memory Controller, Flash Memory System, and Method of Controlling Operation for Data Exchange Between Host System and Flash Memory |
US7526600B2 (en) * | 2003-12-26 | 2009-04-28 | Samsung Electronics Co., Ltd. | Data management device and method for flash memory |
US20050144418A1 (en) * | 2003-12-26 | 2005-06-30 | Kenzo Kita | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US7281114B2 (en) * | 2003-12-26 | 2007-10-09 | Tdk Corporation | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US20050154818A1 (en) * | 2004-01-13 | 2005-07-14 | Ping Chen | Method of accessing a nonvolatile memory |
US7818492B2 (en) * | 2004-02-26 | 2010-10-19 | Supertalent Electronics, Inc. | Source and shadow wear-leveling method and apparatus |
US20070276987A1 (en) * | 2004-02-26 | 2007-11-29 | Super Talent Electronics, Inc. | Source and Shadow Wear-Leveling Method and Apparatus |
US20060026340A1 (en) * | 2004-07-27 | 2006-02-02 | Takafumi Ito | Memory card, card controller mounted on the memory card, and device for processing the memory card |
US20080229428A1 (en) * | 2005-03-07 | 2008-09-18 | Noam Camiel | System and Method For a Dynamic Policies Enforced File System For a Data Storage Device |
US8302178B2 (en) * | 2005-03-07 | 2012-10-30 | Noam Camiel | System and method for a dynamic policies enforced file system for a data storage device |
US7610437B2 (en) | 2005-08-03 | 2009-10-27 | Sandisk Corporation | Data consolidation and garbage collection in direct data file storage memories |
US7450420B2 (en) | 2005-08-03 | 2008-11-11 | Sandisk Corporation | Reclaiming data storage capacity in flash memories |
TWI421684B (en) * | 2005-08-03 | 2014-01-01 | Sandisk Technologies Inc | Reprogrammable non-volatile memory system and method of operating a non-volatile memory system |
US20070033330A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Reclaiming Data Storage Capacity in Flash Memory Systems |
US7552271B2 (en) * | 2005-08-03 | 2009-06-23 | Sandisk Corporation | Nonvolatile memory with block management |
US20070033331A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | NonVolatile Memory With Block Management |
US20070033378A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Flash Memory Systems Utilizing Direct Data File Storage |
US7558905B2 (en) * | 2005-08-03 | 2009-07-07 | Sandisk Corporation | Reclaiming data storage capacity in flash memory systems |
US7558906B2 (en) * | 2005-08-03 | 2009-07-07 | Sandisk Corporation | Methods of managing blocks in nonvolatile memory |
US7562181B2 (en) | 2005-08-03 | 2009-07-14 | Sandisk Corporation | Flash memory systems with direct data file storage utilizing data consolidation and garbage collection |
US7590794B2 (en) | 2005-08-03 | 2009-09-15 | Sandisk Corporation | Data operations in flash memories utilizing direct data file storage |
US7590795B2 (en) | 2005-08-03 | 2009-09-15 | Sandisk Corporation | Flash memory systems utilizing direct data file storage |
US20070186032A1 (en) * | 2005-08-03 | 2007-08-09 | Sinclair Alan W | Flash Memory Systems With Direct Data File Storage Utilizing Data Consolidation and Garbage Collection |
US20070033332A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Methods of Managing Blocks in NonVolatile Memory |
US20070033377A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Data Operations in Flash Memories Utilizing Direct Data File Storage |
US7444478B2 (en) * | 2005-11-18 | 2008-10-28 | International Business Machines Corporation | Priority scheme for transmitting blocks of data |
US20070118698A1 (en) * | 2005-11-18 | 2007-05-24 | Lafrese Lee C | Priority scheme for transmitting blocks of data |
US20070150654A1 (en) * | 2005-12-27 | 2007-06-28 | Samsung Electronics Co., Ltd. | Storage apparatus using non-volatile memory as cache and method of managing the same |
US7774541B2 (en) * | 2005-12-27 | 2010-08-10 | Samsung Electronics Co., Ltd. | Storage apparatus using non-volatile memory as cache and method of managing the same |
WO2009045010A3 (en) * | 2007-10-02 | 2009-07-02 | Huone Inc | Flash memory mapping management method |
WO2009045010A2 (en) * | 2007-10-02 | 2009-04-09 | Huone Inc. | Flash memory mapping management method |
US20090164745A1 (en) * | 2007-12-21 | 2009-06-25 | Alan Sinclair | System and Method for Controlling an Amount of Unprogrammed Capacity in Memory Blocks of a Mass Storage System |
CN110806985A (en) * | 2008-11-06 | 2020-02-18 | 慧荣科技(深圳)有限公司 | Method for managing a memory device and related memory device |
US11748258B2 (en) | 2008-11-06 | 2023-09-05 | Silicon Motion, Inc. | Method for managing a memory apparatus |
US12019540B2 (en) | 2008-11-06 | 2024-06-25 | Silicon Motion, Inc. | Method for managing a memory apparatus |
US8589618B2 (en) | 2009-04-20 | 2013-11-19 | Samsung Electronics Co., Ltd. | Memory system comprising nonvolatile memory device and controller |
US20100268869A1 (en) * | 2009-04-20 | 2010-10-21 | Samsung Electronics Co., Ltd. | Memory system comprising nonvolatile memory device and controller |
CN113110797A (en) * | 2020-01-10 | 2021-07-13 | 祥硕科技股份有限公司 | Data storage system, data storage device and management method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR19990075161A (en) | 1999-10-15 |
US6374324B2 (en) | 2002-04-16 |
KR100319598B1 (en) | 2002-04-06 |
JPH11297078A (en) | 1999-10-29 |
DE19845295A1 (en) | 1999-09-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6374324B2 (en) | Flash memory array access method and device | |
US8032694B2 (en) | Direct logical block addressing flash memory mass storage architecture | |
US8793430B2 (en) | Electronic system having memory with a physical block having a sector storing data and indicating a move status of another sector of the physical block | |
US5485595A (en) | Flash memory mass storage architecture incorporating wear leveling technique without using cam cells | |
US5479638A (en) | Flash memory mass storage architecture incorporation wear leveling technique | |
US6223308B1 (en) | Identification and verification of a sector within a block of mass STO rage flash memory | |
US5907856A (en) | Moving sectors within a block of information in a flash memory mass storage architecture | |
US5388083A (en) | Flash memory mass storage architecture | |
US7191306B2 (en) | Flash memory, and flash memory access method and apparatus | |
US7702844B2 (en) | Address mapping method and mapping information managing method for flash memory, and flash memory using the same | |
US6865658B2 (en) | Nonvolatile data management system using data segments and link information | |
US7287117B2 (en) | Flash memory and mapping control apparatus and method for flash memory | |
KR20010109336A (en) | Method and apparatus to permit adjustable code/data boundary in a nonvolatile memory | |
JP2002366420A (en) | Nonvolatile memory and its rewriting control method | |
JP2004303238A (en) | Flash memory access device and method | |
US10559359B2 (en) | Method for rewriting data in nonvolatile memory and semiconductor device | |
KR100281102B1 (en) | ATA card using the flash memory | |
JPH0896588A (en) | Semiconductor storage device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LG SEMICON CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAN, SANG-WOOK;REEL/FRAME:009849/0757 Effective date: 19990305 |
|
AS | Assignment |
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R Free format text: CHANGE OF NAME;ASSIGNOR:LG SEMICON CO., LTD.;REEL/FRAME:011033/0103 Effective date: 20000530 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 12 |