US20020008302A1 - Polysilicon resistor having adjustable temperature coefficients and the method of making the same - Google Patents
Polysilicon resistor having adjustable temperature coefficients and the method of making the same Download PDFInfo
- Publication number
- US20020008302A1 US20020008302A1 US09/964,192 US96419201A US2002008302A1 US 20020008302 A1 US20020008302 A1 US 20020008302A1 US 96419201 A US96419201 A US 96419201A US 2002008302 A1 US2002008302 A1 US 2002008302A1
- Authority
- US
- United States
- Prior art keywords
- resistor
- doping
- trimming
- resistance
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Definitions
- the present invention relates generally to an improved polysilicon resistor and method for making the same.
- a device according to Isobe, et al. actually requires that two dopings occur for each resistor one with a positive TC1 and a second with a negative TC1 be used so that a zero TC1 resistor can be formed. This increases the complexity of formation of the device. Further both dopings are at high levels of concentrations, which create problems in the manufacturing process.
- the present invention overcomes the shortcomings and deficiencies noted above by providing a new electrically trimmed polysilicon resistor that can be electrically trimmed by controlling the grain boundary resistance by the movement of the impurity doping.
- the second order temperature coefficient can also be altered in predictable manners.
- the trimming range of the resistor itself also can be adjusted over a very wide range.
- the improvement provided in the accuracy of the resistors can make termination devices such as SCSI terminators with fewer and more accurate resistors, making the SCSI terminators cheaper and/or more accurate.
- first and second order temperature coefficients also allows for improved second order fits of resistors or with more linear temperature characteristics. It should be noted that TC2 as will be discussed below decreases considerably with electrical trimming at various doping concentrations (see for example FIG. 6).
- the resistor can be used as a permanent indicator of events such as ESD event or it can act as a type of electrical fuse based upon a programmed change in a resistors characteristics.
- the trimmed resistor can also be used to improved bandgap circuits, A/D and D/A converters. OP-amp offsets, digital potentiometers and delay lines can likewise be improved. Also digital thermometers, oscillators and filters can also benefit from this type of resistor.
- an electrically trimmed resistor could act as a multi-bit analog memory by employing multiple trimmed values of one or more of these resistors.
- FIG. 1 is a block diagram of a resistor formed according to this invention.
- FIG. 2 is a timing diagram of a preferred embodiment for the electrical trimming or adjusting a resistor formed according to this invention.
- FIGS. 3 - 7 are graphs showing experimental test results on various versions resistors according to this invention.
- a lower temperature for the annealing may be used for example at a deposition temperature of 625° C. if a late implant process is employed.
- the low doped late-implanted resistors result in a finer grain size and hence have a higher grain boundary density compared to the highly doped early-implanted resistors. This increase in the grain boundary density results in reduced trimming current density and higher maximum trim percentages.
- the late implant resistor can be trimmed to about 30% of its initial resistance while the early-implant resistor can be trimmed to only about 60% of its initial resistance.
- the inventors have found that using a lower doping along with a lower final anneal temperature allows them to obtain an increased resistivity and the amount of dopant at the grain boundaries to also increase. This allows the resistor to be trimmed using much lower concentrations than had been thought possible.
- the polysilicon resistors used in this example were 0.4 ⁇ m thick, phosphorus-doped and deposited at 625° C. We have used resistors with a dopant concentration in the range ⁇ 6 ⁇ 10 19 cm ⁇ 3 to 3.75 ⁇ 10 20 cm ⁇ 3 and examine the effect of electrical trimming on both TC1, TC2 and resistance. Other dopant species such as Arsenic, Boron and Antinomy, etc. are expected to produce similar results.
- FIGS. 3 The trimming behavior of TC1 and TC2 are shown in FIGS. 3 for a phosphorus concentration 6 ⁇ 10 19 cm ⁇ 3 . This concentration was previously classified as untrimmable by Isobe et al., U.S. Pat. No. 5,187,559.
- the pre-trim sheet resistances in FIG. 3 are scattered around 285 ⁇ /square with TC1 in the 1000 ppm/° C. These data points correspond to different resistors on the same wafer and reflect the normal process variations between resistors. It can be seen that electrical trimming reduces the sheet resistance and also causes the TC1 to increase in a linear fashion. On the other hand, TC2 [FIG. 4] decreases linearly with trimming.
- the inventors herein have used resistors ranging from a phosphorus concentration of ⁇ 6 ⁇ 10 19 cm ⁇ 3 up to ⁇ 3.75 ⁇ 10 20 cm ⁇ 3 . Superimposing the data from these different dopings results in FIG. 5 and FIG. 6. From FIG. 5, it is evident that the magnitude of slope of TC1 versus Sheet Resistance curve increases as the doping is increased. Thus, by using differently doped resistors, we can obtain the same TC1 for different sheet resistances or alternately for a given Sheet Resistance we can obtain different TC1 values by changing the dopant concentration and amount of trim. The shaded area represents the possible TC1-Sheet Resistance combinations and includes the all-important zero TC1 value.
- FIG. 4 shows the variation in TC2 versus Sheet Resistance for the dopant range mentioned above.
- the slope of TC2 versus sheet resistance does not change appreciably after electrically trimming the polysilicon resistors for differently doped resistors. In terms of TC2, trimming has the same effect as increasing the doping concentration during processing.
- the formation of the resistor occurs by the following steps.
- a substrate is initially prepared using known prior art conventional processing.
- a polycyrystalline silicon layer is deposited. This layer is ideally about 4000 ⁇ thick.
- the layer is deposited and annealed at 625° C. with a deposition time of about 62 minutes.
- a poly resistor mask is then aligned and exposed.
- An ion implantation is done to provide the poly doping using a dose of about 1.5E16/cm 2 with the ion energy at 60 keV.
- the insulating oxidation for the poly is formed at 950 ° C. for about 30 minutes.
- the mask for implant resistor is then aligned and exposed using a dose of 2.0E15 to 1.5E16/cm 2 at an energy level of 100 KeV.
- an inter-level dielectric viz. Borophosphosilicate Glass (or commonly called BPSG) is deposited on the wafer.
- the next step is an anneal at 900 C for 20 minutes in order to planarize the surface and densify the BPSG.
- conventional low temperature processing is done. This low temperature processing comprises the following steps. First contacts are etched in the BPSG. Then a TiN barrier layer is deposited on the BPSG. An Al—Cu layer is then deposited. This Al—Cu layer is then patterned and etched. A TEOS deposition for is then done passivation purposes. A nitride deposition is also then done for passivation purposes. The resultant material is then patterned and etched.
- the resistor as formed above can have the resistance and temperature coefficients adjusted by an electrical current either in the form of pulses or direct current.
- a typical timing diagram is given in FIG. 2 for the resistor trimming.
- a resistor formed according to this invention is trimmed by using current pulses of increasing amplitude while monitoring the resistance during the measure period. This is continued until the desired amount of trimming has been achieved.
- the pulse width that has been used successfully for this purpose is 500 us and the period is 10.5 ms.
- the voltages and currents used in prior art systems have generally been too high for easy incorporation into low-voltage devices.
- the lowest threshold trimming current (the current at which the trimming begins) reported by Amemiya et al. was ⁇ 20 mA with a corresponding voltage of ⁇ 16V. This voltage is not compatible with low-voltage processes.
- the inventors herein have made polysilicon resistors with widths ranging from 0.6 um to 1.5 um and lengths ranging from 2 um to 15 um (FIG. 7). It can be seen that the threshold current density for trimming reduces with increasing length and has a weak width dependence The length dependence is thought to be influenced by end effects.
- the dopant species from the highly doped polysilicon contact areas diffuse into the lighter doped regions, reducing the sheet resistance and increasing the grain size. Also, the polysilicon contact areas act as heat sinks reducing the average resistor temperature during trimming. This effect is pronounced for shorter resistors and decreases for longer resistors.
- resistors which trim at very low voltages and currents can be fabricated. Threshold current of ⁇ 5 mA and less have shown acceptable results. Trimming voltages as low as ⁇ 1.5V have also produced successful results.
- resistors are placed over thick oxide (i.e. they have a higher degree of thermal isolation), they can be trimmed at lower currents and voltages compared to the same resistor over a thin oxide.
- a resistor over a thin oxide can lose heat easily to the substrate (the silicon wafer) and hence needs a higher current and voltage to reach the same temperature as a resistor over thick oxide.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6×1019 to 3.75×1020 have shown good results. with a reduced post anneal temperature. Both the first and second order temperature coefficients (TC1 and TC2) can then be adjusted. Using electrical trimming resistors can be produced with highly linear temperature characteristics. By varying the geometries of the resistors, low trimming threshold current densities and voltages can be used to produce good results.
Description
- 1. Field of the Invention
- The present invention relates generally to an improved polysilicon resistor and method for making the same.
- 2. Description of the Related Art
- Various types of polysilicon resistors have been known. However in making polysilicon resistors in the past several problems and deficiencies have been noted. Specifically a trimming of the resistance value either by lasers or by having multiple resistors and having to “blow” links have been needed to obtain high accuracy in the resistance value. Further the resistors that are formed have first and second order temperature coefficients (TC1 and TC2) in normal operation ranges that make them less than ideal.
- Other attempts at other non-laser trimmed resistor such as Isobe, et al. U.S. Pat. No. 5,187,559 and Amemiya et al., U.S. Pat. No. 4,210,996 have been tried. However these also suffer from various problems as to the temperature coefficients and the methods of making them are difficult. As an example although the Amemiya et al. device allows for electrical trimming however the temperature characteristics do not lend themselves to ready usage. Further a device built along the lines Amemiya et al. can only be built using doping concentrations at higher than 1×1020 atoms/
cm 3. Consequently this device is less than desirable. - A device according to Isobe, et al. actually requires that two dopings occur for each resistor one with a positive TC1 and a second with a negative TC1 be used so that a zero TC1 resistor can be formed. This increases the complexity of formation of the device. Further both dopings are at high levels of concentrations, which create problems in the manufacturing process.
- The present invention overcomes the shortcomings and deficiencies noted above by providing a new electrically trimmed polysilicon resistor that can be electrically trimmed by controlling the grain boundary resistance by the movement of the impurity doping. The second order temperature coefficient can also be altered in predictable manners. The trimming range of the resistor itself also can be adjusted over a very wide range.
- By having an electrically trimmed resistor of this type various types of improved and new devices can be built that have not been possible, heretofore.
- The improvement provided in the accuracy of the resistors can make termination devices such as SCSI terminators with fewer and more accurate resistors, making the SCSI terminators cheaper and/or more accurate.
- Improved temperature sensors are also possible. As the temperature coefficients and the resistance of one or more resistors can be independently adjusted an improved differential temperature sensor could be built. This independent adjustment can also make an improved zero temperature coefficient resistor possible that has adjustable temperature characteristics, by using two resistors and trimming them so that they have temperature coefficients of opposite signs.
- The ability to adjust first and second order temperature coefficients also allows for improved second order fits of resistors or with more linear temperature characteristics. It should be noted that TC2 as will be discussed below decreases considerably with electrical trimming at various doping concentrations (see for example FIG. 6).
- Other possibilities include improved anemometers and bolometers with increased sensitivity.
- Also as this “trimming” can be controlled by an electrical circuit the resistor can be used as a permanent indicator of events such as ESD event or it can act as a type of electrical fuse based upon a programmed change in a resistors characteristics.
- The trimmed resistor can also be used to improved bandgap circuits, A/D and D/A converters. OP-amp offsets, digital potentiometers and delay lines can likewise be improved. Also digital thermometers, oscillators and filters can also benefit from this type of resistor.
- As another example an electrically trimmed resistor could act as a multi-bit analog memory by employing multiple trimmed values of one or more of these resistors.
- Other advantages and novel features of the present invention can be understood and appreciated by reference to the following detailed description of the invention, taken in conjunction with the accompanying drawings in which:
- FIG. 1 is a block diagram of a resistor formed according to this invention.
- FIG. 2 is a timing diagram of a preferred embodiment for the electrical trimming or adjusting a resistor formed according to this invention; and
- FIGS.3-7 are graphs showing experimental test results on various versions resistors according to this invention.
- Referring now to the drawings wherein like or similar elements are designated with identical reference numerals.
- In the formation of the polysilicon resistor in the normal prior art process, doping is done very soon in the processing (generally immediately after) the film deposition step or in-situ during film deposition at concentrations of ˜1×1020 cm−3 and annealing at greater than 950° C. However the inventors herein have found that a polysilicon resistor with a much lower concentration of the dopant in the range of 6×1019 cm−3 or less can be built and can be electrically trimmed. This is thought to be possible due to a fine grain size which can result from a late implant process. This allows for a greater ability for trimming and eliminates the need for the double doping of the resistor as in Isobe, et al. Also, a lower temperature for the annealing may be used for example at a deposition temperature of 625° C. if a late implant process is employed. The low doped late-implanted resistors result in a finer grain size and hence have a higher grain boundary density compared to the highly doped early-implanted resistors. This increase in the grain boundary density results in reduced trimming current density and higher maximum trim percentages. For e.g. for a resistor of dimensions width=0.6 um, length=5 um, the late implant resistor can be trimmed to about 30% of its initial resistance while the early-implant resistor can be trimmed to only about 60% of its initial resistance.
- This allows for the use of a phosphorous dopant to create a zero temperature coefficient resistor and also allowing for an electrical trimming of the thus formed resistor. Prior art devices such as are shown in Isobe et al. and Amemiya et al. have neglected changes to the second order coefficient TC2 which is significant when a lower dopant concentration is employed. In fact the prior art devices have indicated that the doping concentration must be greater than 1×1020 atoms/cm3.
- The inventors have found that using a lower doping along with a lower final anneal temperature allows them to obtain an increased resistivity and the amount of dopant at the grain boundaries to also increase. This allows the resistor to be trimmed using much lower concentrations than had been thought possible.
- The polysilicon resistors used in this example were 0.4 μm thick, phosphorus-doped and deposited at 625° C. We have used resistors with a dopant concentration in the range −6×1019 cm−3 to 3.75×1020 cm−3 and examine the effect of electrical trimming on both TC1, TC2 and resistance. Other dopant species such as Arsenic, Boron and Antinomy, etc. are expected to produce similar results.
- The trimming behavior of TC1 and TC2 are shown in FIGS.3 for a
phosphorus concentration 6×1019 cm−3. This concentration was previously classified as untrimmable by Isobe et al., U.S. Pat. No. 5,187,559. The pre-trim sheet resistances in FIG. 3 are scattered around 285 Ω/square with TC1 in the 1000 ppm/° C. These data points correspond to different resistors on the same wafer and reflect the normal process variations between resistors. It can be seen that electrical trimming reduces the sheet resistance and also causes the TC1 to increase in a linear fashion. On the other hand, TC2 [FIG. 4] decreases linearly with trimming. - The inventors herein have used resistors ranging from a phosphorus concentration of ˜6×1019
cm −3 up to ˜3.75×1020 cm−3. Superimposing the data from these different dopings results in FIG. 5 and FIG. 6. From FIG. 5, it is evident that the magnitude of slope of TC1 versus Sheet Resistance curve increases as the doping is increased. Thus, by using differently doped resistors, we can obtain the same TC1 for different sheet resistances or alternately for a given Sheet Resistance we can obtain different TC1 values by changing the dopant concentration and amount of trim. The shaded area represents the possible TC1-Sheet Resistance combinations and includes the all-important zero TC1 value. It can be seen from this that the threshold current density for trimming reduces with increasing length and also has a width dependence. FIG. 4 shows the variation in TC2 versus Sheet Resistance for the dopant range mentioned above. The slope of TC2 versus sheet resistance does not change appreciably after electrically trimming the polysilicon resistors for differently doped resistors. In terms of TC2, trimming has the same effect as increasing the doping concentration during processing. - The formation of the resistor occurs by the following steps. In an exemplary process a substrate is initially prepared using known prior art conventional processing. A polycyrystalline silicon layer is deposited. This layer is ideally about 4000 Å thick. The layer is deposited and annealed at 625° C. with a deposition time of about 62 minutes. A poly resistor mask is then aligned and exposed. An ion implantation is done to provide the poly doping using a dose of about 1.5E16/cm2 with the ion energy at 60 keV. The insulating oxidation for the poly is formed at 950 ° C. for about 30 minutes. The mask for implant resistor is then aligned and exposed using a dose of 2.0E15 to 1.5E16/cm2 at an energy level of 100 KeV. After the resistor has been implanted an inter-level dielectric, viz. Borophosphosilicate Glass (or commonly called BPSG) is deposited on the wafer. The next step is an anneal at 900 C for 20 minutes in order to planarize the surface and densify the BPSG. Then conventional low temperature processing is done. This low temperature processing comprises the following steps. First contacts are etched in the BPSG. Then a TiN barrier layer is deposited on the BPSG. An Al—Cu layer is then deposited. This Al—Cu layer is then patterned and etched. A TEOS deposition for is then done passivation purposes. A nitride deposition is also then done for passivation purposes. The resultant material is then patterned and etched.
- The resistor as formed above can have the resistance and temperature coefficients adjusted by an electrical current either in the form of pulses or direct current. A typical timing diagram is given in FIG. 2 for the resistor trimming. A resistor formed according to this invention is trimmed by using current pulses of increasing amplitude while monitoring the resistance during the measure period. This is continued until the desired amount of trimming has been achieved. The pulse width that has been used successfully for this purpose is 500 us and the period is 10.5 ms.
- The voltages and currents used in prior art systems have generally been too high for easy incorporation into low-voltage devices. For example, the lowest threshold trimming current (the current at which the trimming begins) reported by Amemiya et al. was˜20 mA with a corresponding voltage of ˜16V. This voltage is not compatible with low-voltage processes. The inventors herein have made polysilicon resistors with widths ranging from 0.6 um to 1.5 um and lengths ranging from 2 um to 15 um (FIG. 7). It can be seen that the threshold current density for trimming reduces with increasing length and has a weak width dependence The length dependence is thought to be influenced by end effects. The dopant species from the highly doped polysilicon contact areas diffuse into the lighter doped regions, reducing the sheet resistance and increasing the grain size. Also, the polysilicon contact areas act as heat sinks reducing the average resistor temperature during trimming. This effect is pronounced for shorter resistors and decreases for longer resistors. By choosing suitable geometries resistors which trim at very low voltages and currents can be fabricated. Threshold current of ˜5 mA and less have shown acceptable results. Trimming voltages as low as ˜1.5V have also produced successful results.
- Further if resistors are placed over thick oxide (i.e. they have a higher degree of thermal isolation), they can be trimmed at lower currents and voltages compared to the same resistor over a thin oxide. A resistor over a thin oxide can lose heat easily to the substrate (the silicon wafer) and hence needs a higher current and voltage to reach the same temperature as a resistor over thick oxide. For example, a resistor of size width=2 um and Length=29 um had a trimming threshold at 18.5 mA, 13.3V when placed over thick oxide (4000 A) while the same resistor with only a thin layer of oxide (150 A) separating the silicon wafer from the resistor had a trimming threshold of 34.5 mA, 21V. This demonstrates that it is beneficial (lower trimming voltages and currents) from a trimming standpoint to thermally isolate resistors. One way to do this is to place them over a thick oxide layer so that less heat is lost by the resistor during trimming and the resistor achieves a higher temperature (The resistor heats up when you pass a current through it due to joule-heating or self-heating). An assumption which is implicit in this regard is that the resistor must heat up to a high enough temperature in order to trim.
- Obviously, numerous modifications and variations are possible in view of the teachings above. For example, the temperatures, concentrations, thickness, process sequence or the like can be varied as can the specific trimming stimulus and methodology.
- Accordingly, the present invention is not limited by the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions, without departing from the spirit and scope of the invention as set forth and defined by the following claims.
Claims (15)
1. A resistor having a resistance that can be adjusted by current being passed there through and which is formed as part of a semiconductor device comprising:
a polycrystalline silicon resistor formed of on a layer, wherein said polysilicon resistor is formed using a doping wherein said doping has a concentration of from ˜6×1019 cm−3 to ˜3.75×1020 cm−3.
2. A resistor having a resistance that can be adjusted by current being passed there through and which is formed as part of a semiconductor device comprising:
a polycrystalline silicon resistor formed of on a layer, wherein said polysilicon resistor is formed using a doping wherein said doping has a concentration of less than ˜3.75×1020 cm−3.
3. A method of making a polysilicon resistor comprising the steps of:
providing a substrate,
depositing a polycrystalline layer on said substrate,
aligning and exposing a poly resistor mask,
poly doping the polycrystalline layer,
forming an insulating oxide,
aligning and exposing the mask for the resistor,
depositing an inter level dielectric,
annealing the inter level dielectric, and
completing the processing using low temperature processing.
4. A method as in claim 3 wherein said first annealing step occurs at or below 900° C.
5. A method as in claim 3 wherein said formation of said insulating oxide occurs at or below 950° C.
6. A method as in claim 3 wherein said ion implantation to provide the poly doping results in a concentration of ˜6×1019 cm−3 to ˜3.75×1020 cm−3.
7. A method of trimming a poly silicon resistor to a target resistance formed using a low concentration doping comprising the steps of:
passing an electrical signal through said resistor,
measuring and increasing said passed electrical signal until the resistance of said resistor equals the target resistance.
8. A method of trimming a polysilicon resistor to a target resistance formed using a low concentration doping, as in claim 7 wherein the step of passing am electrical signal is by way of a current pulse through said resistor and said method further comprises:
measuring and increasing said passed current pulse until the resistance of said resistor equals the target resistance.
9. A method of trimming a polysilicon resistor to a target resistance formed using a low concentration doping as in claim 7 wherein the step of passing a current pulse through said resistor is less than 20 mA.
10. A method of trimming a polysilicon resistor to a target resistance formed using a low concentration doping as in claim 7 wherein the step of passing a current pulse through said resistor is done a voltage less than 16V.
11. A resistor having a resistance that can be adjusted by current being passed there through and which is formed as part of a semiconductor device comprising:
a polycrystalline silicon resistor formed of on a layer, wherein said polysilicon resistor is formed using a doping wherein said doping has a concentration of greater than ˜6×1019 cm−3.
12. A resistor having a resistance that can be adjusted by current being passed there through and which is formed as part of a semiconductor device comprising:
a polycrystalline silicon resistor formed of on a layer, wherein said polysilicon resistor is formed using a late implant doping technique.
13. A method as in claim 3 wherein said final annealing step occurs at or below 900° C.
14. A method of trimming a polysilicon resistor to a target resistance formed using a low concentration doping as in claim 7 wherein the electrical signal that is passed is less than 16V.
15. A method as in claim 3 further comprising the step of forming a field oxide layer prior to the depositing of said polycrystaline layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/964,192 US20020008302A1 (en) | 2000-04-26 | 2001-09-26 | Polysilicon resistor having adjustable temperature coefficients and the method of making the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/558,905 US6306718B1 (en) | 2000-04-26 | 2000-04-26 | Method of making polysilicon resistor having adjustable temperature coefficients |
US09/964,192 US20020008302A1 (en) | 2000-04-26 | 2001-09-26 | Polysilicon resistor having adjustable temperature coefficients and the method of making the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/558,905 Division US6306718B1 (en) | 2000-04-26 | 2000-04-26 | Method of making polysilicon resistor having adjustable temperature coefficients |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020008302A1 true US20020008302A1 (en) | 2002-01-24 |
Family
ID=24231472
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/558,905 Expired - Lifetime US6306718B1 (en) | 2000-04-26 | 2000-04-26 | Method of making polysilicon resistor having adjustable temperature coefficients |
US09/964,192 Abandoned US20020008302A1 (en) | 2000-04-26 | 2001-09-26 | Polysilicon resistor having adjustable temperature coefficients and the method of making the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/558,905 Expired - Lifetime US6306718B1 (en) | 2000-04-26 | 2000-04-26 | Method of making polysilicon resistor having adjustable temperature coefficients |
Country Status (1)
Country | Link |
---|---|
US (2) | US6306718B1 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020033519A1 (en) * | 2000-09-15 | 2002-03-21 | Babcock Jeffrey A. | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
WO2004097860A1 (en) * | 2003-03-20 | 2004-11-11 | Microbridge Technologies Inc. | Trimminig temperature coefficients of electronic components and circuits |
US6838747B2 (en) * | 2001-07-31 | 2005-01-04 | Renesas Technology Corp. | Semiconductor device having resistive element formed of semiconductor film |
US20050173779A1 (en) * | 2002-02-11 | 2005-08-11 | Luc Wuidart | Irreversible reduction of the value of a polycrystalline silicon resistor |
US20050258990A1 (en) * | 2001-09-07 | 2005-11-24 | Babcock Jeffrey A | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
US20100163947A1 (en) * | 2008-12-26 | 2010-07-01 | Lee Jong-Ho | Method for fabricating pip capacitor |
US20110220631A1 (en) * | 2008-03-14 | 2011-09-15 | Oleg Grudin | Method of stabilizing thermal resistors |
US9385087B2 (en) | 2013-10-18 | 2016-07-05 | Globalfoundries Inc. | Polysilicon resistor structure having modified oxide layer |
TWI552139B (en) * | 2013-10-07 | 2016-10-01 | 咕果公司 | Variable resolution seamless tileable display |
US9460789B2 (en) | 2014-03-03 | 2016-10-04 | Stmicroelectronics (Grenoble 2) Sas | Non-volatile digital memory including thin film resistors |
US20160359867A1 (en) * | 2013-09-11 | 2016-12-08 | Oracle International Corporation | Adjusting enterprise security using a mobile device |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6532568B1 (en) * | 2000-10-30 | 2003-03-11 | Delphi Technologies, Inc. | Apparatus and method for conditioning polysilicon circuit elements |
US6875828B2 (en) * | 2002-09-04 | 2005-04-05 | Univation Technologies, Llc | Bimodal polyolefin production process and films therefrom |
US8008700B2 (en) * | 2002-12-19 | 2011-08-30 | Sandisk 3D Llc | Non-volatile memory cell with embedded antifuse |
US20070164388A1 (en) * | 2002-12-19 | 2007-07-19 | Sandisk 3D Llc | Memory cell comprising a diode fabricated in a low resistivity, programmed state |
US7660181B2 (en) * | 2002-12-19 | 2010-02-09 | Sandisk 3D Llc | Method of making non-volatile memory cell with embedded antifuse |
US7800933B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance |
US7618850B2 (en) * | 2002-12-19 | 2009-11-17 | Sandisk 3D Llc | Method of making a diode read/write memory cell in a programmed state |
US7800932B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
CA2519690A1 (en) * | 2003-03-20 | 2004-11-11 | Microbridge Technologies Inc. | Bidirectional thermal trimming of electrical resistance |
WO2005006100A2 (en) * | 2003-07-14 | 2005-01-20 | Microbrige Technologies Inc. | Adjusting analog electric circuit outputs |
CN100378958C (en) * | 2003-12-22 | 2008-04-02 | 上海贝岭股份有限公司 | Method for making polysilicon high-ohmic resistor of integrated circuit |
US7269673B2 (en) * | 2004-02-18 | 2007-09-11 | Silicon Image, Inc. | Cable with circuitry for asserting stored cable data or other information to an external device or user |
US7714694B2 (en) * | 2004-09-21 | 2010-05-11 | Microbridge Technologies Canada, Inc. | Compensating for linear and non-linear trimming-induced shift of temperature coefficient of resistance |
US7217981B2 (en) | 2005-01-06 | 2007-05-15 | International Business Machines Corporation | Tunable temperature coefficient of resistance resistors and method of fabricating same |
US7241663B2 (en) * | 2005-04-19 | 2007-07-10 | Texas Instruments Incorporated | Maskless multiple sheet polysilicon resistor |
US7800934B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Programming methods to increase window for reverse write 3D cell |
EP2002453A1 (en) * | 2006-03-23 | 2008-12-17 | Microbridge Technologies Inc. | Compensating for linear and non-linear trimming-induced shift of temperature coefficient of resistance |
JP2009543670A (en) * | 2006-07-17 | 2009-12-10 | メドラッド インコーポレーテッド | Integrated medical imaging system |
US7499355B2 (en) * | 2006-07-31 | 2009-03-03 | Sandisk 3D Llc | High bandwidth one time field-programmable memory |
US7450414B2 (en) | 2006-07-31 | 2008-11-11 | Sandisk 3D Llc | Method for using a mixed-use memory array |
US7495947B2 (en) * | 2006-07-31 | 2009-02-24 | Sandisk 3D Llc | Reverse bias trim operations in non-volatile memory |
US7492630B2 (en) * | 2006-07-31 | 2009-02-17 | Sandisk 3D Llc | Systems for reverse bias trim operations in non-volatile memory |
US7486537B2 (en) * | 2006-07-31 | 2009-02-03 | Sandisk 3D Llc | Method for using a mixed-use memory array with different data states |
US20080023790A1 (en) * | 2006-07-31 | 2008-01-31 | Scheuerlein Roy E | Mixed-use memory array |
US7719874B2 (en) * | 2006-07-31 | 2010-05-18 | Sandisk 3D Llc | Systems for controlled pulse operations in non-volatile memory |
US20080025069A1 (en) * | 2006-07-31 | 2008-01-31 | Scheuerlein Roy E | Mixed-use memory array with different data states |
US7499304B2 (en) * | 2006-07-31 | 2009-03-03 | Sandisk 3D Llc | Systems for high bandwidth one time field-programmable memory |
US7522448B2 (en) * | 2006-07-31 | 2009-04-21 | Sandisk 3D Llc | Controlled pulse operations in non-volatile memory |
US8125019B2 (en) | 2006-10-18 | 2012-02-28 | International Business Machines Corporation | Electrically programmable resistor |
US8111128B2 (en) * | 2007-02-06 | 2012-02-07 | Sensortechnics GmbH | Multi-structure thermally trimmable resistors |
US7830697B2 (en) * | 2007-06-25 | 2010-11-09 | Sandisk 3D Llc | High forward current diodes for reverse write 3D cell |
US8102694B2 (en) * | 2007-06-25 | 2012-01-24 | Sandisk 3D Llc | Nonvolatile memory device containing carbon or nitrogen doped diode |
US8072791B2 (en) * | 2007-06-25 | 2011-12-06 | Sandisk 3D Llc | Method of making nonvolatile memory device containing carbon or nitrogen doped diode |
US7684226B2 (en) * | 2007-06-25 | 2010-03-23 | Sandisk 3D Llc | Method of making high forward current diodes for reverse write 3D cell |
US7800939B2 (en) * | 2007-06-29 | 2010-09-21 | Sandisk 3D Llc | Method of making 3D R/W cell with reduced reverse leakage |
US7759666B2 (en) * | 2007-06-29 | 2010-07-20 | Sandisk 3D Llc | 3D R/W cell with reduced reverse leakage |
US7846782B2 (en) | 2007-09-28 | 2010-12-07 | Sandisk 3D Llc | Diode array and method of making thereof |
US7830698B2 (en) * | 2008-04-11 | 2010-11-09 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US7812335B2 (en) * | 2008-04-11 | 2010-10-12 | Sandisk 3D Llc | Sidewall structured switchable resistor cell |
US8450835B2 (en) * | 2008-04-29 | 2013-05-28 | Sandisk 3D Llc | Reverse leakage reduction and vertical height shrinking of diode with halo doping |
US9595518B1 (en) | 2015-12-15 | 2017-03-14 | Globalfoundries Inc. | Fin-type metal-semiconductor resistors and fabrication methods thereof |
US9806256B1 (en) | 2016-10-21 | 2017-10-31 | Sandisk Technologies Llc | Resistive memory device having sidewall spacer electrode and method of making thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53136980A (en) | 1977-05-04 | 1978-11-29 | Nippon Telegr & Teleph Corp <Ntt> | Resistance value correction method for poly crystal silicon resistor |
JP2658570B2 (en) | 1990-02-28 | 1997-09-30 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
KR100215845B1 (en) * | 1997-03-17 | 1999-08-16 | 구본준 | Fabrication process of semiconductor |
TW331033B (en) * | 1997-08-16 | 1998-05-01 | Winbond Electronics Corp | Static random access memory self-aligned load structure and producing method |
-
2000
- 2000-04-26 US US09/558,905 patent/US6306718B1/en not_active Expired - Lifetime
-
2001
- 2001-09-26 US US09/964,192 patent/US20020008302A1/en not_active Abandoned
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020033519A1 (en) * | 2000-09-15 | 2002-03-21 | Babcock Jeffrey A. | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
US6958523B2 (en) * | 2000-09-15 | 2005-10-25 | Texas Instruments Incorporated | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
US6838747B2 (en) * | 2001-07-31 | 2005-01-04 | Renesas Technology Corp. | Semiconductor device having resistive element formed of semiconductor film |
US20050258990A1 (en) * | 2001-09-07 | 2005-11-24 | Babcock Jeffrey A | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
US7422972B2 (en) | 2001-09-07 | 2008-09-09 | Texas Instruments Incorporated | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
US7427802B2 (en) * | 2002-02-11 | 2008-09-23 | Stmicroelectronics S.A. | Irreversible reduction of the value of a polycrystalline silicon resistor |
US20050173779A1 (en) * | 2002-02-11 | 2005-08-11 | Luc Wuidart | Irreversible reduction of the value of a polycrystalline silicon resistor |
US20060279349A1 (en) * | 2003-03-20 | 2006-12-14 | Oleg Grudin | Trimming temperature coefficients of electronic components and circuits |
WO2004097860A1 (en) * | 2003-03-20 | 2004-11-11 | Microbridge Technologies Inc. | Trimminig temperature coefficients of electronic components and circuits |
US7703051B2 (en) | 2003-03-20 | 2010-04-20 | Microbridge Technologies Inc. | Trimming temperature coefficients of electronic components and circuits |
US20110220631A1 (en) * | 2008-03-14 | 2011-09-15 | Oleg Grudin | Method of stabilizing thermal resistors |
US8847117B2 (en) * | 2008-03-14 | 2014-09-30 | Sensortechnics GmbH | Method of stabilizing thermal resistors |
US20100163947A1 (en) * | 2008-12-26 | 2010-07-01 | Lee Jong-Ho | Method for fabricating pip capacitor |
US8039355B2 (en) * | 2008-12-26 | 2011-10-18 | Dongbu Hitek Co., Ltd. | Method for fabricating PIP capacitor |
US20160359867A1 (en) * | 2013-09-11 | 2016-12-08 | Oracle International Corporation | Adjusting enterprise security using a mobile device |
TWI552139B (en) * | 2013-10-07 | 2016-10-01 | 咕果公司 | Variable resolution seamless tileable display |
US9385087B2 (en) | 2013-10-18 | 2016-07-05 | Globalfoundries Inc. | Polysilicon resistor structure having modified oxide layer |
US9460789B2 (en) | 2014-03-03 | 2016-10-04 | Stmicroelectronics (Grenoble 2) Sas | Non-volatile digital memory including thin film resistors |
Also Published As
Publication number | Publication date |
---|---|
US6306718B1 (en) | 2001-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6306718B1 (en) | Method of making polysilicon resistor having adjustable temperature coefficients | |
US5352923A (en) | Trench resistors for integrated circuits | |
US7964919B2 (en) | Thin film resistors integrated at two different metal single die | |
US7704871B2 (en) | Integration of thin film resistors having different TCRs into single die | |
US5187559A (en) | Semiconductor device and process for producing same | |
EP0281276A1 (en) | Fabrication of polycrystalline silicon resistors | |
KR100363667B1 (en) | Stabilized Polysilicon Resistor and Manufacturing Method Thereof | |
EP0145926B1 (en) | Polysilicon resistors compensated with double ion-implantation | |
KR101050867B1 (en) | High resistance value split poly shock resistance with low standard deviation | |
US6960979B2 (en) | Low temperature coefficient resistor | |
US5759887A (en) | Semiconductor device and a method of manufacturing a semiconductor device | |
US5140299A (en) | Article comprising a high value resistor | |
US7202533B1 (en) | Thin film resistors integrated at a single metal interconnect level of die | |
US7038297B2 (en) | Semiconductor diffused resistors with optimized temperature dependence | |
US6242314B1 (en) | Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor | |
US6291306B1 (en) | Method of improving the voltage coefficient of resistance of high polysilicon resistors | |
US6136634A (en) | Method of manufacturing semiconductor resistors | |
JPH06204408A (en) | Diffused resistor for semiconductor device | |
JPS63169057A (en) | Method of forming electric resistor by doping semiconductor material and integrated circuit manufactured by the method | |
US4701241A (en) | Method of making a resistor | |
EP0116702A2 (en) | Method for forming polycrystalline silicon resistors having reproducible and controllable resistivities | |
US6645803B1 (en) | Method for modifying the doping level of a silicon layer | |
US10014364B1 (en) | On-chip resistors with a tunable temperature coefficient of resistance | |
RU2376668C1 (en) | Method of making high-ohmic polysilicon resistor | |
EP0257677A2 (en) | Trimmable high value polycrystalline silicon resisitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |