US20020001945A1 - Method of manufacturing metal pattern of semiconductor device - Google Patents

Method of manufacturing metal pattern of semiconductor device Download PDF

Info

Publication number
US20020001945A1
US20020001945A1 US09/794,616 US79461601A US2002001945A1 US 20020001945 A1 US20020001945 A1 US 20020001945A1 US 79461601 A US79461601 A US 79461601A US 2002001945 A1 US2002001945 A1 US 2002001945A1
Authority
US
United States
Prior art keywords
layer
pattern
metal
forming
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/794,616
Other versions
US6451691B2 (en
Inventor
Won-sang Song
In-sun Park
Kyung-Bum Koo
Young-Cheon Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YOUNG-CHEON, KOO, KYUNG-BUM, PARK, IN-SUN, SONG, WON-SANG
Publication of US20020001945A1 publication Critical patent/US20020001945A1/en
Application granted granted Critical
Publication of US6451691B2 publication Critical patent/US6451691B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids

Definitions

  • the present invention relates to a method of manufacturing a metal pattern of a semiconductor device, and more particularly, to a method of manufacturing a metal pattern of a semiconductor device which has improved stability and adhesiveness for subsequent processes.
  • FIGS. 1A to 1 D are schematic cross-sectional views illustrating the conventional method of manufacturing a metal pattern of a semiconductor device.
  • an insulating layer 110 comprising silicon oxide is formed on a semiconductor substrate 100 having an impurity doped region 101 .
  • An opening 112 which exposes the impurity doped region 101 is formed in the insulating layer 110 by a photolithography process.
  • FIG. 1B illustrates the processes for forming a metal pattern.
  • a Ti (titanium) layer 121 is formed by depositing Ti by a sputtering or a CVD method to a thickness of about 30-500 ⁇ . The Ti layer 121 is formed to improve adhesiveness between a subsequently deposited metal material and the underlying silicon oxide layer.
  • a TiN (titanium nitride) layer 122 is formed as a barrier layer to a thickness of about 50-2000 ⁇ . The TiN layer 122 is formed to prevent an impregnation of a subsequently deposited metal material to form a metal layer contacting the underlying active region.
  • a metal such as tungsten, aluminum, or the like is deposited to a thickness of about 300-8000 ⁇ to form a metal layer 123 , and a SiN (silicon nitride) layer 124 is then deposited on metal layer 123 .
  • the SiN layer 124 is formed by depositing SiN using a low pressure chemical vapor deposition (LPCVD) method.
  • the LPCVD is a deposition method for forming thin films using a chemical reaction by employing heat energy in a reaction vessel where the pressure is maintained at about 200-700 torr.
  • the LPCVD is performed by heat-treating at about 400-600° C. with a mixed gas of SiH 4 and N 2 , or a mixed gas of SiH 4 and N 2 O as source gases. With this method, the uniformity and step coverage of the resulting film is good and a large number of wafers can be processed at once.
  • an anisotropic etching from the upper layer is to implemented by using a photoresist pattern 130 as an etching mask to form a desired pattern.
  • a photoresist pattern 130 Beneath the photoresist pattern 130 , an SiN pattern 124 a , a metal layer pattern 123 a , a TiN pattern 122 a and a Ti pattern 121 a are successively formed.
  • the SiN pattern 124 a formed on the metal layer pattern 123 a functions as an anti-reflective layer during a subsequent photolithography process, and it also reinforces shoulders of SiN spacers formed on both sidewalls of the metal pattern.
  • sidewalls of each pattern Ti pattern 121 b , TiN pattern 122 b , metal layer pattern 123 a , and SiN pattern 124 a ) are exposed.
  • the photoresist pattern 130 is removed and SiN is deposited on the thus obtained pattern.
  • An etch back process is implemented to form SiN spacers 125 on side walls of the patterns to prevent an oxidation of a metal, and to implement a self aligned contact hole (SAC) process to manufacture a metal pattern 120 .
  • the LPCVD deposition parameters for forming the SiN spacers 125 are the same as those for the SiN layer 124 .
  • a defect may be generated by a thermal budget on the metal layer during the spacer forming process after forming the metal pattern.
  • the thermal budget may generate gases from layers surrounding the metal layer, such as an insulating layer.
  • the gases for example, oxygen, humidity, etc., can function as oxidizing agents and potentially oxidize surrounding exposed metal, especially an exposed portion of the Ti pattern which has a high reactivity. If so, the adhesiveness and the stability of the metal pattern is reduced. If a subsequent metal layer pattern having a strong stress characteristic is formed on the oxidized Ti pattern, a separation of a portion of the Ti layer can be induced if the applied stress is larger than a critical value at an edge portion of the Ti pattern.
  • FIG. 2 illustrates graphs obtained by detecting amounts of gases generated from an insulating layer during a heat treatment for the formation of a subsequent layer.
  • ‘a’ corresponds to H 2 0 gas
  • ‘b’ corresponds to O 2 gas when the insulating layer (silicon oxide layer) is formed and as the subsequent layer (SiN layer) is formed.
  • FIG. 2 confirms that an appreciable amount of oxidizing gases are generated during the heat treatment.
  • the gas generated from one wafer does not induce a considerable problem, however, when a process is implemented for about ten wafers simultaneously, the proportional increased in gas generated might induce a lifting of the metal pattern.
  • U.S. Pat. No. 5,705,428, issued to Liu et al. discloses a method of forming a nitride layer on side walls of a metal pattern by injecting additional N 2 gas during a typical etching process.
  • additional injected N 2 gas produces undesirable polymer residues, and the etching efficiency and etching ratio are reduced.
  • a high vacuum environment is required during the etching when utilizing some types of equipment, but the addition of N 2 gas deteriorates the etching.
  • H 2 O is added during an ashing process using oxygen to form a metal oxide at an edge portion of the metal layer.
  • the oxide compound is not uniformly formed, but is partially formed depending on the type of the metal, the grain sizes of the metal, and the quality of the interface of the metal. Accordingly, the control of the formation of the oxide layer is difficult and sometimes this oxide layer weakens the adhesiveness of the metal.
  • a method of manufacturing a metal pattern of a semiconductor device is provided. First, a Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer. An exposed portion of the Ti layer pattern forms TiN as a main product by implementing a heat treatment process under an atmosphere of a compound including nitrogen.
  • a method of manufacturing a metal pattern of a semiconductor device including the following steps.
  • a Ti layer and a metal layer are formed on a semiconductor substrate or an insulating layer.
  • a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer.
  • a metal nitride layer is formed by depositing metal nitride on the wiring pattern.
  • a metal nitride pattern is formed on side walls of the Ti layer pattern and the metal layer pattern by etching the metal nitride layer.
  • an exposed portion of a Ti layer which has high reactivity and induces various problems while implementing other processes, is treated by a compound including nitrogen in advance to form a nitride layer to protect the Ti layer, and therefore, the various problems associated with the exposed Ti layer can be overcome.
  • FIGS. 1 A- 1 D are cross-sectional views showing a conventional method of manufacturing a metal pattern of a semiconductor device
  • FIG. 2 is a graph obtained by detecting the amount of gas generated from an insulating layer during a heat treatment for the formation of a subsequent layer;
  • FIGS. 3 A- 3 E are schematic cross-sectional views showing a method of manufacturing a metal pattern according to a first embodiment of the present invention
  • FIG. 4 is a cross-sectional view of a metal pattern manufactured by a second embodiment of the present invention.
  • FIGS. 5 A- 5 C are cross-sectional views showing a method of manufacturing a metal pattern according to a third embodiment of the present invention.
  • FIGS. 3 A- 3 E are schematic cross-sectional views illustrating a method of manufacturing a metal pattern according to a first embodiment of the present invention.
  • an insulating layer 210 of silicon oxide is formed on a semiconductor substrate 200 in which an impurity doped region 210 is formed.
  • An opening 212 which exposes the impurity doped region 210 is formed on the insulating layer 210 by a photolithography process.
  • a Ti layer 221 is formed by depositing Ti by a sputtering method or a CVD method to a thickness of about 30-500 ⁇ .
  • the Ti layer functions to increase the adhesiveness between a subsequently deposited metal material and an underlying silicon oxide layer.
  • a TiN (titanium nitride) layer 222 is formed as a barrier layer to a thickness of about 50-2000 ⁇ .
  • the TiN layer 222 is formed to prevent an impregnation of a subsequently deposited metal material to form a metal layer contacting the underlying active region.
  • a Ti/TiN layer is applied as a barrier layer between a silicon layer and a metal layer, while a Ti layer or TiN layer is applied between metal layers.
  • a metal layer 223 is formed by depositing a metal such as tungsten, aluminum, or the like by a CVD method or a sputtering method to a thickness of about 300-8000 ⁇ .
  • tungsten As for the metal material for forming the metal layer, tungsten, aluminum, aluminum-copper alloy, aluminum-copper-tungsten alloy, aluminum-scandium alloy, copper, cobalt, gold, silver, molybdenum, etc. can be used. Among them, tungsten is preferably applied because it has a low resistivity and a high melting point, and thus has good chemical vapor deposition characteristics and good step coverage.
  • tungsten hexafluoride (WF 6 ) having a boiling point is at room temperature, is preferable to tungsten hexachloride (WCl 6 ), which has a high melting point and is in a solid state at room temperature.
  • Aluminum itself has a low melting point of 600° C., and a processing temperature for a mixture of aluminum and silicon is about 577° C. Therefore, processing at a high temperatures is difficult and voids will likely be generated in the resulting device. But, aluminum is cheaper than tungsten and has a low resistivity, and so a process control using aluminum is advantageous as well. Furthermore, aluminum has good reflow characteristics. Accordingly, aluminum is widely used as the metal material.
  • the barrier layer including Ti/metal, such as Ti/TiN/W, Ti/W, Ti/TiN/Al, Ti/Al, etc.
  • Copper has a high diffusion coefficient with respect to silicon oxide and silicon, and thus is not generally used as a barrier layer. For example, if copper is diffused into an insulating layer, the insulating layer becomes conductive thereby reducing the insulating characteristics. However, copper is cheap and has a low resistivity and so efforts continue for ways to successfully employ copper as a barrier layer.
  • an SiN layer 224 is formed by depositing SiN.
  • the SiN layer 224 is formed by depositing SiN in the presence of a mixed gas of SiH 4 and N 2 , or a mixed gas of SiH 4 and N 2 0 , at about 400-600° C. using an LPCVD method.
  • a photoresist pattern 230 is formed by depositing, exposing and developing a photoresist layer using a typical photolithography process.
  • an anisotropic RIE (reactive ion etching) method is performed using the photoresist pattern 230 as an etching mask. Then, the photoresist layer 230 is removed to obtain desired patterns.
  • the resulting patterns starting with the uppermost layer, are an SiN pattern 224 a , a metal layer pattern 223 a , a TiN pattern 222 a and a Ti pattern 221 a.
  • the SiN pattern 224 a formed on the metal layer pattern 223 a functions as an anti-reflective layer during the subsequently implemented photolithography process, and also functions to reinforce the shoulder of SiN spacers which will be formed at the sidewalls of a metal pattern.
  • each pattern i.e., Ti pattern 221 b , TiN pattern 222 b , metal layer pattern 223 b , and SiN pattern 224 b
  • the Ti pattern 221 a which has a good reactivity and a weak stress
  • the metal layer pattern 223 a which has a stronger stress than that of the Ti pattern 221 a
  • the TiN pattern 222 a being interposed between them.
  • a TiN layer 221 c is formed by heat treating in an atmosphere of a compound including nitrogen, thereby nitrifying an exposed sidewall portion of the Ti pattern 221 b.
  • a compound including nitrogen nitrogen gas, ammonia gas, a compound including nitrogen ion, or a compound including nitrogen atom, can be used.
  • any compounds which can react with the exposed Ti and form TiN on the surface of the Ti pattern can be used.
  • the heat treating is implemented by a RTA (rapid thermal annealing) process or a furnace annealing process.
  • the precise parameters of the heat treating process can be modified according to the equipment employed. For example, the heat treating may take a shorter time when RTA equipment is used, because the desired temperature can be reached in a shorter time. Conversely, heat treating takes longer in a furnace because it takes longer to reach the desired temperature. Accordingly, the heat treating condition should be controlled so as to form the TiN layer 221 c to a thickness of about 10-500 ⁇ , and more preferably, 10-50 ⁇ on the side walls of the Ti pattern 221 a.
  • the present inventors found that the heat treating is preferably implemented by an RTA process under an atmosphere range of about
  • the exposed portion of the Ti layer forms TiN as a main product.
  • the presence of oxygen is inevitable in the heat treating environment.
  • TiON can thus be formed as a byproduct of the heat treating under an atmosphere including both nitrogen and oxygen.
  • the TiON byproduct does not affect the operation and objectives of the present invention, and thus an additional process to avoid the formation of TiON is not required.
  • undesirable TiO 2 can be formed and so the amount of oxygen should be controlled.
  • heat treating is conducted in a furnace, it is preferably performed in the furnace annealing equipment under an atmosphere range of bout 1 ⁇ 10 ⁇ 10 -760 torr, at a temperature range of about 500-750° C., for about 40-60 minutes.
  • SiN is deposited on the thus obtained pattern at about 400-600° C. by the LPCVD method.
  • SiN spacers 225 are formed on side walls of the metal pattern by implementing an etch back process, and a metal pattern 220 having spacers on side walls thereof is formed.
  • SiN spacers 225 prevent an oxidation of the metal and facilitates an SAC forming process.
  • the formation of the SiN layer to form the SiN spacers 225 can be implemented after the heat treating in situ.
  • the processes for nitrifying the exposed portion of the TiN layer and the subsequent formation of the SiN layer to form the SiN spacers are closely connected, thereby avoiding excessive delay in forming the nitride layer. According to this embodiment, since the process for forming the SiN spacers is implemented after the passivation process of the exposed Ti layer, the oxidation of the Ti layer during the subsequent heat treating can be overcome.
  • FIG. 4 is a cross-sectional view of a metal pattern manufactured by a second embodiment of the present invention.
  • the exposed side walls of the metal layer 223 b also can form a nitride compound 223 c.
  • the thickness of the nitride compound 223 c depends on the reactivity with the metal according to the type of the metal be used.
  • the metal nitride compound is preferable because it protects the metal layer and has no known negative effects.
  • a metal nitride layer can be formed on the side walls of the metal pattern after the etching of the metal layer by using the photoresist pattern to prevent a generation of a defect due to an exposed Ti layer.
  • the metal nitride layer is formed by depositing a metal nitride compound at a low temperature to a thickness of about 10-500 ⁇ , and preferably to about 10-50 ⁇ , and then implementing an etch back process until the surface of the substrate is exposed.
  • FIGS. 5 A- 5 C are cross-sectional views showing a method of manufacturing a metal pattern according to the third embodiment of the present invention.
  • an SiN pattern 224 a , a metal layer pattern 223 a , a TiN pattern 222 a , and a Ti pattern 221 a are formed in the same manner as described with regard to FIG. 3C. After forming these patterns, the side walls of each pattern are exposed as described previously.
  • TiN is deposited on the thus obtained etched pattern, by a sputtering method or a CVD method, to a thickness of about 10-500 ⁇ , and preferably to a thickness of about 50 ⁇ to form a thin TiN layer 226 .
  • an etch back process is implemented until the substrate is exposed to form a TiN pattern 226 a which has a spacer shape, on the side walls of the etched pattern. Then, SiN is deposited on the thus obtained pattern and an etch back process is implemented to form an SiN spacer on side walls of the metal pattern.
  • the SiN spacer functions to prevent an oxidation of the metal and reinforces an SAC process.
  • the metal nitride is additionally deposited and then etched, which increases the complexity of the process.
  • this additional nitride layer improves the adhesiveness and stability of the metal pattern. Considering these effects, the more complex process can be readily applied.
  • the metal nitride compounds TiN, WN, and the like can be used. More preferably, the deposition of the metal nitride compounds is implemented under an atmosphere of a compound including nitrogen.
  • the metal pattern is formed on a substrate or an insulating layer.
  • the metal pattern also can be formed on an interlayer dielectric for an interconnection.
  • the present invention can be applied to all types of devices including a metal pattern having a barrier layer, for example, a DRAM, SRAM, CMOS, Bi-MOS, MOSFET, etc.
  • nitride layer is formed on an exposed portion of a Ti layer, which has a high reactivity and functions as a protecting layer according to the method of the present invention, it should be understood that the present invention can be applied to other metal layers if the spirit of the present invention is utilized to solve the problems as described herein.
  • the decrease in the stability or adhesiveness of a metal pattern attributed to an indirect influence of a subsequent thermal process, can be overcome and a metal pattern of a semiconductor device having good stability and adhesion qualities can be manufactured.
  • the formation of the nitride layer on side walls of the metal pattern is separately implemented, this process does not affect other processes. Accordingly, the Ti layer can be effectively protected without accompanying side-effects or adverse consequences.
  • the heat treating under an atmosphere of a compound including nitrogen is implemented after the etching of the metal pattern and before the subsequent thermal process, the Ti layer which has a high reactivity can be protected.
  • the heat treating at a high temperature induces the generation of gas from surrounding layers, such as the insulating layer, to reduce an amount of gas generated during the subsequent thermal process. Therefore, even if ten or more wafers are subjected to the thermal process, a lifting of the metal layer rarely occurs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method of manufacturing a metal pattern of a semiconductor device, and more particularly, to a method of manufacturing a metal pattern of a semiconductor device which has improved stability and adhesiveness for subsequent processes. [0002]
  • 2. Description of the Related Art [0003]
  • Semiconductor devices require high capacity and fast operating speeds to power today's electronic devices. Accordingly, semiconductor device manufacturing methods continually strive to improve the integration density, reliability, and response times of the devices. [0004]
  • However, as the integration density increases and the overall size of the device itself decreases, limitations are encountered. For example, as the critical dimension of the device is reduced to sub-micron size or less in order to increase the integration density, the channel lengths, distances between active regions, sizes of via holes or studs, contact areas between metals, etc. are reduced. This causes various problems, such as short channel effect (SCE) or stability, with regard to a transistor for example. Also, problems concerning resistance, stability, or adhesiveness between layers are generated as the critical dimension of metal patterns is reduced. The stability or adhesiveness of the metal pattern may deteriorate during the implementing processes to form a metal pattern after depositing a metal, or due to an indirect influence of a subsequent process. [0005]
  • FIGS. 1A to [0006] 1D are schematic cross-sectional views illustrating the conventional method of manufacturing a metal pattern of a semiconductor device. Referring to FIG. 1A, an insulating layer 110 comprising silicon oxide is formed on a semiconductor substrate 100 having an impurity doped region 101. An opening 112 which exposes the impurity doped region 101 is formed in the insulating layer 110 by a photolithography process.
  • FIG. 1B illustrates the processes for forming a metal pattern. First, a Ti (titanium) [0007] layer 121 is formed by depositing Ti by a sputtering or a CVD method to a thickness of about 30-500 Å. The Ti layer 121 is formed to improve adhesiveness between a subsequently deposited metal material and the underlying silicon oxide layer. On the Ti layer 121, a TiN (titanium nitride) layer 122 is formed as a barrier layer to a thickness of about 50-2000 Å. The TiN layer 122 is formed to prevent an impregnation of a subsequently deposited metal material to form a metal layer contacting the underlying active region. Thereafter, a metal such as tungsten, aluminum, or the like is deposited to a thickness of about 300-8000 Å to form a metal layer 123, and a SiN (silicon nitride) layer 124 is then deposited on metal layer 123.
  • The SiN [0008] layer 124 is formed by depositing SiN using a low pressure chemical vapor deposition (LPCVD) method. The LPCVD is a deposition method for forming thin films using a chemical reaction by employing heat energy in a reaction vessel where the pressure is maintained at about 200-700 torr. The LPCVD is performed by heat-treating at about 400-600° C. with a mixed gas of SiH4 and N2, or a mixed gas of SiH4 and N2O as source gases. With this method, the uniformity and step coverage of the resulting film is good and a large number of wafers can be processed at once.
  • Referring to FIG. 1C, an anisotropic etching from the upper layer is to implemented by using a [0009] photoresist pattern 130 as an etching mask to form a desired pattern. Beneath the photoresist pattern 130, an SiN pattern 124 a, a metal layer pattern 123 a, a TiN pattern 122 a and a Ti pattern 121 a are successively formed. The SiN pattern 124 a formed on the metal layer pattern 123 a functions as an anti-reflective layer during a subsequent photolithography process, and it also reinforces shoulders of SiN spacers formed on both sidewalls of the metal pattern. After implementing this etching, note that sidewalls of each pattern (Ti pattern 121 b, TiN pattern 122 b, metal layer pattern 123 a, and SiN pattern 124 a) are exposed.
  • Referring to FIG. 1D, the [0010] photoresist pattern 130 is removed and SiN is deposited on the thus obtained pattern. An etch back process is implemented to form SiN spacers 125 on side walls of the patterns to prevent an oxidation of a metal, and to implement a self aligned contact hole (SAC) process to manufacture a metal pattern 120. The LPCVD deposition parameters for forming the SiN spacers 125 are the same as those for the SiN layer 124.
  • The SAC process is briefly explained as follows. Present semiconductor devices have a design rule of 0.15 μm or less, and accordingly, the critical dimension is reduced and contact holes must be formed in even thicker interlayer dielectric layers. As a result, it becomes difficult to maintain the process margins during the formation of the contact hole, and in order to ensure the process margin, spacers are formed on the side walls of the pattern. Essentially, the spacer secures the process margin and is called a shoulder margin. [0011]
  • During the manufacturing process of the metal pattern, the following factors may influence the characteristics of the metal layer. [0012]
  • A defect may be generated by a thermal budget on the metal layer during the spacer forming process after forming the metal pattern. Also, the thermal budget may generate gases from layers surrounding the metal layer, such as an insulating layer. The gases, for example, oxygen, humidity, etc., can function as oxidizing agents and potentially oxidize surrounding exposed metal, especially an exposed portion of the Ti pattern which has a high reactivity. If so, the adhesiveness and the stability of the metal pattern is reduced. If a subsequent metal layer pattern having a strong stress characteristic is formed on the oxidized Ti pattern, a separation of a portion of the Ti layer can be induced if the applied stress is larger than a critical value at an edge portion of the Ti pattern. [0013]
  • FIG. 2 illustrates graphs obtained by detecting amounts of gases generated from an insulating layer during a heat treatment for the formation of a subsequent layer. In FIG. 2, ‘a’ corresponds to [0014] H 2 0 gas and ‘b’ corresponds to O2 gas when the insulating layer (silicon oxide layer) is formed and as the subsequent layer (SiN layer) is formed. FIG. 2 confirms that an appreciable amount of oxidizing gases are generated during the heat treatment. The gas generated from one wafer does not induce a considerable problem, however, when a process is implemented for about ten wafers simultaneously, the proportional increased in gas generated might induce a lifting of the metal pattern.
  • In order to solve the above-mentioned problem, various methods have been suggested. U.S. Pat. Nos. 5,310,456 and 5,314,576, both issued to Kadomura, disclose a process for protecting side walls of a metal by using a protecting layer. However, this method costs a great deal, is inefficient, and is difficult to implement in a practical way. [0015]
  • U.S. Pat. No. 5,705,428, issued to Liu et al., discloses a method of forming a nitride layer on side walls of a metal pattern by injecting additional N[0016] 2 gas during a typical etching process. However, the additional injected N2 gas produces undesirable polymer residues, and the etching efficiency and etching ratio are reduced. Furthermore, a high vacuum environment is required during the etching when utilizing some types of equipment, but the addition of N2 gas deteriorates the etching.
  • In another method, H[0017] 2O is added during an ashing process using oxygen to form a metal oxide at an edge portion of the metal layer. However, the oxide compound is not uniformly formed, but is partially formed depending on the type of the metal, the grain sizes of the metal, and the quality of the interface of the metal. Accordingly, the control of the formation of the oxide layer is difficult and sometimes this oxide layer weakens the adhesiveness of the metal.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide an advantageous method of manufacturing a metal pattern of a semiconductor device having improved stability and adhesiveness by solving the above-mentioned problems during the manufacturing thereof. [0018]
  • To accomplish this object, a method of manufacturing a metal pattern of a semiconductor device is provided. First, a Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer. An exposed portion of the Ti layer pattern forms TiN as a main product by implementing a heat treatment process under an atmosphere of a compound including nitrogen. [0019]
  • There is also provided a method of manufacturing a metal pattern of a semiconductor device including the following steps. A Ti layer and a metal layer are formed on a semiconductor substrate or an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer. Then, a metal nitride layer is formed by depositing metal nitride on the wiring pattern. A metal nitride pattern is formed on side walls of the Ti layer pattern and the metal layer pattern by etching the metal nitride layer. [0020]
  • In the present invention, an exposed portion of a Ti layer, which has high reactivity and induces various problems while implementing other processes, is treated by a compound including nitrogen in advance to form a nitride layer to protect the Ti layer, and therefore, the various problems associated with the exposed Ti layer can be overcome.[0021]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above object and advantages of the present invention will become more apparent by describing preferred embodiments in detail with reference to the attached drawings in which: [0022]
  • FIGS. [0023] 1A-1D are cross-sectional views showing a conventional method of manufacturing a metal pattern of a semiconductor device;
  • FIG. 2 is a graph obtained by detecting the amount of gas generated from an insulating layer during a heat treatment for the formation of a subsequent layer; [0024]
  • FIGS. [0025] 3A-3E are schematic cross-sectional views showing a method of manufacturing a metal pattern according to a first embodiment of the present invention;
  • FIG. 4 is a cross-sectional view of a metal pattern manufactured by a second embodiment of the present invention; and [0026]
  • FIGS. [0027] 5A-5C are cross-sectional views showing a method of manufacturing a metal pattern according to a third embodiment of the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Hereinafter, the present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. [0028]
  • FIGS. [0029] 3A-3E are schematic cross-sectional views illustrating a method of manufacturing a metal pattern according to a first embodiment of the present invention. Referring to FIG. 3A, an insulating layer 210 of silicon oxide is formed on a semiconductor substrate 200 in which an impurity doped region 210 is formed. An opening 212 which exposes the impurity doped region 210 is formed on the insulating layer 210 by a photolithography process.
  • Referring to FIG. 3B, processes for forming a metal pattern are implemented. First, a [0030] Ti layer 221 is formed by depositing Ti by a sputtering method or a CVD method to a thickness of about 30-500 Å. The Ti layer functions to increase the adhesiveness between a subsequently deposited metal material and an underlying silicon oxide layer. On the Ti layer 221, a TiN (titanium nitride) layer 222 is formed as a barrier layer to a thickness of about 50-2000 Å. The TiN layer 222 is formed to prevent an impregnation of a subsequently deposited metal material to form a metal layer contacting the underlying active region. In general, a Ti/TiN layer is applied as a barrier layer between a silicon layer and a metal layer, while a Ti layer or TiN layer is applied between metal layers. Thereafter, a metal layer 223 is formed by depositing a metal such as tungsten, aluminum, or the like by a CVD method or a sputtering method to a thickness of about 300-8000 Å.
  • As for the metal material for forming the metal layer, tungsten, aluminum, aluminum-copper alloy, aluminum-copper-tungsten alloy, aluminum-scandium alloy, copper, cobalt, gold, silver, molybdenum, etc. can be used. Among them, tungsten is preferably applied because it has a low resistivity and a high melting point, and thus has good chemical vapor deposition characteristics and good step coverage. As for a tungsten source, tungsten hexafluoride (WF[0031] 6), having a boiling point is at room temperature, is preferable to tungsten hexachloride (WCl6), which has a high melting point and is in a solid state at room temperature.
  • Aluminum itself has a low melting point of 600° C., and a processing temperature for a mixture of aluminum and silicon is about 577° C. Therefore, processing at a high temperatures is difficult and voids will likely be generated in the resulting device. But, aluminum is cheaper than tungsten and has a low resistivity, and so a process control using aluminum is advantageous as well. Furthermore, aluminum has good reflow characteristics. Accordingly, aluminum is widely used as the metal material. [0032]
  • In the present invention, various materials can be used as the barrier layer including Ti/metal, such as Ti/TiN/W, Ti/W, Ti/TiN/Al, Ti/Al, etc. Copper has a high diffusion coefficient with respect to silicon oxide and silicon, and thus is not generally used as a barrier layer. For example, if copper is diffused into an insulating layer, the insulating layer becomes conductive thereby reducing the insulating characteristics. However, copper is cheap and has a low resistivity and so efforts continue for ways to successfully employ copper as a barrier layer. [0033]
  • On the [0034] metal layer 223, an SiN layer 224 is formed by depositing SiN. The SiN layer 224 is formed by depositing SiN in the presence of a mixed gas of SiH4 and N2, or a mixed gas of SiH4 and N 2 0, at about 400-600° C. using an LPCVD method. After that, a photoresist pattern 230 is formed by depositing, exposing and developing a photoresist layer using a typical photolithography process.
  • With reference to FIG. 3C, an anisotropic RIE (reactive ion etching) method is performed using the [0035] photoresist pattern 230 as an etching mask. Then, the photoresist layer 230 is removed to obtain desired patterns. The resulting patterns, starting with the uppermost layer, are an SiN pattern 224 a, a metal layer pattern 223 a, a TiN pattern 222 a and a Ti pattern 221 a. The SiN pattern 224 a formed on the metal layer pattern 223 a functions as an anti-reflective layer during the subsequently implemented photolithography process, and also functions to reinforce the shoulder of SiN spacers which will be formed at the sidewalls of a metal pattern.
  • Note that after forming the patterns, sidewalls of each pattern (i.e., [0036] Ti pattern 221 b, TiN pattern 222 b, metal layer pattern 223 b, and SiN pattern 224 b) are exposed. As shown in FIG. 3C, the Ti pattern 221 a, which has a good reactivity and a weak stress, is positioned at the lowest portion, and the metal layer pattern 223 a, which has a stronger stress than that of the Ti pattern 221 a, is positioned above the Ti pattern 221 a, with the TiN pattern 222 a being interposed between them.
  • With reference to FIG. 3D, a [0037] TiN layer 221 c is formed by heat treating in an atmosphere of a compound including nitrogen, thereby nitrifying an exposed sidewall portion of the Ti pattern 221 b. As for the compound including nitrogen, nitrogen gas, ammonia gas, a compound including nitrogen ion, or a compound including nitrogen atom, can be used. In other words, any compounds which can react with the exposed Ti and form TiN on the surface of the Ti pattern can be used. The heat treating is implemented by a RTA (rapid thermal annealing) process or a furnace annealing process.
  • The precise parameters of the heat treating process can be modified according to the equipment employed. For example, the heat treating may take a shorter time when RTA equipment is used, because the desired temperature can be reached in a shorter time. Conversely, heat treating takes longer in a furnace because it takes longer to reach the desired temperature. Accordingly, the heat treating condition should be controlled so as to form the [0038] TiN layer 221 c to a thickness of about 10-500 Å, and more preferably, 10-50 Å on the side walls of the Ti pattern 221 a.
  • After repeated experiments, the present inventors found that the heat treating is preferably implemented by an RTA process under an atmosphere range of about [0039]
  • 1×10[0040] −10-760 torr, at a temperature range of about 500-750° C., for about 3-40 seconds. More preferably, the RTA process is implemented under atmospheric pressure at about 650° C. for about 20 seconds.
  • After the heat treating, the exposed portion of the Ti layer forms TiN as a main product. Sometimes, however, the presence of oxygen is inevitable in the heat treating environment. TiON can thus be formed as a byproduct of the heat treating under an atmosphere including both nitrogen and oxygen. However, the TiON byproduct does not affect the operation and objectives of the present invention, and thus an additional process to avoid the formation of TiON is not required. However, if an excessive amount of oxygen is supplied, undesirable TiO[0041] 2 can be formed and so the amount of oxygen should be controlled.
  • If heat treating is conducted in a furnace, it is preferably performed in the furnace annealing equipment under an atmosphere range of bout 1×10[0042] −10-760 torr, at a temperature range of about 500-750° C., for about 40-60 minutes.
  • With reference to FIG. 3E, SiN is deposited on the thus obtained pattern at about 400-600° C. by the LPCVD method. Then, [0043] SiN spacers 225 are formed on side walls of the metal pattern by implementing an etch back process, and a metal pattern 220 having spacers on side walls thereof is formed. SiN spacers 225 prevent an oxidation of the metal and facilitates an SAC forming process. The formation of the SiN layer to form the SiN spacers 225 can be implemented after the heat treating in situ. The processes for nitrifying the exposed portion of the TiN layer and the subsequent formation of the SiN layer to form the SiN spacers are closely connected, thereby avoiding excessive delay in forming the nitride layer. According to this embodiment, since the process for forming the SiN spacers is implemented after the passivation process of the exposed Ti layer, the oxidation of the Ti layer during the subsequent heat treating can be overcome.
  • FIG. 4 is a cross-sectional view of a metal pattern manufactured by a second embodiment of the present invention. During the heat treating to form the TiN layer on the side walls of the Ti layer (as in FIG. 3D), the exposed side walls of the [0044] metal layer 223 b also can form a nitride compound 223 c. The thickness of the nitride compound 223 c depends on the reactivity with the metal according to the type of the metal be used. The metal nitride compound is preferable because it protects the metal layer and has no known negative effects.
  • As a third embodiment of the present invention, a metal nitride layer can be formed on the side walls of the metal pattern after the etching of the metal layer by using the photoresist pattern to prevent a generation of a defect due to an exposed Ti layer. The metal nitride layer is formed by depositing a metal nitride compound at a low temperature to a thickness of about 10-500 Å, and preferably to about 10-50 Å, and then implementing an etch back process until the surface of the substrate is exposed. [0045]
  • More specifically, FIGS. [0046] 5A-5C are cross-sectional views showing a method of manufacturing a metal pattern according to the third embodiment of the present invention.
  • With reference to FIG. 5A, an [0047] SiN pattern 224 a, a metal layer pattern 223 a, a TiN pattern 222 a, and a Ti pattern 221 a are formed in the same manner as described with regard to FIG. 3C. After forming these patterns, the side walls of each pattern are exposed as described previously.
  • With reference to FIG. 5B, TiN is deposited on the thus obtained etched pattern, by a sputtering method or a CVD method, to a thickness of about 10-500 Å, and preferably to a thickness of about 50 Å to form a [0048] thin TiN layer 226.
  • With reference to FIG. 5C, an etch back process is implemented until the substrate is exposed to form a [0049] TiN pattern 226 a which has a spacer shape, on the side walls of the etched pattern. Then, SiN is deposited on the thus obtained pattern and an etch back process is implemented to form an SiN spacer on side walls of the metal pattern. The SiN spacer functions to prevent an oxidation of the metal and reinforces an SAC process.
  • According to this embodiment, the metal nitride is additionally deposited and then etched, which increases the complexity of the process. However, this additional nitride layer improves the adhesiveness and stability of the metal pattern. Considering these effects, the more complex process can be readily applied. As for the metal nitride compounds, TiN, WN, and the like can be used. More preferably, the deposition of the metal nitride compounds is implemented under an atmosphere of a compound including nitrogen. [0050]
  • The preferred embodiments of the present invention were explained with reference to the formation of a bit line, in which the metal pattern is formed on a substrate or an insulating layer. However, the metal pattern also can be formed on an interlayer dielectric for an interconnection. In addition, the present invention can be applied to all types of devices including a metal pattern having a barrier layer, for example, a DRAM, SRAM, CMOS, Bi-MOS, MOSFET, etc. [0051]
  • While a nitride layer is formed on an exposed portion of a Ti layer, which has a high reactivity and functions as a protecting layer according to the method of the present invention, it should be understood that the present invention can be applied to other metal layers if the spirit of the present invention is utilized to solve the problems as described herein. [0052]
  • According to the present invention, the decrease in the stability or adhesiveness of a metal pattern, attributed to an indirect influence of a subsequent thermal process, can be overcome and a metal pattern of a semiconductor device having good stability and adhesion qualities can be manufactured. [0053]
  • In addition, since the formation of the nitride layer on side walls of the metal pattern is separately implemented, this process does not affect other processes. Accordingly, the Ti layer can be effectively protected without accompanying side-effects or adverse consequences. [0054]
  • Furthermore, since the heat treating under an atmosphere of a compound including nitrogen is implemented after the etching of the metal pattern and before the subsequent thermal process, the Ti layer which has a high reactivity can be protected. At the same time, the heat treating at a high temperature induces the generation of gas from surrounding layers, such as the insulating layer, to reduce an amount of gas generated during the subsequent thermal process. Therefore, even if ten or more wafers are subjected to the thermal process, a lifting of the metal layer rarely occurs. [0055]
  • While the present invention is described in detail referring to the attached embodiments, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the present invention. [0056]

Claims (18)

What is claimed is:
1. A method of manufacturing a metal pattern of a semiconductor device comprising:
sequentially forming a Ti layer and then a metal layer on a substrate;
forming a wiring pattern including a Ti layer pattern and a metal layer pattern by patterning and etching said Ti layer and said metal layer; and
heat treating a resulting structure, under an atmosphere of a compound including nitrogen, to react an exposed portion of said Ti layer pattern to form TiN as a main product on exposed sidewalls of said Ti layer pattern.
2. The method as claimed in claim 1, further comprising:
forming a photoresist pattern after said step of forming of said Ti layer and said metal layer; and
removing said photoresist pattern after said step of forming said wiring pattern.
3. The method as claimed in claim 1, wherein a thickness of said Ti layer is about 30-500 Å.
4. The method as claimed in claim 1, further comprising:
forming a TiN layer on said Ti layer prior to forming said metal layer, such that said metal layer is then formed on said TiN layer; an
patterning and etching said Ti layer, said TiN layer and said metal layer.
5. The method as claimed in claim 4, wherein a thickness of said TiN layer is about 50-2000 Å.
6. The method as claimed in claim 1, further comprising forming an SiN layer on said metal layer, and wherein said SiN layer is etched during said patterning and etching said Ti layer and said metal layer.
7. The method as claimed in claim 1, wherein said metal layer is formed from at least one metal selected from a group consisting of tungsten, aluminum, copper, cobalt, alloys thereof, and compounds including one of them.
8. The method as claimed in claim 1, wherein said compound including nitrogen is formed from one selected from a group consisting of nitrogen gas, ammonia gas, a compound including nitrogen ion, and a compound including nitrogen atom.
9. The method as claimed in claim 1, wherein said heat treating is implemented for a time period sufficient to form a TiN layer having a thickness of about 10-500 Å on the exposed sidewalls of said Ti layer pattern.
10. The method as claimed in claim 9, wherein said heat treating is performed in rapid thermal annealing (RTA) equipment under an atmosphere range of about 1×10−10-760 torr, at a temperature range of about 500-750° C., for about 3-40 seconds.
11. The method as claimed in claim 9, wherein said heat treating is implemented in furnace annealing equipment under an atmosphere range of about 1×1−10-760 torr, at a temperature range of about 500-750° C., for about 40-60 minutes.
12. The method as claimed in claim 1, further comprising depositing an insulating material to form spacers on exposed sidewalls of said Ti layer pattern and said metal layer pattern after said heat treating.
13. The method as claimed in claim 1, wherein TiON is formed as a byproduct on said exposed sidewalls of said Ti layer pattern by said heat treating.
14. The method as claimed in claim 1, wherein the substrate is one of a semiconductor substrate and an insulating layer.
15. The method as claimed in claim 4, further comprising forming an SiN layer on said metal layer, and wherein said SiN layer is etched during said patterning and etching said Ti layer, said TiN layer and said metal layer.
16. A method of manufacturing a metal pattern of a semiconductor device comprising:
forming a Ti layer and a metal layer on a substrate;
forming a wiring pattern including a Ti layer pattern and a metal layer pattern by patterning said Ti layer and said metal layer;
forming a metal nitride layer by depositing metal nitride on said wiring pattern; and
etching said metal nitride layer to form a metal nitride pattern on exposed side walls of said Ti layer pattern and said metal layer pattern.
17. The method of as claimed in claim 16, wherein said metal nitride is one of TiN and WN.
18. The method as claimed in claim 17, wherein the substrate is one of a semiconductor substrate and an insulating layer.
US09/794,616 2000-06-28 2001-02-28 Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern Expired - Fee Related US6451691B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR00-35892 2000-06-28
KR2000-35892 2000-06-28
KR1020000035892A KR100363013B1 (en) 2000-06-28 2000-06-28 Method For Manufacturing Metal Pattern For Semiconductor Device

Publications (2)

Publication Number Publication Date
US20020001945A1 true US20020001945A1 (en) 2002-01-03
US6451691B2 US6451691B2 (en) 2002-09-17

Family

ID=19674376

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/794,616 Expired - Fee Related US6451691B2 (en) 2000-06-28 2001-02-28 Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern

Country Status (3)

Country Link
US (1) US6451691B2 (en)
JP (1) JP4307544B2 (en)
KR (1) KR100363013B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080012143A1 (en) * 2006-07-12 2008-01-17 Jin Ha Park Semiconductor Device and Method of Fabricating the Same
US20110074030A1 (en) * 2009-09-30 2011-03-31 Macronix International Co., Ltd. METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER
US20120175777A1 (en) * 2011-01-12 2012-07-12 Freescale Semiconductor, Inc. Device having conductive substrate via with catch-pad etch-stop
CN110021574A (en) * 2019-04-19 2019-07-16 上海华虹宏力半导体制造有限公司 Semiconductor device structure and its manufacturing method

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617689B1 (en) * 2000-08-31 2003-09-09 Micron Technology, Inc. Metal line and method of suppressing void formation therein
US6511911B1 (en) * 2001-04-03 2003-01-28 Advanced Micro Devices, Inc. Metal gate stack with etch stop layer
US6815337B1 (en) * 2004-02-17 2004-11-09 Episil Technologies, Inc. Method to improve borderless metal line process window for sub-micron designs
KR100536808B1 (en) * 2004-06-09 2005-12-14 동부아남반도체 주식회사 Semiconductor device and manufacturing method thereof
KR20150092581A (en) * 2014-02-05 2015-08-13 삼성전자주식회사 Wiring structure and method of forming the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6232610A (en) * 1985-08-05 1987-02-12 Fujitsu Ltd Manufacture of semiconductor device
JPS62283625A (en) * 1986-06-02 1987-12-09 Fujitsu Ltd Manufacture of electrode of semiconductor device
KR0176715B1 (en) 1990-07-30 1999-04-15 오가 노리오 Dry etching method
JPH05343363A (en) * 1992-06-08 1993-12-24 Matsushita Electric Ind Co Ltd Dry etching method
US5314576A (en) 1992-06-09 1994-05-24 Sony Corporation Dry etching method using (SN)x protective layer
US5514908A (en) * 1994-04-29 1996-05-07 Sgs-Thomson Microelectronics, Inc. Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
JP2768304B2 (en) * 1995-04-13 1998-06-25 日本電気株式会社 Method for manufacturing semiconductor device
US5705428A (en) 1995-08-03 1998-01-06 Chartered Semiconductor Manufacturing Pte, Ltd. Method for preventing titanium lifting during and after metal etching
KR100232160B1 (en) * 1995-09-25 1999-12-01 김영환 Capacitor structure of semiconductor and manufacturing method threreof
US5754390A (en) * 1996-01-23 1998-05-19 Micron Technology, Inc. Integrated capacitor bottom electrode for use with conformal dielectric
KR100276389B1 (en) * 1998-07-03 2000-12-15 윤종용 A capacitor and a method of fabrication the same
US6187674B1 (en) * 1998-12-08 2001-02-13 United Microelectronics Corp. Manufacturing method capable of preventing corrosion and contamination of MOS gate
US6277745B1 (en) * 1998-12-28 2001-08-21 Taiwan Semiconductor Manufacturing Company Passivation method of post copper dry etching

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080012143A1 (en) * 2006-07-12 2008-01-17 Jin Ha Park Semiconductor Device and Method of Fabricating the Same
US20110074030A1 (en) * 2009-09-30 2011-03-31 Macronix International Co., Ltd. METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER
US8076778B2 (en) * 2009-09-30 2011-12-13 Macronix International Co., Ltd. Method for preventing Al-Cu bottom damage using TiN liner
US20120175777A1 (en) * 2011-01-12 2012-07-12 Freescale Semiconductor, Inc. Device having conductive substrate via with catch-pad etch-stop
US8410580B2 (en) * 2011-01-12 2013-04-02 Freescale Semiconductor Inc. Device having conductive substrate via with catch-pad etch-stop
CN110021574A (en) * 2019-04-19 2019-07-16 上海华虹宏力半导体制造有限公司 Semiconductor device structure and its manufacturing method

Also Published As

Publication number Publication date
JP2002026021A (en) 2002-01-25
US6451691B2 (en) 2002-09-17
KR20020001314A (en) 2002-01-09
KR100363013B1 (en) 2002-11-29
JP4307544B2 (en) 2009-08-05

Similar Documents

Publication Publication Date Title
US6020254A (en) Method of fabricating semiconductor devices with contact holes
US6025265A (en) Method of forming a landing pad structure in an integrated circuit
KR100530401B1 (en) Semiconductor device having a low-resistance gate electrode
US20050130380A1 (en) Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level
US6433433B1 (en) Semiconductor device with misaligned via hole
US20040238876A1 (en) Semiconductor structure having low resistance and method of manufacturing same
US6156644A (en) Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby
KR100281887B1 (en) Manufacturing Method of Semiconductor Device
KR100755121B1 (en) Method for forming electrode structure and method for fabricating semiconductor device
US6451691B2 (en) Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern
US6171981B1 (en) Electrode passivation layer of semiconductor device and method for forming the same
JPH1187695A (en) Fabrication of semiconductor device
US20040053491A1 (en) Method of forming a contact in a semiconductor device
US6403458B2 (en) Method for fabricating local interconnect structure for integrated circuit devices, source structures
US7344974B2 (en) Metallization method of semiconductor device
US5502004A (en) Method for manufacturing a semiconductor device with heat treated diffusion layers
EP0514103A1 (en) Barrier metal process for sub-micron contacts
US6657301B2 (en) Contact structure, method of forming the same, semiconductor device, and method of manufacturing the same
US8076235B2 (en) Semiconductor device and fabrication method thereof
US7442639B2 (en) Method of forming plug of semiconductor device
US7524749B2 (en) Metallization method of semiconductor device
US20040058519A1 (en) Method for forming bit line contact
JP3360835B2 (en) Wiring formation method
US20010019159A1 (en) Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same
JP3265593B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SONG, WON-SANG;PARK, IN-SUN;KOO, KYUNG-BUM;AND OTHERS;REEL/FRAME:011579/0354

Effective date: 20010217

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140917