CN110021574A - Semiconductor device structure and its manufacturing method - Google Patents
Semiconductor device structure and its manufacturing method Download PDFInfo
- Publication number
- CN110021574A CN110021574A CN201910318925.3A CN201910318925A CN110021574A CN 110021574 A CN110021574 A CN 110021574A CN 201910318925 A CN201910318925 A CN 201910318925A CN 110021574 A CN110021574 A CN 110021574A
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- Prior art keywords
- layer
- side wall
- device structure
- semiconductor device
- medium layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a kind of semiconductor device structure and its manufacturing method, the semiconductor device structure includes: semiconductor base；Metal wire on semiconductor base；Side wall at metal line sidewalls；And successively cover semiconductor base, side wall and first medium layer and second dielectric layer on metal wire top.The present invention may be implemented in the case where not increasing the height of the passivation layer on metal wire top layer; increase the thickness for being located at the passivation layer of metal layer side-walls; to improve passivation layer to the support protection degree of metal layer at top; it prevents top metal wires from collapsing and/or lacking in subsequent technique, and improves the yields of semiconductor chip.
Description
Technical field
The present invention relates to semiconductor chip manufacturing fields, more particularly, to a kind of semiconductor device structure and its manufacturer
Method.
Background technique
In semiconductor chip manufacturing process, the passivation and metallization of device surface are must can not in semiconductor fabrication process
Few part.Device metallization is the process that applied chemistry or physical treatment method deposit conductive metal film on device, is
The resistance of reduction top metal on the device (TOP metal) line, it usually needs increase the thickness of top metal wires, institute
State thickness >=4um of top metal wires.
It is passivated the various charges that can be reduced in device oxide layer to the surface of semiconductor chip, enhances semiconductor core
The electricity of the blocking capability that piece stains ion, the interconnection and semiconductor chip surface of protecting semiconductor chip internal components is special
Property, prevent semiconductor chip mechanically damaged and chemical damage.
Device surface is passivated i.e. in the blunt of the one covering top metal wires of semiconductor chip surface deposition
Change layer (passivation layer), in the subsequent process, needs to carry out photoetching to the passivation layer, connecting lead wire will be needed
Place passivation layer it is etched open, form lead, but existing passivation layer is too thin, cannot provide enough branch to top metal wires
Support so that top metal wires are insecure, it is subsequent semiconductor chip is thinned during, atop part metal wire can fall
It collapses and/or lacks, to reduce device yield.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the above deficiency, providing one kind can be improved passivation layer to top
The support protection degree of metal layer, prevents top metal wires from collapsing in subsequent technique, the passivation layer of loss.
To solve the above-mentioned problems, the invention is realized by the following technical scheme:
A kind of semiconductor device structure, comprising: semiconductor base；Metal wire on the semiconductor base；It is located at
Side wall at the metal line sidewalls；And it successively covers at the top of the semiconductor base, the side wall and the metal wire
First medium layer and second dielectric layer.
Further, the side wall is the single layer structure of one of silica, silicon oxynitride and silicon nitride composition, or
The laminated construction of any combination thereof composition.
Further, the material of the first medium layer is silica.
Further, the material of the second dielectric layer is silicon nitride.
Further, the metal wire is located on the front surface of the semiconductor base, and the material of the metal wire is aluminium
Or aluminium copper, the thickness range of the metal wire are 4um~6um.
Further, the first medium layer thickness range is
Further, the second dielectric layer thickness range is
On the other hand, a kind of manufacturing method of semiconductor device structure, comprising: semiconductor substrate is provided, it is described partly to lead
It is formed with metal wire in body substrate,
The side wall medium layer for covering the metal wire is formed on the semiconductor base,
The side wall medium layer is etched, forms side wall in the metal line sidewalls；
The first medium layer for covering the side wall and metal wire is formed on the semiconductor base；And
Second dielectric layer is formed on the first medium layer.
Further, the material of the side wall and first medium layer is respectively silica, the material of the second dielectric layer
Material is silicon nitride.
Further, the side wall medium layer and first medium layer are formed in such a way that TEOS is reacted with oxygen.
The present invention has following technical effect that
Semiconductor device structure provided by the invention, by including: to be formed on semiconductor base and be located at partly to lead
The side wall at metal line sidewalls in body substrate, and it is sequentially formed in the semiconductor base, the side wall and the metal
First medium layer and second dielectric layer at the top of line, realize the feelings in the height for not increasing the passivation layer on metal wire top layer
Under condition, the thickness of the passivation layer positioned at metal layer side-walls is increased, improve passivation layer to the support protection degree of metal layer at top,
It prevents top metal wires from collapsing and/or lacking in subsequent technique, improves the yields of semiconductor chip.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the semiconductor device structure of the prior art；
Fig. 2~Fig. 5 is the device profile structure in the manufacturing process of semiconductor device structure provided in an embodiment of the present invention
Schematic diagram.
Specific embodiment
It holds as stated in the background art, existing top metal wires are easy to appear in subsequent semiconductor chip reduction process
The problem of collapsing and/or losing, it has been investigated that, this is because the thickness limitation of the passivation layer due to deposition, causes it to top
Caused by the support protective capability of portion's metal layer is insufficient, specifically, as shown in Figure 1, passivation layer in the prior art includes successively
Be formed on semiconductor base 10 and be covered on the metal wire among semiconductor base 10 (Top Metal) 20 two
The thickness range of silicon oxide layer 30 and silicon nitride layer 40, the silicon dioxide layer 30 and silicon nitride layer 40 is respectivelyThe thickness of simple increase passivation layer is unworkable to solve the above problems, this is because due to increasing
Passivation layer thickness is added, will increase etch period, due to the limitation of traditional photoresist layer thickness and the load effect of figure, has made
Photoresist layer thickness on some isolated top metal wires surfaces is than relatively thin, therefore the case where increasing etch period
Under, the photoresist in isolated top metal wires can be made to be etched completely away, and then etch away the passivation layer in the region, destruction is partly led
Body chip.Thickness without increasing passivation layer then will lead to top metal wires missing, this is because due to the thickness of top metal wires
Degree is thicker, and the surface of top metal wires and the difference in height of semiconductor chip surface are bigger, need after forming lead
This device surface sticks blue film and is protected, and to the device back side carry out reduction processing, to chip carry out reduction processing it
Afterwards, it needs to tear blue film, since passivation layer is too thin, enough supports cannot be provided to top metal wires, so that top metal wires
It is insecure, during tearing blue film, atop part metal wire can be taken away, so that top metal wires lack, reduce device
Yields.
Based on above-mentioned discovery, the present invention is initially formed a sidewall structure by the side-walls in top metal wires, later, in institute
It states and forms first medium layer and second dielectric layer at the top of semiconductor base, the side wall and the top metal wires, it is described
Side wall, first medium layer and second dielectric layer form passivation layer, and the side wall is used to increase the support to the top metal wires
Degree is realized and is increased in the case where not increasing the thickness of the passivation layer on the top surface positioned at top metal wires positioned at top-gold
Belong to the thickness of line side wall to solve the above problems.
For clarity, not describing whole features of a practical embodiment.In the following description, it is not described in detail well known function
Energy and structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that in any one embodiment of reality
Exploitation in, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related quotient
The limitation of industry changes into another embodiment by an embodiment.Additionally, it should think that this development may be multiple
It is miscellaneous and time-consuming, but to those skilled in the art it is only routine work.
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In Fig. 2~Fig. 5, the device layer of semiconductor chip substrate is omitted, only depicts top metal wires in a schematic way
200 and passivation layer structure.It will be understood by those skilled in the art that the matrix 100 can be semiconductor chip.For example, described half
It can be to be located at the positive table of the semiconductor base with pre-production cmos device, the top metal wires 200 in conductor substrate 100
The material of metal wire on face, the metal wire is aluminium or aluminium copper, and thickness range is, for example, 4um~6um.
As shown in figure 5, semiconductor device structure described in the present embodiment, comprising: be formed on semiconductor base 100,
And it is located at the side wall 300 ' of 200 side-walls of top metal wires on semiconductor base 100, and is sequentially formed in and described partly leads
First medium layer 310 and second dielectric layer on 200 top of body substrate 100, the side wall 300 ' and the top metal wires
400。
In the present embodiment, the side wall 300 ' is in silica, silicon oxynitride (oxidized silicon nitride) and silicon nitride
A kind of single layer structure of composition, alternatively, the side wall 300 ' can also be several in silica, silicon oxynitride and silicon nitride
The laminated construction of composition.The thickness range of the side wall 300 ' is between 1 μm~2 μm.
The material of the first medium layer 310 is silica.The second medium layer by layer 400 material be silicon nitride.
The material of the top metal wires 200 is aluminium or aluminium copper.310 thickness range of first medium layer be400 thickness range of second dielectric layer is
It follows that passivation layer of the invention, which realizes, is not increasing the passivation on the top surface positioned at top metal wires
The thickness positioned at top metal wires side wall is increased in the case where the thickness of layer, improves support of the passivation layer to metal layer at top
Protection degree prevents top metal wires from collapsing and/or lacking in subsequent technique, improves the mesh of the yields of semiconductor chip
's.
The present embodiment also discloses a kind of manufacturing method of passivation layer, and the present embodiment is discussed in detail below in conjunction with Fig. 2~Fig. 5
Passivation layer manufacturing method.
Firstly, being formed with top metal on the semiconductor base 100 as shown in Fig. 2, provide semiconductor substrate 100
Line 200.The top metal wires 200 have step difference with the semiconductor base 100, and the altitude range of the step is described
The thickness range of the thickness range of top metal wires 200, the top metal wires 200 is, for example, 4um~6um.
Then, as shown in Fig. 2, forming side wall Jie for covering the top metal wires 200 on the semiconductor base 100
Matter layer 300.
Then, as shown in figure 3, etching the side wall medium layer 300, side wall is formed in 200 side wall of top metal wires
300’。
Specifically, global dry etching is carried out to side wall medium layer 300,
Since the dry etching has anisotropy, i.e., substantially there was only vertical etch, and almost without lateral undercutting,
And then side wall 300 ' can be etched.
Then, the side wall 300 ' and top metal wires are covered as shown in figure 4, being formed on the semiconductor base 100
200 first medium layer 310.
Then, as shown in figure 5, forming second dielectric layer 400 on the first medium layer 310.
In the present embodiment, the material of the side wall medium layer 300 and first medium layer 310 is respectively silica, institute
The material for stating second dielectric layer 400 is silicon nitride, the passivation layer using silicon nitride as final passivation protection layer, this be because
It can inhibit the diffusion of impurity and moisture well for it.Preferably, using PECVD (plasma reinforced chemical vapour deposition) mode
The second dielectric layer 400 is formed, the silicon nitride layer with good step covering power and high homogeneity can be obtained.
In the present embodiment, the side wall medium layer 300 and first medium layer 310 use TEOS (ethyl orthosilicate) and oxygen
The mode of solid/liquid/gas reactions is formed.Specifically, PECVD (plasma reinforced chemical vapour deposition) can be used, silicon dioxide layer is generated
Technological temperature be 400 degrees Celsius gases used for ethyl orthosilicate and oxygen.
In conclusion passivation layer of the invention, which realizes, is not increasing the passivation on the top surface positioned at top metal wires
The thickness positioned at top metal wires side wall is increased in the case where the thickness of layer, improves support of the passivation layer to metal layer at top
Protection degree prevents top metal wires from collapsing and/or lacking in subsequent technique, improves the mesh of the yields of semiconductor chip
's.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. a kind of semiconductor device structure characterized by comprising
Semiconductor base；
Metal wire on the semiconductor base；
Side wall at the metal line sidewalls；And
Successively cover the first medium layer and second medium at the top of the semiconductor base, the side wall and the metal wire
Layer.
2. semiconductor device structure as described in claim 1, which is characterized in that the side wall is silica, silicon oxynitride
With the single layer structure of one of silicon nitride composition, or any combination thereof composition laminated construction.
3. semiconductor device structure as described in claim 1, which is characterized in that the material of the first medium layer is titanium dioxide
Silicon.
4. semiconductor device structure as described in claim 1, which is characterized in that the material of the second dielectric layer is nitridation
Silicon.
5. semiconductor device structure as described in claim 1, which is characterized in that the material of the metal wire is aluminium or aluminum bronze
Alloy, the thickness range of the metal wire are 4um~6um.
6. semiconductor device structure as claimed in claim 1 or 3, which is characterized in that the first medium layer thickness range be
7. semiconductor device structure as described in claim 1 or 4, which is characterized in that the second dielectric layer thickness range is
8. a kind of manufacturing method of semiconductor device structure characterized by comprising
Semiconductor substrate is provided, is formed with metal wire on the semiconductor base,
The side wall medium layer for covering the metal wire is formed on the semiconductor base,
The side wall medium layer is etched, forms side wall in the metal line sidewalls；
The first medium layer for covering the side wall and metal wire is formed on the semiconductor base；And
Second dielectric layer is formed on the first medium layer.
9. the manufacturing method of semiconductor device structure as claimed in claim 8, which is characterized in that the side wall medium layer dioxy
One of SiClx, silicon oxynitride and silicon nitride composition single layer structure, or any combination thereof composition laminated construction；The side
The thickness range of wall dielectric layer is 1 μm~2 μm；
The material of the first medium layer is silica, and thickness range is
The material of the second dielectric layer is silicon nitride, and thickness range is
10. the manufacturing method of semiconductor device structure as claimed in claim 9, which is characterized in that the side wall medium layer and
First medium layer is formed in such a way that TEOS is reacted with oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910318925.3A CN110021574A (en) | 2019-04-19 | 2019-04-19 | Semiconductor device structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910318925.3A CN110021574A (en) | 2019-04-19 | 2019-04-19 | Semiconductor device structure and its manufacturing method |
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| Publication Number | Publication Date |
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| CN110021574A true CN110021574A (en) | 2019-07-16 |
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| CN201910318925.3A Pending CN110021574A (en) | 2019-04-19 | 2019-04-19 | Semiconductor device structure and its manufacturing method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001945A1 (en) * | 2000-06-28 | 2002-01-03 | Song Won-Sang | Method of manufacturing metal pattern of semiconductor device |
| CN101438388A (en) * | 2006-05-04 | 2009-05-20 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| CN109494214A (en) * | 2017-09-11 | 2019-03-19 | 联华电子股份有限公司 | The connection structure of semiconductor device with and preparation method thereof |
-
2019
- 2019-04-19 CN CN201910318925.3A patent/CN110021574A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001945A1 (en) * | 2000-06-28 | 2002-01-03 | Song Won-Sang | Method of manufacturing metal pattern of semiconductor device |
| CN101438388A (en) * | 2006-05-04 | 2009-05-20 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| CN109494214A (en) * | 2017-09-11 | 2019-03-19 | 联华电子股份有限公司 | The connection structure of semiconductor device with and preparation method thereof |
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Application publication date: 20190716 |
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