US20010045845A1 - Interface circuit and signal transmission method - Google Patents
Interface circuit and signal transmission method Download PDFInfo
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- US20010045845A1 US20010045845A1 US09/734,686 US73468600A US2001045845A1 US 20010045845 A1 US20010045845 A1 US 20010045845A1 US 73468600 A US73468600 A US 73468600A US 2001045845 A1 US2001045845 A1 US 2001045845A1
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- constant current
- electronic device
- logic signal
- lsi
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
Definitions
- the present invention in general relates to an interface circuit used for transmission of logic signals among a plurality of electronic devices. More particularly, this invention relates to an interface circuit and a signal transmission method suitable for use in a plurality of electronic devices having different power supply voltages.
- FIG. 6 is a block diagram showing the configuration of a conventional magnetic disk apparatus.
- a HDC (hard disk controller) 1 is connected to a host 9 via a SCSI (Small Computer System Interface) bus which is not illustrated.
- SCSI Small Computer System Interface
- various commands such as a read command and write command
- write data to be written onto a magnetic disk M described later and read data read out from the magnetic disk M are transmitted and received.
- the HDC 1 controls components of the magnetic disk apparatus.
- a MPU (Micro Processing Unit) 2 controls components of the apparatus.
- a read/write control and power save control are the major example of such control.
- a read channel 3 includes a modulation circuit for writing write data onto the magnetic disk M, a parallel/serial conversion circuit for converting parallel write data to serial data, and a demodulation circuit for reading out read data from the magnetic disk M.
- the read channel 3 includes a serial/parallel conversion circuit for converting serial read data to parallel data, and a synthesizer circuit for generating timing signals to be used as timing of components of the apparatus by conducting frequency multiplication on the frequency of an oscillation circuit using a crystal oscillator.
- a head IC 4 drives a magnetic head 5 .
- the head IC 4 delivers read data fed from the magnetic head 5 to the read channel 3 , and delivers write data fed from the read channel 3 to the magnetic head 5 .
- the magnetic head 5 is disposed in close vicinity to the magnetic disk M.
- the magnetic head 5 has a function of magnetically writing write data onto the magnetic disk M and a function of magnetically reading out read out from the magnetic disk M.
- a SPM (spindle motor) 6 drives and rotates the magnetic disk M.
- a VCM (voice coil motor) 7 moves the magnetic head 5 in the radial direction of the magnetic disk M.
- a servo controller 8 effects servo control by controlling the SPM 6 and the VCM 7 .
- the HDC 1 , MPU 2 , read channel 3 , head IC 4 , and servo controller 8 are electronic devices such as LSIs and ICs, and driven with different power supply voltages.
- FIG. 7 an LSI A and an LSI B correspond to two among the HDC 1 , the MPU 2 , the read channel 3 and so on shown in FIG. 6.
- a logic signal S 1 of the LSI A also has a level of 5.0 V.
- a logic signal S 2 of the LSI B also has a level of 2.5 V. That is, the logic signal S 1 of the LSI A has a level of 5.0 V, whereas the logic signal S 2 of the LSI B has a level of 2.5 V. If the logic signal S 1 of 5.0 V is inputted to the LSI B while leaving this state intact, therefore, the logic signal S 1 exceeds the breakdown voltage of the LSI B and there is a possibility of the LSI B being destroyed.
- a level converter C for conducting level adjustment of the logic signal between the LSI A and the LSI B.
- the level converter C converts the logic signal S 1 of 5.0 V to the logic signal S 2 of 2.5 V conforming to the LSI B.
- the LSI A and the LSI B normally function.
- the level converter C for conducting the level adjustment of the logic signals must be used in the conventional technique when a plurality of electronic devices driven with different voltages are to be utilized. Therefore, it is necessary to select an electronic device which conforms to the level conversion characteristic of the level converter C. Even if an electronic device is high in performance as a simple substance, therefore, the electronic device cannot be used in the electronic apparatus so long as it does not conform to the level conversion characteristic, in the case of the conventional technique. Therefore, usable electronic devices are restricted naturally. This results in a problem that the circuit design is severely restricted.
- a constant current control unit outputs a constant current to the second electronic device
- a logic signal generation unit generates a logic signal having a level conforming to the second electronic device on the basis of the constant current.
- logic signal transmission using the constant current is conducted between the first electronic device and the second electronic device, and a logic signal having a level conforming to the second electronic device is generated on the basis of the constant current, in the second electronic device. Accordingly, even if a plurality of electronic devices driven with different power supply voltages are present, the level of the logic signal can be easily conformed. As a result, it becomes possible to increase the degree of freedom of the circuit design and shorten the circuit design time.
- FIG. 1 is a block diagram showing a schematic configuration of a first embodiment according to the present invention
- FIG. 2 is a block diagram showing a configuration of the first embodiment according to the present invention.
- FIG. 3 is a block diagram showing a configuration of a second embodiment according to the present invention.
- FIG. 4 is a block diagram showing a configuration of a third embodiment according to the present invention.
- FIG. 5 is a block diagram showing a configuration of a fourth embodiment according to the present invention.
- FIG. 6 is a block diagram showing a configuration of a conventional magnetic disk apparatus.
- FIG. 7 is a block diagram showing a configuration of a conventional interface circuit.
- FIG. 1 is a block diagram showing a schematic configuration according to a first embodiment of the present invention.
- An LSI 10 and an LSI 20 shown in FIG. 1 are mounted on one electronic apparatus which is not illustrated, and driven with different power supply voltages, respectively.
- the LSI 10 is also different from the LSI 20 in logic signal level.
- the logic signal level of the LSI 10 is also 5.0 V.
- an interface circuit for sending out a constant current I 4 to the LSI 20 is incorporated. When the constant current I 4 flows, a logic signal S 0 is at a high level. When the constant current I 4 does not flow, the logic signal S 0 is at a low level.
- the logic signal level of the LSI 20 is also 2.5 V.
- an interface circuit for generating a logic signal of a level (2.5 V) conforming to the LSI 20 from a constant current I 4 is incorporated. In this way, the logic signal level of the LSI 10 is 5.0 V, whereas the logic signal level of the LSI B is 2.5 V.
- the LSI 10 includes an interface circuit 15 and an internal circuit 16 .
- a transistor 11 is a PNP transistor for effecting on/off control on the output of the constant current I 4 .
- This transistor 11 is supplied with the first power supply voltage V cc1 at its emitter.
- a resistor R 1 is interposed between a collector of the transistor 11 and ground GND.
- the resistor R 1 has a very large resistance value r 1 in order that a constant current I 2 ⁇ the constant current I 4 .
- a diode 12 is connected between the emitter and base of the transistor 11 in parallel.
- the diode 12 and the transistor 11 form a current mirror circuit.
- a constant current I 1 flowing through the diode 12 is equal to the constant current I 2 flowing through the emitter of the transistor 11 .
- a constant current source 13 is interposed between a cathode of the diode 12 and the internal circuit 16 . The constant current source 13 functions to let the constant current I 1 flow.
- the internal circuit 16 is a circuit for implementing the function of the LSI 10 .
- the internal circuit 16 executes the operation based on a logic signal S 10 .
- the logic signal S 10 has a level of 5.0 V.
- a switch 14 is connected in parallel to the diode 12 , and controlled to turn on/off by a control circuit which is not illustrated.
- a connection line 30 is connected between the LSI 10 and the LSI 20 .
- the connection line 30 serves as a transmission path of the constant current I 4 (logic signal S 0 ).
- the LSI 20 includes an interface circuit 24 and an internal circuit 25 .
- a transistor 21 is an NPN transistor which is controlled to turn on/off by the constant current I 4 .
- a resistor R 2 is interposed between an emitter of the transistor 21 and the ground GND.
- a diode 22 and a diode 23 form a series circuit.
- the series circuit is interposed between a base of the transistor 21 and the ground GND.
- the internal circuit 25 is a circuit for implementing the function of the LSI 20 .
- the internal circuit 25 executes the operation on the basis of a logic signal S 20 .
- the logic signal S 20 has a level of 2.5 V ( ⁇ the level of the logic signal S 10 ).
- a constant current I 1 determined by the constant current source 13 flows through the diode 12 , and in addition, the constant current I 2 having the same value as the constant current I 1 flows through the emitter of the transistor 11 included in the current mirror circuit.
- the constant current I 2 is divided into a constant current I 3 flowing through the collector of the transistor 11 and the constant current I 4 flowing through the connection line 30 . Since the resistance value r 1 of the resistor R 1 is very large, the current I 3 ⁇ 0. Therefore, it follows that the constant current I 2 ⁇ constant current I 4 .
- a drop voltage V D ( ⁇ 1.4 V) occurs across the series circuit formed of the diodes 22 and 23 , and a base-emitter voltage V BE ( ⁇ 0.7 V) occurs between the base and the emitter of the transistor 21 .
- the level of the logic signal S 20 can be conformed to the LSI 20 without using the conventional level converter C (see FIG. 7), by setting the resistance value r 2 of the resistor R 2 and the resistance value r 3 of the resistor R 3 to suitable values.
- the resistors R 2 and R 3 may be variable resistors. In this case, logic signals of arbitrary levels can be generated. As a result, it becomes easy to mount any electronic devices driven with different power supply voltages on an electronic apparatus.
- logic signal transmission is conducted between the LSI 10 and the LSI 20 by using the constant current I 4 , and the logic signal S 20 having the level conforming to the LSI 20 is generated in the LSI 20 on the basis of the constant current I 4 .
- the degree of circuit design can be increased and the circuit design time can be shortened.
- FIG. 3 is a block diagram showing a configuration of a second embodiment according to the present invention.
- components corresponding to those of FIG. 2 are denoted by same legends.
- an LSI 40 is provided instead of the LSI 20 shown in FIG. 2.
- the LSI 40 includes an interface circuit 44 and an internal circuit 45 .
- a constant current source 41 functions to let a constant current I 6 flow.
- the constant current source 41 is connected to a second power supply voltage V cc2 .
- a transistor 42 and a transistor 43 form an ECL (Emitter Coupled Logic) circuit.
- the transistor 42 is a PNP transistor interposed between the constant current source 41 and the ground GND.
- the transistor 42 is connected to a connection line 30 at its base, connected to the constant current source 41 at its emitter, and connected to the ground GND at its collector.
- a resistor R 4 is interposed between the base of the transistor 42 and the ground GND.
- the transistor 43 is a PNP transistor disposed in parallel to the transistor 42 and interposed between the constant current source 41 and the ground GND. In other words, the transistor 43 is connected at its emitter to the constant current source 41 and the emitter of the transistor 42 , and connected at its collector to the ground GND via a resistor R 5 .
- the transistor 43 is supplied with a reference voltage V ref at its base.
- the reference voltage V ref is set to a value obtained by subtracting 0.5 (V) from a drop voltage V R4 incurred across the resistor R 4 .
- the internal circuit 45 is a circuit for implementing the function of the LSI 40 .
- the internal circuit 45 operates on the basis of a logic signal S 40 .
- the logic signal S 40 has a level of 2.5 V ( ⁇ level of the logic signal S 10 ).
- the constant current I 4 flows into the interface circuit 44 , then a drop voltage V R4 occurs across a resistor R 4 . Since the reference voltage V ref is applied to the base of the transistor 43 at this time, the constant current I 6 flows through the resistor R 5 via the transistor 43 as a result of the function of the ECL circuit. Accordingly, a high level logic signal S 40 represented as the resistance value r 5 of the resistor R 5 ⁇ constant current I 5 is inputted to the internal circuit 45 . In other words, in the second embodiment, the level of the logic signal S 40 can be conformed to the LSI 40 without using the conventional level converter C (see FIG. 7) , by setting the resistance value r 5 of the resistor R 5 to a suitable value.
- the resistor R 5 may be a variable resistor.
- logic signal transmission is conducted between the LSI 10 and the LSI 40 by using the constant current I 4 , and the logic signal S 40 having the level conforming to the LSI 20 is generated in the LSI 40 on the basis of the constant current I 4 .
- the degree of circuit design can be increased and the circuit design time can be shortened.
- FIG. 4 is a block diagram showing a configuration of a third embodiment according to the present invention.
- components corresponding to those of FIG. 2 are denoted by same legends.
- an LSI 50 is provided instead of the LSI 10 shown in FIG. 2.
- the LSI 50 includes an interface circuit 56 and an internal circuit 16 .
- a transistor 52 In the interface circuit 56 , a transistor 52 , a constant current source 53 , a diode 54 , and a switch 55 are provided instead of the resistor R 1 shown in FIG. 2.
- the transistor 52 is an NPN transistor for shortening the attenuation time of the constant current I 4 .
- the transistor 52 is connected at its collector to the collector of the transistor 11 , and connected at its emitter to the ground GND.
- the constant current source 53 functions to let a constant current I 8 flow.
- the diode 54 is interposed between the constant current source 53 and the ground GND.
- the diode 54 and the transistor 52 form a current mirror circuit.
- the switch 55 is connected in parallel to the diode 54 and controlled to turn on/off by a control circuit which is not illustrated.
- the switch 14 and the switch 55 are turned on/off by inverse logics.
- the switch 14 is turned off and the switch 55 is turned on in the above described configuration, then the constant current I 1 determined by the constant current source 13 flows through the diode 12 , and in addition, a constant current I 2 having the same value as the constant current I 1 flows through the emitter of the transistor 11 included in the current mirror circuit. Through the connection line 30 , therefore, the constant current I 4 ( ⁇ constant current I 2 ) flows. On the other hand, since the switch 55 is in the on-state, the constant current I 8 flows through the switch 55 , but it does not flow through the diode 54 .
- the transistor 52 , the constant current source 53 , and the switch 55 are provided, and the sink constant current I 7 is let flow in the direction opposite to that of the constant current I 4 . Therefore, the attenuation time of the constant current I 4 can be shortened. As a result, the response characteristic can be improved.
- FIG. 5 is a block diagram showing a configuration of the fourth embodiment.
- components corresponding to those of FIG. 4 are denoted by same legends.
- the LSI 40 (see FIG. 3) is provided instead of the LSI 20 shown in FIG. 4. Operation of flow of the sink constant current I 7 shown in FIG. 5 and effects of the sink constant current I 7 are similar to those of the third embodiment, and consequently description of them will be omitted.
- logic signal transmission using the constant current is conducted between the first electronic device and the second electronic device, and a logic signal having a level conforming to the second electronic device is generated on the basis of the constant current, in the second electronic device, as heretofore described.
- the level of the logic signal can be conformed simply. This brings about an effect that it becomes possible to increase the degree of freedom of the circuit design and shorten the circuit design time.
- a logic signal conforming to the second electronic device is generated by an extremely simple element, i.e., a resistor. This brings about an effect that the circuit design time can be further shortened.
- the resistor is a variable resistor. Accordingly, a logic signal having an arbitrary level can be generated. This brings about an effect that it becomes easy to mount any electronic devices driven with different power supply voltages on an electronic apparatus.
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Abstract
Description
- The present invention in general relates to an interface circuit used for transmission of logic signals among a plurality of electronic devices. More particularly, this invention relates to an interface circuit and a signal transmission method suitable for use in a plurality of electronic devices having different power supply voltages.
- As the technique advances, a plurality of electronic devices such as LSIs (Large Scale Integrated circuits) or ICs (Integrated Circuits) are mounted on each electronic apparatus. By conducting transmission and reception of logic signals between these electronic devices, given operation is executed. Recently, however, power supply voltages of a plurality of electronic devices tend to differ according to manufactures. Therefore, there frequently occurs such a situation that the level of the logic signal also differs among a plurality of electronic devices.
- Heretofore, therefore, it has been necessary to adjust the level of the logic signal among a plurality of devices. This results in such a state that evil effects attendant upon the adjustment, such as a longer circuit design time and restriction of usable electronic devices, cannot be overlooked. Heretofore, therefore, a measure and method capable of effectively solving such problems have been desired earnestly.
- As an example of the above described electronic apparatus having a plurality of electronic devices, a magnetic disk apparatus shown in FIG. 6 will now be described. FIG. 6 is a block diagram showing the configuration of a conventional magnetic disk apparatus. As shown in FIG. 6, in this magnetic disk apparatus, a HDC (hard disk controller)1 is connected to a
host 9 via a SCSI (Small Computer System Interface) bus which is not illustrated. Between theHDC 1 and thehost 9 via the SCSI bus, various commands (such as a read command and write command), write data to be written onto a magnetic disk M described later, and read data read out from the magnetic disk M are transmitted and received. TheHDC 1 controls components of the magnetic disk apparatus. - A MPU (Micro Processing Unit)2 controls components of the apparatus. A read/write control and power save control are the major example of such control. A read
channel 3 includes a modulation circuit for writing write data onto the magnetic disk M, a parallel/serial conversion circuit for converting parallel write data to serial data, and a demodulation circuit for reading out read data from the magnetic disk M. In addition, theread channel 3 includes a serial/parallel conversion circuit for converting serial read data to parallel data, and a synthesizer circuit for generating timing signals to be used as timing of components of the apparatus by conducting frequency multiplication on the frequency of an oscillation circuit using a crystal oscillator. - A
head IC 4 drives amagnetic head 5. Thehead IC 4 delivers read data fed from themagnetic head 5 to the readchannel 3, and delivers write data fed from the readchannel 3 to themagnetic head 5. Themagnetic head 5 is disposed in close vicinity to the magnetic disk M. Themagnetic head 5 has a function of magnetically writing write data onto the magnetic disk M and a function of magnetically reading out read out from the magnetic disk M. - A SPM (spindle motor)6 drives and rotates the magnetic disk M. A VCM (voice coil motor) 7 moves the
magnetic head 5 in the radial direction of the magnetic disk M.A servo controller 8 effects servo control by controlling theSPM 6 and the VCM 7. TheHDC 1,MPU 2, readchannel 3,head IC 4, andservo controller 8 are electronic devices such as LSIs and ICs, and driven with different power supply voltages. - Therefore, levels of logic signals transmitted and received between these electronic devices also differ depending on electronic devices. In the conventional magnetic disk apparatus, therefore, the level adjustment of logic signals is conducted by an interface circuit shown in FIG. 7. In FIG. 7, an LSI A and an LSI B correspond to two among the
HDC 1, theMPU 2, the readchannel 3 and so on shown in FIG. 6. The LSI A is driven by a first power supply voltage Vcc1 (=5.0 V). A logic signal S1 of the LSI A also has a level of 5.0 V. - On the other hand, the LSI B is driven with a second power supply voltage Vcc2 (=2.5 V) which differs from the first power supply voltage Vcc1 (=5.0 V). A logic signal S2 of the LSI B also has a level of 2.5 V. That is, the logic signal S1 of the LSI A has a level of 5.0 V, whereas the logic signal S2 of the LSI B has a level of 2.5 V. If the logic signal S1 of 5.0 V is inputted to the LSI B while leaving this state intact, therefore, the logic signal S1 exceeds the breakdown voltage of the LSI B and there is a possibility of the LSI B being destroyed.
- In the conventional interface circuit, therefore, there is provided a level converter C for conducting level adjustment of the logic signal between the LSI A and the LSI B. The level converter C converts the logic signal S1 of 5.0 V to the logic signal S2 of 2.5 V conforming to the LSI B. By virtue of the level adjustment conducted by the level converter C, the LSI A and the LSI B normally function.
- Thus, the level converter C for conducting the level adjustment of the logic signals must be used in the conventional technique when a plurality of electronic devices driven with different voltages are to be utilized. Therefore, it is necessary to select an electronic device which conforms to the level conversion characteristic of the level converter C. Even if an electronic device is high in performance as a simple substance, therefore, the electronic device cannot be used in the electronic apparatus so long as it does not conform to the level conversion characteristic, in the case of the conventional technique. Therefore, usable electronic devices are restricted naturally. This results in a problem that the circuit design is severely restricted.
- Furthermore, if the level converter C is not used, there is a restriction that a plurality of electronic devices which are equal in logic signal level must be selected. This results in a problem that the circuit design time becomes longer by the time required for selection.
- It is an object of the present invention to provide an interface circuit and signal transmission method capable of increasing the degree of freedom of the circuit design using a plurality of electronic devices driven with different voltages and shortening the circuit design time.
- In the present invention, a constant current control unit outputs a constant current to the second electronic device, and a logic signal generation unit generates a logic signal having a level conforming to the second electronic device on the basis of the constant current. Thus, logic signal transmission using the constant current is conducted between the first electronic device and the second electronic device, and a logic signal having a level conforming to the second electronic device is generated on the basis of the constant current, in the second electronic device. Accordingly, even if a plurality of electronic devices driven with different power supply voltages are present, the level of the logic signal can be easily conformed. As a result, it becomes possible to increase the degree of freedom of the circuit design and shorten the circuit design time.
- Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
- FIG. 1 is a block diagram showing a schematic configuration of a first embodiment according to the present invention;
- FIG. 2 is a block diagram showing a configuration of the first embodiment according to the present invention;
- FIG. 3 is a block diagram showing a configuration of a second embodiment according to the present invention;
- FIG. 4 is a block diagram showing a configuration of a third embodiment according to the present invention;
- FIG. 5 is a block diagram showing a configuration of a fourth embodiment according to the present invention;
- FIG. 6 is a block diagram showing a configuration of a conventional magnetic disk apparatus; and
- FIG. 7 is a block diagram showing a configuration of a conventional interface circuit.
- Preferred embodiments of an interface circuit and a signal transmission method according to the present invention will be described by referring to the attached drawing. The present invention is not limited to these embodiments.
- FIG. 1 is a block diagram showing a schematic configuration according to a first embodiment of the present invention. An
LSI 10 and anLSI 20 shown in FIG. 1 are mounted on one electronic apparatus which is not illustrated, and driven with different power supply voltages, respectively. In addition, theLSI 10 is also different from theLSI 20 in logic signal level. - In other words, the
LSI 10 is driven with a first power supply voltage Vcc1 (=5.0 V). The logic signal level of theLSI 10 is also 5.0 V. Within theLSI 10, an interface circuit for sending out a constant current I4 to theLSI 20 is incorporated. When the constant current I4 flows, a logic signal S0 is at a high level. When the constant current I4 does not flow, the logic signal S0 is at a low level. - On the other hand, the
LSI 20 is driven with a second power supply voltage Vcc2 (=2.5 V) which is different from the first power supply voltage Vcc1 (=5.0 V). The logic signal level of theLSI 20 is also 2.5 V. Within theLSI 10, an interface circuit for generating a logic signal of a level (2.5 V) conforming to theLSI 20 from a constant current I4 is incorporated. In this way, the logic signal level of theLSI 10 is 5.0 V, whereas the logic signal level of the LSI B is 2.5 V. - More detailed configuration of the first embodiment will now be described with reference to FIG. 2. In FIG. 2, components corresponding to those of FIG. 1 are denoted by same legends. The
LSI 10 includes aninterface circuit 15 and aninternal circuit 16. In theinterface circuit 15, atransistor 11 is a PNP transistor for effecting on/off control on the output of the constant current I4. Thistransistor 11 is supplied with the first power supply voltage Vcc1 at its emitter. A resistor R1 is interposed between a collector of thetransistor 11 and ground GND. The resistor R1 has a very large resistance value r1 in order that a constant current I2≈the constant current I4. - A
diode 12 is connected between the emitter and base of thetransistor 11 in parallel. Thediode 12 and thetransistor 11 form a current mirror circuit. A constant current I1 flowing through thediode 12 is equal to the constant current I2 flowing through the emitter of thetransistor 11. A constantcurrent source 13 is interposed between a cathode of thediode 12 and theinternal circuit 16. The constantcurrent source 13 functions to let the constant current I1 flow. - The
internal circuit 16 is a circuit for implementing the function of theLSI 10. Theinternal circuit 16 executes the operation based on a logic signal S10. The logic signal S10 has a level of 5.0V. A switch 14 is connected in parallel to thediode 12, and controlled to turn on/off by a control circuit which is not illustrated. Aconnection line 30 is connected between theLSI 10 and theLSI 20. Theconnection line 30 serves as a transmission path of the constant current I4 (logic signal S0). - On the other hand, the
LSI 20 includes aninterface circuit 24 and aninternal circuit 25. In theinterface circuit 24, atransistor 21 is an NPN transistor which is controlled to turn on/off by the constant current I4. Thetransistor 21 is supplied at its collector with the second power supply voltage Vcc2 (=2.5 V) via a resistor R3. The second power supply voltage Vcc2 (=2.5 V) is different from the first power supply voltage Vcc1 (=5.0 V) for theLSI 10. - A resistor R2 is interposed between an emitter of the
transistor 21 and the ground GND. A diode 22 and adiode 23 form a series circuit. The series circuit is interposed between a base of thetransistor 21 and the ground GND. Theinternal circuit 25 is a circuit for implementing the function of theLSI 20. Theinternal circuit 25 executes the operation on the basis of a logic signal S20. The logic signal S20 has a level of 2.5 V (≠the level of the logic signal S10). - If the
switch 14 is turned off, then a constant current I1 determined by the constantcurrent source 13 flows through thediode 12, and in addition, the constant current I2 having the same value as the constant current I1 flows through the emitter of thetransistor 11 included in the current mirror circuit. The constant current I2 is divided into a constant current I3 flowing through the collector of thetransistor 11 and the constant current I4 flowing through theconnection line 30. Since the resistance value r1 of the resistor R1 is very large, the current I3≈0. Therefore, it follows that the constant current I2≈constant current I4. - When the constant current I4 flows into the
interface circuit 24, a drop voltage VD (≈1.4 V) occurs across the series circuit formed of thediodes 22 and 23, and a base-emitter voltage VBE (≈0.7 V) occurs between the base and the emitter of thetransistor 21. As a result, a drop voltage VR2 of approximately 0.7 V (=drop voltage VD−base-emitter voltage VBE) occurs across a resistor R2, and a current I5 (=drop voltage VR2/resistance value r2 of the resistor R2) flows. - At this time, the current I5 flows through the resistor R3 as well. Therefore, a drop voltage VR3 (=resistance value r3 of the resistor R3×current I5) occurs across the resistor R3. Accordingly, a logic signal S20 of a low level represented as (second power supply voltage Vcc2−drop voltage VR3) is inputted to the
internal circuit 25. - In other words, in the first embodiment, the level of the logic signal S20 can be conformed to the
LSI 20 without using the conventional level converter C (see FIG. 7), by setting the resistance value r2 of the resistor R2 and the resistance value r3 of the resistor R3 to suitable values. The resistors R2 and R3 may be variable resistors. In this case, logic signals of arbitrary levels can be generated. As a result, it becomes easy to mount any electronic devices driven with different power supply voltages on an electronic apparatus. - On the other hand, if the
switch 14 is turned on, then the constant current I1 ceases to flow through thediode 12, and consequently it follows that the constant current I2=0. Therefore, the constant current I4=0, and the base voltage of thetransistor 21 also becomes 0 V. Since thetransistor 21 thus turns off, the second power supply voltage Vcc2, i.e., a high level logic signal S20 is inputted to theinternal circuit 25. - As heretofore described, in the first embodiment, logic signal transmission is conducted between the
LSI 10 and theLSI 20 by using the constant current I4, and the logic signal S20 having the level conforming to theLSI 20 is generated in theLSI 20 on the basis of the constant current I4. Even in a plurality of electronic devices driven with different voltages, therefore, logic signal levels can be conformed simply. As a result, the degree of circuit design can be increased and the circuit design time can be shortened. - FIG. 3 is a block diagram showing a configuration of a second embodiment according to the present invention. In FIG. 3, components corresponding to those of FIG. 2 are denoted by same legends. In FIG. 3, an
LSI 40 is provided instead of theLSI 20 shown in FIG. 2. TheLSI 40 includes aninterface circuit 44 and aninternal circuit 45. - In the
interface circuit 44, a constantcurrent source 41 functions to let a constant current I6 flow. The constantcurrent source 41 is connected to a second power supply voltage Vcc2. A transistor 42 and atransistor 43 form an ECL (Emitter Coupled Logic) circuit. Thetransistor 42 is a PNP transistor interposed between the constantcurrent source 41 and the ground GND. Thetransistor 42 is connected to aconnection line 30 at its base, connected to the constantcurrent source 41 at its emitter, and connected to the ground GND at its collector. A resistor R4 is interposed between the base of thetransistor 42 and the ground GND. - The
transistor 43 is a PNP transistor disposed in parallel to thetransistor 42 and interposed between the constantcurrent source 41 and the ground GND. In other words, thetransistor 43 is connected at its emitter to the constantcurrent source 41 and the emitter of thetransistor 42, and connected at its collector to the ground GND via a resistor R5. Thetransistor 43 is supplied with a reference voltage Vref at its base. The reference voltage Vref is set to a value obtained by subtracting 0.5 (V) from a drop voltage VR4 incurred across the resistor R4. Theinternal circuit 45 is a circuit for implementing the function of theLSI 40. Theinternal circuit 45 operates on the basis of a logic signal S40. The logic signal S40 has a level of 2.5 V (≠level of the logic signal S10). - If the
switch 14 is turned off, then a constant current I1 determined by the constantcurrent source 13 flows through thediode 12, and in addition, the constant current I2 having the same value as the constant current I1 flows through the emitter of thetransistor 11 included in the current mirror circuit. In the same way as the case of the first embodiment, therefore, the constant current I4 (≈constant current I2) flows through theconnection line 30. - If the constant current I4 flows into the
interface circuit 44, then a drop voltage VR4 occurs across a resistor R4. Since the reference voltage Vref is applied to the base of thetransistor 43 at this time, the constant current I6 flows through the resistor R5 via thetransistor 43 as a result of the function of the ECL circuit. Accordingly, a high level logic signal S40 represented as the resistance value r5 of the resistor R5×constant current I5 is inputted to theinternal circuit 45. In other words, in the second embodiment, the level of the logic signal S40 can be conformed to theLSI 40 without using the conventional level converter C (see FIG. 7) , by setting the resistance value r5 of the resistor R5 to a suitable value. The resistor R5 may be a variable resistor. - On the other hand, if the
switch 14 is turned on, then the constant current I1 ceases to flow through thediode 12, and consequently it follows that the constant current I2=0. Therefore, the constant current I4=0, and the base voltage of thetransistor 21 also becomes 0 V. Since all of the constant current I6 flows into thetransistor 42, the constant current I6 does not flow through the transistor 43 (resistor R5) In this case, a logic signal S40 of a low level (ground GND level) is inputted to theinternal circuit 45. - As heretofore described, in the second embodiment, logic signal transmission is conducted between the
LSI 10 and theLSI 40 by using the constant current I4, and the logic signal S40 having the level conforming to theLSI 20 is generated in theLSI 40 on the basis of the constant current I4. Even in a plurality of electronic devices driven with different voltages, therefore, logic signal levels can be conformed simply. As a result, the degree of circuit design can be increased and the circuit design time can be shortened. - With reference to the first embodiment, there has been made description to the effect that the constant current I4 ceases to flow when the
switch 14 shown in FIG. 2 is turned on. As a matter of fact, however, an attenuation time depending on circuit constants occurs until the constant current I4 attenuates to 0. This attenuation time becomes a factor which aggravates the response characteristic. Therefore, it is desirable to shorten the attenuation time as short as possible and thereby improve the response characteristic. Hereafter, this case will be described as a third embodiment. - FIG. 4 is a block diagram showing a configuration of a third embodiment according to the present invention. In FIG. 4, components corresponding to those of FIG. 2 are denoted by same legends. In FIG. 4, an
LSI 50 is provided instead of theLSI 10 shown in FIG. 2. TheLSI 50 includes aninterface circuit 56 and aninternal circuit 16. In theinterface circuit 56, atransistor 52, a constantcurrent source 53, adiode 54, and aswitch 55 are provided instead of the resistor R1 shown in FIG. 2. - The
transistor 52 is an NPN transistor for shortening the attenuation time of the constant current I4. Thetransistor 52 is connected at its collector to the collector of thetransistor 11, and connected at its emitter to the ground GND. The constantcurrent source 53 functions to let a constant current I8 flow. Thediode 54 is interposed between the constantcurrent source 53 and the ground GND. Thediode 54 and thetransistor 52 form a current mirror circuit. Theswitch 55 is connected in parallel to thediode 54 and controlled to turn on/off by a control circuit which is not illustrated. Theswitch 14 and theswitch 55 are turned on/off by inverse logics. - If the
switch 14 is turned off and theswitch 55 is turned on in the above described configuration, then the constant current I1 determined by the constantcurrent source 13 flows through thediode 12, and in addition, a constant current I2 having the same value as the constant current I1 flows through the emitter of thetransistor 11 included in the current mirror circuit. Through theconnection line 30, therefore, the constant current I4 (≈constant current I2) flows. On the other hand, since theswitch 55 is in the on-state, the constant current I8 flows through theswitch 55, but it does not flow through thediode 54. - Therefore, no current flows through the
transistor 52 included in the current mirror circuit. Accordingly, thetransistor 52 is turned off. If thereafter the constant current I4 flows into theLSI 20, then operation similar to the operation of the first embodiment described earlier is conducted. - If the
switch 14 is turned on and theswitch 55 is turned off, then the constant current I1 ceases to flow through thediode 12. On the other hand, since theswitch 55 is in the off state, the constant current I8 flows through thediode 54 and consequently thetransistor 52 turns on. Therefore, a sink constant current I7 flows through theconnection line 30 in a direction opposite to that of the constant current I4. As a result, the constant current I4 is canceled by the sink constant current I7 and attenuated rapidly. - As heretofore described, in the third embodiment, the
transistor 52, the constantcurrent source 53, and theswitch 55 are provided, and the sink constant current I7 is let flow in the direction opposite to that of the constant current I4. Therefore, the attenuation time of the constant current I4 can be shortened. As a result, the response characteristic can be improved. - With reference to the third embodiment, there has been described an example in which the means for letting the sink constant current I7 shown in FIG. 4 flow are provided to improve the response characteristic between the
LSI 50 and theLSI 20. This may be applied to the second embodiment. Hereafter, this case will be described as a fourth embodiment. - FIG. 5 is a block diagram showing a configuration of the fourth embodiment. In FIG. 5, components corresponding to those of FIG. 4 are denoted by same legends. In FIG. 5, the LSI40 (see FIG. 3) is provided instead of the
LSI 20 shown in FIG. 4. Operation of flow of the sink constant current I7 shown in FIG. 5 and effects of the sink constant current I7 are similar to those of the third embodiment, and consequently description of them will be omitted. - According to the present invention, logic signal transmission using the constant current is conducted between the first electronic device and the second electronic device, and a logic signal having a level conforming to the second electronic device is generated on the basis of the constant current, in the second electronic device, as heretofore described. Even in a plurality of electronic devices driven with different power supply voltages, therefore, the level of the logic signal can be conformed simply. This brings about an effect that it becomes possible to increase the degree of freedom of the circuit design and shorten the circuit design time.
- Further, a sink constant current is let flow in a direction opposite to that of the constant current. This brings about an effect that the attenuation time is shortened and consequently the response characteristic can be improved.
- Further, a logic signal conforming to the second electronic device is generated by an extremely simple element, i.e., a resistor. This brings about an effect that the circuit design time can be further shortened.
- Further, the resistor is a variable resistor. Accordingly, a logic signal having an arbitrary level can be generated. This brings about an effect that it becomes easy to mount any electronic devices driven with different power supply voltages on an electronic apparatus.
- Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
Claims (5)
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JP2000151796A JP3847527B2 (en) | 2000-05-23 | 2000-05-23 | Interface circuit and signal transmission method |
JP2000-151796 | 2000-05-23 |
Publications (2)
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US20010045845A1 true US20010045845A1 (en) | 2001-11-29 |
US6377072B2 US6377072B2 (en) | 2002-04-23 |
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US09/734,686 Expired - Lifetime US6377072B2 (en) | 2000-05-23 | 2000-12-13 | Interface circuit and signal transmission method |
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US (1) | US6377072B2 (en) |
JP (1) | JP3847527B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224816A1 (en) * | 2008-02-28 | 2009-09-10 | Semikron Elektronik Gimbh & Co. Kg | Circuit and method for signal voltage transmission within a driver of a power semiconductor switch |
CN112904122A (en) * | 2021-01-22 | 2021-06-04 | 维沃移动通信有限公司 | Insertion detection circuit and electronic device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW557629B (en) * | 2002-01-16 | 2003-10-11 | Pixart Imaging Inc | Transmission line driving circuit |
KR100476952B1 (en) * | 2002-10-14 | 2005-03-16 | 삼성전자주식회사 | Connecting apparatus between two different volatage |
JP4327113B2 (en) * | 2005-02-25 | 2009-09-09 | Okiセミコンダクタ株式会社 | Interface between different power sources and semiconductor integrated circuit |
JP5206348B2 (en) * | 2008-11-18 | 2013-06-12 | 株式会社デンソー | Control circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE8912984U1 (en) * | 1989-11-02 | 1990-03-29 | Siemens AG, 1000 Berlin und 8000 München | Interface circuit between two electrical circuits operated at different operating voltages |
JP2982196B2 (en) * | 1990-02-06 | 1999-11-22 | 日本電気株式会社 | Different power supply interface circuit |
US5691654A (en) * | 1995-12-14 | 1997-11-25 | Cypress Semiconductor Corp. | Voltage level translator circuit |
US5680063A (en) * | 1996-04-23 | 1997-10-21 | Motorola, Inc. | Bi-directional voltage translator |
US6154057A (en) * | 1998-12-07 | 2000-11-28 | Motorola, Inc. | Bi-directional voltage translator |
-
2000
- 2000-05-23 JP JP2000151796A patent/JP3847527B2/en not_active Expired - Lifetime
- 2000-12-13 US US09/734,686 patent/US6377072B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224816A1 (en) * | 2008-02-28 | 2009-09-10 | Semikron Elektronik Gimbh & Co. Kg | Circuit and method for signal voltage transmission within a driver of a power semiconductor switch |
EP2110950A1 (en) * | 2008-02-28 | 2009-10-21 | SEMIKRON Elektronik GmbH & Co. KG | Switch and method for transferring signal voltage within a driver of a voltage semiconductor |
US8754698B2 (en) | 2008-02-28 | 2014-06-17 | Semikron Elektronik Gmbh & Co. Kg | Circuit and method for signal voltage transmission within a driver of a power semiconductor switch |
CN112904122A (en) * | 2021-01-22 | 2021-06-04 | 维沃移动通信有限公司 | Insertion detection circuit and electronic device |
Also Published As
Publication number | Publication date |
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US6377072B2 (en) | 2002-04-23 |
JP2001332965A (en) | 2001-11-30 |
JP3847527B2 (en) | 2006-11-22 |
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