KR100588177B1 - Semiconductor device and disk drive device using same - Google Patents

Abstract

Provided are a semiconductor field and a disk drive device which reduce the possibility of malfunction and at the same time realize miniaturization and cost reduction.

When the circuit serving as the source of noise becomes operable, the control circuit C turns on the switch circuit SW so that the two N-channel MOS type FETs Q2 connected in parallel with the P-channel MOS type FETs Q1. The inverter is constituted by (Q3), and the threshold voltage of the inverter is lowered by increasing the current capability of the MOS type FET side of the N-channel of the inverter.

Description

Semiconductor device and disk drive device using same

The present invention relates to a semiconductor device and a disk drive device such as FDD, HDD, PD, CD-ROM using the same.

5 is a block diagram of a floppy disk drive (FDD) device, which is one of disk drive devices.

In Fig. 5, 1 is an interface driving circuit, 2 is a control circuit, 3 is a read / write circuit, 4 is a stepping motor driving circuit, 5 is a spindle motor driving circuit, 6 is The lead light head, 7 is an erase head, 8 is a stepping motor, 9 is a spindle motor, 10 is an index sensor, 11 is a track sensor, and 100 is an external host device such as a personal computer.

In addition, the interface driving circuit 1, the control circuit 2, the read write circuit 3, and the stepping motor driving circuit 4 are ICs (semiconductor integrated circuits) of one chip.

The operation of each part will be described.

The interface drive circuit 1 is not shown in which data is exchanged between the host device 100 and the control circuit 2, and the exchange is performed between the host device 100 and the read write circuit 3. The format and transfer method of the data written on the magnetic disk and the data read from the magnetic disk are matched.

The control circuit 2 controls the writing and reading of data to a magnetic disk (not shown) in response to the data input from the host apparatus 100 through the interface driving circuit 1, and indicates an operation state of the FDD apparatus. Data and the like are outputted to the host device 100 through the interface driving circuit 1.

Under the control of the control circuit 2, the read write circuit 3 writes and reads data to and from the magnetic disk in response to the data input from the host apparatus 100 through the interface driving circuit 1 when writing data. The data is written to the magnetic disk by causing a current to flow through the coils constituting the lead write head 6 for use and the erase head 7 for erasing the data recorded on the magnetic disk. do.

On the other hand, when reading data, the data is read from the magnetic disk by the voltage generated in the coil constituting the read write head 6 in accordance with the recorded data, and the read data is read through the host device 1 through the interface driving circuit 1. Output to (100).

The stepping motor driving circuit 4 drives the stepping motor 8 for transferring the lead light head 6 and the erase head 7 in the radial direction of the magnetic disk, under the control of the control circuit 2.

The spindle motor driving circuit 5 drives the spindle motor 9 for rotating the magnetic disk under the control of the control circuit 2.

The index sensor 10 controls whether the magnetic disk is rotating normally, and the track sensor 11 controls whether the lead light head 6 and the erase head 7 are located at the outermost circumference of the magnetic disk. It is for the circuit 2 to detect.

Here, as shown in Fig. 6, the input stage first stage of the conventional interface drive circuit 1 is a P-channel MOS FET (hereinafter referred to as "PMOS") Q1 and an N-channel MOS FET (hereinafter referred to as "PMOS"). , as referred to) (at the same time as the connection pads (P) input terminal (I) of the inverter that is in Q2), the power supply voltage V _cc "NMOS" Reverse bias between the pull-up resistor R1 and pull-down resistor R2 connected in series between the reference potential GND and the reference potential GND, and the supply voltage V _CC and the reference potential GND, respectively. Is connected to the connection point of two protective diodes Di1 and Di2 connected in series.

These circuits are formed inside the IC (left side of the broken line H).

Then, the threshold voltage of the inverter which is set to V _cc / 2, that is, be the low level is input to the pad (P) when the input of the inverter to be smaller than V _cc / 2 PMOS (Q1) is ON and NMOS (Q2 ) Is turned OFF and the output of the inverter is at high level (V _cc ). On the other hand, when the high level is input to the pad (P) and the input of the inverter is larger than V _cc / 2, the PMOS (Q1) is turned off and the NMOS (Q2) Is turned on, and the output of the inverter becomes low level (ground level).

In addition, the threshold voltage of the inverter is set to V _cc / 2, which is the center of the power supply voltage V _cc , to set the input threshold voltage at almost the center of the high level and low level input to the pad P. .

By the way, the output section and the stepping motor driving circuit 4 in the interface driving circuit 1 have a circuit for processing a large current (hereinafter referred to as a "large current driver"). Since it is formed on a chip, the power supply voltage V _cc fluctuates when the large current driver is switched on or off, or the NPN transistor constituting the large current driver due to the counter current component of the motor driven by the large current driver. The collector of (T1) is below the ground potential. For example, the collector of the NPN transistor T1 in the large current driver is an emitter, and the P-type substrate connected to the ground level is used as the base, and the protection diode (Di2) is used. The parasitic NPN transistor T2, which is a collector of the negative electrode), is turned on, and as shown by the arrow in FIG. 6, the resistor R1 and the diode Di2 A current flows (hereinafter referred to as "parasitic current"), which causes a voltage drop due to the resistance R1 and the parasitic current.

When such a phenomenon occurs, the voltage input to the inverter becomes lower than when the phenomenon is not occurring even though the voltage input to the pad P is equal to a predetermined impedance (hereinafter referred to as “input”). Drop ''.

In the conventional input unit, if an input drop occurs when a high level slightly higher than the threshold voltage of the inverter is input to the pad P, the input level of the inverter decreases to fall below the threshold voltage. In other cases, the PMOS Q1 is turned on and the output of the inverter becomes high level. As a result, there is a possibility that a malfunction of the FDD device occurs.

In addition, the input drop becomes more pronounced as the input unit and the high current driver are adjacent to each other, so that an input restriction and the high current driver in the IC chip cannot be adjacent to each other in order to suppress a malfunction as the FDD device.

As a result, the chip area is increased, thereby increasing the size of the IC, thereby causing a problem of high cost.

Therefore, an object of the present invention is to provide a semiconductor device and a disk drive device which reduce the possibility of malfunction and at the same time realize miniaturization and cost reduction.

In order to achieve the above object, in the invention described in claim 1, an output circuit, an input circuit which may misjudge an input signal by an output state of the output circuit, and a data output from the output circuit. A semiconductor device having control and control means for processing data input from said input circuit,

The control means changes the input threshold voltage of the input circuit in accordance with the output state of the output circuit.

In the invention described in claim 2, in the invention described in claim 1, the input circuit is an inverter circuit, and the input threshold voltage is changed while switching the number of transistors constituting the inverter circuit. I'm going to let you.

In addition, according to the invention described in claim 3, there is provided a large current output circuit for driving a motor, an input circuit which may misjudge an input signal due to the output state of the large current output circuit, and data from the large current output circuit. A semiconductor device comprising a semiconductor device serving as a control means for controlling output and processing data input from the input circuit, wherein the disk driving device reads data recorded on the recording medium while rotating the disk-type recording medium by the motor. And the control means changes the input threshold voltage of the input circuit in accordance with the output state of the output circuit.

In the invention described in claim 4, in the disk drive device according to claim 3, a stepping motor or a spindle motor is connected to the large current output circuit, and a host device is connected to the input circuit.

In the invention described in claim 5, in the disk drive device according to claim 3 or 4, a head for reading and writing data through a read write circuit is connected to the control means.

In addition, in the invention described in claim 6, there is provided a large current output circuit for driving a motor, an input circuit which may misjudge an input signal depending on the output state of the large current output circuit, and data from the large current output circuit. A motor drive device having a semiconductor device as a control means for controlling output and processing data input from the input circuit,

The control means changes the input threshold voltage of the input circuit in accordance with the output state of the output circuit.

With each of the above configurations, for example, when considering a semiconductor device for an FDD device, which is shown in the prior art, when the high current driver is operated, the threshold voltage of the inverter of the input unit is lowered to a certain extent. Even if it occurs, the input signal is not misjudged.

(Example)

EMBODIMENT OF THE INVENTION Below, embodiment of this invention is described, referring drawings.

Fig. 1 is a diagram showing the configuration of the first stage of the input section in the interface driver circuit 1 of the FDD device which is one embodiment of the present invention.

Q3 is an NMOS, and its drain-source is connected in parallel with the NMOS Q2, and its gate is connected to the gate of the NMOS Q2 through the switch circuit SW, and the resistor R3 is connected to the gate of the NMOS Q2. Connected to ground level.

In addition, the same part as FIG. 6 shown as a prior art attaches | subjects the same code | symbol, and abbreviate | omits description.

In addition, the block diagram as an FDD apparatus is the same as FIG.

With the above arrangement, when the switch circuit SW is OFF, the gate of the NMOS Q3 is at the ground level and the NMOS Q3 is turned OFF, so that the inverter is composed of the PMOS Q1 and the NMOS Q2. When the switch circuit SW is ON, the voltage of the gate of the NMOS Q3 is substantially the same as that of the gate of the NMOS Q2, so that the inverter is connected to two NMOS Q2s connected in parallel with the PMOS Q1 ( Q3), the current capability on the NMOS side is increased than when the switch circuit SW is OFF, and the input threshold voltage of the inverter is lowered.

The ON / OFF control of the switch circuit SW is applied to an enable signal E for switching the operation and non-operation of a circuit, for example, a source of noise such as a large current driver, to the control circuit C. Do it in accordance with.

Specifically, the switch circuit SW is turned ON when the enable signal E becomes operable, and the switch circuit SW is turned OFF when the enable signal E becomes inoperable. .

As a result, when the circuit serving as the source of noise can operate, the threshold voltage of the inverter is automatically lowered than when the circuit serving as the source of noise cannot operate.

Specifically, the threshold voltage of the inverter is lowered by the average input drop voltage.

Considering the above, when the high level is input to the pad P, when the circuit which generates the noise is operable, an input drop occurs as in the prior art, and the inverter has a normal threshold voltage V. _{Even if a} voltage lower than _{CC /} 2 is input, the threshold voltage of the inverter itself is also lower than the average input drop voltage of V _{CC /} 2, so that the input signal is misjudged even if a certain amount of input drop occurs. There will be no.

As a result, the possibility of malfunction as an FDD device is reduced.

In addition, when the circuit used as the source of noise is inoperable, the threshold voltage of the inverter becomes normal V _{CC /} 2, which is the center value of the high level and the low level input to the pad P and thus the pad P. The malfunction of the FDD device due to the noise that jumps on can be minimized.

In this way, even if a certain amount of input drop occurs, the input signal is not misjudged, thereby reducing the arrangement constraint that the input unit cannot be adjacent to the circuit that generates the noise, thereby reducing the chip area. This makes it possible to reduce the size and cost of the standard as an FDD device.

Although only the embodiment of FIG. 1 has been described, the presence or absence of the resistors R1, R2 and the protective diodes Di1, Di2 may be determined depending on the type of the circuit connected to the pad P. As shown in FIG.

In addition, the method of changing the threshold voltage of an inverter may use another general method.

It is also possible to change the threshold voltage in response to a change in the power supply voltage.

The switch SW and the resistor R3 may be externally attached to the IC as shown in FIG. 2.

In this way, the input threshold voltage can be set arbitrarily.

In addition, although two NMOSs which comprise an inverter are shown in FIG. 1, it may be set as the structure shown, for example in FIG.

In this way, the threshold voltage of the inverter can be set to three or more, so that there are a plurality of circuits that generate noise sources, and even if the degree of input drop generated by the operation differs for each of these circuits, It becomes the number.

In addition, in FIG. 3, the control circuit C is comprised so that ON / OFF of the some switch circuit SW may be switched based on the some enable signal E. As shown in FIG.

In addition, when the input to the inverter rises due to the operation of the circuit which is the source of noise, a plurality of PMOSs are provided and the plurality of PMOSs are divided and used according to whether or not the operation of the circuit which is the source of noise is possible or impossible. Therefore, the threshold voltage of the inverter may be increased when the circuit which is the source of noise generation is operable.

For example, as shown in Fig. 4, the gate of the PMOS Qm is connected to the input terminal I of the inverter through the switch circuit SW, and the resistor Rm is connected to the power supply voltage V _CC . When the connection is made, the switch circuit SW is switched ON / OFF (ON in an operable state and OFF in an inoperable state) depending on whether the circuit which is the source of noise can be operated or not. do.

As described above, according to the semiconductor device and the disk drive device of the present invention, it is possible to reduce the possibility of malfunction and to attain miniaturization and cost reduction.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing the configuration of an input unit in an interface driving circuit in an FDD apparatus according to one embodiment of the present invention.

Fig. 2 is a circuit diagram showing another configuration of an input unit in an interface driving circuit in an FDD device according to one embodiment of the present invention.

Fig. 3 is a circuit diagram showing still another configuration of an input unit in an interface driving circuit in an FDD device according to one embodiment of the present invention.

Fig. 4 is a circuit diagram showing still another configuration of an input unit in an interface driving circuit in an FDD device according to one embodiment of the present invention.

5 is a block diagram of an FDD device which is one of disk drive devices.

Fig. 6 is a circuit diagram showing the configuration of an input unit in an interface driving circuit in a conventional FDD apparatus.

(Explanation of symbols for the main parts of the drawing)

1. Interface driving circuit

2. Control circuit

3. Read / Write Circuit

4. Stepping motor driving circuit

5. Spindle motor driving circuit

6. Leadlight head

7. Elace head

8. Stepping motor

9. Spindle Motor

10. Index sensor

11. Track sensor

Q1, Qm PMOS (MOS-type FETs in P-channel)

Q2, Q3,... , Qn NMOS (N-channel MOS type FET)

R1. Resistor for pull up

R2. Pull-down resistor

R3, R4,... , Rn, Rm resistance

Di1, Di2. Protective diode

SW. Switch circuit

C. Control Circuit

Claims (6)

An output circuit, an input circuit which may misjudge an input signal according to the output state of the output circuit, and control means for controlling data output from the output circuit and processing data input from the input circuit. In a semiconductor device having, And the control means changes the input threshold voltage of the input circuit in accordance with the output state of the output circuit. The method of claim 1, And the input circuit is an inverter circuit, wherein the input threshold voltage is changed while switching the number of transistors constituting the inverter circuit. A large current output circuit for driving a motor, an input circuit which may misjudge an input signal by the output state of the large current output circuit, control of data output from the large current output circuit, and input from the input circuit. A disk drive device having a semiconductor device comprising control means for processing data, wherein the disk drive device reads the data recorded on the recording medium while rotating the disk-shaped recording medium by the motor, And the control means changes the input threshold voltage of the input circuit in accordance with the output state of the output circuit. The method of claim 3, A stepping motor or a spindle motor is connected to the large current output circuit, and a host device is connected to the input circuit. The method according to claim 3 or 4, And a head for reading / writing data through the read write circuit is connected to the control means. A large current output circuit for driving a motor, an input circuit which may misjudge an input signal by the output state of the large current output circuit, control of data output from the large current output circuit, and input from the input circuit. A motor drive apparatus having a semiconductor device comprising control means for processing data, And the input threshold voltage of the input circuit is changed by the control means in accordance with the output state of the output circuit.