US20010038566A1 - Memory component with short access time - Google Patents
Memory component with short access time Download PDFInfo
- Publication number
- US20010038566A1 US20010038566A1 US09/773,221 US77322101A US2001038566A1 US 20010038566 A1 US20010038566 A1 US 20010038566A1 US 77322101 A US77322101 A US 77322101A US 2001038566 A1 US2001038566 A1 US 2001038566A1
- Authority
- US
- United States
- Prior art keywords
- cell array
- local data
- memory component
- strips
- component according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims description 18
- 230000004913 activation Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
Definitions
- the invention relates to a memory component having a cell array with a plurality of memory cells configured such that a number of bits are synchronously accessible.
- the maximum clock frequency is limited by that unit which requires the maximum time for performing a process step.
- no unit is allowed to require significantly more time than the rest of the units for performing a process step.
- the access time to a desired number of bits in a memory chip must not exceed the time of one clock cycle. If this were the case, then an additional clock cycle would be required until the information packet were conveyed further, since the information packet waiting at the output of the memory chip can only be conveyed further clock cycle by clock cycle.
- the processing units which are coupled to the memory component and require this information packet in order to perform their work would each have their work interrupted for the length of one clock cycle.
- FIG. 3 shows a schematic structure of a cell array 1 of a memory component according to the prior art.
- the cell array 1 includes a plurality of cell array strips 2 which are separated from one another by local data line strips 3 which are parallel to the cell array strips 2 and are adjacent on both sides.
- the cell array strips 2 essentially include a plurality of memory cells 7 .
- the local data line strips 3 have a plurality of local data lines 4 .
- the cell array 1 additionally has output amplifiers 6 to which a main data line 5 is in each case connected. This main data line 5 runs perpendicularly both to the cell array strips 2 and to the local data line strips 3 .
- a specific memory cell 7 If a specific memory cell 7 is to be accessed, then it must be activated. To that end, a plurality of word lines 11 are provided, which run parallel to the local data line strips 3 and within a specific cell array strip 2 . Furthermore, a plurality of column lines 12 are provided, which run parallel to the main data lines 5 and intersect the word lines 11 at crossover points 13 . Each memory cell 7 can be assigned to one of the crossover points 13 in an unambiguous manner. The activation of a crossover point 13 takes place through the activation of the corresponding word and column line 11 , 12 . If the crossover point 13 is activated, then the assigned memory cells 7 can be accessed.
- FIG. 5 shows a schematic illustration of the path covered by a bit when it is read from a memory component or written to a memory component.
- crossover point 13 i.e. precisely two word lines 11 and two column lines 12 .
- a memory component including:
- a cell array having a plurality of memory cells disposed in the cell array, the cell array being configured such that n bits are synchronously accessible in a synchronous memory access, n being an integer number;
- the switches being disposed such that a longest possible propagation time of a bit in given ones of the local data lines used for the synchronous memory access is shorter, the further away from associated ones of the output amplifiers the given ones of the local data lines are relative to further ones of the local data lines which are simultaneously required for the synchronous memory access.
- the object of the invention is achieved with a memory module having a plurality of memory cells disposed within a cell array, the cells are in each case connected via a bit line to a preamplifier and, from the latter, via a local data line and a main data line connected to the local data line by a switch, to an output amplifier, a number of n bits being accessed synchronously, wherein switches are disposed in such a way that the longest possible propagation time of a bit in the local data lines is shorter, the further away from the output amplifiers the local data lines are relative to the other local data lines which are simultaneously required in the event of a synchronous memory access.
- the main data lines are disposed perpendicular to the cell array strips.
- the cell array strips define an axis which is centrally centered with respect to the cell array strips and parallel to the main data lines; and in each case two of the switches which lie on a same one of the local data line strips are disposed at a substantially identical distance from the axis.
- the cell array is configured such that eight, sixteen, thirty-two or sixty-four bits are accessed in the synchronous memory access.
- the plurality of output amplifiers are eight, sixteen, thirty-two or sixty-four output amplifiers.
- Each bit stored in a memory cell traverses, once it has been activated, an individual path to an output amplifier assigned to the bit.
- This path is principally composed of a path portion covered by the bit on a local data line strip, and of a path portion covered by the bit on a main data line.
- This means that the individual paths of the individual bits have six different path lengths depending on the position of the memory cells, of the associated switches and thus of the associated output amplifiers.
- the propagation times of the individual bits from the memory cell as far as the output amplifier differ, therefore. Since, in the event of a synchronous memory access, the bits brought to an output of the memory component can only be conveyed further when all of the bits are present, the bit having the longest propagation time is crucial for the access time.
- the central idea of the invention is to configure the individual paths of the individual bits in such a way as to avoid individual paths having a long propagation time. For compensation, the path length of the individual paths having a short propagation time is increased. The largely equal distribution of the number of individual paths having short, medium and long propagation times is thus redistributed into a small number of individual paths having short and long propagation times and a high number of individual paths having a medium propagation time.
- FIG. 1 is a schematic plan view of an embodiment of the memory component according to the invention.
- FIG. 2 is a schematic plan view of an embodiment of a memory component according to the prior art
- FIG. 3 is a schematic plan view of the structure of a memory component according to the prior art
- FIG. 4 is a schematic view of a detail of FIG. 3 illustrating memory cells at two crossover points.
- FIG. 5 is a circuit diagram illustrating a path of a bit from a memory cell to an output amplifier.
- FIG. 1 there is shown a particularly preferred embodiment of a memory component according to the invention.
- This memory component is configured for a synchronous access to sixteen bits.
- two switches 10 which lie on an identical local data line strip 14 , 15 , 16 , 17 , 18 are at an identical distance 20 from an axis 19 of the memory component.
- a V-shaped configuration structure of the switches 10 is thus produced.
- This configuration structure may, for example, be repeated periodically with increasing distance from the output amplifiers 6 and can also be transferred to memory components having synchronous access to more or fewer than sixteen bits, for example thirty-two bits.
- the switches 10 which lie on the local data line strip 14 have the longest signal propagation time with respect to the main data line 5 , the maximum signal propagation distance 21 therefor must be kept as small as possible. This is achieved by the switches 10 being centered in the middle with respect to the cell array strips 2 on the local data line strips 14 . Maximum signal propagation distances 21 which are longer than half the length of a local data line strip, as shown for example in FIG. 2, are thus avoided. As a result, the maximum propagation time of a bit is reduced, which makes it possible to have a higher clock rate for the memory chip.
Landscapes
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- The invention relates to a memory component having a cell array with a plurality of memory cells configured such that a number of bits are synchronously accessible.
- In the case of memory components which are clocked synchronously, a specific number of stored bits are to be accessed simultaneously. As a rule, the number is eight, sixteen or thirty-two bits. In this context, “simultaneously” means that all bits which are to be read synchronously have to be brought to an output of the memory component within a predefined, fixed period of time, and from the output they are transferred further as an “information packet.” This period of time is typically in the range of nanoseconds.
- In an electronic data processing system, such as e.g. a computer, the maximum clock frequency is limited by that unit which requires the maximum time for performing a process step. Thus, no unit is allowed to require significantly more time than the rest of the units for performing a process step. This means, inter alia, that the access time to a desired number of bits in a memory chip must not exceed the time of one clock cycle. If this were the case, then an additional clock cycle would be required until the information packet were conveyed further, since the information packet waiting at the output of the memory chip can only be conveyed further clock cycle by clock cycle. The processing units which are coupled to the memory component and require this information packet in order to perform their work would each have their work interrupted for the length of one clock cycle.
- The access time required both when reading and when storing bits is thus a parameter whose value should be as small as possible.
- FIG. 3 shows a schematic structure of a cell array1 of a memory component according to the prior art. The cell array 1 includes a plurality of
cell array strips 2 which are separated from one another by localdata line strips 3 which are parallel to thecell array strips 2 and are adjacent on both sides. Thecell array strips 2 essentially include a plurality ofmemory cells 7. The localdata line strips 3 have a plurality oflocal data lines 4. The cell array 1 additionally hasoutput amplifiers 6 to which amain data line 5 is in each case connected. Thismain data line 5 runs perpendicularly both to thecell array strips 2 and to the localdata line strips 3. - If a
specific memory cell 7 is to be accessed, then it must be activated. To that end, a plurality ofword lines 11 are provided, which run parallel to the localdata line strips 3 and within a specificcell array strip 2. Furthermore, a plurality ofcolumn lines 12 are provided, which run parallel to themain data lines 5 and intersect theword lines 11 atcrossover points 13. Eachmemory cell 7 can be assigned to one of thecrossover points 13 in an unambiguous manner. The activation of acrossover point 13 takes place through the activation of the corresponding word andcolumn line crossover point 13 is activated, then the assignedmemory cells 7 can be accessed. - FIG. 5 shows a schematic illustration of the path covered by a bit when it is read from a memory component or written to a memory component. Once a bit stored in a
memory cell 7 has been activated via aword line 11 and a column line 12 (cf. FIG. 4) it is brought via abit line 8 to apreamplifier 9, which is provided on alocal data line 4 of a localdata line strip 3 and constitutes a connecting element between thebit line 8 and thelocal data line 4. The bit amplified by the preamplifier then passes via thelocal data line 4 to aswitch 10, which lies on amain data line 5 and constitutes a connecting element between thelocal data line 4 and themain data line 5. Thisswitch 10 forwards the signal via themain data line 5 to anoutput amplifier 6, which raises the signal to a desired output level and subsequently forwards it to an output of the memory chip. - In the case of Synchronous Dynamic Random Access Memory chips (SDRAMS) which synchronously access sixteen bits, it is customary to assign in each case four
memory cells 7 to a specific crossover point 13 (cf. FIG. 4). Thus, if acrossover point 13 is selected by way of the activation of thecorresponding word line 11 and/orcolumn line 12, then the associated fourmemory cells 7 are activated and the bits stored therein are brought via thebit line 8 to therespective preamplifiers 9, or bits to be stored are delivered via thepreamplifiers 9 to thememory cells 7. - Thus, four bits are read or written through the activation of a
specific crossover point 13. This means that in the event of an access to sixteen bits, precisely fourcrossover points 13, i.e. precisely twoword lines 11 and twocolumn lines 12, have to be activated. - In order to avoid data collisions on the bit lines and the local data lines, care must be taken, therefore, to ensure that two adjacent
cell array strips 2 or twoword lines 11 within the samecell array strip 2 are never activated simultaneously. This is indicated in FIG. 3 by the arrow brackets A and B, which each represent one of the possible combinations of activatedcell array strips 2. - It is accordingly an object of the invention to provide a memory component which overcomes the above-mentioned disadvantages of the heretofore-known memory components of this general type and which minimizes the access time to a desired number of bits in the event of a synchronous access.
- With the foregoing and other objects in view there is provided, in accordance with the invention, a memory component, including:
- a cell array having a plurality of memory cells disposed in the cell array, the cell array being configured such that n bits are synchronously accessible in a synchronous memory access, n being an integer number;
- a plurality of bit lines connected to respective ones of the memory cells;
- a plurality of preamplifiers connected to respective ones of the bit lines;
- a plurality of local data lines connected to respective ones of the preamplifiers;
- a plurality of switches connected to respective ones of the local data lines;
- a plurality of main data lines connected to respective ones of the switches;
- a plurality of output amplifiers connected to respective ones of the main data lines; and
- the switches being disposed such that a longest possible propagation time of a bit in given ones of the local data lines used for the synchronous memory access is shorter, the further away from associated ones of the output amplifiers the given ones of the local data lines are relative to further ones of the local data lines which are simultaneously required for the synchronous memory access.
- In other words, the object of the invention is achieved with a memory module having a plurality of memory cells disposed within a cell array, the cells are in each case connected via a bit line to a preamplifier and, from the latter, via a local data line and a main data line connected to the local data line by a switch, to an output amplifier, a number of n bits being accessed synchronously, wherein switches are disposed in such a way that the longest possible propagation time of a bit in the local data lines is shorter, the further away from the output amplifiers the local data lines are relative to the other local data lines which are simultaneously required in the event of a synchronous memory access.
- In accordance with another feature of the invention, the cell array is formed of a plurality of cell array strips; and local data line strips are disposed parallel to one another and adjacent on both sides of the cell array strips such that the cell array strips are separated from one another by the local data line strips.
- In accordance with yet another feature of the invention, the local data line strips include at least four of the local data lines.
- In accordance with a further feature of the invention, the main data lines are disposed perpendicular to the cell array strips.
- In accordance with another feature of the invention, the cell array strips define an axis which is centrally centered with respect to the cell array strips and parallel to the main data lines; and in each case two of the switches which lie on a same one of the local data line strips are disposed at a substantially identical distance from the axis.
- In accordance with another feature of the invention, the cell array is configured such that eight, sixteen, thirty-two or sixty-four bits are accessed in the synchronous memory access.
- In accordance with yet another feature of the invention, the plurality of output amplifiers are eight, sixteen, thirty-two or sixty-four output amplifiers.
- Each bit stored in a memory cell traverses, once it has been activated, an individual path to an output amplifier assigned to the bit. This path is principally composed of a path portion covered by the bit on a local data line strip, and of a path portion covered by the bit on a main data line. This means that the individual paths of the individual bits have six different path lengths depending on the position of the memory cells, of the associated switches and thus of the associated output amplifiers. The propagation times of the individual bits from the memory cell as far as the output amplifier differ, therefore. Since, in the event of a synchronous memory access, the bits brought to an output of the memory component can only be conveyed further when all of the bits are present, the bit having the longest propagation time is crucial for the access time.
- The central idea of the invention is to configure the individual paths of the individual bits in such a way as to avoid individual paths having a long propagation time. For compensation, the path length of the individual paths having a short propagation time is increased. The largely equal distribution of the number of individual paths having short, medium and long propagation times is thus redistributed into a small number of individual paths having short and long propagation times and a high number of individual paths having a medium propagation time.
- A further feature of the invention is that the configuration of the individual parts is preferably implemented by way of the configuration or placement of the switches on the local data line strips which are formed of local data lines. The length of the individual path covered by the bit on the local data line strip can be varied in a targeted manner by way of the position of the switches. In this case, the placement or positioning of the switches on a local data line strip which is farthest away from the output amplifiers relative to the other local data line strips which are simultaneously required for a synchronous memory access is configured in such a way that these switches lie as far as possible in the middle of the local data line strip. This makes it possible to avoid maximal signal propagation distances and thus maximal propagation times on the local data lines since at most half a length of the local data line strip then has to be traversed.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a memory component with short access time, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 is a schematic plan view of an embodiment of the memory component according to the invention;
- FIG. 2 is a schematic plan view of an embodiment of a memory component according to the prior art;
- FIG. 3 is a schematic plan view of the structure of a memory component according to the prior art;
- FIG. 4 is a schematic view of a detail of FIG. 3 illustrating memory cells at two crossover points; and
- FIG. 5 is a circuit diagram illustrating a path of a bit from a memory cell to an output amplifier.
- Referring now to the figures of the drawings in detail, in which same reference symbols are used for corresponding structural parts, and first, particularly, to FIG. 1 thereof, there is shown a particularly preferred embodiment of a memory component according to the invention. This memory component is configured for a synchronous access to sixteen bits. In each case two
switches 10 which lie on an identical localdata line strip identical distance 20 from anaxis 19 of the memory component. The further away from theoutput amplifiers 6 the local data line strips 14, 15, 16, 17, 18 are, the nearer to theaxis 19 are theouter switches 10 which lie on the local data line strips 14, 15, 16, 17, 18. A V-shaped configuration structure of theswitches 10 is thus produced. - This configuration structure may, for example, be repeated periodically with increasing distance from the
output amplifiers 6 and can also be transferred to memory components having synchronous access to more or fewer than sixteen bits, for example thirty-two bits. - Since the
switches 10 which lie on the localdata line strip 14 have the longest signal propagation time with respect to themain data line 5, the maximumsignal propagation distance 21 therefor must be kept as small as possible. This is achieved by theswitches 10 being centered in the middle with respect to the cell array strips 2 on the local data line strips 14. Maximum signal propagation distances 21 which are longer than half the length of a local data line strip, as shown for example in FIG. 2, are thus avoided. As a result, the maximum propagation time of a bit is reduced, which makes it possible to have a higher clock rate for the memory chip.
Claims (13)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10004109A DE10004109C2 (en) | 2000-01-31 | 2000-01-31 | Memory module with short access time |
DE10004109 | 2000-01-31 | ||
DE10004109.4 | 2000-01-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010038566A1 true US20010038566A1 (en) | 2001-11-08 |
US6388944B2 US6388944B2 (en) | 2002-05-14 |
Family
ID=7629300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/773,221 Expired - Lifetime US6388944B2 (en) | 2000-01-31 | 2001-01-31 | Memory component with short access time |
Country Status (6)
Country | Link |
---|---|
US (1) | US6388944B2 (en) |
EP (1) | EP1124231A1 (en) |
JP (1) | JP3957977B2 (en) |
KR (1) | KR100392317B1 (en) |
DE (1) | DE10004109C2 (en) |
TW (1) | TW502259B (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6711091B1 (en) | 2002-09-27 | 2004-03-23 | Infineon Technologies Ag | Indication of the system operation frequency to a DRAM during power-up |
US6809914B2 (en) | 2002-05-13 | 2004-10-26 | Infineon Technologies Ag | Use of DQ pins on a ram memory chip for a temperature sensing protocol |
US6873509B2 (en) | 2002-05-13 | 2005-03-29 | Infineon Technologies Ag | Use of an on-die temperature sensing scheme for thermal protection of DRAMS |
WO2005038811A1 (en) * | 2003-09-30 | 2005-04-28 | Infineon Technologies Ag | Memory arrangement comprising a plurality of ram modules |
US20050122832A1 (en) * | 2002-09-30 | 2005-06-09 | Infineon Technologies North America Corp. | On-die detection of the system operation frequency in a DRAM to adjust DRAM operations |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100873623B1 (en) | 2007-07-10 | 2008-12-12 | 주식회사 하이닉스반도체 | Semiconductor memory apparatus |
US20100146415A1 (en) * | 2007-07-12 | 2010-06-10 | Viasat, Inc. | Dns prefetch |
US8549099B2 (en) * | 2007-07-12 | 2013-10-01 | Viasat, Inc. | Methods and systems for javascript parsing |
US8171135B2 (en) * | 2007-07-12 | 2012-05-01 | Viasat, Inc. | Accumulator for prefetch abort |
US20100180005A1 (en) * | 2009-01-12 | 2010-07-15 | Viasat, Inc. | Cache cycling |
EP2511886B1 (en) * | 2009-12-31 | 2017-05-10 | Nautilus Hyosung Inc. | Automatic teller machine |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5636158A (en) * | 1995-03-13 | 1997-06-03 | Kabushiki Kaisha Toshiba | Irregular pitch layout for a semiconductor memory device |
JPH08263985A (en) * | 1995-03-24 | 1996-10-11 | Nec Corp | Semiconductor memory |
JPH1040682A (en) * | 1996-07-23 | 1998-02-13 | Mitsubishi Electric Corp | Semiconductor memory |
US5966315A (en) * | 1997-09-30 | 1999-10-12 | Siemens Aktiengesellschaft | Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines |
JP2000030447A (en) * | 1998-07-14 | 2000-01-28 | Mitsubishi Electric Corp | Semiconductor storage |
JP2000048566A (en) * | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
-
2000
- 2000-01-31 DE DE10004109A patent/DE10004109C2/en not_active Expired - Fee Related
-
2001
- 2001-01-16 EP EP01100894A patent/EP1124231A1/en not_active Withdrawn
- 2001-01-30 JP JP2001021717A patent/JP3957977B2/en not_active Expired - Fee Related
- 2001-01-30 TW TW090101790A patent/TW502259B/en not_active IP Right Cessation
- 2001-01-31 US US09/773,221 patent/US6388944B2/en not_active Expired - Lifetime
- 2001-01-31 KR KR10-2001-0004519A patent/KR100392317B1/en not_active IP Right Cessation
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6809914B2 (en) | 2002-05-13 | 2004-10-26 | Infineon Technologies Ag | Use of DQ pins on a ram memory chip for a temperature sensing protocol |
US6873509B2 (en) | 2002-05-13 | 2005-03-29 | Infineon Technologies Ag | Use of an on-die temperature sensing scheme for thermal protection of DRAMS |
US6711091B1 (en) | 2002-09-27 | 2004-03-23 | Infineon Technologies Ag | Indication of the system operation frequency to a DRAM during power-up |
US20050122832A1 (en) * | 2002-09-30 | 2005-06-09 | Infineon Technologies North America Corp. | On-die detection of the system operation frequency in a DRAM to adjust DRAM operations |
US6952378B2 (en) | 2002-09-30 | 2005-10-04 | Infineon Technologies Ag | Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations |
US6985400B2 (en) | 2002-09-30 | 2006-01-10 | Infineon Technologies Ag | On-die detection of the system operation frequency in a DRAM to adjust DRAM operations |
WO2005038811A1 (en) * | 2003-09-30 | 2005-04-28 | Infineon Technologies Ag | Memory arrangement comprising a plurality of ram modules |
US20060250881A1 (en) * | 2003-09-30 | 2006-11-09 | Helmut Kandolf | Memory arrangement having a plurality of RAM chips |
US7362650B2 (en) | 2003-09-30 | 2008-04-22 | Infineon Technologies Ag | Memory arrangement having a plurality of RAM chips |
Also Published As
Publication number | Publication date |
---|---|
US6388944B2 (en) | 2002-05-14 |
KR100392317B1 (en) | 2003-07-22 |
DE10004109C2 (en) | 2001-11-29 |
JP3957977B2 (en) | 2007-08-15 |
JP2001256780A (en) | 2001-09-21 |
EP1124231A1 (en) | 2001-08-16 |
DE10004109A1 (en) | 2001-08-09 |
TW502259B (en) | 2002-09-11 |
KR20010078194A (en) | 2001-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100220000B1 (en) | Memory module arranged for data and parity bits | |
US6762948B2 (en) | Semiconductor memory device having first and second memory architecture and memory system using the same | |
US6614700B2 (en) | Circuit configuration with a memory array | |
US20030103370A1 (en) | Ferroelectric memory device and method to sequentially link same | |
US6388944B2 (en) | Memory component with short access time | |
US6396766B1 (en) | Semiconductor memory architecture for minimizing input/output data paths | |
JP3185694B2 (en) | Semiconductor memory device having data bus line structure with increased bandwidth for high-speed burst read / write | |
US20040004897A1 (en) | Layout structures of data input/output pads and peripheral circuits of integrated circuit memory devices | |
WO2003007303A3 (en) | Memory device having different burst order addressing for read and write operations | |
US6470417B1 (en) | Emulation of next generation DRAM technology | |
US7430150B2 (en) | Method and system for providing sensing circuitry in a multi-bank memory device | |
KR20050022855A (en) | Multi-port memory device | |
US6678204B2 (en) | Semiconductor memory device with high-speed operation and methods of using and designing thereof | |
KR100303806B1 (en) | Multi-bank system semiconductor memory device capable of operating at high speed | |
US6359827B1 (en) | Method of constructing a very wide, very fast distributed memory | |
JP2003196996A (en) | System and method for testing column redundancy of integrated circuit memory | |
CN100392761C (en) | Semiconductor memory device | |
US6449210B1 (en) | Semiconductor memory array architecture | |
KR100515863B1 (en) | Semiconductor integrated circuit | |
US6628562B2 (en) | Method and apparatus for high-speed read operation in semiconductor memory | |
US6396763B1 (en) | DRAM having a reduced chip size | |
JP2973895B2 (en) | Semiconductor storage device | |
KR100380023B1 (en) | Semiconductor memory device for reducing size of chip of short side | |
KR100443355B1 (en) | Semiconductor memory device using commomn bus in normal mode and test mode | |
US7428182B1 (en) | Electronic circuit system, and signal transmission method, to improve signal transmission efficiency and simplify signal transmission management |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NORTHWESTERN UNIVERSITY, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JOISHA, PRAMOD G.;BANERJEE, PRITHVIRAJ;SHENOY, NAGARAJ;REEL/FRAME:011910/0476 Effective date: 20010129 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHROGMEIER, PETER;DIETRICH, STEFAN;PARTSCH, TORSTEN;AND OTHERS;SIGNING DATES FROM 20010316 TO 20010918;REEL/FRAME:024456/0406 |
|
AS | Assignment |
Owner name: QIMONDA AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:024626/0001 Effective date: 20060425 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
|
AS | Assignment |
Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036539/0196 Effective date: 20150708 |