US20010018221A1 - Method of manufacturing ferroelectric memory device - Google Patents
Method of manufacturing ferroelectric memory device Download PDFInfo
- Publication number
- US20010018221A1 US20010018221A1 US09/791,616 US79161601A US2001018221A1 US 20010018221 A1 US20010018221 A1 US 20010018221A1 US 79161601 A US79161601 A US 79161601A US 2001018221 A1 US2001018221 A1 US 2001018221A1
- Authority
- US
- United States
- Prior art keywords
- layer
- ferroelectric
- memory device
- gate structure
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000012535 impurity Substances 0.000 claims abstract description 50
- 238000000137 annealing Methods 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 257
- 239000007789 gas Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000012298 atmosphere Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 36
- 229910052710 silicon Inorganic materials 0.000 description 36
- 239000010703 silicon Substances 0.000 description 36
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000003213 activating effect Effects 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 9
- 230000008025 crystallization Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 230000010287 polarization Effects 0.000 description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 229910052801 chlorine Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000002349 favourable effect Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 4
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 229910000457 iridium oxide Inorganic materials 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- QDZRBIRIPNZRSG-UHFFFAOYSA-N titanium nitrate Chemical compound [O-][N+](=O)O[Ti](O[N+]([O-])=O)(O[N+]([O-])=O)O[N+]([O-])=O QDZRBIRIPNZRSG-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910020294 Pb(Zr,Ti)O3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Definitions
- the present invention relates to a method of manufacturing a ferroelectric memory device capable of nonvolatile data storage utilizing a polarization of a ferroelectric layer.
- a ferroelectric memory device is a nonvolatile memory device in which a ferroelectric layer is used.
- a ferroelectric layer is used.
- a polarization becomes complete in the ferroelectric layer, and the direction of the polarization is retained even after removing the electric field.
- FIG. 2 is a schematically sectional view showing the most basic structure of a ferroelectric memory element.
- a gate structure is formed, in which a ferroelectric layer 5 (F) and a metal layer 6 (M) as a gate electrode are stacked on the surface of a silicon substrate 1 (S).
- a pair of N-type diffused layers 2 , 2 serving as a source and a drain are formed with the gate structure interposed therebetween.
- a MIS transistor using a ferroelectric layer as an insulating layer is fabricated.
- the surface of the silicon substrate 1 between the N-type diffused layers 2 , 2 takes a state in which electrons are induced and a state in which holes are induced.
- the threshold value of a voltage to be applied to the metal layer 6 for making conductive the pair of the N-type diffused layers 2 , 2 changes between two kinds, namely, “high” and “low” in accordance with the direction of the polarization of the ferroelectric layer 5 . Therefore, binary data of “0” or “1” can be stored in a nonvolatile manner.
- FIG. 4 a structure of a ferroelectric memory element is shown in which a metal layer 4 (M) is interposed between the insulating layer 3 and the ferroelectric layer 5 to form a gate structure.
- M metal layer 4
- the alignment in the surface boundary between the insulating layer 3 and the ferroelectric layer 5 need not be considered, a satisfactorily crystallized insulating layer 3 can be formed on the silicon substrate 1 and at the same time, the ferroelectric layer 5 can be satisfactorily crystallized. Further, the metal layer 4 can prevent the diffusion of the ferroelectric material.
- both of the structures shown in FIGS. 3 and 4 have the following problem in the manufacturing process thereof.
- the pair of N-type diffused layers 2 , 2 serving as a source and a drain are formed by implanting N-type impurity ions in the silicon substrate 1 and thereafter activating the N-type impurities implanted in the surface of the silicon substrate 1 through activated annealing.
- the activated annealing comprises heating the silicon substrate 1 at a temperature of 900 to 950° C. in a furnace for 1 to 2 hours.
- the ferroelectric layer 5 is subjected to such a heat treatment, the polarization characteristics of the ferroelectric layer 5 are deteriorated.
- a process of fabricating a MFMIS structure shown in FIG. 4 is required to comprise steps of fabricating a MIS transistor section, then activating the pair of N-type impurity diffused layers 2 , 2 , and thereafter forming a capacitor section in which the ferroelectric layer is interposed between the metal layers 4 , 6 .
- FIG. 5 is a schematically sectional view for explaining a practical structural example of a ferroelectric memory element having the structure shown in FIG. 4.
- an insulating layer 3 and a metal layer 4 a are stacked on the surface of the silicon substrate 1 to form a MIS gate structure, and a pair of N-type diffused layers 2 , 2 are formed on both sides of the MIS gate structure respectively.
- a capacitor structure comprising a metal layer 4 b , a ferroelectric layer 5 and a metal layer 6 is formed in a different position from that of the MIS transistor.
- a connecting section 7 comprising wiring layers and plugs connects the metal layer 4 a of the MIS transistor and the metal layer 4 b on the capacitor side.
- a disadvantage of the structure shown in FIG. 5 is that since the transistor section and the capacitor section are formed in the separate regions, the area occupied by a memory cell on the silicon substrate 1 becomes large and high level integration is hard to attain.
- This disadvantage is somewhat decreased by adopting the structure shown in FIG. 6.
- a large-sized insulating layer 3 and a similarly large-sized metal layer 4 are stacked on a silicon substrate 1 to form a MIS structure, and thereafter, N-type impurities are implanted in the silicon substrate 1 and activated by annealing to form a pair of N-type diffused layers 2 , 2 in the surface layer section of the silicon substrate 1 .
- a ferroelectric layer 5 and a metal layer 6 are formed and stacked in order on the silicon substrate 1 .
- the area of the gate structure section in which the insulating layer 3 and the metal layer 4 are stacked is required to be larger than the area of the structure section in which the ferroelectric layer 5 and the metal layer 6 is stacked. This is so because it is necessary to secure a margin between a mask for patterning the gate structure section in which the insulating layer 3 and the metal layer 4 are stacked and a mask for patterning the structure section in which the ferroelectric layer 5 and the metal layer 6 are stacked.
- An object of the present invention is to provide a method of manufacturing a ferroelectric memory device capable of advantageously attaining high level integration.
- a method of manufacturing a ferroelectric memory device comprises steps of stacking a ferroelectric layer and a conductor layer on a semiconductor substrate in order, forming a gate structure section including the ferroelectric layer and the conductor layer by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into a pair of regions spaced apart from each other with the gate structure section interposed therebetween in a surface layer section of the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities so as to form a pair of impurity diffused layers in the pair of regions respectively.
- the gate structure section comprising the ferroelectric layer and the conductor layer is formed through a manufacturing process including the etching step using the common mask layer. And impurities are introduced into the semiconductor substrate in a self-aligning manner with respect to the gate structure section.
- a transistor comprising the gate structure section including the ferroelectric layer and the conductor layer, and the impurity diffused regions formed with the gate structure interposed therebetween can be formed in a small area.
- the impurities introduced into the semiconductor substrate are activated by annealing, whereby a pair of impurity defused layers are formed with the gate structure section interposed therebetween.
- the ferroelectric layer is crystallized at the same time.
- annealing for crystallizing the ferroelectric layer and annealing for activating the impurity ions are performed in a common step as abovementioned.
- the ferroelectric layer can be prevented from being deteriorated.
- the annealing of the semiconductor substrate can be completed only by once, heat damage to the semiconductor substrate can be reduced. Accordingly, the characteristics of the ferroelectric memory device can be improved.
- the manufacturing process can be simplified.
- An advantage of this invention is that the crystallization of the ferroelectric layer and the activation of the impurities are performed in a common annealing step.
- the ferroelectric layer and the conductor layer constituting the gate structure section can be patterned by etching using a common mask layer, and though the impurity diffused layers are formed in a self-aligning manner using the gate structure section formed as abovementioned, the characteristics of the ferroelectric layer can be prevented from being deteriorated.
- a method of manufacturing a ferroelectric memory device further comprises a step of forming an insulating layer on the semiconductor substrate before forming the ferroelectric layer.
- an insulating layer is interposed between the ferroelectric layer and the surface of the semiconductor substrate, and therefore, a gate structure section having a MFIS structure (see FIG. 3) can be formed.
- the method may further comprises a step of forming a different conductor layer after forming the insulating layer and before forming the ferroelectric layer, and this different conductor layer may be formed between the insulating layer and the ferroelectric layer.
- a gate structure section having so-called a MFMIS structure (see FIG. 4) can be formed.
- the annealing step for crystallizing the ferroelectric layer and activating the impurities preferably comprises lamp annealing.
- the characteristics of the ferroelectric layer can be prevented from being deteriorated, unlike a case of the conventional activated annealing performed in a furnace.
- the impurity diffused layers form a so-called shallow junction, the impurities implanted into the semiconductor substrate are sufficiently activated by a short time heat treatment such as lamp annealing, to form favorable impurity diffused layers.
- the time period and the temperature of the lamp annealing are preferably determined on the basis of the material constituting the ferroelectric layer and the distance between the pair of the impurity diffused layers. That is, the conditions for performing the lamp annealing are adequately determined on the basis of the material of the ferroelectric layer and the channel length, so that both of the crystallization of the ferroelectric layer and the activation of the impurities implanted into the semiconductor substrate can be satisfactorily performed at the same time in the common annealing step.
- FIGS. 1A to 1 D are sectional views showing steps of manufacturing a ferroelectric memory device according to an embodiment of the present invention in order.
- FIG. 2 is a schematically sectional view showing the structure of a MFS type ferroelectric memory element which is the most basic structure of a ferroelectric memory device.
- FIG. 3 is a schematically sectional view for explaining the structure of a ferroelectric memory element having a MFIS type gate structure.
- FIG. 4 is a schematically sectional view for explaining the structure of a ferroelectric memory element having a MFMIS type gate structure.
- FIG. 5 is a schematically sectional view showing an example of a conventional structure in which a transistor section and a capacitor section are formed in separate positions to fabricate substantially a MFMIS type ferroelectric memory element.
- FIG. 6 is a schematically sectional view showing an example of a conventional structure in which a capacitor section is stacked on a transistor section to fabricate a MFMIS type ferroelectric memory element.
- FIGS. 1A to 1 D are sectional views for explaining a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.
- a ferroelectric memory element having a gate structure of so-called MFMIS type is formed.
- a silicon oxide layer 12 as an insulating layer, a polysilicon layer 13 , a lower electrode layer 14 (a conductor layer), a ferroelectric layer 15 and an upper electrode layer 16 (another conductor layer) are stacked in this order and formed on a surface of a silicon substrate 11 (a semiconductor substrate).
- the silicon oxide layer 12 can be formed by heat-oxidizing the surface of the silicon substrate 11 .
- the polysilicon layer 13 can be formed by a reduced pressure CVD (chemical vapor deposition) method using silane gas and hydrogen gas as material gases.
- the polysilicon layer 13 is made to have a low resistance by introducing impurities such as phosphorus or the like therein.
- the lower electrode layer 14 and the upper electrode layer 16 are conductor layers made of metal and can be formed by sputtering.
- the lower electrode layer 14 is preferably formed of a material having a high barrier effect preventing diffusion of the ferroelectric material, and an iridium layer, an iridium oxide layer or a laminate layer consisting of an iridium layer and an iridium oxide layer, for example, can be applied.
- the upper electrode layer 16 can be formed of, for example, an iridium layer, an iridium oxide layer or a laminate layer consisting of an iridium layer and an iridium oxide layer.
- the lower electrode layer 16 and the upper electrode layer 14 can be formed of a platinum layer or a laminate layer consisting of a platinum layer and an iridium layer.
- the ferroelectric layer 15 is a layer formed of an ferroelectric material such as PZT (Pb(Zr,Ti)O 3 ), SBT (SrBi 2 Ta 2 O 9 ) or STN (Sr 2 (Ta,Nb) 2 O 7 ) and having a thickness of 1000 ⁇ to 2000 ⁇ , and it can be stacked on the surface of the lower electrode layer 14 using, for example, a sol-gel method, a sputter method, a MOCVD method (metal organic chemical vapor deposition), a laser abrasion method, a pulsed laser deposition method or the like. Immediately after stacked on the lower electrode 14 , the ferroelectric layer 15 has not been crystallized yet.
- PZT Pb(Zr,Ti)O 3
- SBT SrBi 2 Ta 2 O 9
- STN Sr 2 (Ta,Nb) 2 O 7
- a mask layer 18 for forming a gate structure section 20 is patterned on the surface of the upper electrode layer 16 .
- the mask layer 18 is preferably formed of a hard mask layer of, for example, silicon oxide, titanium nitrate, alumina or the like.
- the mask layer 18 in common, patterning of all the layers constituting the gate structure section 20 (except the silicon oxide layer 12 ) is performed by etching. That is, the upper electrode layer 16 , the ferroelectric layer 15 , the lower electrode layer 14 and the polysilicon layer 13 are etched by dry etching in this order. By changing over the gas used in etching each layer, the etching can be satisfactorily performed with ensuring the uniformity in the wafer surfaces.
- a gas including chlorine is used in etching the upper electrode layer 16 and the lower electrode layer 14
- a gas including fluorine is used in etching the ferroelectric layer 15
- a gas including HBr or a mixed gas including chlorine and fluorine is used in etching the polysilicon layer 13 .
- each layer By changing over the gas used in etching each layer as abovementioned, uniform etching can be performed in plural gate structures 20 formed in a wafer surface. Further, it is preferable to remove the residue at need after completing the etching of one layer or more than one layers.
- the polysilicon layer 13 can be etched with a gas including chlorine
- the upper electrode layer 16 and the lower electrode layer 14 are etched at the same time with the polysilicon layer 13 when a gas including chlorine is used.
- a gas including fluorine or a mixed gas including fluorine and chlorine it is preferable to use a gas including HBr in etching the polysilicon layer 13 .
- the etching of the polysilicon layer 13 using a gas including HBr enables to perform the patterning of the polysilicon layer 13 without giving damage to the silicon oxide layer 12 , because the etching selection ratio of the polysilicon layer 13 in relation to the silicon oxide layer 12 is large.
- the gate structure section 20 shown in FIG. 1B can be formed on the silicon substrate 11 . Since each layer is patterned using the common mask layer 18 to form the gate structure section 20 , it is not necessary to take a margin between plural masks into consideration. Accordingly, the gate structure section 20 can be formed on a small area.
- boron ions as N-type impurities are injected into the silicon substrate 11 in a self-aligning manner with respect to the gate structure section 20 .
- the N-type impurity ions injected into the outer layer of the silicon substrate 11 are shown with marks “X”.
- lamp annealing is performed.
- the N-type impurity ions injected into the outer layer of the silicon substrate 11 are activated, so that a pair of N-type impurity diffused layers 11 , 12 , which are spaced from each other with the gate structure section 20 therebetween, are formed as shown in FIG. 1D.
- heating for the crystallization of the ferroelectric layer 15 is also performed.
- Treating conditions used in the lamp annealing step are adequately determined in accordance with the channel length L of the gate structure section 20 , namely, the distance between the pair of the N-type impurity diffused layers 21 , 22 , and the kind of the ferroelectric material constituting the ferroelectric layer 15 .
- the channel length L is about 0.18 ⁇ m, that is, the design rule is about 0.18 ⁇ m and the ferroelectric layer 15 is formed of STN (its crystallization temperature: 900 to 1100° C.)
- the impurities injected into the surface layer section of the silicon substrate 11 can be satisfactorily activated and at the same time the ferroelectric layer 15 can be satisfactorily crystallized by performing the lamp annealing for about 1 second to a few seconds under a temperature of about 1050° C.
- the pair of N-type impurity diffused layers 21 , 22 form a so-called shallow junction, which can be completely activated by such a momentary heating treatment in a sense as abovementioned.
- PZT and SBT can be additionally exemplified. These materials have crystallization temperatures of about 550 to 800° C. and about 750 to 900° C., respectively.
- the temperature and the time period employed in the lamp annealing are preferably determined with taking such a crystallization temperature of the material of the ferroelectric layer 15 into consideration. However, when the temperature of the heat applied to the silicon substrate 11 in the annealing step is higher than the abovementioned crystallization temperature, the amount of the heat applied to the ferroelectric layer 15 is adjusted by shortening the time period of the lamp annealing step, so that the ferroelectric layer 15 can be satisfactorily crystallized.
- annealing for activating impurity ions injected into a semiconductor substrate is performed in a nitrogen atmosphere so as to prevent oxidization of the surface boundary.
- annealing for crystallizing a ferroelectric layer is generally performed in an oxygen atmosphere so as to prevent dissipation of oxygen from the ferroelectric layer. This is so because a ferroelectric material is generally formed of an oxide, and therefore its characteristics are degraded if oxygen is dissipated therefrom.
- the lamp annealing is performed, for example, in an oxygen atmosphere.
- the reason is that the surface of the silicon substrate 11 at the time of the annealing is covered with the silicon oxide layer 12 and therefore, it is not necessary to take oxidization of the surface of the silicon substrate 11 into consideration.
- the lamp annealing can be performed in an oxygen atmosphere in order to maintain the characteristics of the ferroelectric layer 15 .
- the lamp annealing can be performed in a nitrogen atmosphere.
- the lamp annealing can be performed in an atmosphere of a mixed gas consisting of nitrogen and oxygen.
- the silicon oxide layer 12 is damaged at the time of the ion injection. Accordingly, it is preferable to remove the silicon oxide layer 12 by wet etching after performing the annealing, and then to form a new silicon oxide layer 19 by oxidization of the surface of the silicon substrate 11 .
- the plural layers constituting the gate structure section 20 including the upper electrode layer 16 and the ferroelectric layer 15 are patterned using the common mask layer 18 , as abovementioned.
- the gate structure section 20 can be extremely minimized, unlike the abovementioned conventional art in which a transistor section and a capacitor section are formed in separate manufacturing processes (see FIGS. 5 and 6).
- a ferroelectric memory device of high level integration can be realized.
- the pair of N-type impurity diffused layers 21 , 22 are formed with a interposition of the gate structure section 20 therebetween.
- the transistor area can be also minimized by this, a ferroelectric memory device of high level integration can be realized.
- the heat treatment for both of activating the impurities and crystallizing the ferroelectric layer 14 is achieved by the common lamp annealing. Therefore, a ferroelectric layer 15 having favorable characteristics can be obtained, so that a ferroelectric memory device having excellent memory characteristics can be realized.
- the ferroelectric layer 15 is etched using the mask layer 18 and thereafter crystallized, the crystallization of the end face 15 a of the ferroelectric layer 15 is also satisfactory. Accordingly, current leakage from the edge portion of the ferroelectric layer 15 can be prevented. Thereby, the memory characteristics can be also improved.
- a ferroelectric memory device manufactured according to this embodiment has a feature that the end faces of the stacked layers constituting the gate structure section 20 are continuous.
- FIG. 3 An embodiment of the present invention has been described above, but the present invention can be embodied in another form.
- a method of manufacturing a ferroelectric memory device having gate structure sections of MFMIS type has been described in the abovementioned embodiment, but the present invention can be applied to a method of manufacturing a ferroelectric memory device having gate structure sections of MFS type shown in FIG. 2 or having gate structure sections of MFIS type as shown in FIG. 3.
- a metal layer and a ferroelectric layer are patterned using a common mask layer and a pair of impurity diffused layers are formed in a self-aligning manner with respect to the patterned and formed gate structure section.
- a ferroelectric memory device can be manufactured in which a pair of P-type impurity diffused layers are formed with the gate structure section 20 interposed therebetween to constitute a memory cell by a P-channel type transistor.
- arsenic ions for example, as the P-type impurity ions are injected into the silicon substrate 11 in the step shown in FIG. 1C.
- the gas is changed over in etching each of the layers constituting the gate structure section 20 .
- a gas including e.g. chlorine or HBr without changing over the gas.
Abstract
A method of manufacturing a ferroelectric memory device which has a gate structure constituted by a ferroelectric layer and a conductor layer stacked on a semiconductor substrate. The method includes steps of forming the gate structure section by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities thereby to form a pair of impurity diffused layers.
Description
- 1. Field of the Invention
- The present invention relates to a method of manufacturing a ferroelectric memory device capable of nonvolatile data storage utilizing a polarization of a ferroelectric layer.
- 2. Description of Related Arts
- A ferroelectric memory device is a nonvolatile memory device in which a ferroelectric layer is used. When an electric field is applied to a ferroelectric layer, a polarization becomes complete in the ferroelectric layer, and the direction of the polarization is retained even after removing the electric field. By utilizing this, nonvolatile data storage can be performed.
- FIG. 2 is a schematically sectional view showing the most basic structure of a ferroelectric memory element. A gate structure is formed, in which a ferroelectric layer5 (F) and a metal layer 6 (M) as a gate electrode are stacked on the surface of a silicon substrate 1 (S). A pair of N-type diffused
layers - By applying a voltage of, e.g. 5V between the
metal layer 6 and thesilicon substrate 1, an electric field oriented in a direction from themetal layer 6 toward thesilicon substrate 5 or from thesilicon substrate 5 toward themetal layer 6 is applied to theferroelectric layer 5. This forms, in theferroelectric layer 5, a polarization aligned with the direction of the applied electric field. The polarization is retained after removing the electric field applied between themetal layer 6 and thesilicon substrate 1. - As a result, the surface of the
silicon substrate 1 between the N-type diffusedlayers metal layer 6 for making conductive the pair of the N-type diffusedlayers ferroelectric layer 5. Therefore, binary data of “0” or “1” can be stored in a nonvolatile manner. - In the structure shown in FIG. 2, it is difficult to form a satisfactorily crystallized
ferroelectric layer 5 on thesilicon substrate 1. Further, this structure has another problem that the ferroelectric material is diffused in thesilicon substrate 1. Accordingly, it has been proposed that another insulating layer 3 (I) is interposed between thesilicon substrate 1 and theferroelectric layer 5 as shown in FIG. 3. - In the structure shown in FIG. 3, it is necessary to obtain a favorable alignment in the surface boundary between the
silicon substrate 1 and theinsulating layer 3 and at the same time obtain a favorable alignment between theinsulating layer 3 and theferroelectric layer 5. Therefore, this structure has a problem that the material of theinsulating layer 3 and the method for forming the same is strictly limited. Further, theinsulating layer 3 does not have a satisfactory barrier effect for preventing the diffusion of the ferroelectric material. - On the other hand, in FIG. 4, a structure of a ferroelectric memory element is shown in which a metal layer4 (M) is interposed between the
insulating layer 3 and theferroelectric layer 5 to form a gate structure. In this structure, since the alignment in the surface boundary between theinsulating layer 3 and theferroelectric layer 5 need not be considered, a satisfactorily crystallizedinsulating layer 3 can be formed on thesilicon substrate 1 and at the same time, theferroelectric layer 5 can be satisfactorily crystallized. Further, themetal layer 4 can prevent the diffusion of the ferroelectric material. - However, both of the structures shown in FIGS. 3 and 4 have the following problem in the manufacturing process thereof. The pair of N-type diffused
layers silicon substrate 1 and thereafter activating the N-type impurities implanted in the surface of thesilicon substrate 1 through activated annealing. The activated annealing comprises heating thesilicon substrate 1 at a temperature of 900 to 950° C. in a furnace for 1 to 2 hours. However, when theferroelectric layer 5 is subjected to such a heat treatment, the polarization characteristics of theferroelectric layer 5 are deteriorated. - In order to avoid this disadvantage, for example, a process of fabricating a MFMIS structure shown in FIG. 4 is required to comprise steps of fabricating a MIS transistor section, then activating the pair of N-type impurity diffused
layers metal layers - FIG. 5 is a schematically sectional view for explaining a practical structural example of a ferroelectric memory element having the structure shown in FIG. 4. In this ferroelectric memory element, an
insulating layer 3 and ametal layer 4 a are stacked on the surface of thesilicon substrate 1 to form a MIS gate structure, and a pair of N-type diffusedlayers metal layer 4 b, aferroelectric layer 5 and ametal layer 6 is formed in a different position from that of the MIS transistor. And a connectingsection 7 comprising wiring layers and plugs connects themetal layer 4 a of the MIS transistor and themetal layer 4 b on the capacitor side. - A disadvantage of the structure shown in FIG. 5 is that since the transistor section and the capacitor section are formed in the separate regions, the area occupied by a memory cell on the
silicon substrate 1 becomes large and high level integration is hard to attain. - This disadvantage is somewhat decreased by adopting the structure shown in FIG. 6. In the structure shown in FIG. 6, a large-sized
insulating layer 3 and a similarly large-sized metal layer 4 are stacked on asilicon substrate 1 to form a MIS structure, and thereafter, N-type impurities are implanted in thesilicon substrate 1 and activated by annealing to form a pair of N-type diffusedlayers silicon substrate 1. Then, aferroelectric layer 5 and ametal layer 6 are formed and stacked in order on thesilicon substrate 1. - When this structure is adopted, the area of the gate structure section in which the
insulating layer 3 and themetal layer 4 are stacked is required to be larger than the area of the structure section in which theferroelectric layer 5 and themetal layer 6 is stacked. This is so because it is necessary to secure a margin between a mask for patterning the gate structure section in which theinsulating layer 3 and themetal layer 4 are stacked and a mask for patterning the structure section in which theferroelectric layer 5 and themetal layer 6 are stacked. - Thus, when the structure shown in FIG. 6 is adopted, a large-sized area of gate structure section is also required. Therefore, in this case, the attainment of high level integration is limited
- An object of the present invention is to provide a method of manufacturing a ferroelectric memory device capable of advantageously attaining high level integration.
- A method of manufacturing a ferroelectric memory device according to the present invention comprises steps of stacking a ferroelectric layer and a conductor layer on a semiconductor substrate in order, forming a gate structure section including the ferroelectric layer and the conductor layer by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into a pair of regions spaced apart from each other with the gate structure section interposed therebetween in a surface layer section of the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities so as to form a pair of impurity diffused layers in the pair of regions respectively.
- According to the present invention, the gate structure section comprising the ferroelectric layer and the conductor layer is formed through a manufacturing process including the etching step using the common mask layer. And impurities are introduced into the semiconductor substrate in a self-aligning manner with respect to the gate structure section.
- Accordingly, a transistor comprising the gate structure section including the ferroelectric layer and the conductor layer, and the impurity diffused regions formed with the gate structure interposed therebetween can be formed in a small area.
- The impurities introduced into the semiconductor substrate are activated by annealing, whereby a pair of impurity defused layers are formed with the gate structure section interposed therebetween. In this annealing step, the ferroelectric layer is crystallized at the same time.
- According to the present invention, annealing for crystallizing the ferroelectric layer and annealing for activating the impurity ions are performed in a common step as abovementioned. As a result, the ferroelectric layer can be prevented from being deteriorated. Further, since the annealing of the semiconductor substrate can be completed only by once, heat damage to the semiconductor substrate can be reduced. Accordingly, the characteristics of the ferroelectric memory device can be improved. In addition, the manufacturing process can be simplified.
- An advantage of this invention is that the crystallization of the ferroelectric layer and the activation of the impurities are performed in a common annealing step. By adopting such a step, the ferroelectric layer and the conductor layer constituting the gate structure section can be patterned by etching using a common mask layer, and though the impurity diffused layers are formed in a self-aligning manner using the gate structure section formed as abovementioned, the characteristics of the ferroelectric layer can be prevented from being deteriorated.
- It is preferable that a method of manufacturing a ferroelectric memory device according to the present invention further comprises a step of forming an insulating layer on the semiconductor substrate before forming the ferroelectric layer.
- According to this method, an insulating layer is interposed between the ferroelectric layer and the surface of the semiconductor substrate, and therefore, a gate structure section having a MFIS structure (see FIG. 3) can be formed.
- Further, the method may further comprises a step of forming a different conductor layer after forming the insulating layer and before forming the ferroelectric layer, and this different conductor layer may be formed between the insulating layer and the ferroelectric layer.
- According to this method, a gate structure section having so-called a MFMIS structure (see FIG. 4) can be formed. In this case, it is preferable to pattern the pair of conductor layers and the ferroelectric layer interposed therebetween using the common mask layer.
- The annealing step for crystallizing the ferroelectric layer and activating the impurities preferably comprises lamp annealing. Thereby, the characteristics of the ferroelectric layer can be prevented from being deteriorated, unlike a case of the conventional activated annealing performed in a furnace. When the impurity diffused layers form a so-called shallow junction, the impurities implanted into the semiconductor substrate are sufficiently activated by a short time heat treatment such as lamp annealing, to form favorable impurity diffused layers.
- The time period and the temperature of the lamp annealing are preferably determined on the basis of the material constituting the ferroelectric layer and the distance between the pair of the impurity diffused layers. That is, the conditions for performing the lamp annealing are adequately determined on the basis of the material of the ferroelectric layer and the channel length, so that both of the crystallization of the ferroelectric layer and the activation of the impurities implanted into the semiconductor substrate can be satisfactorily performed at the same time in the common annealing step.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention given with reference to the accompanying drawings.
- FIGS. 1A to1D are sectional views showing steps of manufacturing a ferroelectric memory device according to an embodiment of the present invention in order.
- FIG. 2 is a schematically sectional view showing the structure of a MFS type ferroelectric memory element which is the most basic structure of a ferroelectric memory device.
- FIG. 3 is a schematically sectional view for explaining the structure of a ferroelectric memory element having a MFIS type gate structure.
- FIG. 4 is a schematically sectional view for explaining the structure of a ferroelectric memory element having a MFMIS type gate structure.
- FIG. 5 is a schematically sectional view showing an example of a conventional structure in which a transistor section and a capacitor section are formed in separate positions to fabricate substantially a MFMIS type ferroelectric memory element.
- FIG. 6 is a schematically sectional view showing an example of a conventional structure in which a capacitor section is stacked on a transistor section to fabricate a MFMIS type ferroelectric memory element.
- FIGS. 1A to1D are sectional views for explaining a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention. In this manufacturing process, a ferroelectric memory element having a gate structure of so-called MFMIS type is formed.
- Firstly, as shown in FIG. 1A, a
silicon oxide layer 12 as an insulating layer, apolysilicon layer 13, a lower electrode layer 14 (a conductor layer), aferroelectric layer 15 and an upper electrode layer 16 (another conductor layer) are stacked in this order and formed on a surface of a silicon substrate 11 (a semiconductor substrate). - The
silicon oxide layer 12 can be formed by heat-oxidizing the surface of thesilicon substrate 11. Thepolysilicon layer 13 can be formed by a reduced pressure CVD (chemical vapor deposition) method using silane gas and hydrogen gas as material gases. Thepolysilicon layer 13 is made to have a low resistance by introducing impurities such as phosphorus or the like therein. - The
lower electrode layer 14 and theupper electrode layer 16 are conductor layers made of metal and can be formed by sputtering. Thelower electrode layer 14 is preferably formed of a material having a high barrier effect preventing diffusion of the ferroelectric material, and an iridium layer, an iridium oxide layer or a laminate layer consisting of an iridium layer and an iridium oxide layer, for example, can be applied. Similarly, theupper electrode layer 16 can be formed of, for example, an iridium layer, an iridium oxide layer or a laminate layer consisting of an iridium layer and an iridium oxide layer. In addition, thelower electrode layer 16 and theupper electrode layer 14 can be formed of a platinum layer or a laminate layer consisting of a platinum layer and an iridium layer. - The
ferroelectric layer 15 is a layer formed of an ferroelectric material such as PZT (Pb(Zr,Ti)O3), SBT (SrBi2Ta2O9) or STN (Sr2(Ta,Nb)2O7) and having a thickness of 1000 Å to 2000 Å, and it can be stacked on the surface of thelower electrode layer 14 using, for example, a sol-gel method, a sputter method, a MOCVD method (metal organic chemical vapor deposition), a laser abrasion method, a pulsed laser deposition method or the like. Immediately after stacked on thelower electrode 14, theferroelectric layer 15 has not been crystallized yet. Then, as shown in FIG. 1B, amask layer 18 for forming agate structure section 20 is patterned on the surface of theupper electrode layer 16. Themask layer 18 is preferably formed of a hard mask layer of, for example, silicon oxide, titanium nitrate, alumina or the like. - Using the
mask layer 18 in common, patterning of all the layers constituting the gate structure section 20 (except the silicon oxide layer 12) is performed by etching. That is, theupper electrode layer 16, theferroelectric layer 15, thelower electrode layer 14 and thepolysilicon layer 13 are etched by dry etching in this order. By changing over the gas used in etching each layer, the etching can be satisfactorily performed with ensuring the uniformity in the wafer surfaces. For example, a gas including chlorine is used in etching theupper electrode layer 16 and thelower electrode layer 14, and a gas including fluorine is used in etching theferroelectric layer 15, while a gas including HBr or a mixed gas including chlorine and fluorine is used in etching thepolysilicon layer 13. - By changing over the gas used in etching each layer as abovementioned, uniform etching can be performed in
plural gate structures 20 formed in a wafer surface. Further, it is preferable to remove the residue at need after completing the etching of one layer or more than one layers. - Though the
polysilicon layer 13 can be etched with a gas including chlorine, theupper electrode layer 16 and thelower electrode layer 14 are etched at the same time with thepolysilicon layer 13 when a gas including chlorine is used. Accordingly, it is preferable to use a gas including fluorine or a mixed gas including fluorine and chlorine. Further, it is more preferable to use a gas including HBr in etching thepolysilicon layer 13. The etching of thepolysilicon layer 13 using a gas including HBr enables to perform the patterning of thepolysilicon layer 13 without giving damage to thesilicon oxide layer 12, because the etching selection ratio of thepolysilicon layer 13 in relation to thesilicon oxide layer 12 is large. - By etching the
upper electrode layer 16,ferroelectric layer 15, thelower electrode layer 14 and thepolysilicon layer 13 in order using themask layer 18 in common as abovementioned, thegate structure section 20 shown in FIG. 1B can be formed on thesilicon substrate 11. Since each layer is patterned using thecommon mask layer 18 to form thegate structure section 20, it is not necessary to take a margin between plural masks into consideration. Accordingly, thegate structure section 20 can be formed on a small area. - Then, as shown in FIG. 1C, after removing the mask layer28 at need, boron ions as N-type impurities, for example, are injected into the
silicon substrate 11 in a self-aligning manner with respect to thegate structure section 20. In FIG. 1c, the N-type impurity ions injected into the outer layer of thesilicon substrate 11 are shown with marks “X”. - Thereafter, lamp annealing is performed. By this lamp annealing, the N-type impurity ions injected into the outer layer of the
silicon substrate 11 are activated, so that a pair of N-type impurity diffused layers 11, 12, which are spaced from each other with thegate structure section 20 therebetween, are formed as shown in FIG. 1D. At the same time with this, heating for the crystallization of theferroelectric layer 15 is also performed. - Treating conditions used in the lamp annealing step are adequately determined in accordance with the channel length L of the
gate structure section 20, namely, the distance between the pair of the N-type impurity diffused layers 21, 22, and the kind of the ferroelectric material constituting theferroelectric layer 15. For example, when the channel length L is about 0.18 μm, that is, the design rule is about 0.18 μm and theferroelectric layer 15 is formed of STN (its crystallization temperature: 900 to 1100° C.), the impurities injected into the surface layer section of thesilicon substrate 11 can be satisfactorily activated and at the same time theferroelectric layer 15 can be satisfactorily crystallized by performing the lamp annealing for about 1 second to a few seconds under a temperature of about 1050° C. When a minutegate structure section 20 having a channel length of about 0.18 μm is formed, the pair of N-type impurity diffused layers 21, 22 form a so-called shallow junction, which can be completely activated by such a momentary heating treatment in a sense as abovementioned. - As a material of the
ferroelectric layer 15, PZT and SBT can be additionally exemplified. These materials have crystallization temperatures of about 550 to 800° C. and about 750 to 900° C., respectively. The temperature and the time period employed in the lamp annealing are preferably determined with taking such a crystallization temperature of the material of theferroelectric layer 15 into consideration. However, when the temperature of the heat applied to thesilicon substrate 11 in the annealing step is higher than the abovementioned crystallization temperature, the amount of the heat applied to theferroelectric layer 15 is adjusted by shortening the time period of the lamp annealing step, so that theferroelectric layer 15 can be satisfactorily crystallized. - The atmosphere in which the lamp annealing is performed will be described here. Generally, activated annealing for activating impurity ions injected into a semiconductor substrate is performed in a nitrogen atmosphere so as to prevent oxidization of the surface boundary. On the other hand, annealing for crystallizing a ferroelectric layer is generally performed in an oxygen atmosphere so as to prevent dissipation of oxygen from the ferroelectric layer. This is so because a ferroelectric material is generally formed of an oxide, and therefore its characteristics are degraded if oxygen is dissipated therefrom.
- In this embodiment, the lamp annealing is performed, for example, in an oxygen atmosphere. The reason is that the surface of the
silicon substrate 11 at the time of the annealing is covered with thesilicon oxide layer 12 and therefore, it is not necessary to take oxidization of the surface of thesilicon substrate 11 into consideration. In addition, since only an extremely short time heat treatment is performed in the annealing, unlike a heat treatment in a furnace, it is not necessary to take oxidization by heat into consideration. - It is preferable to perform the lamp annealing in an oxygen atmosphere in order to maintain the characteristics of the
ferroelectric layer 15. However, when theferroelectric layer 15 abundantly includes oxygen from the beginning, the lamp annealing can be performed in a nitrogen atmosphere. Further, the lamp annealing can be performed in an atmosphere of a mixed gas consisting of nitrogen and oxygen. - The
silicon oxide layer 12 is damaged at the time of the ion injection. Accordingly, it is preferable to remove thesilicon oxide layer 12 by wet etching after performing the annealing, and then to form a newsilicon oxide layer 19 by oxidization of the surface of thesilicon substrate 11. - According to the method of manufacturing ferroelectric memory device of this embodiment, the plural layers constituting the
gate structure section 20 including theupper electrode layer 16 and theferroelectric layer 15 are patterned using thecommon mask layer 18, as abovementioned. Thereby thegate structure section 20 can be extremely minimized, unlike the abovementioned conventional art in which a transistor section and a capacitor section are formed in separate manufacturing processes (see FIGS. 5 and 6). As a result, a ferroelectric memory device of high level integration can be realized. - Further, by implanting N-type impurity ions in the
silicon substrate 11 in a self-aligning manner with respect to thegate structure 20 and then activating the same through lamp annealing, the pair of N-type impurity diffused layers 21, 22 are formed with a interposition of thegate structure section 20 therebetween. The transistor area can be also minimized by this, a ferroelectric memory device of high level integration can be realized. - Further, according to the method of this embodiment, instead of activating the impurities injected into the
silicon substrate 11 after crystallizing theferroelectric layer 15, the heat treatment for both of activating the impurities and crystallizing theferroelectric layer 14 is achieved by the common lamp annealing. Therefore, aferroelectric layer 15 having favorable characteristics can be obtained, so that a ferroelectric memory device having excellent memory characteristics can be realized. In addition, since theferroelectric layer 15 is etched using themask layer 18 and thereafter crystallized, the crystallization of the end face 15 a of theferroelectric layer 15 is also satisfactory. Accordingly, current leakage from the edge portion of theferroelectric layer 15 can be prevented. Thereby, the memory characteristics can be also improved. - Further, since the heat treatment for activating the impurities injected into the
silicon substrate 11 and the heat treatment for crystallizing theferroelectric layer 15 are performed in a step, the manufacturing process is simplified and heat damage given to thesilicon substrate 11 is reduced. Thereby, the operation characteristics of the ferroelectric memory device can be also improved. - A ferroelectric memory device manufactured according to this embodiment has a feature that the end faces of the stacked layers constituting the
gate structure section 20 are continuous. On the other hand, according to the conventional method described above with reference to FIG. 5 or FIG. 6, it is impossible to manufacture a ferroelectric memory device provided with gate structure sections each including a ferroelectric layer and having straight end faces. That is, according to methods for manufacturing a ferroelectric memory device ever known, it is impossible to form thegate structure section 20 having continuous end faces (side faces) and satisfactorily maintain the characteristics of theferroelectric layer 15, unlike the abovementioned embodiment. - An embodiment of the present invention has been described above, but the present invention can be embodied in another form. For example, a method of manufacturing a ferroelectric memory device having gate structure sections of MFMIS type has been described in the abovementioned embodiment, but the present invention can be applied to a method of manufacturing a ferroelectric memory device having gate structure sections of MFS type shown in FIG. 2 or having gate structure sections of MFIS type as shown in FIG. 3. In either of these cases, it is preferable that a metal layer and a ferroelectric layer are patterned using a common mask layer and a pair of impurity diffused layers are formed in a self-aligning manner with respect to the patterned and formed gate structure section. Further, it is preferable to perform the activation of the impurity diffused layers and the crystallization of the ferroelectric layer in a common step of adequate annealing such as lamp annealing.
- Whichever structure is adopted as a gate structure section, at least a metal layer and a ferroelectric layer patterned using a common mask layer have continuous end faces.
- Further, though a pair of N-type impurity diffused layers are formed with the
gate structure section 20 interposed therebetween in the abovementioned embodiment, a ferroelectric memory device can be manufactured in which a pair of P-type impurity diffused layers are formed with thegate structure section 20 interposed therebetween to constitute a memory cell by a P-channel type transistor. In this case, arsenic ions, for example, as the P-type impurity ions are injected into thesilicon substrate 11 in the step shown in FIG. 1C. - Further, in the abovementioned embodiment, the gas is changed over in etching each of the layers constituting the
gate structure section 20. However, if the etching uniformity in a wafer surface is favorable, all of the layers constituting thegate structure section 20 can be etched using a gas including e.g. chlorine or HBr without changing over the gas. - Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
- This application corresponds to the Japanese Patent Application No. 2000-47782 filed in the Japanese Patent Office on Feb. 24, 2000, the entire disclosure of which is incorporated herein by reference.
Claims (10)
1. A method of manufacturing a ferroelectric memory device comprising the steps of:
stacking a ferroelectric layer and a conductor layer on a semiconductor substrate in order,
forming a gate structure section including the ferroelectric layer and the conductor layer by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer,
introducing impurities into a pair of regions spaced apart from each other with the gate structure section interposed therebetween in a surface layer section of the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and
annealing simultaneously both of the ferroelectric layer and the impurities introduced into the semiconductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities, thereby to form a pair of impurity diffused layers in the pair of regions respectively.
2. A method of manufacturing a ferroelectric memory device as claimed in , further comprising a step of forming an insulating layer on the semiconductor substrate before forming the ferroelectric layer, the gate structure section being formed on the insulating layer.
claim 1
3. A method of manufacturing a ferroelectric memory device as claimed in , further comprising a step of forming a different conductor layer after forming the insulating layer and before forming the ferroelectric layer, to interpose the different conductor layer between the insulating layer and the ferroelectric layer.
claim 2
4. A method of manufacturing a ferroelectric memory device as claimed in , in which the different conductor layer is patterned using the common mask layer to constitute the gate structure section.
claim 3
5. A method of manufacturing a ferroelectric memory device as claimed in , in which the annealing includes lamp annealing.
claim 1
6. A method of manufacturing a ferroelectric memory device as claimed in , in which the time period and the temperature of the lamp annealing are determined on the basis of the material constituting the ferroelectric layer and the distance between the pair of the impurity diffused layers.
claim 5
7. A method of manufacturing a ferroelectric memory device as claimed in , in which the impurity diffused layers form a shallow junction.
claim 5
8. A method of manufacturing a ferroelectric memory device as claimed in , in which the lamp annealing is performed in an oxygen atmosphere.
claim 5
9. A method of manufacturing a ferroelectric memory device as claimed in , in which the lamp annealing is performed in a nitrogen atmosphere.
claim 5
10. A method of manufacturing a ferroelectric memory device as claimed in , in which the lamp annealing is performed in an atmosphere of a mixed gas of nitrogen and oxygen.
claim 5
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/108,381 US20020098599A1 (en) | 2000-02-24 | 2002-03-29 | Method of manufacturing ferroelectric memory device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000047782A JP4303389B2 (en) | 2000-02-24 | 2000-02-24 | Method for manufacturing ferroelectric memory device |
JP2000-047782 | 2000-02-24 | ||
JP2000-47782 | 2000-02-24 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/108,381 Division US20020098599A1 (en) | 2000-02-24 | 2002-03-29 | Method of manufacturing ferroelectric memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010018221A1 true US20010018221A1 (en) | 2001-08-30 |
US6387762B2 US6387762B2 (en) | 2002-05-14 |
Family
ID=18569976
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/791,616 Expired - Lifetime US6387762B2 (en) | 2000-02-24 | 2001-02-26 | Method of manufacturing ferroelectric memory device |
US10/108,381 Abandoned US20020098599A1 (en) | 2000-02-24 | 2002-03-29 | Method of manufacturing ferroelectric memory device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/108,381 Abandoned US20020098599A1 (en) | 2000-02-24 | 2002-03-29 | Method of manufacturing ferroelectric memory device |
Country Status (2)
Country | Link |
---|---|
US (2) | US6387762B2 (en) |
JP (1) | JP4303389B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1302978A2 (en) * | 2001-10-16 | 2003-04-16 | Sharp Kabushiki Kaisha | Method of making a self-aligned ferroelectric memory transistor |
US6737282B2 (en) * | 2001-09-06 | 2004-05-18 | Industrial Technology Research Institute | Method for producing a single integrated device containing a plurality of passive elements |
US20170309322A1 (en) * | 2016-04-20 | 2017-10-26 | Micron Technology, Inc. | Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays |
US10861862B1 (en) * | 2019-06-24 | 2020-12-08 | Wuxi Petabyte Technologies Co, Ltd. | Ferroelectric memory devices |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4803845B2 (en) * | 2002-08-20 | 2011-10-26 | 独立行政法人産業技術総合研究所 | Manufacturing method of semiconductor ferroelectric memory device |
US6943039B2 (en) * | 2003-02-11 | 2005-09-13 | Applied Materials Inc. | Method of etching ferroelectric layers |
JP2008078417A (en) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | Semiconductor memory device and manufacturing method thereof |
US8564063B2 (en) | 2010-12-07 | 2013-10-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
CN105047670B (en) * | 2015-06-29 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | The manufacture method of SONOS devices |
CN105762178A (en) * | 2016-03-04 | 2016-07-13 | 西安电子科技大学 | Ferroelectric field effect transistor based on GeSn material, and preparation method for ferroelectric field effect transistor |
CN105633169A (en) * | 2016-03-04 | 2016-06-01 | 西安电子科技大学 | Ferro-electric field effect transistor based on InAs material and preparation method of ferro-electric field effect transistor |
JP6751866B2 (en) * | 2016-04-22 | 2020-09-09 | 国立研究開発法人産業技術総合研究所 | Manufacturing method of semiconductor ferroelectric storage element and semiconductor ferroelectric storage transistor |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2788265B2 (en) * | 1988-07-08 | 1998-08-20 | オリンパス光学工業株式会社 | Ferroelectric memory, driving method and manufacturing method thereof |
JP3264506B2 (en) * | 1991-11-18 | 2002-03-11 | ローム株式会社 | Ferroelectric nonvolatile memory device |
JP3369827B2 (en) * | 1995-01-30 | 2003-01-20 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
DE69730377T2 (en) * | 1996-05-30 | 2005-09-01 | Oki Electric Industry Co., Ltd. | Permanent semiconductor memory cell and its manufacturing method |
JPH10223845A (en) * | 1996-12-05 | 1998-08-21 | Sanyo Electric Co Ltd | Manufacture of dielectric element |
US6287637B1 (en) * | 1997-07-18 | 2001-09-11 | Ramtron International Corporation | Multi-layer approach for optimizing ferroelectric film performance |
JP2000349245A (en) * | 1999-06-02 | 2000-12-15 | Sony Corp | Dielectric capacitor, memory and manufacture of the same |
JP4445091B2 (en) * | 2000-04-07 | 2010-04-07 | 康夫 垂井 | Ferroelectric memory element |
-
2000
- 2000-02-24 JP JP2000047782A patent/JP4303389B2/en not_active Expired - Lifetime
-
2001
- 2001-02-26 US US09/791,616 patent/US6387762B2/en not_active Expired - Lifetime
-
2002
- 2002-03-29 US US10/108,381 patent/US20020098599A1/en not_active Abandoned
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6737282B2 (en) * | 2001-09-06 | 2004-05-18 | Industrial Technology Research Institute | Method for producing a single integrated device containing a plurality of passive elements |
EP1302978A2 (en) * | 2001-10-16 | 2003-04-16 | Sharp Kabushiki Kaisha | Method of making a self-aligned ferroelectric memory transistor |
EP1302978A3 (en) * | 2001-10-16 | 2008-01-09 | Sharp Kabushiki Kaisha | Method of making a self-aligned ferroelectric memory transistor |
US20170309322A1 (en) * | 2016-04-20 | 2017-10-26 | Micron Technology, Inc. | Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays |
US10636471B2 (en) * | 2016-04-20 | 2020-04-28 | Micron Technology, Inc. | Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays |
US11276449B2 (en) | 2016-04-20 | 2022-03-15 | Micron Technology, Inc. | Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays |
US11955156B2 (en) | 2016-04-20 | 2024-04-09 | Micron Technology, Inc. | Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays |
US10861862B1 (en) * | 2019-06-24 | 2020-12-08 | Wuxi Petabyte Technologies Co, Ltd. | Ferroelectric memory devices |
US20200402986A1 (en) * | 2019-06-24 | 2020-12-24 | Wuxi Petabyte Technologies Co., Ltd. | Ferroelectric memory devices |
Also Published As
Publication number | Publication date |
---|---|
JP4303389B2 (en) | 2009-07-29 |
US20020098599A1 (en) | 2002-07-25 |
JP2001237390A (en) | 2001-08-31 |
US6387762B2 (en) | 2002-05-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5424238A (en) | Method for producing a semiconductor device having a ferroelectric storage cell | |
KR100522211B1 (en) | Semiconductor device and method of fabricating the same | |
US6645779B2 (en) | FeRAM (ferroelectric random access memory) and method for forming the same | |
US7667252B2 (en) | Semiconductor nonvolatile storage element and method of fabricating the same | |
US20130178038A1 (en) | Semiconductor device and method of manufacturing the same | |
US20090224301A1 (en) | Semiconductor memory device and method of manufacturing thereof | |
US6387762B2 (en) | Method of manufacturing ferroelectric memory device | |
KR20000035211A (en) | Ferroelectric nonvolatile transistor and method of making same | |
US5460992A (en) | Fabricating non-volatile memory device having a multi-layered gate electrode | |
JP4522088B2 (en) | Manufacturing method of semiconductor device | |
US6906367B2 (en) | Semiconductor device and method of fabricating the same | |
KR100405146B1 (en) | Process for producing a structured metal oxide-containing layer | |
US6750501B2 (en) | Transistor type ferroelectric body nonvolatile storage element | |
US6908867B2 (en) | Method of manufacturing a FeRAM with annealing process | |
KR0155866B1 (en) | Ferroelectric memory device and its manufacturing method | |
KR19990084635A (en) | Ferroelectric Transistor Memory Devices | |
US6784057B2 (en) | Semiconductor device and nonvolatile semiconductor memory device comprising a plurality of semiconductor elements as well as process for the same | |
US6455329B1 (en) | Method for fabricating a capacitor in a semiconductor device | |
KR20030074438A (en) | Method for fabricating capacitor | |
KR20020066966A (en) | Method of fabricating ferroelectric memory transistors | |
US20010023951A1 (en) | Method of manufacturing a ferroelectric capacitor | |
KR20020079380A (en) | Non-volatile semiconductor memory device and method for producing the same | |
JPH02288368A (en) | Manufacture of semiconductor device | |
KR100465832B1 (en) | Ferroelectric Random Access Memory and fabricating method of the same | |
KR20010061110A (en) | Method for manufacturing non-volatile ferroelectric memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ROHM CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAKASU, HIDEMI;NAKAMURA, TAKASHI;REEL/FRAME:011909/0526;SIGNING DATES FROM 20010219 TO 20010227 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |