US20010017557A1 - Circuit for data signal recovery and clock signal regeneration - Google Patents
Circuit for data signal recovery and clock signal regeneration Download PDFInfo
- Publication number
- US20010017557A1 US20010017557A1 US09/811,801 US81180101A US2001017557A1 US 20010017557 A1 US20010017557 A1 US 20010017557A1 US 81180101 A US81180101 A US 81180101A US 2001017557 A1 US2001017557 A1 US 2001017557A1
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- United States
- Prior art keywords
- regulating stage
- pll regulating
- pll
- clock signal
- circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- the invention relates to a circuit, which can be completely integrated in an electronic module (chip), for data signal recovery and clock signal regeneration from an incoming serial data signal stream with a retiming circuit.
- the circuit uses a PLL (phase locked loop) regulating stage which is provided with a voltage-controlled oscillator (VCO) and to which the serial data signal stream is fed.
- VCO voltage-controlled oscillator
- the invention is directed, in particular, at the recovery and the retiming of data signals and clock signals, respectively, from serial data streams, e.g. in transceiver circuits for ATM (asynchronous transfer mode), SONET (synchronous optical network) and SDH (synchronous digital hierarchy) applications. It is known to realize the reconditioning of data signals and clock signals with the aid of a PLL regulating stage and retiming flip-flop. There are diverse types of phase and frequency detectors for this purpose.
- the incoming data signal is generally a serial bit sequence encumbered with noise and jitter.
- Various requirements are imposed on a transceiver which receives and evaluates this data signal stream, in order that a signal of required quality is produced again on the output side.
- Two important requirements, which, however, are partly at odds with one another, are the values for the jitter tolerance and for the jitter transfer.
- the jitter tolerance defines the maximum permissible input jitter which the circuit can still process in a manner free from errors. This value should be as large as possible.
- the jitter transfer defines the maximum permissible jitter which is allowed to be transferred from the input to the output. It should be as small as possible.
- a large bandwidth enables the PLL regulating loop to effect rapid following in terms of the frequency and phase of the incoming signal and thus reliable sampling in the temporal center of a data bit. This fact then also results in the circuit having high input sensitivity.
- a small PLL regulating loop bandwidth is necessary for a low jitter transfer. This ensures that the PLL regulating stage does not follow the high-frequency jitter, noise and other interference and thus impair the quality of the recovered data signal.
- the object of the invention is to provided a circuit, which can be completely integrated on an electronic chip and thus implemented without external circuitry, for the recovery and for the retiming of data signals and clock signals, respectively, from serial data streams, in particular for a simpler construction of ATM, SONET and SDH-conforming transceiver circuits for possible use in signal transmission links in the gigabit range, the jitter requirements being complied with and, consequently, a data signal of required quality, that is to say having a prescribed low bit error rate, being produced again on the output side.
- a circuit for data signal recovery and clock signal regeneration from an incoming serial data signal stream comprising data bits comprises:
- a first PLL regulating stage having a voltage-controlled oscillator, an input receiving a serial data signal stream, and an output outputting a clock signal;
- a second PLL regulating stage connected to the output of the first PLL regulating stage and in series therewith, the second PLL regulating stage having an input receiving the clock signal and an output outputting an output clock signal;
- the first and second PLL regulating stages being independent of one another and each being optimally adjustable separately, whereby the first PLL regulating stage is set at a first bandwidth, and the second PLL regulating stage is set at a second bandwidth smaller than the first bandwidth.
- the objects of the invention are achieved, according to the invention, which relates to a circuit of the type mentioned in the introduction, by virtue of the fact that there is connected downstream of the PLL regulating stage in series a second PLL regulating stage, that the two PLL regulating stages are independent and are each optimally adjustable separately, that the first PLL regulating stage is set in such a way that it has a large bandwidth and is optimized for maximum jitter tolerance, and that the second PLL regulating stage is set in such a way that it has a small bandwidth and is optimized for minimum jitter transfer.
- the invention thus solves the problem by connecting two independent PLL regulating stages in series, for each of which the optimum setting is performed separately.
- the first PLL regulating stage has a large bandwidth and regenerates the level of the incoming signal.
- the signal/noise ratio becomes less critical and the second PLL regulating stage can guarantee error-free data regeneration, even without sampling in the absolute center of a data bit.
- the second PLL regulating stage has a small bandwidth and can thus be optimized for low jitter transfer.
- the second PLL regulating stage is configured to synchronize the clock signal and the output clock signal and wherein a transition from the first PLL regulating stage to the second PLL regulating stage is performed via a synchronization of the clock signal and the output clock signal realized in the second PLL regulating stage. That is, the transition from the first PLL regulating stage to the second PLL regulating stage is performed by means of synchronization of the two clock signals which is carried out in the second PLL regulating stage.
- the second PLL regulating stage can be realized in a simple manner and without a high technical outlay on circuitry.
- a constant frequency crystal oscillator is provided to stabilize a reference frequency of the first PLL regulating stage.
- the circuit is particularly suitable in a transceiver circuit at an end of a transmission link of a telecommunications and data transmission network.
- the signal transmission link operates in a gigabit range.
- FIGURE of the drawing is a schematic block circuit diagram of a circuit according to the invention.
- an incoming digital data stream DATA IN is fed to a first PLL regulating stage 2 via an isolation amplifier 1 .
- the reference frequency f Ref of the PLL regulating stage 2 is formed by a crystal oscillator 3 , is therefore stable in frequency and holds a voltage-controlled oscillator in a valid operating range.
- the first PLL regulating stage 2 is provided with a voltage-controlled oscillator (VCO) 4 , which may be realized by a ring oscillator, for example, and an integrator 5 , with which the bandwidth of the PLL regulating stage 2 is determined.
- VCO voltage-controlled oscillator
- the finally recovered data signals and clock signals DATA OUT and CLOCK OUT respectively, are passed out from the second PLL regulating stage 6 via a respective isolation amplifier 9 and 10 .
- the optimum setting for the two independent PLL regulating stages 2 and 6 is performed separately in each case.
- the first PLL regulating stage 2 has a large bandwidth and regenerates the level of the incoming signal DATA IN.
- the signal/noise ratio thus becomes less critical, and the second PLL regulating stage 6 ensures error-free data recovery, and it does not necessarily have to effect sampling in the absolute center of the data bits of the data signals DATA fed from the first PLL regulating stage 2 .
- the second PLL regulating stage 6 has a small bandwidth and can be optimized for minimum jitter transfer.
- the transition from the first PLL regulating stage 2 , in which the data signals DATA and clock signals CLOCK are recovered, is effected by means of synchronization of the two clock signals CLOCK and CLOCK OUT in the PLL regulating stage 6 , which can be realized in a relatively simple manner.
Abstract
The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.
Description
- This application is a continuation of copending International Application No. PCT/DE99/02742, filed Sep. 1, 1999, which designated the United States.
- Field of the Invention
- The invention relates to a circuit, which can be completely integrated in an electronic module (chip), for data signal recovery and clock signal regeneration from an incoming serial data signal stream with a retiming circuit. The circuit uses a PLL (phase locked loop) regulating stage which is provided with a voltage-controlled oscillator (VCO) and to which the serial data signal stream is fed.
- The invention is directed, in particular, at the recovery and the retiming of data signals and clock signals, respectively, from serial data streams, e.g. in transceiver circuits for ATM (asynchronous transfer mode), SONET (synchronous optical network) and SDH (synchronous digital hierarchy) applications. It is known to realize the reconditioning of data signals and clock signals with the aid of a PLL regulating stage and retiming flip-flop. There are diverse types of phase and frequency detectors for this purpose. Reference is had, in this context, to a paper by Hans-Jürgen Herzog entitled “Auswahl von Bausteinen für die Daten- und Taktregenerierung in Telekom- und Datennetzen” [“Selection of modules for data and clock regeneration in telecommunications and data networks”], published in the journal “HF-Praxis”,
issue 5, 1998,volume 4, pp. 12-14. - The incoming data signal is generally a serial bit sequence encumbered with noise and jitter. Various requirements are imposed on a transceiver which receives and evaluates this data signal stream, in order that a signal of required quality is produced again on the output side. Two important requirements, which, however, are partly at odds with one another, are the values for the jitter tolerance and for the jitter transfer. The jitter tolerance defines the maximum permissible input jitter which the circuit can still process in a manner free from errors. This value should be as large as possible. The jitter transfer defines the maximum permissible jitter which is allowed to be transferred from the input to the output. It should be as small as possible.
- In order to fulfill these jitter requirements, the bandwidth of the PLL regulating loop used in the reconditioning of data signals and clock signals must be adapted to the requirements. A large PLL regulating loop bandwidth is necessary for a large jitter tolerance.
- A large bandwidth enables the PLL regulating loop to effect rapid following in terms of the frequency and phase of the incoming signal and thus reliable sampling in the temporal center of a data bit. This fact then also results in the circuit having high input sensitivity.
- A small PLL regulating loop bandwidth is necessary for a low jitter transfer. This ensures that the PLL regulating stage does not follow the high-frequency jitter, noise and other interference and thus impair the quality of the recovered data signal.
- In order to simultaneously meet both conditions to some extent, one is thus forced to adopt a compromise. In this case, the bandwidth of such a PLL regulating loop is in a very narrow range. Since a PLL regulating stage can in part comprise highly nonlinear components, particularly in the case of completely integrated PLL regulating loops, it is difficult to calculate or realize the bandwidth.
- The object of the invention is to provided a circuit, which can be completely integrated on an electronic chip and thus implemented without external circuitry, for the recovery and for the retiming of data signals and clock signals, respectively, from serial data streams, in particular for a simpler construction of ATM, SONET and SDH-conforming transceiver circuits for possible use in signal transmission links in the gigabit range, the jitter requirements being complied with and, consequently, a data signal of required quality, that is to say having a prescribed low bit error rate, being produced again on the output side.
- With this and other objects in view there is provided, in accordance with the invention, a circuit for data signal recovery and clock signal regeneration from an incoming serial data signal stream comprising data bits. The circuit, which is completely integrateable into an electronic component, comprises:
- a first PLL regulating stage having a voltage-controlled oscillator, an input receiving a serial data signal stream, and an output outputting a clock signal;
- a second PLL regulating stage connected to the output of the first PLL regulating stage and in series therewith, the second PLL regulating stage having an input receiving the clock signal and an output outputting an output clock signal;
- the first and second PLL regulating stages being independent of one another and each being optimally adjustable separately, whereby the first PLL regulating stage is set at a first bandwidth, and the second PLL regulating stage is set at a second bandwidth smaller than the first bandwidth.
- In other words, the objects of the invention are achieved, according to the invention, which relates to a circuit of the type mentioned in the introduction, by virtue of the fact that there is connected downstream of the PLL regulating stage in series a second PLL regulating stage, that the two PLL regulating stages are independent and are each optimally adjustable separately, that the first PLL regulating stage is set in such a way that it has a large bandwidth and is optimized for maximum jitter tolerance, and that the second PLL regulating stage is set in such a way that it has a small bandwidth and is optimized for minimum jitter transfer.
- The invention thus solves the problem by connecting two independent PLL regulating stages in series, for each of which the optimum setting is performed separately. The first PLL regulating stage has a large bandwidth and regenerates the level of the incoming signal.
- As a result, the signal/noise ratio becomes less critical and the second PLL regulating stage can guarantee error-free data regeneration, even without sampling in the absolute center of a data bit. The second PLL regulating stage has a small bandwidth and can thus be optimized for low jitter transfer.
- Complete integration on a single chip is possible since the circuit according to the invention can tolerate relatively large parameter fluctuations of the circuit.
- In accordance with an added feature of the invention, the second PLL regulating stage is configured to synchronize the clock signal and the output clock signal and wherein a transition from the first PLL regulating stage to the second PLL regulating stage is performed via a synchronization of the clock signal and the output clock signal realized in the second PLL regulating stage. That is, the transition from the first PLL regulating stage to the second PLL regulating stage is performed by means of synchronization of the two clock signals which is carried out in the second PLL regulating stage. The second PLL regulating stage can be realized in a simple manner and without a high technical outlay on circuitry.
- In accordance with an additional feature of the invention, a constant frequency crystal oscillator is provided to stabilize a reference frequency of the first PLL regulating stage.
- In accordance with another feature of the invention, the circuit is particularly suitable in a transceiver circuit at an end of a transmission link of a telecommunications and data transmission network.
- In the preferred embodiment of the invention, the signal transmission link operates in a gigabit range.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a circuit for data signal recovery and clock signal regeneration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
- The sole FIGURE of the drawing is a schematic block circuit diagram of a circuit according to the invention.
- Referring now to the FIGURE of the drawing in detail, an incoming digital data stream DATA IN is fed to a first
PLL regulating stage 2 via anisolation amplifier 1. The reference frequency fRef of the PLL regulatingstage 2 is formed by acrystal oscillator 3, is therefore stable in frequency and holds a voltage-controlled oscillator in a valid operating range. - The first
PLL regulating stage 2 is provided with a voltage-controlled oscillator (VCO) 4, which may be realized by a ring oscillator, for example, and anintegrator 5, with which the bandwidth of the PLL regulatingstage 2 is determined. There is connected downstream of the first PLL regulating stage 2 a secondPLL regulating stage 6, which is likewise provided with a voltage-controlled oscillator 7 and anintegrator 8 which critically determines the bandwidth of the secondPLL regulating stage 6. - The finally recovered data signals and clock signals DATA OUT and CLOCK OUT respectively, are passed out from the second
PLL regulating stage 6 via arespective isolation amplifier PLL regulating stages PLL regulating stage 2 has a large bandwidth and regenerates the level of the incoming signal DATA IN. - The signal/noise ratio thus becomes less critical, and the second
PLL regulating stage 6 ensures error-free data recovery, and it does not necessarily have to effect sampling in the absolute center of the data bits of the data signals DATA fed from the firstPLL regulating stage 2. - In contrast to the first
PLL regulating stage 2, the secondPLL regulating stage 6 has a small bandwidth and can be optimized for minimum jitter transfer. The transition from the firstPLL regulating stage 2, in which the data signals DATA and clock signals CLOCK are recovered, is effected by means of synchronization of the two clock signals CLOCK and CLOCK OUT in the PLL regulatingstage 6, which can be realized in a relatively simple manner.
Claims (6)
1. A circuit for data signal recovery and clock signal regeneration from an incoming serial data signal stream comprising data bits, comprising:
a first PLL regulating stage having a voltage-controlled oscillator, an input receiving a serial data signal stream, and an output outputting a clock signal;
a second PLL regulating stage connected to said output of said first PLL regulating stage and in series therewith, said second PLL regulating stage having an input receiving the clock signal and an output outputting an output clock signal;
said first and second PLL regulating stages being independent of one another and each being optimally adjustable separately, whereby said first PLL regulating stage is set at a first bandwidth, and said second PLL regulating stage is set at a second bandwidth smaller than the first bandwidth.
2. The circuit according to , wherein said second PLL regulating stage is configured to synchronize the clock signal and the output clock signal and wherein a transition from said first PLL regulating stage to said second PLL regulating stage is performed via a synchronization of the clock signal and the output clock signal realized in said second PLL regulating stage.
claim 1
3. The circuit according to , which comprises a constant frequency crystal oscillator connected to stabilize a reference frequency of said first PLL regulating stage.
claim 1
4. The circuit according to in combination with a transceiver circuit at an end of a transmission link of a telecommunications and data transmission network.
claim 1
5. The circuit according to in combination with a signal transmission link operating in a gigabit range.
claim 1
6. An electronic module, comprising the circuit according to completely integrated in the electronic module.
claim 1
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19842711A DE19842711C2 (en) | 1998-09-17 | 1998-09-17 | Circuit for data signal recovery and clock signal regeneration |
| DE19842711.5 | 1998-09-17 | ||
| DE19842711 | 1998-09-17 | ||
| PCT/DE1999/002742 WO2000018008A2 (en) | 1998-09-17 | 1999-09-01 | Circuit for recovering a data signal and regenerating a clock signal |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE1999/002742 Continuation WO2000018008A2 (en) | 1998-09-17 | 1999-09-01 | Circuit for recovering a data signal and regenerating a clock signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20010017557A1 true US20010017557A1 (en) | 2001-08-30 |
| US6433599B2 US6433599B2 (en) | 2002-08-13 |
Family
ID=7881349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/811,801 Expired - Lifetime US6433599B2 (en) | 1998-09-17 | 2001-03-19 | Circuit for data signal recovery and clock signal regeneration |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6433599B2 (en) |
| EP (1) | EP1114539B1 (en) |
| JP (1) | JP2002525954A (en) |
| CA (1) | CA2344192C (en) |
| DE (1) | DE19842711C2 (en) |
| WO (1) | WO2000018008A2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2835122A1 (en) * | 2002-01-22 | 2003-07-25 | Zarlink Semiconductor Inc | Circuit for measuring the precision of a clock signal, and associated method |
| US20040153894A1 (en) * | 2003-01-21 | 2004-08-05 | Zarlink Semiconductor Inc. | Method of measuring the accuracy of a clock signal |
| US7006590B2 (en) | 2000-06-08 | 2006-02-28 | Zarlink Semiconductor Inc. | Timing circuit with dual phase locked loops |
| EP1793498A2 (en) | 2005-12-02 | 2007-06-06 | Altera Corporation | Programmable transceivers that are able to operate over wide frequency ranges |
| US20080232524A1 (en) * | 2007-03-22 | 2008-09-25 | Mediatek Inc. | Jitter-tolerance-enhanced cdr using a gdco-based phase detector |
| US7742556B1 (en) * | 2005-09-13 | 2010-06-22 | Marvell International Ltd. | Circuits, methods, apparatus, and systems for recovery of spread spectrum clock |
| US20150103966A1 (en) * | 2006-03-14 | 2015-04-16 | Guenter Maerzinger | Transceiver |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2816569B1 (en) * | 2000-11-15 | 2003-02-14 | Bosch Sist De Frenado Sl | REACTION DISC DEVICE, ITS MANUFACTURING METHOD, AND ASSISTANCE SERVOMOTOR COMPRISING SUCH A DEVICE |
| US7245685B2 (en) * | 2000-12-05 | 2007-07-17 | Ericsson Ab | Filtering for timing distribution system in networking products |
| DE10060911A1 (en) | 2000-12-07 | 2002-06-27 | Infineon Technologies Ag | Phase locked loop for the recovery of a clock signal from a data signal |
| US6768362B1 (en) * | 2001-08-13 | 2004-07-27 | Cypress Semiconductor Corp. | Fail-safe zero delay buffer with automatic internal reference |
| JP2003152694A (en) * | 2001-11-14 | 2003-05-23 | Mitsubishi Electric Corp | Data/clock reproducing device |
| CN100449967C (en) * | 2001-12-22 | 2009-01-07 | 中兴通讯股份有限公司 | Equipment for restoring E3/T3 branch signal from synchronous digital transmission system |
| GB0205350D0 (en) | 2002-03-07 | 2002-04-24 | Zarlink Semiconductor Inc | Clock synchronisation over a packet network using SRTS without a common network clock |
| EP1811670B1 (en) | 2003-04-02 | 2010-03-10 | Christopher Julian Travis | Number controlled oscillator and a method of establishing an event clock |
| US6842056B1 (en) * | 2003-06-24 | 2005-01-11 | Intel Corporation | Cascaded phase-locked loops |
| US20050193290A1 (en) * | 2004-02-25 | 2005-09-01 | Cho James B. | Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer |
| US7376158B2 (en) * | 2004-04-22 | 2008-05-20 | Scientific-Atlanta, Inc. | Rate limited control mechanism for MPEG PCR dejittering |
| US7929648B2 (en) * | 2006-03-31 | 2011-04-19 | Ati Technologies Inc. | Clock error detection apparatus and method |
| US8102196B1 (en) * | 2008-06-27 | 2012-01-24 | National Semiconductor Corporation | Programmable dual phase-locked loop clock signal generator and conditioner |
| US10951390B2 (en) * | 2018-02-05 | 2021-03-16 | Arris Enterprises Llc | Two-stage IP de-jitter algorithm in a multiplexer for a group of statistically multiplexed single program transport streams |
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| GB1531632A (en) * | 1976-05-28 | 1978-11-08 | Westinghouse Brake & Signal | Phase-locked loop arrangements |
| US4234852A (en) * | 1978-11-15 | 1980-11-18 | Mccorkle John W | Coherent frequency shift key demodulator |
| JPS6331314A (en) * | 1986-07-25 | 1988-02-10 | Toshiba Corp | Phase locked loop circuit |
| JPS63136718A (en) * | 1986-11-28 | 1988-06-08 | Hitachi Ltd | Pll circuit |
| US4802009A (en) * | 1987-07-13 | 1989-01-31 | Rca Licensing Corporation | Digitally controlled phase locked loop system |
| US5072195A (en) * | 1990-04-05 | 1991-12-10 | Gazelle Microcircuits, Inc. | Phase-locked loop with clamped voltage-controlled oscillator |
| JPH04313917A (en) * | 1991-03-29 | 1992-11-05 | Mitsubishi Electric Corp | Double pll device |
| US5363419A (en) * | 1992-04-24 | 1994-11-08 | Advanced Micro Devices, Inc. | Dual phase-locked-loop having forced mid range fine control zero at handover |
| US5717730A (en) * | 1995-12-22 | 1998-02-10 | Microtune, Inc. | Multiple monolithic phase locked loops |
| JPH09284126A (en) * | 1996-04-15 | 1997-10-31 | Sony Corp | Pll circuit and decoder |
| WO1998010519A1 (en) * | 1996-09-04 | 1998-03-12 | Siemens Aktiengesellschaft | Low-jitter phase-locking loop |
| US6215835B1 (en) * | 1997-08-22 | 2001-04-10 | Lsi Logic Corporation | Dual-loop clock and data recovery for serial data communication |
| US6218876B1 (en) * | 1999-01-08 | 2001-04-17 | Altera Corporation | Phase-locked loop circuitry for programmable logic devices |
-
1998
- 1998-09-17 DE DE19842711A patent/DE19842711C2/en not_active Expired - Lifetime
-
1999
- 1999-09-01 CA CA002344192A patent/CA2344192C/en not_active Expired - Fee Related
- 1999-09-01 WO PCT/DE1999/002742 patent/WO2000018008A2/en active IP Right Grant
- 1999-09-01 EP EP99953656A patent/EP1114539B1/en not_active Expired - Lifetime
- 1999-09-01 JP JP2000571561A patent/JP2002525954A/en active Pending
-
2001
- 2001-03-19 US US09/811,801 patent/US6433599B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7006590B2 (en) | 2000-06-08 | 2006-02-28 | Zarlink Semiconductor Inc. | Timing circuit with dual phase locked loops |
| FR2835122A1 (en) * | 2002-01-22 | 2003-07-25 | Zarlink Semiconductor Inc | Circuit for measuring the precision of a clock signal, and associated method |
| US20040153894A1 (en) * | 2003-01-21 | 2004-08-05 | Zarlink Semiconductor Inc. | Method of measuring the accuracy of a clock signal |
| US7742556B1 (en) * | 2005-09-13 | 2010-06-22 | Marvell International Ltd. | Circuits, methods, apparatus, and systems for recovery of spread spectrum clock |
| EP1793498A2 (en) | 2005-12-02 | 2007-06-06 | Altera Corporation | Programmable transceivers that are able to operate over wide frequency ranges |
| EP1793498A3 (en) * | 2005-12-02 | 2010-12-08 | Altera Corporation | Programmable transceivers that are able to operate over wide frequency ranges |
| US20150103966A1 (en) * | 2006-03-14 | 2015-04-16 | Guenter Maerzinger | Transceiver |
| US9948450B2 (en) | 2006-03-14 | 2018-04-17 | Intel Deutschland Gmbh | Frequency generator |
| US20080232524A1 (en) * | 2007-03-22 | 2008-09-25 | Mediatek Inc. | Jitter-tolerance-enhanced cdr using a gdco-based phase detector |
| US8019022B2 (en) * | 2007-03-22 | 2011-09-13 | Mediatek Inc. | Jitter-tolerance-enhanced CDR using a GDCO-based phase detector |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19842711C2 (en) | 2002-01-31 |
| CA2344192C (en) | 2004-03-09 |
| WO2000018008A3 (en) | 2000-05-25 |
| JP2002525954A (en) | 2002-08-13 |
| US6433599B2 (en) | 2002-08-13 |
| EP1114539B1 (en) | 2003-12-03 |
| EP1114539A2 (en) | 2001-07-11 |
| WO2000018008A2 (en) | 2000-03-30 |
| DE19842711A1 (en) | 2000-03-30 |
| CA2344192A1 (en) | 2000-03-30 |
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