WO1998010519A1 - Low-jitter phase-locking loop - Google Patents

Low-jitter phase-locking loop Download PDF

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Publication number
WO1998010519A1
WO1998010519A1 PCT/DE1997/001908 DE9701908W WO9810519A1 WO 1998010519 A1 WO1998010519 A1 WO 1998010519A1 DE 9701908 W DE9701908 W DE 9701908W WO 9810519 A1 WO9810519 A1 WO 9810519A1
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Prior art keywords
oscillator
phase
frequency
controller
controlled
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PCT/DE1997/001908
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German (de)
French (fr)
Inventor
Volkmar Rebmann
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Siemens Aktiengesellschaft
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Publication of WO1998010519A1 publication Critical patent/WO1998010519A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator

Definitions

  • the invention relates to a phase-locked loop according to the features of the preamble of patent claim 1.
  • Phase locked loops are used to generate an output signal that is phase locked to a reference frequency signal.
  • the basic structure of phase-locked loops is described, for example, in the reference Tietze, Schenk, “Semiconductor circuit technology”, 9th edition, 1991, pages 954 to 967.
  • the controller implemented there is designed as a PI controller, in particular as an RC
  • the charge pump delivers pulses of positive or negative current pulses depending on the comparison result of the phase detector
  • the proportional part which ensures the stability of the overall system
  • the pulsed activation of the loop filter from the charge pump, together with the proportional control part means that the output signal of the loop filter has corresponding control impulses by means of which the controllable n oscillator output vibration is corrected in frequency. These control pulses generate frequency and phase interference in the output signal of the oscillator, so-called frequency and phase jitter.
  • the control pulses and the phase jitter generated thereby are also present in the steady state, since the oscillation frequency of the controlled oscillator changes due to supply voltage fluctuations and leak effects, for example in the capacitor of the loop filter. If the phase locked loop is operated as a frequency multiplier with a Divider in the feedback circuit, the oscillator oscillates freely during the number of oscillations set by the divider ratio. The frequency and phase deviation of the oscillator accumulates during this free-running time, the adjustment effect due to the control pulses is correspondingly large.
  • Oscillators are usually implemented as integrated circuits.
  • the transmission characteristics of the transistors are subject to the so-called 1 / f noise, which is caused by the unavoidable defects in the atomic lattice of the semiconductor crystal.
  • the 1 / noise is considerable in particular in the case of implementations with CMOS transistors. It is effective up to orders of magnitude close to the desired control accuracy of the phase locked loop. Especially in the
  • Video technology requires phase locked loops that oscillate at around 100 MHz.
  • the 1 / f noise then extends into the range of 1 MHz, so that the required tuning accuracy of the control loop, which is in the range of kHz, can no longer be achieved.
  • the effect of the phase and frequency jitter on the one hand and the effect of the 1 / f noise on the other hand is dependent on the loop gain of the phase locked loop.
  • the loop gain through which the control bandwidth is determined, is proportional to the proportional portion of the loop filter.
  • a high loop gain is necessary.
  • the jitter effects are also proportional to the loop gain.
  • the l / f noise effects are inversely proportional to the loop gain. Consequently, changing the loop gain reduces one of the effects but increases the other.
  • the object of the invention is to provide a phase locked loop which enables an output signal with as little jitter as possible at high operating frequencies.
  • the phase locked loop should be realizable as an integrated circuit in CMOS circuit technology.
  • the invention is based on the principle of suppressing the control pulses when the oscillator supplying the output signal is activated effectively. This oscillator is therefore only controlled with the integral part of the controller.
  • measures are proposed in order to obtain the highest possible amplification and a correspondingly high bandwidth of the control range of the phase-locked loop without increasing the phase jitter.
  • the phase-locked loop has an unchanged good stability behavior.
  • the oscillator located in the feedback branch is designed as a ring oscillator with a variable feedback length that is shortened or lengthened by the control pulses. This gives the control loop a sufficiently high control gain. Due to component fluctuations and the 1 / f current noise, the frequencies of the output signals of the two oscillators may differ. Readjustment is therefore provided, by means of which the frequency difference between the two oscillators is corrected.
  • a further I or PI controller is provided, which is connected on the input side to the outputs of the two oscillators.
  • the phase difference between the oscillators, which is generated by shortening or lengthening the ring oscillator due to the control by the proportional control component, is determined by a delay element. maintained despite the frequency readjustment between the two oscillators.
  • Figure 1 shows an embodiment of a phase locked loop
  • Figure 2 shows an implementation for the oscillator in the feedback branch.
  • the phase-locked loop according to FIG. 1 contains an input connection 1, to which a reference signal VI with a reference frequency is fed.
  • a phase detector 2 the phase difference is determined between the reference signal VI and a feedback signal VF to be explained later.
  • the phase detector 2 Depending on the phase difference, the phase detector 2 generates pulse-like output signals PU, PD.
  • a pulse PU is generated when the feedback signal VF lags the reference signal VI.
  • a corresponding correction of the signal VF is initiated by the pulse PU. Otherwise, when the feedback signal VF leads the reference signal VI, the pulse PD is generated and the signal VF is corrected accordingly.
  • An integral controller is formed by a charge pump 3 and an integrator connected downstream of it on the output side.
  • the latter is a capacitor 4, which is charged or discharged by current pulses from the charge pump.
  • the capacitor 4 In the case of a pulse PU, the capacitor 4 is charged by a current pulse + Ip, in the case of a pulse PD the capacitor 4 is discharged by a current pulse -Ip.
  • the control signal VC which can be tapped at the connection 5 of the capacitor has an integral character with respect to the phase difference between the signals VI, VF.
  • a voltage-controlled oscillator (VCO) 61 is controlled with respect to its oscillation frequency by the control signal VC at the connection 5, and with respect to its phase by the pulses PD, PU.
  • At the output 7 of the oscillator 61 there is a signal whose frequency is synchronized with the frequency of the input signal VI in the steady state. If the circuit is used as a frequency is operated multiple times, there is a divider 9 in the feedback path, by means of whose divider ratio 1: N the multiplication ratio N is set.
  • the oscillator 61 consists of a runtime chain 80 made up of delay elements connected in series, for example inverters, the output of which is fed back to the input.
  • the runtime chain is supplied with a controllable current source 81 for control via the connection 5 with the signal VC.
  • the length of the delay chain can be shortened or lengthened compared to the middle tap 83 by means of corresponding switches 82 or 84.
  • the output signal of the oscillator 61 is shifted by a negative or a positive time period with respect to a central position of a clock edge of its output signal.
  • the switches 82, 84 are controlled by the proportional control signals PU and PD, the switch 85 is controlled when none of the signals PU, PD has a pulse. During the pulse pause of the signals PU, PD, the switch 85 is closed and the mean feedback length is set. This results in phase jumps dependent on the pulse duration in the output signal of the oscillator 61.
  • the special design of the oscillator 61 shown in FIG. 4 responds very quickly to the control pulses, so that the control loop formed has a high loop gain for a large capture range of the oscillator.
  • a further oscillator 62 is also provided, which is also controlled by the integral signal VC.
  • the oscillator 62 has a corresponding one in comparison to the oscillator 61
  • oscillator 62 Since the oscillators 61, 62 are controlled by the same signal VC, they oscillate at essentially the same frequency. Compared to oscillator 61, however, oscillator 62 has no phase jitter, since it is only controlled by the integral component, but not by the proportional component of the control loop becomes. The output signal VO is therefore present at the output of the oscillator 62 as a low-jitter signal.
  • a further phase detector and charge pump device 63 is therefore provided with an element 64 which generates an I component, by means of which the oscillator 61 is adjusted.
  • the oscillator 62 can also be adjusted.
  • a delay element 65 is provided, via which the output signal of the oscillator 61 is coupled into one of the phase detector inputs of the device 63.
  • the delay time of the timing element 65 can preferably be set by the device 63 via an integral element 66.
  • the output signal VO is fed into the other phase detector input of the device 63 either directly or via another - not shown - adjustable delay element.
  • the switch 67 is expediently switched on during a first half of the period of the feedback signal VF generated by the divider factor N in the divider 9, and the switch 68 during the second period.
  • the delay element 65 is designed in accordance with the ring oscillator 61 with a controllable current source which supplies the inverter chain , but without feedback.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

In order to avoid phase jitter a phase-locking loop is provided with a frequency controlled oscillator (62) conditioning an output signal (VO). Said oscillator is started only by the integral component (4) of a PI-controller. An oscillator (61) in the feedback branch of the control loop circuit is controlled by the integral and proportional component (4, PU, PD) of the control loop. In the embodiment of the invention this oscillator (61) is realized in the form of a ring oscillator with feedback length that can be modified by the proportional component (PU, PD). Between the oscillators (61, 62) frequency synchronization is effected by frequency correction system (63 ... 68). The phase-locking loop presents a high bandwidth with high frequency accuracy and can also be realized for high working frequencies in CMOS technology.

Description

Beschreibung description
Ji terarmer PhasenregelkreisLow phase locked loop
Die Erfindung betrifft einen Phasenregelkreis nach den Merkmalen des Oberbegriffs des Patentanspruchs 1.The invention relates to a phase-locked loop according to the features of the preamble of patent claim 1.
Phasenregelkreiεe (PLL) werden verwendet, um ein an ein Refe- renzfre-guenzsignal phasenstarr gekoppeltes AusgangsSignal zu erzeugen. Der prinzipielle Aufbau von Phasenregelkreisen ist beispielsweise in der Literaturstelle Tietze, Schenk, „Halbleiterschaltungstechnik", 9. Auflage, 1991, Seiten 954 bis 967 beschrieben. In praktischen Realisierungen wird der dort ausgeführte Regler als PI-Regler ausgeführt, insbeson- dere als ein RC-Glied, das eingangsseitig von einer Ladungspumpe angesteuert wird. Die Ladungspumpe liefert in Abhängigkeit vom Vergleichsergebnis des Phasendetektors pulsweise positive oder negative Stromimpulse. Das RC-Schleifenfilter erzeugt daraus das Regelsignal für einen freguenzsteuerbaren, insbesondere spannungssteuerbaren Oszillator. Das Schleifenfilter umfaßt einen integrierenden Teil sowie einen für die Stabilität des Gesamtsystems sorgenden Proportionalteil. Die pulsweise Ansteuerung des Schleifenfilters aus der Ladungspumpe bewirkt zusammen mit dem proportionalen Regelanteil, daß das Ausgangssignal des Schleifenfilters entsprechende Regelimpulse aufweist, durch die die vom steuerbaren Oszillator abgegebene Schwingung frequenzmäßig korrigiert wird. Diese Regelimpulse erzeugen Frequenz- und Phasenstörungen im Aus- gangssignal des Oszillators, sogenannten Frequenz- und Pha- senjitter.Phase locked loops (PLL) are used to generate an output signal that is phase locked to a reference frequency signal. The basic structure of phase-locked loops is described, for example, in the reference Tietze, Schenk, “Semiconductor circuit technology”, 9th edition, 1991, pages 954 to 967. In practical implementations, the controller implemented there is designed as a PI controller, in particular as an RC The charge pump delivers pulses of positive or negative current pulses depending on the comparison result of the phase detector The proportional part which ensures the stability of the overall system The pulsed activation of the loop filter from the charge pump, together with the proportional control part, means that the output signal of the loop filter has corresponding control impulses by means of which the controllable n oscillator output vibration is corrected in frequency. These control pulses generate frequency and phase interference in the output signal of the oscillator, so-called frequency and phase jitter.
Die Regelimpulse und der dadurch erzeugte Phasenjitter liegen auch im eingeschwungenen Zustand vor, da sich aufgrund von VersorgungsspannungsSchwankungen und Leckeffekten, beispiels- weise im Kondensator des Schleifenfilters, die Schwingfrequenz des gesteuerten Oszillators verändert. Wenn der Phasenregelkreis als Frequenzvervielfacher betrieben wird mit einem Teiler im Rückkopplungskreis, schwingt der Oszillator während der durch das Teilerverhältnis eingestellten Anzahl von Schwingungen frei. Die Fre-quenz- und Phasenabweichung des Oszillators akkumuliert sich während dieser Freilaufzeit auf, der Nachstelleffekt durch die Regelimpulse wird entsprechend groß.The control pulses and the phase jitter generated thereby are also present in the steady state, since the oscillation frequency of the controlled oscillator changes due to supply voltage fluctuations and leak effects, for example in the capacitor of the loop filter. If the phase locked loop is operated as a frequency multiplier with a Divider in the feedback circuit, the oscillator oscillates freely during the number of oscillations set by the divider ratio. The frequency and phase deviation of the oscillator accumulates during this free-running time, the adjustment effect due to the control pulses is correspondingly large.
Oszillatoren werden üblicherweise als integrierte Schaltungen realisiert. Die Übertragungskennlinien der Transistoren un- terliegen dem sogenannten 1/f-Rauschen, das von den unvermeidbaren Störstellen im Atomgitter des Halbleiterkristalls verursacht wird. Insbesondere bei Realisierungen mit CMOS- Transistoren ist das 1/ -Rauschen erheblich. Es ist bis zu Größenordnungen in der Nähe der angestrebten Regelungsgenau- igkeit des Phasenregelkreises wirksam. Insbesondere in derOscillators are usually implemented as integrated circuits. The transmission characteristics of the transistors are subject to the so-called 1 / f noise, which is caused by the unavoidable defects in the atomic lattice of the semiconductor crystal. The 1 / noise is considerable in particular in the case of implementations with CMOS transistors. It is effective up to orders of magnitude close to the desired control accuracy of the phase locked loop. Especially in the
Videotechnik sind Phasenregelkreise erforderlich, die bei etwa 100 MHz schwingen. Das 1/f-Rauschen reicht dann bis in den Bereich von 1 MHz, so daß die erforderliche Abstimmungsgenauigkeit des Regelkreises, die im Bereich von kHz liegt, nicht mehr erreicht werden kann.Video technology requires phase locked loops that oscillate at around 100 MHz. The 1 / f noise then extends into the range of 1 MHz, so that the required tuning accuracy of the control loop, which is in the range of kHz, can no longer be achieved.
Die Auswirkung des Phasen- und Frequenzj itters einerseits und die Auswirkung des 1/f-Rauschens andererseits ist von der Schleifenverstärkung des Phasenregelkreises abhängig. Die Schleifeπverstärkung, durch die die Regelbandbreite festgelegt wird, verläuft proportional zum Proportionalanteil des Schleifenfilters. Um einen möglichst großen Fangbereich des Phasenregelkreises zu erhalten, ist eine hohe Schleifenver- stärkung erforderlich. Die Jittereffekte sind bekanntlich ebenfalls proportional der Schleifenverstärkung. Die l/f-Rau- scheffekte verlaufen umgekehrt proportional zur Schleifenverstärkung. Folglich wird durch eine Veränderung der Schleifenverstärkung zwar einer der Effekte verringert, der andere jedoch erhöht. Die Realisierung eines Phasenregelkreises mit herkömmlichen Konzepten bei hoher Qualität, d. h. großerThe effect of the phase and frequency jitter on the one hand and the effect of the 1 / f noise on the other hand is dependent on the loop gain of the phase locked loop. The loop gain, through which the control bandwidth is determined, is proportional to the proportional portion of the loop filter. In order to obtain the largest possible catchment area of the phase locked loop, a high loop gain is necessary. As is well known, the jitter effects are also proportional to the loop gain. The l / f noise effects are inversely proportional to the loop gain. Consequently, changing the loop gain reduces one of the effects but increases the other. The realization of a phase locked loop with conventional concepts with high quality, d. H. greater
Bandbreite, geringem Jitter, geringem Rauschen, ist deshalb kaum möglich. Die Aufgabe der Erfindung besteht darin, einen Phasenregel - kreis anzugeben, der ein möglichst jitterarmes Ausgangssignal bei hohen Arbeitsfrequenzen ermöglicht. Der Phasenregelkreis soll als integrierte Schaltung in CMOS-Schaltungstechnik realisierbar sein.Bandwidth, low jitter, low noise is therefore hardly possible. The object of the invention is to provide a phase locked loop which enables an output signal with as little jitter as possible at high operating frequencies. The phase locked loop should be realizable as an integrated circuit in CMOS circuit technology.
Erfindungsgemäß wird diese Aufgabe durch einen Phasenregelkreis nach den Merkmalen des Patentanspruchs 1 gelöst.According to the invention, this object is achieved by a phase-locked loop according to the features of patent claim 1.
Der Erfindung liegt das Prinzip zugrunde, bei der wirksamen Ansteuerung des das Ausgangssignal lieferenden Oszillators die Regelimpulse zu unterdrücken. Dieser Oszillator wird deshalb nur mit dem Integralanteil des Reglers angesteuert. In einer vorteilhaften Ausgestaltung der Erfindung werden Maßnahmen vorgeschlagen, um eine möglichst hohe Verstärkung und eine entsprechend hohe Bandbreite des Regelbereichs des Phasenregelkreises zu erhalten, ohne daß der Phasenjitter erhöht wird. Der Phasenregelkreis weist hierbei ein unverändert gu- tes Stabilitätsverhalten auf.The invention is based on the principle of suppressing the control pulses when the oscillator supplying the output signal is activated effectively. This oscillator is therefore only controlled with the integral part of the controller. In an advantageous embodiment of the invention, measures are proposed in order to obtain the highest possible amplification and a correspondingly high bandwidth of the control range of the phase-locked loop without increasing the phase jitter. The phase-locked loop has an unchanged good stability behavior.
In dieser bevorzugten Ausführungsform ist der im Rückkopplungszweig liegende Oszillator als Ringoszillator mit veränderbarer Rückkopplungslänge ausgeführt, die durch die Rege- limpulse verkürzt oder verlängert wird. Der Regelkreis erhält dadurch eine ausreichend hohe Regelverstärkung. Aufgrund von Bauelementeschwankungen und dem 1/f-Stromrauschen können die Frequenzen der Ausgangssignale der beiden Oszillatoren voneinander abweichen. Deshalb ist eine Nachregelung vorgesehen, durch die die Frequenzdifferenz der beiden Oszillatoren aus- geregelt wird. Hierzu ist ein weiterer I- oder PI-Regler vorgesehen, der eingangsseitig mit den Ausgängen der beiden Oszillatoren verbunden ist. Durch ein Verzögerungsglied wird die Phasendifferenz zwischen den Oszillatoren, die durch die Verkürzung bzw. Verlängerung des Ringoszillators aufgrund der Ansteuerung durch den Proportionalregelanteil erzeugt wird, trotz der Frequenznachregelung zwischen den beiden Oszillatoren beibehalten.In this preferred embodiment, the oscillator located in the feedback branch is designed as a ring oscillator with a variable feedback length that is shortened or lengthened by the control pulses. This gives the control loop a sufficiently high control gain. Due to component fluctuations and the 1 / f current noise, the frequencies of the output signals of the two oscillators may differ. Readjustment is therefore provided, by means of which the frequency difference between the two oscillators is corrected. For this purpose, a further I or PI controller is provided, which is connected on the input side to the outputs of the two oscillators. The phase difference between the oscillators, which is generated by shortening or lengthening the ring oscillator due to the control by the proportional control component, is determined by a delay element. maintained despite the frequency readjustment between the two oscillators.
Nachfolgend wird die Erfindung anhand der in der Zeichnung dargestellten Ausführungsbeispiele näher erläutert. Es zeigenThe invention is explained in more detail below on the basis of the exemplary embodiments illustrated in the drawing. Show it
Figur 1 ein Ausführungsbeispiel eines Phasenregelkreises, Figur 2 eine Realisierung für den Oszillator im Rückkopplungszweig.Figure 1 shows an embodiment of a phase locked loop, Figure 2 shows an implementation for the oscillator in the feedback branch.
Der Phasenregelkreis nach Figur 1 enthält einen Eingangsanschluß 1, an dem ein Referenzsignal VI mit einer Referenz- frequenz eingespeist wird. In einem Phasendetektor 2 wird die Phasendif eren∑ zwischen dem Referenzsignal VI und einem spä- ter noch zu erläuternden rückgekoppelten Signal VF ermittelt. Der Phasendetektor 2 erzeugt je nach Phasendifferenz pulswei- se AusgangsSignale PU, PD. Ein Impuls PU wird erzeugt, wenn das rückgekoppelte Signal VF dem Referenzsignal VI nacheilt. Durch den Impuls PU wird eine entsprechende Korrektur des Si- gnals VF veranlaßt. Im anderen Fall, wenn das rückgekoppelte Signal VF dem Referenzsignal VI voreilt, wird der Impuls PD erzeugt und das Signal VF entsprechend korrigiert. Ein Integralregler wird durch eine Ladungspumpe 3 und ein ihr aus- gangsseitig nachgeschaltetes Integrierglied gebildet. Letzte- res ist ein Kondensator 4, der von Stromimpulsen der Ladungs- pumpe auf- oder entladen wird. Bei einem Impuls PU wird der Kondensator 4 durch einen Stromimpuls +Ip aufgeladen, bei einem Impuls PD wird der Kondensator 4 durch einen Stromimpuls -Ip entladen. Das am Anschluß 5 des Kondensators abgreifbare Regelsignal VC weist bezogen auf die Phasendifferenz zwischen den Signalen VI, VF Integralcharakter auf. Ein spannungsge- steuerter Oszillator (VCO) 61 wird bezüglich seiner Schwingfrequenz durch das Steuersignal VC am Anschluß 5 gesteuert, bezüglich seiner Phase durch die Impulse PD, PU. Am Ausgang 7 des Oszillators 61 liegt ein Signal vor, dessen Frequenz mit der Frequenz des EingangsSignals VI im eingeschwungenen Zustand synchronisiert ist. Wenn die Schaltung als Frequenzver- vielfacher betrieben wird, liegt im Rückkopplungspfad ein Teiler 9, durch dessen Teilerverhältnis 1:N das Vervielfachungsverhältnis N eingestellt wird.The phase-locked loop according to FIG. 1 contains an input connection 1, to which a reference signal VI with a reference frequency is fed. In a phase detector 2, the phase difference is determined between the reference signal VI and a feedback signal VF to be explained later. Depending on the phase difference, the phase detector 2 generates pulse-like output signals PU, PD. A pulse PU is generated when the feedback signal VF lags the reference signal VI. A corresponding correction of the signal VF is initiated by the pulse PU. Otherwise, when the feedback signal VF leads the reference signal VI, the pulse PD is generated and the signal VF is corrected accordingly. An integral controller is formed by a charge pump 3 and an integrator connected downstream of it on the output side. The latter is a capacitor 4, which is charged or discharged by current pulses from the charge pump. In the case of a pulse PU, the capacitor 4 is charged by a current pulse + Ip, in the case of a pulse PD the capacitor 4 is discharged by a current pulse -Ip. The control signal VC which can be tapped at the connection 5 of the capacitor has an integral character with respect to the phase difference between the signals VI, VF. A voltage-controlled oscillator (VCO) 61 is controlled with respect to its oscillation frequency by the control signal VC at the connection 5, and with respect to its phase by the pulses PD, PU. At the output 7 of the oscillator 61 there is a signal whose frequency is synchronized with the frequency of the input signal VI in the steady state. If the circuit is used as a frequency is operated multiple times, there is a divider 9 in the feedback path, by means of whose divider ratio 1: N the multiplication ratio N is set.
Gemäß Figur 2 besteht der Oszillator 61 aus einer Laufzei - kette 80 aus hintereinander geschalteten Laufzeitgliedern , beispielsweise Invertern, deren Ausgang auf den Eingang rückgekoppelt ist. Zur Ansteuerung über den Anschluß 5 mit dem Signal VC wird die Laufzeitkette mit einer steuerbaren Strom- quelle 81 versorgt. Die Länge der Verzögerungskette kann gegenüber dem mittleren Abgriff 83 mittels entsprechender Schalter 82 oder 84 verkürzt bzw. verlängert werden. Dadurch wird das Ausgangssignal des Oszillators 61 gegenüber einer mittleren Lage einer Taktflanke seines Ausgangssignals um ei- nen negativen bzw. einen positiven Zeitabschnitt verschoben. Die Schalter 82, 84 werden dabei von den Proportionalsteuersignalen PU bzw. PD gesteuert, der Schalter 85 wird dann gesteuert, wenn keines der Signale PU, PD einen Impuls aufweist. Während der Impulspause der Signale PU, PD ist der Schalter 85 geschlossen und die mittlere Rückkopplungslänge eingestellt. Es entstehen dadurch von der Impulsdauer abhängige Phasensprünge im Ausgangssignal des Oszillators 61. Die spezielle in Figur 4 gezeigte Ausführung des Oszilllators 61 spricht auf die Regelimpulse sehr schnell an, so daß der ge- bildete Regelkreis eine hohe Schleifenverstärkung aufweist für einen großen Fangbereich des Oszillators.According to FIG. 2, the oscillator 61 consists of a runtime chain 80 made up of delay elements connected in series, for example inverters, the output of which is fed back to the input. The runtime chain is supplied with a controllable current source 81 for control via the connection 5 with the signal VC. The length of the delay chain can be shortened or lengthened compared to the middle tap 83 by means of corresponding switches 82 or 84. As a result, the output signal of the oscillator 61 is shifted by a negative or a positive time period with respect to a central position of a clock edge of its output signal. The switches 82, 84 are controlled by the proportional control signals PU and PD, the switch 85 is controlled when none of the signals PU, PD has a pulse. During the pulse pause of the signals PU, PD, the switch 85 is closed and the mean feedback length is set. This results in phase jumps dependent on the pulse duration in the output signal of the oscillator 61. The special design of the oscillator 61 shown in FIG. 4 responds very quickly to the control pulses, so that the control loop formed has a high loop gain for a large capture range of the oscillator.
Außerdem ist ein weiterer Oszillator 62 vorgesehen, der ebenfalls vom Integralsignal VC gesteuert wird. Der Oszillator 62 weist im Vergleich zum Oszillator 61 einen entsprechendenA further oscillator 62 is also provided, which is also controlled by the integral signal VC. The oscillator 62 has a corresponding one in comparison to the oscillator 61
Aufbau bei der mittleren Ringoszillatorlänge auf. Da die Oszillatoren 61, 62 vom gleichen Signal VC gesteuert werden, schwingen sie im wesentlichen bei der gleichen Frequenz. Der Oszillator 62 weist jedoch im Vergleich zum Oszillator 61 keinen Phasenjitter auf, da er nur vom Integralanteil, nicht aber vom Proportionalanteil des Regelkreises angesteuert wird. Am Ausgang des Oszillators 62 liegt deshalb das Ausgangssignal VO als jitterarmes Signal vor.Structure at the mean ring oscillator length. Since the oscillators 61, 62 are controlled by the same signal VC, they oscillate at essentially the same frequency. Compared to oscillator 61, however, oscillator 62 has no phase jitter, since it is only controlled by the integral component, but not by the proportional component of the control loop becomes. The output signal VO is therefore present at the output of the oscillator 62 as a low-jitter signal.
Aufgrund von Schwankungen der Bauelementeparameter der Oszil- latoren 61, 62 und aufgrund des l/f-Stromrauschens und des thermischen Rauschens entsteht zwischen den Oszillatoren 61, 62 allmählich ein geringer Frequenzunterschied. Das Stromrauschen überlagert sich hierbei dem Steuerstrom 81 (Figur 2) als statistisch unabhängige Störung. Um die Frequenzdifferenz auszuregeln, ist deshalb eine weiterere Phasendetektor- und Ladungspumpeneinrichtung 63 mit einem einen I-Anteil erzeugenden Element 64 vorgesehen, durch das der Oszillator 61 nachgestellt wird. Alternativ kann auch der Oszillator 62 nachgestellt werden. Um den Phasenunterschied zwischen den Oszillatoren 61, 62 beizubehalten bzw. um an den Eingängen der Einrichtung 63 den Phasenunterschied auszugleichen, ist ein Verzögerungsglied 65 vorgesehen, über welches das Ausgangssignal des Oszillators 61 in einen der Phasendetek- toreingänge der Einrichtung 63 eingekoppelt wird. Die Verzö- gerungszeit des Zeitgliedes 65 ist von der Einrichtung 63 vorzugsweise über ein Integralglied 66 einstellbar. In den anderen Phasendetektoreingang der Einrichtung 63 wird das Ausgangssignal VO entweder direkt oder über ein weiteres - nicht dargestelltes - einstellbares Verzögerungsglied einge- speist. Zweckmäßigerweise kann zusätzlich vorgesehen werden, daß die Nachstellung des Oszillators 61 und des Verzögerungε- glieds 65 vom Regler 63, 64 bzw. 66 abwechselnd durchgeführt wird. Zweckmäßigerweise wird während einer ersten Hälfte der durch den Teilerfaktor N im Teiler 9 erzeugten Periode des rückgekopppelten Signals VF der Schalter 67 eingeschaltet, während der zweiten Periode der Schalter 68. Das Verzögerungsglied 65 wird entsprechend dem Ringoszillator 61 ausgeführt mit einer steuerbaren, die Inverterkette versorgenden Stromquelle, jedoch ohne Rückkopplung. Due to fluctuations in the component parameters of the oscillators 61, 62 and due to the l / f current noise and the thermal noise, a slight frequency difference gradually arises between the oscillators 61, 62. The current noise is superimposed on the control current 81 (FIG. 2) as a statistically independent disturbance. In order to compensate for the frequency difference, a further phase detector and charge pump device 63 is therefore provided with an element 64 which generates an I component, by means of which the oscillator 61 is adjusted. Alternatively, the oscillator 62 can also be adjusted. In order to maintain the phase difference between the oscillators 61, 62 or to compensate for the phase difference at the inputs of the device 63, a delay element 65 is provided, via which the output signal of the oscillator 61 is coupled into one of the phase detector inputs of the device 63. The delay time of the timing element 65 can preferably be set by the device 63 via an integral element 66. The output signal VO is fed into the other phase detector input of the device 63 either directly or via another - not shown - adjustable delay element. Appropriately, provision can additionally be made for the readjustment of the oscillator 61 and the delay element 65 to be carried out alternately by the controller 63, 64 and 66. The switch 67 is expediently switched on during a first half of the period of the feedback signal VF generated by the divider factor N in the divider 9, and the switch 68 during the second period. The delay element 65 is designed in accordance with the ring oscillator 61 with a controllable current source which supplies the inverter chain , but without feedback.

Claims

Patentansprüche claims
1. Phasenregelkreis mit einem Phasendiskriminator (2), dem ein Referenzsignal (VI) zuführbar ist, einem vom Phasendiskriminator (2) ansteuerbaren Regler (3, 4), der einen Integralanteil (4) und einen Proportionalanteil (PU, PD) umfaßt, und einem vom Regler (3, 4) ansteuerbaren, frequenzsteuerbaren Oszillatormitteln (61, 62), durch die ein zum Referenz- signal synchrones Ausgangssignal (VO) erzeugbar ist, und die auf den Phasendiskriminator (2) rückgekoppelt sind, d a d u r c h g e k e n n z e i c h n e t, daß die Oszillatormittel einen ersten (62) und einen zweiten (61) frequenzsteuerbaren Oszillator umfassen, daß der erste Oszil- lator (62) nur vom Integralanteil (4) des Reglers (3, 4) ansteuerbar ist, daß am ersten Oszillator (62) das Ausgangs- signal (VO) abgreifbar ist, daß der zweite Oszillator (61) ausgangsseitig auf den Phasendiskriminator (2) rückgekoppelt ist und daß der zweite Oszillator (61) vom Proportionalanteil (PU, PD) und Integralanteil (4) des Reglers (3, 4) ansteuerbar ist.1. phase locked loop with a phase discriminator (2) to which a reference signal (VI) can be fed, a controller (3, 4) which can be controlled by the phase discriminator (2) and which comprises an integral component (4) and a proportional component (PU, PD), and a frequency controllable oscillator means (61, 62) which can be controlled by the controller (3, 4) and by means of which an output signal (VO) synchronous to the reference signal can be generated and which are fed back to the phase discriminator (2), characterized in that the oscillator means have a The first (62) and a second (61) frequency-controllable oscillator include that the first oscillator (62) can only be controlled by the integral part (4) of the controller (3, 4), that the output signal on the first oscillator (62) (VO) can be tapped that the second oscillator (61) on the output side is fed back to the phase discriminator (2) and that the second oscillator (61) has a proportional component (PU, PD) and integral component (4) of the controller (3, 4) a is controllable.
2. Phasenregelkreis nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß die Ausgänge des ersten und des zweiten Ozillators (62, 61) über Mittel zur Frequenznachführung (63, ..., 68) auf einen der Oszillatoren (61 bzw. 62) rückgekoppelt sind.2. Phase locked loop according to claim 1, so that the outputs of the first and the second oscillators (62, 61) are fed back to one of the oscillators (61 and 62) via means for frequency tracking (63, ..., 68).
3. Phasenregelkreis nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t , daß die Mittel zur Frequenznachführung einen weiteren Phasendiskriminator (63) enthalten, in den das Ausgangssignal des zweiten Oszillators (61) und das Ausgangssignal (VO) des ersten Oszillators (62) einkoppelbar sind, daß mindestens einem der Eingänge des weiteren Phasendiskriminators (63) ein weiteres Verzögerungsglied (65) vorgeschaltet ist, und daß durch den weiteren Phasendiskriminator (63) ausgangsseitig über je- weils einen weiteren Regler (63, 64, 66) der zweite oder der erste Oszillator (62, 61) bzw. das weitere Verzöger ngsglied (65) steuerbar sind.3. Phase locked loop according to claim 2, characterized in that the means for frequency tracking contain a further phase discriminator (63) into which the output signal of the second oscillator (61) and the output signal (VO) of the first oscillator (62) can be coupled in that at least one A further delay element (65) is connected upstream of the inputs of the further phase discriminator (63), and that the other phase discriminator (63) because another controller (63, 64, 66) the second or the first oscillator (62, 61) or the further delay element (65) can be controlled.
4. Phasenregelkreis nach Anspruch 3 , d a d u r c h g e k e n n z e i c h n e t, daß das weitere Verzögerungsglied (65) und der zweite Oszillator (61) durch die weiteren Regler (63, 64, 66) abwechselnd steuerbar sind.4. phase locked loop according to claim 3, d a d u r c h g e k e n n z e i c h n e t that the further delay element (65) and the second oscillator (61) can be controlled alternately by the further controller (63, 64, 66).
5. Phasenregelkreis nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß der zweite Oszillator (61) ein eine Verzögerungskette (80) umfassender Ringoszillator ist, deren Kettenlänge vom Propor- tionalanteil (PU, PD) des Reglers (3, 4) veränderbar ist.5. phase locked loop according to one of claims 1 to 4, characterized in that the second oscillator (61) is a delay chain (80) comprising ring oscillator, the chain length of the proportional portion (PU, PD) of the controller (3, 4) is variable .
6. Phasenregelkreis nach Anspruch 5, d a d u r c h g e k e n n z e i c h n e t, daß der Phasendiskriminator (2) einen ersten Impuls (PU) abgibt, wenn das rückgekoppelte Signal (VF) dem Referenzsignal (VI) nacheilt, und einen zweiten Impuls (PD) , wenn das rückgekoppelte Signal (VF) dem Referenzsignal (VI) voreilt, daß die Verzögerungskette (80) des zweiten Oszillators (61) durch den ersten Impuls (PU) verkürzt und durch den zweiten Impuls (PD) verlängert wird und daß zur frequenzmäßigen Steuerung der Oszillatoren (61, 62) eine vom Phasendiskriminator (2) ansteuerbare Ladungspumpe (3) vorgesehen ist, durch die ein Kondensator (4) auf- und entladbar ist. 6. phase locked loop according to claim 5, characterized in that the phase discriminator (2) emits a first pulse (PU) when the feedback signal (VF) lags the reference signal (VI), and a second pulse (PD) when the feedback signal ( VF) leads the reference signal (VI) that the delay chain (80) of the second oscillator (61) is shortened by the first pulse (PU) and lengthened by the second pulse (PD) and that the frequency control of the oscillators (61, 62 ) a charge pump (3) which can be controlled by the phase discriminator (2) and through which a capacitor (4) can be charged and discharged is provided.
PCT/DE1997/001908 1996-09-04 1997-09-01 Low-jitter phase-locking loop WO1998010519A1 (en)

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