US20010011752A1 - High-voltage device and method for manufacturing high-voltage device - Google Patents
High-voltage device and method for manufacturing high-voltage device Download PDFInfo
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- US20010011752A1 US20010011752A1 US09/792,571 US79257101A US2001011752A1 US 20010011752 A1 US20010011752 A1 US 20010011752A1 US 79257101 A US79257101 A US 79257101A US 2001011752 A1 US2001011752 A1 US 2001011752A1
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- 238000000034 method Methods 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000005684 electric field Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Definitions
- the present invention relates to a semiconductor and a method for manufacturing a semiconductor. More particularly, the present invention relates to a high-voltage device and a method for manufacturing a high-voltage device.
- a high voltage device is one of the most important devices utilized in a highly integrated circuit.
- Erasable programmable read only memory (EPROM) and flash memory are two of the high-voltage devices most often used in computers and electronic products.
- the formation of an isolation layer is used for the purpose of increasing the channel length.
- the high-voltage device is able to work normally at a high electrical voltage.
- FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage device.
- a field oxide layer 102 is located on a P-type substrate 100 .
- a gate oxide layer 103 is located on the P-type silicon substrate 100 .
- a gate electrode 104 is located on the field oxide layer 102 and the gate oxide layer 103 .
- a source region 106 and a drain region 108 are located in the P-type substrate 100 .
- An N ⁇ -type doped region 112 is located in the substrate beneath the drain region 108 , the field oxide layer 102 and a portion of the gate electrode 104 .
- a P-type doped region 114 is located under the source region 106 and a portion of the gate electrode 104 .
- the dopant concentration of the drift region which is the dopant concentration of the N ⁇ -type doped region 112 .
- the current-driving performance and the channel conductivity between the source region 106 and the drain region 108 under the gate electrode 104 in the substrate 100 are decreased.
- the invention provides a high-voltage device constructed on a substrate having a first conductive type.
- the high-voltage device comprise a first well region with the first conductive type, a second well region with a second conductive type, several field oxide layers, several first doped regions with the second conductive type, a shallow trench isolation, a second doped region with the first conductive type, a third well region with the first conductive type, a gate structure, a source region with the second conductive type and a drain region with the second conductive type.
- the first well region is located in the substrate and the second well region is also located in the substrate but isolated from the first well region.
- Several field oxide layers are located on a surface of the second well region.
- One of the field oxide layers is positioned on the margin of the second well region near the first well region.
- the shallow trench isolation is located between the field oxide layers in the second well region.
- the first doped regions are located beneath the field oxide layers.
- the second doped region is located beneath the shallow trench isolation in the second well region.
- the third well region is located in the first well region and expands from a surface of the first well region into the first well region.
- the gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.
- the source region the drain region are relatively located in the first and the second well regions exposed by the gate structure and the field oxide layers.
- the invention also provides a method for forming a high-voltage device.
- a substrate having a first conductive type is provided.
- a first well region with the first conductive type is formed in the substrate.
- a second well region with a second conductive type is formed in the substrate.
- a pad oxide layer and a patterned silicon nitride layer are formed on the substrate in sequence.
- Several first doped regions with the second conductive type are formed in the second well region under portions of the pad oxide layer exposed by the patterned silicon nitride layer.
- Several field oxide layers are formed on the portions of the pad oxide layer above the first doped regions.
- the patterned silicon nitride layer and the pad oxide layer are removed.
- a shallow trench isolation is formed in the second well region between the field oxide layers.
- a third well region with the first conductive type is formed in the first well region while a second doped region with the first conductive type is formed in the second well region beneath the shallow trench isolation.
- a gate structure is formed on the substrate between the first and second well regions and laterally expands to cover a portion of the first and the third well regions and the field oxide layer.
- a source with the second conductive type and a drain with the second conductive type are respectively formed in the third well region and the second well region exposed by the gate structure and the field oxide layer.
- the second conductive type when the first conductive type is N-type, the second conductive type is P-type. Simultaneously, when the first conductive type is P-type, the second conductive type is N-type. Incidentally, a dosage of the third well region is higher than that of the first well region.
- a depletion region exists between the second doped region and the second well region. Furthermore, the dosage of the second well region is lower than that of the conventional N ⁇ -type doped region 112 . Therefore, it can provide a bulk breakdown around the drain region.
- FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage device
- FIGS. 2A through 2D are schematic, cross-sectional views of the process for manufacturing a high-voltage device in a preferred embodiment according to the invention.
- FIGS. 2A through 2D are schematic, cross-sectional views of the process for manufacturing a high-voltage device in a preferred embodiment according to the invention.
- a substrate 200 a with a first conductive type and a substrate 200 b with a second conductive type are provided.
- the substrate 200 a can be a P-type substrate or a P-type well and the substrate 200 b can be an N-type substrate or an N-type well, for example.
- the combination between the substrate 200 a and the substrate 200 b is either the combination of a P-type substrate with an N-type well or the combination of a P-type well with an N-type substrate.
- An ion implantation process is performed to form well regions 202 a and 202 b with the first conductive type respectively in the substrate 200 a and the substrate 200 b.
- Each dosage of the well regions 202 a and 202 b is about 1 ⁇ 10 12 -1 ⁇ 10 13 atoms/cm 2 .
- An ion implantation is performed to form well regions 204 a and 204 b with the second conductive type respectively in the substrate 200 a and the substrate 200 b .
- the dosages of the well regions 204 a and 204 b are each about 1 ⁇ 10 12 -1 ⁇ 10 13 atoms/cm 2 .
- the dosages of the well regions 204 a and 202 b are lower than that of the conventional N ⁇ -type doped region 112 (as shown in FIG. 1).
- a drive-in process is performed.
- a pad oxide layer 206 and a patterned silicon nitride layer 208 are formed in sequence over the substrates 200 a and 200 b .
- the patterned silicon nitride layer 208 exposes portions of the pad oxide layer 206 above the well regions 204 a and 202 b .
- the exposed portions of the pad oxide layer 206 are used to form field oxide layer in the subsequent process.
- a doped region 210 a with the second conductive type and a doped region 210 b with the first conductive type are respectively formed in the well regions 204 a and 202 b under the exposed portions of the pad oxide layer 206 .
- the dosages of the doped regions 210 a and 210 b are each about 1 ⁇ 10 12 -1 ⁇ 10 14 atoms/cm 2 .
- Field oxide layers 212 a and 212 b are respectively formed on the doped regions 210 a and 210 b .
- One of the field oxide layers 212 a is located over the well region 204 a and near the margin of the well region 202 a .
- one of the field oxide layers 210 b is located over the well region 202 b and near the margin of the well region 204 b.
- the patterned silicon nitride layer 208 and the pad oxide layer 206 are removed in sequence.
- Trenches 215 a and 215 b are respectively formed in the substrate 200 a between the field oxide layers 210 a and in the substrate 200 b between the field oxide layers 210 b.
- An oxide layer 214 is formed over the substrates 200 a and 200 b. Portions of the oxide layer 214 respectively located in the trenches 215 a and 215 b are respectively denoted as linear layers 214 a and 214 b.
- the method for forming the oxide layer 214 can be thermal oxidation and the thickness of the oxide layer 214 is about 100-500 angstroms.
- Oxide layers 216 a and 216 b are formed in the trenches 215 a and 215 b and fill the trenches 215 a and 215 b.
- the oxide layers 216 a and 216 b are used as shallow trench isolations.
- the method in the formation of the shallow trench isolations 216 a and 216 b comprises the steps of forming an oxide layer (not shown) on the oxide layer 214 with a thickness of about 5000-9000 angstroms by atmospheric pressure chemical vapor deposition (APCVD), and then performing a densification process to reinforce the compactness of the oxide layer in the trenches 215 a and 215 b.
- the densification process is performed at a temperature of about 1000 centigrade for 10-30 minutes.
- a chemical-mechanical polishing (CMP) is performed to remove a portion of the oxide layer, thereby to expose the surface of the oxide layer 214 and to form the oxide layers 216 a and 216 b.
- CMP chemical-mechanical polishing
- a well region 218 a with the first conductive type is formed in the well region 202 a while a doped region 218 b with the first conductive type is formed in the well region 204 a under the shallow trench isolation 216 a.
- the dosages of the well region 218 a and the doped region 218 b are each about 1 ⁇ 10 13 -1 ⁇ 10 14 atoms/cm 2 .
- the well region 218 a expands from the surface of the well region 202 a into the well region 202 a and merges with a portion of the well region 202 a.
- the dosage of the doped region 218 a is higher than that of the well region 202 a.
- a well region 220 a with the second conductive type is formed in the well region 204 b while a doped region 220 b with the second conductive type is formed in the well region 202 b under the shallow trench isolation 216 b .
- the dosages of the well region 220 a and doped region 220 b are each about 1 ⁇ 10 13 -1 ⁇ 10 14 atoms/cm 2 .
- the well region 220 a expands from the surface of the well region 204 b into the well region 204 b and merges with a portion of the well region 204 b.
- the dosage of the doped region 220 a is higher than that of the well region 204 b.
- an oxide layer (not shown) and a conductive layer (not shown) are formed over the substrates 200 a and 200 b.
- the conductive layer, the oxide layer and the oxide layer 214 layer are patterned to form a gate electrode 222 a and a gate oxide layer 214 c on the substrate 200 a and to form a gate electrode 222 b and a gate oxide layer 214 d on the substrate 200 b .
- the patterned conductive layer is transformed into the gate electrodes 222 a and 222 b and the patterned oxide layer and the patterned oxide layer 214 together form the gate oxide layers 214 c and 214 d .
- the gate structure constructed by the gate electrode 222 a and the gate oxide layer 214 c is located on the substrate 200 a between the well regions 202 a and 204 a and laterally expands over portions of the well regions 202 a , 218 a and the field oxide layer 212 a .
- the gate structure constructed by the gate electrode 222 b and the gate oxide layer 214 d are located on the substrate 200 b between the well regions 202 b and 204 b and laterally expands over portions of the well regions 204 b , 220 a and the field oxide layer 212 b.
- a source region 224 a with the second conductive type and a drain region 224 b with the second conductive type are respectively formed in the well regions 218 a and 204 a exposed by the gate structure and the field oxide layer 212 a.
- the dosages of the source region 224 a and the drain region 224 b are each about 1 ⁇ 10 15 atoms/cm 2 -1 ⁇ 10 16 atoms/cm 2 .
- Each dosage of the source region 224 a and the drain region 224 b is higher than those of the well regions 202 a and 204 a.
- a source region 226 a with the first conductive type and a drain region 226 b with the first conductive type are respectively formed in the well regions 220 a and 202 b exposed by the gate structure and the field oxide layer 212 b . Therefore, the manufacturing process for forming the high-voltage device is finished.
- the dosages of the source region 226 a and the drain region 226 b are each about 1 ⁇ 10 15 atoms/cm 2 -1 ⁇ 10 16 atoms/cm 2 .
- Each dosage of the source region 226 a and the drain region 226 b is higher than those of the well regions 202 b and 204 b.
- the second conductive type is P-type.
- the first conductive type is N-type
- the second conductive type is N-type.
- the method according to the invention not only can be applied in the formation of a single-type MOS, such as NMOS or PMOS, but also can be applied in the formation of a complementary metal-oxide semiconductor (CMOS).
- CMOS complementary metal-oxide semiconductor
- the well region 202 a with the first conductive type and the well region 204 a with the second conductive type isolated from the well region 202 a are located in the substrate 200 a with the first conductive type.
- Several field oxide layers 212 a are located on the surface of the well region 204 a and one of the field oxide layer 212 a is positioned on the margin of the well region 204 a near the well region 202 a.
- the shallow trench isolation 216 a is located between the field oxide layers 212 a in the well region 204 a .
- the doped region 210 a with the second conductive type is located beneath the field oxide layers 210 a and the doped region 218 b with the first conductive type is located beneath the shallow trench isolation 216 a in the well region 204 a.
- the well region 218 a with the first conductive type located in the well region 202 a expands from the surface of the well region 202 a into the well region 202 a.
- the gate structure is positioned on the substrate 200 a between the well regions 202 a and 204 a and covers over a portion of the well regions 202 a, 218 a and the field oxide layer 212 a .
- the source region 224 a with the second conductive type and the drain region 224 b with the second conductive type are respectively located in the well regions 218 a and 204 a exposed by the gate structure and the field oxide layer 212 a.
- each dosage of the well regions 204 a and 202 b is lower than that of the conventional N ⁇ -type doped region 112 . Therefore, it can provide a bulk breakdown around the drain regions 224 b and 226 b.
Abstract
A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers. A source region with the second conductive type and a drain region with the second conductive type are respectively located in the third and the second well regions exposed by the gate structure and the field oxide layers.
Description
- 1. Field of Invention
- The present invention relates to a semiconductor and a method for manufacturing a semiconductor. More particularly, the present invention relates to a high-voltage device and a method for manufacturing a high-voltage device.
- 2. Description of Related Art
- A high voltage device is one of the most important devices utilized in a highly integrated circuit. Erasable programmable read only memory (EPROM) and flash memory are two of the high-voltage devices most often used in computers and electronic products.
- Due to the increasing number of semiconductor devices incorporated in integrated circuits, the size of transistors needs to be decreased. Accordingly, as the channel length of the transistors is decreased, the operating speed is increased. However, the short channel effect caused by the reduced channel length is becoming serious. If the voltage level is fixed as the channel length is shortened, the strength of the electrical field is increased according to the equation, electrical field=electrical voltage/channel length. Thus, as the strength of the electrical field increases, the energy of electrons increases and electrical breakdown is likely to occur.
- In the conventional high-voltage device, the formation of an isolation layer is used for the purpose of increasing the channel length. Hence, the high-voltage device is able to work normally at a high electrical voltage.
- FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage device. As shown in FIG. 1, a
field oxide layer 102 is located on a P-type substrate 100. Agate oxide layer 103 is located on the P-type silicon substrate 100. Agate electrode 104 is located on thefield oxide layer 102 and thegate oxide layer 103. Asource region 106 and adrain region 108 are located in the P-type substrate 100. An N−-type dopedregion 112 is located in the substrate beneath thedrain region 108, thefield oxide layer 102 and a portion of thegate electrode 104. A P-type dopedregion 114 is located under thesource region 106 and a portion of thegate electrode 104. - In order to increase the breakdown voltage of the high-voltage device, it is necessary to decrease the dopant concentration of the drift region, which is the dopant concentration of the N−-type doped
region 112. However, the current-driving performance and the channel conductivity between thesource region 106 and thedrain region 108 under thegate electrode 104 in thesubstrate 100 are decreased. - Additionally, when the manufacturing technique is promoted to a sub-quarter micron level, for example, a line width of 0.18 microns or less, it is difficult to decrease the typical design rule of the high-voltage device.
- The invention provides a high-voltage device constructed on a substrate having a first conductive type. The high-voltage device comprise a first well region with the first conductive type, a second well region with a second conductive type, several field oxide layers, several first doped regions with the second conductive type, a shallow trench isolation, a second doped region with the first conductive type, a third well region with the first conductive type, a gate structure, a source region with the second conductive type and a drain region with the second conductive type. The first well region is located in the substrate and the second well region is also located in the substrate but isolated from the first well region. Several field oxide layers are located on a surface of the second well region. One of the field oxide layers is positioned on the margin of the second well region near the first well region. The shallow trench isolation is located between the field oxide layers in the second well region. The first doped regions are located beneath the field oxide layers. The second doped region is located beneath the shallow trench isolation in the second well region. The third well region is located in the first well region and expands from a surface of the first well region into the first well region. The gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers. The source region the drain region are relatively located in the first and the second well regions exposed by the gate structure and the field oxide layers.
- The invention also provides a method for forming a high-voltage device. A substrate having a first conductive type is provided. A first well region with the first conductive type is formed in the substrate. A second well region with a second conductive type is formed in the substrate. A pad oxide layer and a patterned silicon nitride layer are formed on the substrate in sequence. Several first doped regions with the second conductive type are formed in the second well region under portions of the pad oxide layer exposed by the patterned silicon nitride layer. Several field oxide layers are formed on the portions of the pad oxide layer above the first doped regions. The patterned silicon nitride layer and the pad oxide layer are removed. A shallow trench isolation is formed in the second well region between the field oxide layers. A third well region with the first conductive type is formed in the first well region while a second doped region with the first conductive type is formed in the second well region beneath the shallow trench isolation. A gate structure is formed on the substrate between the first and second well regions and laterally expands to cover a portion of the first and the third well regions and the field oxide layer. A source with the second conductive type and a drain with the second conductive type are respectively formed in the third well region and the second well region exposed by the gate structure and the field oxide layer.
- In the method described above, when the first conductive type is N-type, the second conductive type is P-type. Simultaneously, when the first conductive type is P-type, the second conductive type is N-type. Incidentally, a dosage of the third well region is higher than that of the first well region.
- In the invention, around the source region, the first well region contains the third well region. Since the dosage of the third well region is higher than that of the first well region, the depletion region existing between the first and the third well regions is relatively small. According to the equation of electrical field=electrical voltage/channel length, the relatively small depletion region possesses a relatively high electric field. Hence, the conductivity and the electric-field intensity of the high-voltage device are increased. Therefore, the current-driving performance is increased.
- Moreover, around the drain region, a depletion region exists between the second doped region and the second well region. Furthermore, the dosage of the second well region is lower than that of the conventional N−-type doped
region 112. Therefore, it can provide a bulk breakdown around the drain region. - It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
- FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage device; and
- FIGS. 2A through 2D are schematic, cross-sectional views of the process for manufacturing a high-voltage device in a preferred embodiment according to the invention.
- FIGS. 2A through 2D are schematic, cross-sectional views of the process for manufacturing a high-voltage device in a preferred embodiment according to the invention.
- As shown in FIG. 2A, a
substrate 200 a with a first conductive type and asubstrate 200 b with a second conductive type are provided. Thesubstrate 200 a can be a P-type substrate or a P-type well and thesubstrate 200 b can be an N-type substrate or an N-type well, for example. In the manufacturing process for forming a CMOS, the combination between thesubstrate 200 a and thesubstrate 200 b is either the combination of a P-type substrate with an N-type well or the combination of a P-type well with an N-type substrate. An ion implantation process is performed to form wellregions substrate 200 a and thesubstrate 200 b. Each dosage of thewell regions - An ion implantation is performed to form well
regions substrate 200 a and thesubstrate 200 b. The dosages of thewell regions well regions pad oxide layer 206 and a patternedsilicon nitride layer 208 are formed in sequence over thesubstrates silicon nitride layer 208 exposes portions of thepad oxide layer 206 above thewell regions pad oxide layer 206 are used to form field oxide layer in the subsequent process. - A doped
region 210 a with the second conductive type and a dopedregion 210 b with the first conductive type are respectively formed in thewell regions pad oxide layer 206. The dosages of the dopedregions regions well region 204 a and near the margin of thewell region 202 a. Moreover, one of the field oxide layers 210 b is located over thewell region 202 b and near the margin of thewell region 204 b. - As shown in FIG. 2B, the patterned
silicon nitride layer 208 and thepad oxide layer 206 are removed in sequence.Trenches substrate 200 a between the field oxide layers 210 a and in thesubstrate 200 b between the field oxide layers 210 b. Anoxide layer 214 is formed over thesubstrates oxide layer 214 respectively located in thetrenches linear layers oxide layer 214 can be thermal oxidation and the thickness of theoxide layer 214 is about 100-500 angstroms. - Oxide layers216 a and 216 b are formed in the
trenches trenches shallow trench isolations oxide layer 214 with a thickness of about 5000-9000 angstroms by atmospheric pressure chemical vapor deposition (APCVD), and then performing a densification process to reinforce the compactness of the oxide layer in thetrenches oxide layer 214 and to form the oxide layers 216 a and 216 b. - As shown in FIG. 2C, a
well region 218 a with the first conductive type is formed in thewell region 202 a while a dopedregion 218 b with the first conductive type is formed in thewell region 204 a under theshallow trench isolation 216 a. The dosages of thewell region 218 a and the dopedregion 218 b are each about 1×1013-1×1014 atoms/cm2. Additionally, thewell region 218 a expands from the surface of thewell region 202 a into thewell region 202 a and merges with a portion of thewell region 202 a. In the invention, the dosage of the dopedregion 218 a is higher than that of thewell region 202 a. - A
well region 220 a with the second conductive type is formed in thewell region 204 b while a dopedregion 220 b with the second conductive type is formed in thewell region 202 b under theshallow trench isolation 216 b. The dosages of thewell region 220 a and dopedregion 220 b are each about 1×1013-1×1014 atoms/cm2. Additionally, thewell region 220 a expands from the surface of thewell region 204 b into thewell region 204 b and merges with a portion of thewell region 204 b. In the invention, the dosage of the dopedregion 220 a is higher than that of thewell region 204 b. - As shown in FIG. 2D, an oxide layer (not shown) and a conductive layer (not shown) are formed over the
substrates oxide layer 214 layer are patterned to form agate electrode 222 a and agate oxide layer 214 c on thesubstrate 200 a and to form agate electrode 222 b and agate oxide layer 214 d on thesubstrate 200 b. The patterned conductive layer is transformed into thegate electrodes oxide layer 214 together form the gate oxide layers 214 c and 214 d. The gate structure constructed by thegate electrode 222 a and thegate oxide layer 214 c is located on thesubstrate 200 a between thewell regions well regions field oxide layer 212 a. The gate structure constructed by thegate electrode 222 b and thegate oxide layer 214 d are located on thesubstrate 200 b between thewell regions well regions field oxide layer 212 b. - A
source region 224 a with the second conductive type and adrain region 224 b with the second conductive type are respectively formed in thewell regions field oxide layer 212 a. The dosages of thesource region 224 a and thedrain region 224 b are each about 1×1015 atoms/cm2-1×1016 atoms/cm2. Each dosage of thesource region 224 a and thedrain region 224 b is higher than those of thewell regions - A
source region 226 a with the first conductive type and adrain region 226 b with the first conductive type are respectively formed in thewell regions field oxide layer 212 b. Therefore, the manufacturing process for forming the high-voltage device is finished. The dosages of thesource region 226 a and thedrain region 226 b are each about 1×1015 atoms/cm2-1×1016 atoms/cm2. Each dosage of thesource region 226 a and thedrain region 226 b is higher than those of thewell regions - Notably, when the first conductive type is N-type, the second conductive type is P-type. Simultaneously, when the first conductive type is P-type, the second conductive type is N-type. The method according to the invention not only can be applied in the formation of a single-type MOS, such as NMOS or PMOS, but also can be applied in the formation of a complementary metal-oxide semiconductor (CMOS).
- In the invention, the
well region 202 a with the first conductive type and thewell region 204 a with the second conductive type isolated from thewell region 202 a are located in thesubstrate 200 a with the first conductive type. Several field oxide layers 212 a are located on the surface of thewell region 204 a and one of thefield oxide layer 212 a is positioned on the margin of thewell region 204 a near thewell region 202 a. Theshallow trench isolation 216 a is located between the field oxide layers 212 a in thewell region 204 a. The dopedregion 210 a with the second conductive type is located beneath the field oxide layers 210 a and the dopedregion 218 b with the first conductive type is located beneath theshallow trench isolation 216 a in thewell region 204 a. Thewell region 218 a with the first conductive type located in thewell region 202 a expands from the surface of thewell region 202 a into thewell region 202 a. The gate structure is positioned on thesubstrate 200 a between thewell regions well regions field oxide layer 212 a. Additionally, thesource region 224 a with the second conductive type and thedrain region 224 b with the second conductive type are respectively located in thewell regions field oxide layer 212 a. - Around the
source regions well regions well regions well region 218 a is larger than that of thewell region 202 a and the dosage of thewell region 220 a is larger than that of thewell region 204 b, the depletion regions existing respectively between thewell regions well regions - Moreover, around the
drain regions region 218 b and thewell region 204 a and between the dopedregion 220 b and thewell region 202 b. Furthermore, each dosage of thewell regions region 112. Therefore, it can provide a bulk breakdown around thedrain regions - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (29)
1. A high-voltage device constructed on a substrate having a first conductive type, the high-voltage device comprising:
a first well region with the first conductive type located in the substrate;
a second well region with the second conductive type located in the substrate and isolated from the first well region;
a plurality of field oxide layers located on a surface of the second well region;
a shallow trench isolation located between the field oxide layers in the second well region;
a first doped region with the second conductive type located beneath the field oxide layers;
a second doped region with the first conductive type located beneath the shallow trench isolation in the second well region;
a third well region with the first conductive type located in the first well region, wherein the third well region expands from a surface of the first well region into the first well region;
a gate structure positioned on the substrate between the first and the second well regions, wherein the gate structure covers a portion of the first, the third well regions and the field oxide layers;
a source region with the second conductive type located in the third well region exposed by the gate structure; and
a drain region with the second conductive type located in the second well region exposed by the gate structure and the field oxide layers.
2. The high-voltage device of , wherein when the first conductive type is N-type, the second conductive type is P-type.
claim 1
3. The high-voltage device of , wherein when the first conductive type is P-type, the second conductive type is N-type.
claim 1
4. The high-voltage device of , wherein a dosage of the first well region is about 1×1012-1×1013 atoms/cm2.
claim 1
5. The high-voltage device of , wherein a dosage of the second well region is about 1×1012-1×1013 atoms/cm2.
claim 1
6. The high-voltage device of , wherein a dosage of the third well region is about 1×1013-1×1014 atoms/cm2.
claim 1
7. The high-voltage device of , wherein a dosage of the third well region is higher than that of the first well region.
claim 1
8. The high-voltage device of , wherein a dosage of the first doped region is about 1×1012-1×1014 atoms/cm2.
claim 1
9. The high-voltage device of , wherein a dosage of the second doped region is about 1×1013-1×1014 atoms/cm2.
claim 1
10. A method for manufacturing a high-voltage device, comprising the steps of:
providing a P-type substrate and an N-type substrate;
forming a first P-type well region and a second P-type well region respectively in the P-type substrate and the N-type substrate;
forming a first N-type well region and a second N-type well region respectively in the P-type substrate and the N-type substrate;
forming a plurality of first field oxide layers and a plurality of second oxide layers respectively on the first N-type well region and the second P-type well region, wherein each of the first field oxide layers possesses a first N-type doped region beneath the first field oxide layer and each of the second field oxide layers possesses a first P-type doped region beneath the second field oxide layer;
forming a first and a second shallow trench isolations respectively in the first N-type well region between the first field oxide layers and in the second P-type well region between the second field oxide layers;
forming a third P-type well region in the first P-type well region while a second P-type doped region is formed in the first N-type well region beneath the first shallow trench isolation;
forming a third N-type well region in the second N-type well region while a second N-type doped region is formed in the second P-type well region beneath second the shallow trench isolation;
forming a first and a second gate structures respectively on the P-type substrate between the first P-type and the first N-type regions and on the N-type substrate between the second N-type and the second P-type well regions, wherein the first gate structure laterally expands to cover a portion of the first and the third P-type well regions and the first field oxide layer and the second gate structure laterally expands to cover a portion of the second and the third N-type well regions and the field second oxide layer;
forming an N-type source and an N-type drain respectively in the third P-type well region and the first N-type well region exposed by the first gate structure and the first field oxide layer; and
forming a P-type source and a P-type drain respectively in the third N-type well region and the second P-type well region exposed by the second gate structure and the second field oxide layer.
11. The method of , wherein a dosage of the third P-type well region is about 1×1013-1×1014atoms/cm2.
claim 10
12. The method of , wherein a dosage of the third N-type well region is about 1×1013-1×1014atoms/cm2.
claim 10
13. The method of , wherein dosages of the first and the second P-type well regions are each about 1×1012-1×1013 atoms/cm2.
claim 10
14. The method of , wherein dosages of the first and the second N-type well regions are each about 1×1012-1×1013 atoms/cm2.
claim 10
15. The method of , wherein a dosage of the second P-type doped region is about 1×1013-1×1014 atoms/cm2.
claim 10
16. The method of , wherein a dosage of the second N-type well region is about 1×1013-1×1014 atoms/cm2.
claim 10
17. The method of , wherein a dosage of the third P-type well region is higher than that of the first P-type well region.
claim 10
18. The method of , wherein a dosage of the third N-type well region is higher than that of the second N-type well region.
claim 10
19. The method of , wherein a dosage of the first N-type doped region is about 1×1012-1×1014 atoms/cm2.
claim 10
20. The method of , wherein a dosage of the first P-type doped region is about 1×1012-1×1014 atoms/cm2.
claim 10
21. A method for forming a high-voltage device, comprising the steps of:
providing a substrate having a first conductive type;
forming a first well region with the first conductive type in the substrate;
forming a second well region with a second conductive type in the substrate;
forming a pad oxide layer and a patterned silicon nitride layer on the substrate in sequence;
forming a plurality of first doped regions with the second conductive type respectively in the second well region under portions of the pad oxide layer exposed by the patterned silicon nitride layer;
forming a plurality of field oxide layers respectively on portions of the pad oxide layer above the first doped regions;
removing the patterned silicon nitride layer and the pad oxide layer;
forming a shallow trench isolation in the second well region between the field oxide layers;
forming a third well region with the first conductive type in the first well region while a second doped region with the first conductive type is formed in the second well region beneath the shallow trench isolation;
forming a gate structure on the substrate between the first and second well regions, wherein the gate structure laterally expands to cover a portion of the first well region, the third well region, and the field oxide layer; and
forming a source with the second conductive type and a drain with the second conductive type respectively in the third well region and the second well region exposed by the gate structure and the field oxide layer.
22. The method of , wherein when the first conductive type is N-type, the second conductive type is P-type.
claim 1
23. The method of , wherein when the first conductive type is P-type, the second conductive type is N-type.
claim 1
24. The method of , wherein a dosage of the first well region is about 1×1012-1×1013 atoms/cm2.
claim 1
25. The method of , wherein a dosage of the second well region is about 1×1012-1×1013 atoms/cm2.
claim 1
26. The method of , wherein a dosage of the third well region is about 1×1013-1×1014 atoms/cm2.
claim 1
27. The method of , wherein a dosage of the third well region is higher than that of the first well region.
claim 1
28. The method of , wherein a dosage of the first doped region is about 1×1012-1×1014 atoms/cm2.
claim 1
29. The method of , wherein a dosage of the second doped region is about 1×1013-1×1014 atoms/cm2.
claim 1
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JP4030257B2 (en) * | 2000-08-14 | 2008-01-09 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
JP2002237575A (en) * | 2001-02-08 | 2002-08-23 | Sharp Corp | Semiconductor device and its manufacturing method |
US6501139B1 (en) * | 2001-03-30 | 2002-12-31 | Matrix Semiconductor, Inc. | High-voltage transistor and fabrication process |
US6720223B2 (en) | 2002-04-30 | 2004-04-13 | Hewlett-Packard Development Company, L.P. | Power |
US6800497B2 (en) | 2002-04-30 | 2004-10-05 | Hewlett-Packard Development Company, L.P. | Power switching transistor and method of manufacture for a fluid ejection device |
JP4346322B2 (en) * | 2003-02-07 | 2009-10-21 | 株式会社ルネサステクノロジ | Semiconductor device |
CN1591800A (en) * | 2003-09-01 | 2005-03-09 | 上海宏力半导体制造有限公司 | Method for mfg. improed structure high-voltage elements |
US7122876B2 (en) * | 2004-08-11 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation-region configuration for integrated-circuit transistor |
US20060108641A1 (en) * | 2004-11-19 | 2006-05-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having a laterally graded well structure and a method for its manufacture |
CN100428473C (en) * | 2006-11-02 | 2008-10-22 | 崇贸科技股份有限公司 | Semiconductor structure of high voltage side drive and its manufacturing method |
CN101320752B (en) * | 2007-06-06 | 2010-08-11 | 旺宏电子股份有限公司 | Lateral diffusion metal-oxide-semiconductor element with low opening resistor and manufacturing method thereof |
US8017486B2 (en) * | 2007-06-22 | 2011-09-13 | Macronix International Co., Ltd. | Method of fabricating low on-resistance lateral double-diffused MOS device |
US9171726B2 (en) * | 2009-11-06 | 2015-10-27 | Infineon Technologies Ag | Low noise semiconductor devices |
US9343538B2 (en) * | 2011-05-13 | 2016-05-17 | Richtek Technology Corporation | High voltage device with additional isolation region under gate and manufacturing method thereof |
KR101291751B1 (en) * | 2011-12-29 | 2013-07-31 | 주식회사 동부하이텍 | Semiconductor device and method for fabricating the same |
CN106158957B (en) | 2015-04-10 | 2019-05-17 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor field effect pipe and its manufacturing method |
CN107785367B (en) * | 2016-08-31 | 2021-10-15 | 无锡华润上华科技有限公司 | Device integrated with depletion type junction field effect transistor and manufacturing method thereof |
US10833206B2 (en) | 2018-12-11 | 2020-11-10 | Micron Technology, Inc. | Microelectronic devices including capacitor structures and methods of forming microelectronic devices |
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US5047358A (en) * | 1989-03-17 | 1991-09-10 | Delco Electronics Corporation | Process for forming high and low voltage CMOS transistors on a single integrated circuit chip |
US5670816A (en) * | 1989-04-07 | 1997-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5548147A (en) * | 1994-04-08 | 1996-08-20 | Texas Instruments Incorporated | Extended drain resurf lateral DMOS devices |
KR100202635B1 (en) * | 1995-10-13 | 1999-06-15 | 구본준 | Resurf edmos transistor and high voltage analog multiplex circuit using the same |
US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
US5976923A (en) * | 1998-12-08 | 1999-11-02 | United Microelectronics Corp. | Method for fabricating a high-voltage semiconductor device |
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