經濟部智慧財產局員工消費合作社印製 148573 5 529tuf.doc/006 A/ B7 五、發明説明（1) 本發明是有關於一種積體電路之結構與製造方法，且 特別是有關於一種高壓元件與其製造方法。 一般在積體電路元件中，會包括有一些高壓元件，例 如可編程唯讀記憶體（Electrically Programmable .Read-Only Memory ; EPROM)或是快問記億體（Flash Memory)，就是屬於一種高壓元件。 當金氧半元件尺寸日益縮小時，隨之縮短的通道長度 會使得電晶體的操作速度變快。但因通道縮短而衍生的短 通道效應（Short Channe丨Effect)亦相對日益嚴重。根據 電場=電壓/長度的公式可以得知，若施加的電壓不變，而 電晶體的通道長度縮短，通道的電場強度將因而增加，而 使通道內之電子的能量受此電場的加速而提升，進而增加 電崩潰（Electrical Breakdown)的現象。 一般爲了避免高壓金氧半元件短通道效應，主要是利 用隔離層的形成，以藉由源極/汲極和閘極之間距離的增 加，達到降低通道內橫向電場之目的，使金氧半元件在高 電壓的操作之下，仍能正常運作。 請參照第1圖，其繪示爲習知的一種高壓元件之結構 剖面圖。在P型的半導體基底100上形成有場氧化層102、 氧化層103與閘極104，在基底100中形成有用以作爲源 極區與汲極區的N+型摻雜區106與108。而在汲極區108 與靠近汲極區108之部分閘極104下方，有队型摻雜區 Π2，且在源極區106與靠近源極區丨06之部分閘極104 下方，有一 P型摻雜區114。 3 本紙張尺度適f中國國家標準（CNS ) Λ4見格（210X297^] (請先閲讀背面之注意事項再填寫本頁) 448573 5529ivv f.doc/006 A7 B7 五、發明説明（爻） 由於爲了提高崩潰電壓（breakdown voltage)，需降 低漂移區（drift region)的摻雜（doping)濃度，也就是N_ 型摻雜區丨12之摻雜濃度，但是，卻也同時降低了元件的 電流驅動能力（performance)以及在閘極104下方之基底 100中源極區丨16與汲極區108之間的通道導電値。 此外，隨著元件持續縮小至次四分之一微米Οιώ-Ο u a r t e r Μ1 c r ο η ) ， 例如 線寬達 0 . 18 微米或 更小時 ，傳統 高壓元件之設計準則（de s i gn r u 1 e)不易縮小。 本發明就是提供一種高壓元件，其架構於一基底上， 此高壓元件之結構簡述如下：一第一導電型第一井區、一 第二導電型第二井區、一第一導電型第三井區、一第二導 電型第一摻雜區、一第一導電型第二摻雜區、數個場氧化 層、一淺溝渠隔離、一閘級結構、一第二導電型源極區以 及一第二導電型汲極區。第一井區位於基底中，而第二井 區則位於基底中，且與第一井區並不相連。場氧化層位於 第二井區之表面，且場氧化層下方具有第一摻雜區。淺溝 {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印數 摻雜區。第三井區位於第一井區中，且由第一井區之表面 延伸至第一井區中。閘極結構則位於第一與第二井區之間 的基底上，並延伸覆蓋部分第一井區、第三井區以及該場 氧化層。此外源極區，位於閘極結構之一側的第三井區 中，而汲極區，位於閘極結構另一側之場氧化層旁所裸露 之第二井區中。 本發明提供一種高壓元件之製造方法，此方法簡述如 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐〉 經濟部智慧財產局員工消費合作社印製 ^48573 5^29tw f,doc/0(!6 ^ B7 五、發明説明（彡） 下：首先提供一基底，之後於基底內形成一第一導電型第 一井區，接著，在基底內形成一第二導電型第二井區，且 第一與第二井區互不相連。繼之，在第二井區上形成數個 場氧化層，其中場氧化層下方之第二井區中分別形成有第 .二導電型第一摻雜區。續之，於場氧化層之間，形成一淺 溝渠隔離。於該溝渠隔離下方之第二井區中以及第一并區 中，分別形成第一導電型第二摻雜區以及第一導電型第三 井區。之後，在第一與第二井區之間的基底上形成一閘極 結構，並延伸覆蓋部分第一與第三井區以及場氧化層。最 後，於閘極結構所裸露之基底內的第三井區與第二井區一 第二導電型汲極區與一第二導電型源極區。 依照本發明的一較佳實施例，其中第一導電型爲一 N 型時，則第二導電型爲一 P型，同樣的當第一導電型爲一 P型時，則第二導電型爲一 N型。此外第三井區之一離子 摻雜劑量大於第一井區之一離子摻雜劑量。 於源極區方面，在第一井區中形成第三井區，由於第 三井區之離子摻雜劑量高於第一并區之離子摻雜劑量，因 此第一與第三井區之間的空乏區較小，根據電場=電壓/長 度的公式可知，較小的空乏區將可提高電場強度，因此可 以增加高壓元件之導電値與電場強度，進而增加元件驅動 電流。 再者，於汲極區方面，由於在淺溝渠隔離下方形成有 第二摻雜區與第二并區之間的空乏區，再加上第二井區之 摻雜劑量較習知之型摻雜區112的摻雜劑量小，因此可 5 本紙ϋ度ΐΐ用中國國家標準（CNS ) A4規格了210X297公嫠) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局5®工消費合作社印製 48 573 A7 ^529twt'.doc/006 B7五、發明説明（令） 在汲極區提供一較大的崩潰電壓値。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例1並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第丨圖繪示爲習知的一種高壓元件之結構剖面圖： 第2A圖至第2D圖所示，爲根據本發明一較佳實施例 之一種高壓元件之製造方法流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 100、200a、200b :基底 102、212a、212b :場氧化層 10 3、214 :氧化層 104、222a、222b :閘極 106、224a、226a :源極 108、224b、226b :汲極 112 : N型摻雜區 114 : P型摻雜區 202a、202b、204a、204b、218a、220a :井區 206 :墊氧化層 208 :圖案化氮化矽層 210a、210b、218b、220b :摻雜區 214a、214b :襯氧化層 214c、214d :閘氧化層 215a、2丨5b :溝渠 6 ! -- ϊ I , 1 I I— I -I -I- I ί - tn - -I I t -- ! (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐} A7 B7 448 5 7 3 5529tvv r.doc/〇〇6 五、發明説明（夕） 216a、2i6b :淺溝渠隔離 實施ί歹1 第2Α圖至第汕圖所示，爲根據本發明一較佳實施例 之一種高壓元件之製造方法流程剖面圖。此方法不僅可適 用於製造單一種MOS(例如NMOS或PMOS)，並且亦適用於 製造互補式金氧半導體（CM0S>。 請參照第2A圖’首先提供基底200a與200b。之後’ 進行一離子植入製程，在基底2〇〇a與200b內分別形成第 ―導電型井區202a與202b。其中，井區202a與202b之 摻雜劑量約爲12個數量級。 進行一離子植入製程，在基底200a與200b內分別形 成第二導電型井區204a與204b。其中，井區204a與204b 之摻雜劑量約爲12個數量級’且井區204a與202b之離 子摻雜劑量相較於習知之R型摻雜區112之摻雜劑量’此 摻雜劑量較小。 之後1進行離子驅入（drive in) °接著，在基底200 a 與200b之上，依序形成墊氧化層（pad 〇xide)206與圖案 化之氮化矽層208。其中，圖案化之氮化矽層208裸露部 分井區204a與202b上方的墊氧化層206，此裸露之部分 墊氧化層206在後續製程中，用於形成場氧化層。 繼之，進行一離子植入製程’分別在圖案化之氮化矽 層208所裸露之墊氧化層206下方的井區204a與202b 中，形成第二導電型摻雜區210a與第一導電型摻雜區 7 本紙張尺度逍用中國國家標準（CNS) Μ規格（210X29?公釐） !^> n ί n m In ί ,- f — i n If I--*1T c请先閱讀背齒之注意事項真填寫本頁) 經濟部智慧財產局員工消費合作社印製 448 5 7 3 5 5 2 91 u f. d c / Ο Ο (τ kl B7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（έ) 210b。其中摻雜區210a與210b之摻雜劑量約爲12〜14 個數量級。然後，在摻雜區210a與210b上，分別形成場 氧化層212a與212b。其中，場氧化層212a之一位於井區 204a上方並且接近井區204a之邊緣，而場氧化層212b之 .一位於井區202b上方並且接近井區202b之邊緣。 接著，請參照第2B圖，依序移除圖案化氮化矽層208 與墊氧化層206。接著，在場氧化層212a之間以及在場氧 化層212b之間，別形成溝渠215a與2154。之後於基底 200a與200b上方形成一層氧化層214。位於溝渠215a與 215b中之部分氧化層214a與214b則是做爲後續形成之淺 溝渠隔離的襯氧化層，且氧化層214之厚度約爲100-500 埃，且其形成方法例如是熱氧化法。 之後，在溝渠215a與215b中，分別形成一層氧化層 216a與216b，並塡滿溝渠215a與215b，此氧化層216a 與216b則是做爲淺溝渠隔離216a與216b。此淺溝渠隔離 216a與216b之形成方法例如是在基底200a與200b上方， 以常壓化學氣相沉積法（atmospheric pressure chemical vapor deposition’ APCVD)形成一層厚度約爲 5000 至 9000 埃的氧化層（未繪示），之後，進行一進行密化 (Densification)步驟，以強化氧化砂層材質之緊密度， 而此密化步驟例如是在溫度約lOOOt，進行時間約10-30 分鐘。最後，以化學機械硏磨法（chemical-mechanical polishing，CMP)移除部分氧化層直到裸露出氧化層214 之表面，以在溝渠215a與215b中形成淺溝渠隔離216a —-I —1 —Λ n^l nil :11 I- I I I - n ^1· 一flJ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家楼準（CMS ) A4规格（210X297公釐） 448573 i529Mvr.doc/006 A7 B7 經濟部智慧財產局β工消費合作社印製 五、發明説明（7) 與 216b 。 請參照第2C圖’接著，同時於井區202a與淺溝渠隔 離216a下方之井區204a中，形成一第一導電型井區218a 與一第一導電型摻雜區218b，其中井區218a與摻雜區 .2i8b之摻雜劑量約爲丨3個數量級。并區218a係由井區 202a之表面延伸至井區202a中，且融合（merge )部分井區 202a。在本發明中，井區218a之摻雜劑量大於井區202a 之摻雜劑量。 之後，同時於井區204b與淺溝渠隔離216b下方之井 區202b中，形成一第二導電型井區220a與一第二導電型 摻雜區220b，其中井區220a與摻雜區220b之摻雜劑量約 爲13個數量級。井區220a係由井區204b之表面延伸至 井區204b中，且融合部分井區204b。在本發明中，井區 220a之離子摻雜劑量大於并區204b之離子摻雜劑量。 續之，請參照第2D圖，於基底200a與200b上方形 成一層氧化層（未繪示），之後於氧化層上方形成一層導電 層（未繪示）。接著，定義導電層、氧化層與氧化層214， 分別在基底200a與200b上，形成閘極222a與閘氧化層 214c以及閘極222b與閘氧化層214d。其中，閘氧化層214c 與214d係由圖案化的氧化層與圖案化之氧化層214所組 成。其中，在基底200a上方所形成之具有閘極222a與閘 氧化層214c之閘極結構延伸覆蓋部分井區202a、218a以 及場氧化層212a，而在基底200b上方所形成之具有閘極 222b與閘氧化層214d之閘極結構延伸覆蓋部分井區 9 (請先閲讀背面之注意事項再填寫本頁) 衮- 訂 本紙張尺度通用中國國家榡準（CNS ) Α4規格（210Χ297公嫠） 經濟部智慧財產局員工消費合作社印製 448573 5 5 2 91 w f, d 〇 c / Ο Ο ή A 7 __B7 五、發明説明（没） 204b、220a以及場氧化層212b。 繼之’以閘極222a、場氧化層2l〇a與淺溝渠隔離216a 爲罩幕，分別於井區218a與204a中形成具有第二導電型 之源極區224a與汲極區224b，其中，源極區224a與汲極 .區224b之離子摻雜劑量約爲15個數量級，且源極區224a 與汲極區224b之離子摻雜劑量大於井區204a之離子摻雜 劑量。 續之，以閘極222b、場氧化層2l〇b與淺溝渠隔離216b 爲罩幕，分別於井區220b與202b中形成具有第一導電型 之源極區226a與汲極區226b ’其中，源極區226a與汲極 區226b之離子摻雜劑量約爲15個數量級，且源極區226a 與汲極區226b之離子摻雜劑量大於井區202b之離子摻雜 劑量。 在本發明中，當第一導電型是N型時，則第二導電型 是P型’反過來說，當第一導電型是P型時，則第二導電 型是N型。 於本發明中，在基底200a中，具有兩不相連之第一 導電型井區202a與第二導電型井區204a。在井區204a之 表面具有數個場氧化層212a，場氧化層212a之一位於靠 近井區202a之井區204a的邊緣，且場氧化層212a之間 具有一淺溝渠隔離216a。其中，場氧化層212a下方形成 有第二導電型摻雜區21〇a，而淺溝渠隔離216a下方形成 有第一導電型摻雜區21而在井區202a中，形成有由 井區202a之表面延伸至井區202a中的第一導電型井區 I. ml I I - I I - I K -1 m - n 1^1 i (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家樣準（CNS ) A4规格（210 X 297公釐） 經濟部智慧財產局員工消费合作杜印製 * 448 5 7 5529twf.d〇c/006 A7 _B7___ 五、發明説明（f ) 2i8a。在基底200a之表面上具有一閘極結構’此閘極結 構覆蓋部分井區218a與202a以及場氧化層212a。此外' 在閘極結構之一側所裸露之的井區218a中’形成有一第 二導電型源極區224a，在閘極結構另一側場氧化層212a 旁所裸露之井區204a中’形成有一汲極區224b。 於源極區224a與226a方面’在井區202a以及204b 中分別形成井區218a與220a ’由於井區218a與220a之 離子摻雜劑量分別高於井區202a與204b之離子摻雜劑 量，因此井區202a與218a之間，以及井區204b與220a 之間的空乏區較小，根據電場=電壓/長度的公式可知，較 小的空乏區將可提高電場強度，因此可以增加高壓元件之 導電値與電場強度，進而增加元件驅動電流。 再者，於汲極區224b與226b方面，由於在淺溝渠隔 離216a與216b下方分別有摻雜區218b與井區2Q4a之 間，以及摻雜區220b與并區202b之間之空乏區，再加上 井區204a與202b之摻雜劑量較習知之N·型摻雜區112的 摻雜劑量小，因此在汲極區可以提供較大的崩潰電壓値^ 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） .In in n^— n i ^^—^1 n n^i -*「* (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 148573 5 529tuf.doc / 006 A / B7 V. Description of the invention (1) The present invention relates to the structure and manufacturing method of an integrated circuit, and in particular to a high-voltage component With its manufacturing method. Generally, integrated circuit components include some high-voltage components, such as Electrically Programmable Read-Only Memory (EPROM) or Flash Memory, which are high-voltage components. . As the size of metal-oxide half-elements is shrinking, the shorter channel length will make the transistor operate faster. However, the short channel effect (Short Channe 丨 Effect) derived from the shortening of the channel is also becoming increasingly serious. According to the formula of electric field = voltage / length, if the applied voltage is unchanged and the channel length of the transistor is shortened, the electric field strength of the channel will increase, and the energy of the electrons in the channel will be increased by the acceleration of this electric field. , And then increase the phenomenon of electrical breakdown (Electrical Breakdown). Generally, in order to avoid the short-channel effect of the high-voltage metal-oxide half-element, the formation of an isolation layer is mainly used to reduce the lateral electric field in the channel by increasing the distance between the source / drain and the gate, so that the metal-oxide half-element The components can still operate normally under high voltage operation. Please refer to FIG. 1, which is a cross-sectional view showing a structure of a conventional high-voltage component. A field oxide layer 102, an oxide layer 103, and a gate electrode 104 are formed on the P-type semiconductor substrate 100. N + type doped regions 106 and 108 are formed in the substrate 100 and serve as source and drain regions. Under the drain region 108 and a portion of the gate 104 near the drain region 108, there is a line-type doped region Π2, and under the source region 106 and a portion of the gate 104 near the source region 丨 06, there is a P-type Doped region 114. 3 This paper is suitable for Chinese National Standards (CNS) Λ4 see the standard (210X297 ^) (Please read the notes on the back before filling in this page) 448573 5529ivv f.doc / 006 A7 B7 V. Description of the invention (爻) Increasing the breakdown voltage requires lowering the doping concentration in the drift region, that is, the doping concentration in the N_-type doped region, but it also reduces the current driving capability of the device. (Performance) and the channel conduction between the source region 16 and the drain region 108 in the substrate 100 under the gate 104. In addition, as the device continues to shrink to the next quarter micron Οιώ-Ο uarter Μ1 cr ο η), for example, with a line width of 0.18 microns or less, the design guidelines (de si gn ru 1 e) of conventional high-voltage components are not easily reduced. The present invention provides a high-voltage component, which is structured on a substrate. The structure of the high-voltage component is briefly described as follows: a first conductive type first well region, a second conductive type second well region, and a first conductive type first well region. Mitsui region, a second conductivity type first doped region, a first conductivity type second doped region, several field oxide layers, a shallow trench isolation, a gate-level structure, a second conductivity type source region And a second conductivity type drain region. The first well area is located in the basement, and the second well area is located in the basement and is not connected to the first well area. The field oxide layer is located on the surface of the second well region, and has a first doped region under the field oxide layer. Shallow ditch {Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The third well zone is located in the first well zone and extends from the surface of the first well zone into the first well zone. The gate structure is located on the substrate between the first and second well areas, and extends to cover part of the first well area, the third well area, and the field oxide layer. In addition, the source region is located in a third well region on one side of the gate structure, and the drain region is located in a second well region exposed next to the field oxide layer on the other side of the gate structure. The present invention provides a method for manufacturing high-voltage components. This method is briefly described if the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy ^ 48573 5 ^ 29tw f, doc / 0 (! 6 ^ B7 V. Description of the invention (彡) Below: first provide a substrate, and then form a first conductive type first well region in the substrate, and then, form a second conductive type second well region in the substrate, And the first and second well areas are not connected to each other. Next, several field oxide layers are formed on the second well area, wherein the second well type below the field oxide layer is formed with a second conductive type first dopant, respectively. Miscellaneous regions. Continuing, a shallow trench isolation is formed between the field oxide layers. A first conductivity type second doped region and a first conductive region are formed in the second well region and the first parallel region below the trench isolation, respectively. A conductive third well region. Then, a gate structure is formed on the substrate between the first and second well regions, and extends to cover part of the first and third well regions and the field oxide layer. Finally, the gate electrode Third well zone in the exposed base of the structure A second well region, a second conductivity type drain region and a second conductivity type source region. According to a preferred embodiment of the present invention, when the first conductivity type is an N type, the second conductivity type is a P type. Similarly, when the first conductivity type is a P type, the second conductivity type is an N type. In addition, the ion doping dose of one ion in the third well region is greater than the ion doping dose of one in the first well region. In the source region, a third well region is formed in the first well region. Since the ion doping dose of the third well region is higher than the ion doping dose of the first parallel region, the The empty region is small. According to the formula of electric field = voltage / length, it can be known that a smaller empty region will increase the electric field strength, so it can increase the conductive 値 and electric field strength of the high-voltage component, and then increase the element driving current. In terms of regions, the empty region between the second doped region and the second parallel region is formed under the shallow trench isolation. In addition, the doped dose of the second well region is higher than that of the conventional doped region 112. Small, so it can be used for 5 papers in accordance with Chinese National Standard (CNS) A4 210X297) (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economy 5® Industrial and Consumer Cooperatives 48 573 A7 ^ 529twt'.doc / 006 B7 V. Description of the Invention (Order) The drain region provides a larger breakdown voltage 为. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment 1 is given below in conjunction with the accompanying drawings for details The description is as follows: Brief description of the drawings: Figure 丨 shows a cross-sectional view of a conventional structure of a high-voltage component: Figures 2A to 2D show a high-voltage component according to a preferred embodiment of the present invention. The cross-sectional view of the manufacturing method process. Among them, the relationship between each icon number and the component name is as follows: 100, 200a, 200b: substrate 102, 212a, 212b: field oxide layer 10 3, 214: oxide layer 104, 222a, 222b: gate 106 , 224a, 226a: Source 108, 224b, 226b: Drain 112: N-type doped region 114: P-type doped region 202a, 202b, 204a, 204b, 218a, 220a: Well region 206: Pad oxide layer 208: Patterned silicon nitride layers 210a, 210b, 218b, 220b: doped regions 214a, 214b : Liner oxide layers 214c, 214d: gate oxide layers 215a, 2 丨 5b: trench 6!-Ϊ I, 1 II— I -I -I- I ί-tn--II t-! (Please read the back first Please note this page before filling in this page) This paper size adopts Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 448 5 7 3 5529tvv r.doc / 〇〇6 5. Description of invention (Xi) 216a, 2i6b : Implementation of shallow trench isolation Figure 1A through Figure 2A to Figure 3 are cross-sectional views of a method for manufacturing a high-voltage component according to a preferred embodiment of the present invention. This method is not only suitable for manufacturing a single type of MOS (such as NMOS or PMOS), but also suitable for manufacturing complementary metal-oxide semiconductors (CM0S>). Please refer to FIG. 2A, “First provide substrates 200a and 200b. After that, perform an ion implantation” In the manufacturing process, the first conductive well regions 202a and 202b are respectively formed in the substrates 200a and 200b. The doping dose of the well regions 202a and 202b is about 12 orders of magnitude. An ion implantation process is performed on the substrate. 200a and 200b form second conductive well regions 204a and 204b, respectively. Among them, the doping doses of well regions 204a and 204b are about 12 orders of magnitude ', and the ion doping doses of well regions 204a and 202b are compared with the conventional R The doping dose of the type doped region 112 is smaller. Then, an ion drive in is performed. Then, a pad oxide layer (pad OXide) is sequentially formed on the substrates 200 a and 200 b. 206 and the patterned silicon nitride layer 208. Among them, the patterned silicon nitride layer 208 exposes part of the pad oxide layer 206 over the well regions 204a and 202b, and this exposed part of the pad oxide layer 206 is used in subsequent processes for A field oxide layer is formed. The ion implantation process is used to form a second conductivity type doped region 210a and a first conductivity type doped region in the well regions 204a and 202b under the pad oxide layer 206 exposed by the patterned silicon nitride layer 208, respectively. Paper size: Chinese National Standard (CNS) M specification (210X29? Mm)! ^ ≫ n ί nm In ί,-f — in If I-* 1T cPlease read the notes on the back teeth first and fill in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 448 5 7 3 5 5 2 91 u f. Dc / Ο Ο (τ kl B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on the consumer cooperation of employees. The doping doses of the doped regions 210a and 210b are about 12 to 14 orders of magnitude. Then, field oxide layers 212a and 212b are formed on the doped regions 210a and 210b, respectively. One of the field oxide layers 212a is located in the well. Above the region 204a and near the edge of the well region 204a, and the field oxide layer 212b is located above the well region 202b and near the edge of the well region 202b. Next, referring to FIG. 2B, sequentially remove the patterned silicon nitride layer 208 and pad oxide layer 206. Next, between field oxide layer 212a and field oxide layer 21 Between 2b, do not form trenches 215a and 2154. Then, an oxide layer 214 is formed above the substrates 200a and 200b. Part of the oxide layers 214a and 214b in the trenches 215a and 215b are used as the liner oxidation for the subsequent shallow trench isolation. Layer, and the thickness of the oxide layer 214 is about 100-500 angstroms, and the formation method is, for example, a thermal oxidation method. Thereafter, an oxide layer 216a and 216b are formed in the trenches 215a and 215b, respectively, and the trenches 215a and 215b are filled, and the oxide layers 216a and 216b are used as shallow trench isolations 216a and 216b. The method for forming the shallow trench isolation 216a and 216b is, for example, to form an oxide layer (without thickness) of about 5000 to 9000 angstroms (atmospheric pressure chemical vapor deposition 'APCVD) over the substrates 200a and 200b. (Illustrated), and then a densification step is performed to strengthen the tightness of the oxidized sand layer material, and the densification step is performed at a temperature of about 1,000 t, for a time of about 10-30 minutes. Finally, a part of the oxide layer is removed by chemical-mechanical polishing (CMP) until the surface of the oxide layer 214 is exposed to form a shallow trench isolation in the trenches 215a and 215b. 216a —-I —1 —Λ n ^ l nil: 11 I- III-n ^ 1 · One flJ (Please read the notes on the back before filling this page) This paper size is applicable to China National Building Standard (CMS) A4 (210X297 mm) 448573 i529Mvr.doc / 006 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, β Industrial Consumer Cooperative, V. Invention Description (7) and 216b. Please refer to FIG. 2C. Next, in the well area 204a below the well area 202a and the shallow trench isolation 216a, a first conductivity type well area 218a and a first conductivity type doped area 218b are formed. The well area 218a and Doped region. The doping dose of 2i8b is about 3 orders of magnitude. The merged area 218a extends from the surface of the well area 202a into the well area 202a, and merges part of the well area 202a. In the present invention, the doping dose of the well region 218a is greater than the doping dose of the well region 202a. Then, in the well region 202b below the well region 204b and the shallow trench isolation 216b, a second conductivity type well region 220a and a second conductivity type doped region 220b are formed. The well region 220a and the doped region 220b are doped together. Miscellaneous doses are about 13 orders of magnitude. The well area 220a extends from the surface of the well area 204b into the well area 204b, and merges a part of the well area 204b. In the present invention, the ion doping dose in the well region 220a is greater than the ion doping dose in the merge region 204b. Continuing, please refer to FIG. 2D. An oxide layer (not shown) is squared on the substrates 200a and 200b, and then a conductive layer (not shown) is formed over the oxide layer. Next, a conductive layer, an oxide layer, and an oxide layer 214 are defined, and a gate electrode 222a and a gate oxide layer 214c and a gate electrode 222b and a gate oxide layer 214d are formed on the substrates 200a and 200b, respectively. The gate oxide layers 214c and 214d are composed of a patterned oxide layer and a patterned oxide layer 214. Among them, a gate structure with a gate electrode 222a and a gate oxide layer 214c formed over the substrate 200a extends to cover part of the well regions 202a, 218a and a field oxide layer 212a, and a gate electrode 222b and a gate formed over the substrate 200b The gate structure of the oxide layer 214d extends to cover part of the well area 9 (please read the precautions on the back before filling this page)-The size of the paper is in accordance with China National Standards (CNS) Α4 (210 × 297 cm) Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau 448 573 5 5 2 91 wf, d 〇c / 〇 ή A 7 __B7 V. Description of the invention (none) 204b, 220a and field oxide layer 212b. Next, using the gate electrode 222a, the field oxide layer 21a, and the shallow trench isolation 216a as a mask, a source region 224a and a drain region 224b having a second conductivity type are formed in the well regions 218a and 204a, respectively. Among them, The ion doping doses of the source region 224a and the drain region 224b are about 15 orders of magnitude, and the ion doping dosages of the source region 224a and the drain region 224b are greater than the ion doping dosages of the well region 204a. Continuing, a gate electrode 222b, a field oxide layer 21b, and a shallow trench isolation 216b are used as masks, and a source region 226a and a drain region 226b having a first conductivity type are formed in the well regions 220b and 202b, respectively. The ion doping doses of the source region 226a and the drain region 226b are about 15 orders of magnitude, and the ion doping doses of the source region 226a and the drain region 226b are greater than the ion doping doses of the well region 202b. In the present invention, when the first conductivity type is an N type, then the second conductivity type is a P type '. Conversely, when the first conductivity type is a P type, the second conductivity type is an N type. In the present invention, in the substrate 200a, there are two disconnected first conductive well regions 202a and a second conductive well region 204a. There are several field oxide layers 212a on the surface of the well area 204a. One of the field oxide layers 212a is located near the edge of the well area 204a near the well area 202a, and there is a shallow trench isolation 216a between the field oxide layers 212a. The second conductivity type doped region 21a is formed under the field oxide layer 212a, and the first conductivity type doped region 21 is formed under the shallow trench isolation 216a. In the well region 202a, a surface formed by the well region 202a is formed. Extending to the first conductive well area I. ml II-II-IK -1 m-n 1 ^ 1 i in well area 202a (Please read the precautions on the back before filling this page) This paper size applies to Chinese national samples Standard (CNS) A4 size (210 X 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation Du printed * 448 5 7 5529twf.d〇c / 006 A7 _B7___ 5. Description of the invention (f) 2i8a. A gate structure is provided on the surface of the substrate 200a. This gate structure covers part of the well regions 218a and 202a and the field oxide layer 212a. In addition, a second conductivity type source region 224a is formed in the well region 218a exposed on one side of the gate structure, and is formed in the well region 204a exposed near the field oxide layer 212a on the other side of the gate structure. There is a drain region 224b. With respect to the source regions 224a and 226a, 'well regions 218a and 220a are formed in well regions 202a and 204b, respectively', because the ion doping doses of well regions 218a and 220a are higher than those of well regions 202a and 204b, respectively, The empty area between the well areas 202a and 218a and between the well areas 204b and 220a is small. According to the formula of electric field = voltage / length, it can be known that a smaller empty area will increase the strength of the electric field and therefore increase the conductivity of the high-voltage component.値 and the electric field strength, thereby increasing the element drive current. Furthermore, in terms of the drain regions 224b and 226b, there are empty regions between the doped region 218b and the well region 2Q4a under the shallow trench isolation 216a and 216b, respectively, and between the doped region 220b and the merge region 202b. In addition, the doping dose of the well regions 204a and 202b is smaller than that of the conventional N-type doped region 112, so a larger breakdown voltage can be provided in the drain region. Although the present invention has been described in a preferred embodiment, The disclosure is as above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the attached application. The patent scope shall prevail. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm).