TW202111773A - High voltage device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a high voltage device and manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductive type, and a conductive layer of the sub-gate has a second conductive type or is an intrinsic semiconductor structure.

Description

High-voltage component and manufacturing method thereof

The present invention relates to a high-voltage component and a manufacturing method thereof, in particular to a high-voltage component and a manufacturing method thereof that can improve the transient response performance during conduction operation.

1A and 1B respectively show a schematic cross-sectional view and a schematic top view of a conventional high-voltage device 100. The so-called high-voltage device in this article refers to a semiconductor device whose drain voltage is higher than 5V during normal operation. Generally speaking, taking the high-voltage device 100 shown in Figures 1A and 1B as an example, there is a drift region 12a between the drain 19 and the body region 16 of the high-voltage device 100 (as indicated by the dashed line in Figure 1A). The pole 19 is separated from the body region 16, and the lateral length of the drift region 12a is adjusted according to the operating voltage to withstand during normal operation. As shown in FIGS. 1A and 1B, the high-voltage device 100 includes a well region 12, an insulating structure 13, a drift oxide region 14, a body region 16, a gate electrode 17, a source electrode 18, and a drain electrode 19. Wherein, the conductivity type of the well region 12 is N-type and is formed on the substrate 11, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operating area 13a as the main active area during operation of the high-voltage element 100 . The range of the operation area 13a is indicated by the thick black dashed frame in Figure 1B. As shown in FIG. 1A, part of the gate 17 is on the drift region 12a, covering part of the drift oxide region 14. Generally speaking, the thickness of the drift oxide region 14 is about 2,500 to 15,000 Angstroms (Å), and the thickness of the gate oxide layer 173 in the gate electrode 17 is about 20 Å to 500 Å. The thickness of the drift oxide region 14 is much higher than the thickness of the gate oxide layer 173, at least more than 5 times. The thicker drift oxide region 14 can block the high potential when the high-voltage device 100 is in non-conducting operation, so that a relatively high electric field falls in the thicker drift oxide region 14 to improve the non-conduction breakdown protection of the high-voltage device 100 Voltage. However, although the thicker drift oxide region 14 increases the withstand voltage of the high-voltage device 100 (the non-conduction breakdown protection voltage is increased), the on-resistance and the gate-drain capacitance of the high-voltage device 100 are also relatively increased, resulting in The speed of operation is reduced, and the performance of the component is reduced.

In view of this, the present invention provides a high-voltage component and a manufacturing method thereof that can increase the operating speed and improve the transient response performance without affecting the thickness of the drift oxide region.

In one aspect, the present invention provides a high-voltage device, including: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other in a vertical direction; a drift oxide region, Formed on the upper surface and connected to the upper surface, and located on and connected to a drift region in an operating region; a well region having a first conductivity type formed on the semiconductor layer for the operation Area, and in the vertical direction, the well area is located below the upper surface and connected to the upper surface; a body area having a second conductivity type, formed in the well area of the operation area, and in the vertical direction In the direction, the body area is located under the upper surface and connected to the upper surface; a gate is formed in the operation area on the upper surface of the semiconductor layer, and part of the body area is located directly under the gate and connected At the gate to provide a reversal current channel for the high-voltage element in a conduction operation; at least one sub-gate is formed on the drift oxide region and directly above at least part of the drift region, the sub-gate Arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the drift oxide region; and a source and a drain having the first conductivity type, and the source and the drain are formed in The upper surface is under and connected to the operation area of the upper surface, and the source and the drain are respectively located in the body region below the outside of the gate and in the well region on the side away from the body region, and In a channel direction, the drift region is located between the drain and the body region and in the well region close to the upper surface, which serves as a drift current channel for the high-voltage element in the conduction operation, and from the upper From the view, the sub-gate is between the gate and the drain, the source and the drain are located under the upper surface and connected to the upper surface; wherein, the conductive layer of the gate has the first One conductivity type, and the conductive layer of the sub-gate has the second conductivity type or a pure semiconductor structure.

From another point of view, the present invention provides a method for manufacturing a high-voltage device, including: forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; forming an insulating structure on the upper surface and Connected to the upper surface to define an operating region; forming a drift oxide region on the upper surface and connected to the upper surface, and located on a drift region in the operating region and connected to the drift region; forming a drift oxide region The well area is in the operation area of the semiconductor layer, and the well area is located below and connected to the upper surface, the well area has a first conductivity type; a body area is formed in the well area of the operation area , And the body region is located below the upper surface and connected to the upper surface, the body region has a second conductivity type; a gate is formed in the operation region on the upper surface of the semiconductor layer, and part of the body region is located The gate is directly below and connected to the gate to provide a reversal current channel for the high-voltage element in a conduction operation; at least one sub-gate is formed on the drift oxide region, and at least part of the drift region is positive Above, the sub-gate and the gate are arranged in parallel, the sub-gate is located on the drift oxide region and connected to the drift oxide region; and a source and a drain are formed under the upper surface and connected to the upper surface In the operation area, the source and the drain have the first conductivity type, and are respectively located in the body region below the outside of the gate and in the well region far away from the body region, and are in a channel In the direction, the drift region is located in the interval between the drain and the body, and in the well region close to the upper surface, to serve as a drift current channel of the high-voltage element in the conduction operation, and as viewed from the top view, the The sub-gate is between the gate and the drain, and the source and the drain are located under the upper surface and connected to the upper surface; wherein the conductive layer of the gate has the first conductivity type, And the conductive layer of the sub-gate has the second conductivity type or a pure semiconductor structure.

From another point of view, the present invention provides a high-voltage device comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; and a drift oxide region formed on the upper surface And connected to the upper surface and located on and connected to a drift region in an operating region; a drift well region having a first conductivity type formed in the operating region of the semiconductor layer under the upper surface And the drift well area is located under the upper surface and connected to the upper surface; a channel well area having the second conductivity type is formed in the operation area under the upper surface, the channel well area and the drift well Areas adjoin in a channel direction; a buried layer, with a first conductivity type, is formed under the channel well area and connected to the channel well area, and the buried layer is in the operation area and completely covers the channel well area ; A gate formed in the operating region on the upper surface of the semiconductor layer, part of the channel well region is located directly below the gate and connected to the gate, used to provide the high-voltage component in a conduction operation An inversion current channel; at least one sub-gate is formed on the drift oxide region and directly above at least part of the drift region, the sub-gate is arranged in parallel with the gate, and the sub-gate is located in the drift On the oxidation region and connected to the drift oxidation region; and a source electrode and a drain electrode having the first conductivity type, and the source electrode and the drain electrode are formed under the upper surface and connected to the operation area of the upper surface And the source and the drain are respectively located in the channel well region below the outside of the gate and in the drift well region on the side far from the channel well region, and in a channel direction, the drift region is located in the Between the drain and the channel well region, in the drift well region close to the upper surface, it is used as a drift current channel of the high-voltage element in the conduction operation, and as viewed from the top view, the sub-gate intermediary Between the gate and the drain; wherein, the conductive layer of the gate has the first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure.

From another point of view, the present invention provides a method for manufacturing a high-voltage device, including: forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; forming a drift oxide region on the upper surface And connected to the upper surface and located on one of the drift regions in the operation area and connected to the drift region; forming a drift well region in the operation region of the semiconductor layer under the upper surface, and the drift well region is located Under the upper surface and connected to the upper surface, the drift well region has a first conductivity type; forming a channel well region in the operation region below the upper surface, the channel well region has the second conductivity type, and The drift well area is adjacent in the direction of a channel; a buried layer is formed under the channel well area and connected with the channel well area, and the buried layer is in the operation area, completely covering the channel well area, and the buried layer has The first conductivity type; forming a gate in the operation area on the upper surface of the semiconductor layer, and a portion of the channel well area is located directly below the gate to provide the high-voltage element in a conduction operation Inverting the current channel; forming at least one sub-gate on the drift oxide region and directly above at least part of the drift region, the sub-gate located on the drift oxide region and connected to the drift oxide region; and forming a source An electrode and a drain are in the operating area below the upper surface, the source and the drain have the first conductivity type, and are respectively located in the channel well region and away from the channel well below the outside of the gate In the drift well region on the side of the zone, and in a channel direction, the drift region is located between the drain and the channel well region, in the drift well region close to the upper surface, and is used as the high-voltage element in the One of the drift current channels in the conduction operation, and from the top view, the sub-gate is between the gate and the drain; wherein the conductive layer of the gate has the first conductivity type, and the sub-gate The conductive layer of the pole has a second conductivity type or a pure semiconductor structure.

In a preferred embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (chemical vapor deposition) structure. deposition, CVD) Oxidation zone.

In a preferred embodiment, at least one of the sub-gate and the gate are directly connected to each other.

In a preferred embodiment, at least one of the sub-gate and the gate are not directly connected to each other.

In a preferred embodiment, the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes a polysilicon structure doped with impurities of the second conductivity type.

In a preferred embodiment, the sub-gate is electrically floating, or electrically connected to the gate or the source.

Detailed descriptions are given below by specific embodiments, so that it will be easier to understand the purpose, technical content, features, and effects of the present invention.

The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiment with reference to the drawings. The drawings in the present invention are all schematic, and are mainly intended to show the process steps and the upper and lower order relationships between the layers. As for the shape, thickness, and width, they are not drawn to scale.

Please refer to Figures 2A and 2B, which show the first embodiment of the present invention. 2A and 2B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 200. As shown in Figures 2A and 2B, the high-voltage device 200 includes: a semiconductor layer 21', a well region 22, an insulating structure 23, a drift oxide region 24, a conductive connection structure 25, a body region 26, a gate 27, and a sub-gate 27' , Source 28 and drain 29. The semiconductor layer 21' is formed on the substrate 21, and the semiconductor layer 21' is in the vertical direction (as indicated by the dashed arrow direction in Figure 2A, the same below), and has an upper surface 21a and a lower surface 21b opposite to each other. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21 by, for example, an epitaxial step, or a part of the substrate 21 is used as the semiconductor layer 21'. The method of forming the semiconductor layer 21' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 2A and 2B, where the insulating structure 23 is formed on the upper surface 21a and connected to the upper surface 21a to define the operating area 23a (as indicated by the dashed frame in FIG. 2B). The insulating structure 23 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21a, and is located on the drift region 22a (as indicated by the dashed frame in Figure 2A) in the operation region 23a and connected to the drift region 22a. In this embodiment, the operating area 23a defined by the insulating structure 23 has only one high-voltage component 200, but the present invention is not limited to this. The operating area 23a defined by the insulating structure 23 may also include a plurality of high-voltage components, such as mirror images. The two high-voltage components arranged in the arrangement are well known to those with ordinary knowledge in the art, and will not be repeated here.

The well region 22 has the first conductivity type and is formed in the operation region 23a of the semiconductor layer 21'. In the vertical direction, the well region 22 is located under the upper surface 21a and connected to the upper surface 21a. The body region 26 has the second conductivity type and is formed in the well region 22 of the operation region 23a. In the vertical direction, the body region 26 is located under the upper surface 21a and connected to the upper surface 21a. The gate 27 is formed in the operating area 23a on the upper surface 21a of the semiconductor layer 21'. From the top view, the gate 27 is substantially along the width direction (as indicated by the solid arrow direction in Figure 2B, The same below) is a rectangular shape extending from above, and in the vertical direction, a part of the body region 26 is located directly under the gate 27 and connected to the gate 27 to provide a reverse current channel for the high-voltage device 200 in the conduction operation. The conductive layer of the gate electrode 27 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 2A and 2B. The sub-gate 27' is formed directly above a portion of the drift region 22a, and is located in the operating region 23a on the drift oxide region 24. As seen from Figure 2B of the upper view, the sub-gates 27' are substantially rectangular extending along the width direction and are arranged in parallel with the gates 27. And the sub-gate 27' spans the entire operating area 23a in the width direction. In the vertical direction, the sub-gate 27' is located on the drift oxidation region 24 and connected to the drift oxidation region 24. In this embodiment, the high-voltage component 200 includes, for example, a sub-gate 27'. According to the high-voltage component of the present invention, the high-voltage component 200 may also include a plurality of sub-gates 27'. The conductive layer of the sub-gate 27' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. In this embodiment, the sub-gate 27' and the gate 27 are not directly connected, and are electrically connected to each other via the conductive connection structure 25. In other embodiments, the sub-gate 27' may also be electrically connected to the source 28. In a preferred embodiment, on the upper surface 21a connected to the body region 26 and the source electrode 28, there is a metal silicide layer (not shown, detailed later) for electrically connecting the body region 26 and the source electrode 28. The source 28; therefore, in this embodiment, the sub-gate 27' is also electrically connected to the body region 26. In another preferred embodiment, the sub-gate 27' may also be electrically floating.

The source 28 and the drain 29 have the first conductivity type. In the vertical direction, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the operating area 23a of the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 below the gate 27 in the channel direction (as indicated by the dashed arrow direction in Figure 2B, the same below) and in the well region 22 on the side away from the body region 26, and in the channel direction Above, the drift region 22a is located between the drain 29 and the body region 26, separates the drain 29 and the body region 26, and is located in the well region 22 close to the upper surface 21a, and is used as a drift of the high-voltage component 200 in the conduction operation Current channel, as seen from the top view, Figure 2B, in the channel direction, the sub-gate 27' is between the gate 27 and the drain 29, and in the vertical direction, the source 28 and the drain 29 are located on the top The surface 21a is below and connected to the upper surface 21a. The conductive connection structure 25 is formed above the gate 27 and the sub-gate 27' to electrically connect the gate 27 and the sub-gate 27', and the conductive connection structure 25 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here.

In this embodiment, the conductive layer of the gate 27 has the first conductivity type, and the conductive layer of the sub-gate 27' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 27' can also be a pure semiconductor structure, such as a pure polysilicon structure.

It should be noted that the so-called inversion current path refers to the area where the high voltage element 200 is applied to the gate 27 during the conduction operation, and an inversion layer is formed under the gate 27 to allow the conduction current to pass. , This is well-known with common knowledge in the field, so I won’t repeat it here.

It should be noted that the so-called drift current channel refers to the region through which the conduction current of the high-voltage device 200 passes in a drifting manner during the conduction operation, which is well known by common knowledge in the art and will not be repeated here.

It should be noted that the upper surface 21a does not refer to a completely flat surface, but refers to a surface of the semiconductor layer 21'. In this embodiment, for example, a portion of the upper surface 21a where the drift oxide region 24 is in contact with the upper surface 21a has a depressed portion.

It should be noted that the gate 27 includes a conductive layer 271 with conductivity, a dielectric layer 273 connected to the upper surface, and a spacer layer 272 with electrical insulation properties; the sub-gate 27' includes a conductive layer 271 with conductivity 'And the spacer layer 272 with electrical insulation properties', which are well known by common knowledge in the art, and will not be repeated here.

It should be noted that the aforementioned "first conductivity type" and "second conductivity type" refer to high-voltage MOS devices where impurities of different conductivity types are doped in the semiconductor composition region (such as but not limited to the aforementioned well region, In the body region, source and drain regions), the semiconductor composition region is made into the first or second conductivity type (for example, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa. Yes), wherein the first conductivity type and the second conductivity type are conductivity types that are electrically opposite to each other.

In addition, it should be noted that the so-called high-voltage MOS device refers to that during normal operation, the voltage applied to the drain is higher than a specific voltage, such as 5V, and the lateral distance between the body region 26 and the drain 29 (the length of the drift region) ) It is adjusted according to the operating voltage that it bears during normal operation, so it can be operated at the higher specific voltage mentioned above. These are all well-known to those with ordinary knowledge in the field, and will not be repeated here.

It should be noted that the number of sub-gates 27' is not limited to one as shown in the figure, and may be plural. It should be noted that, as shown in FIGS. 2A and 2B, the sub-gate 27' and the gate 27 are not directly connected, but are electrically connected through the conductive connection structure 25. In another embodiment, the sub-gate 27' and The gate 27 can be directly connected. Here, the so-called direct connection means that the gate conductor layer 271 is in direct contact with the sub-gate conductor layer 271'.

It is worth noting that one of the technical features of the present invention superior to the prior art is that according to the present invention, taking the embodiment shown in Figures 2A and 2B as an example, when at least one sub-gate 27' is formed in the drift oxide region 24, and arranged in parallel with the gate 27, when the high-voltage device 200 is not conducting, each sub-gate 27' along the edge of the width direction will have a relatively high electric field, so that the electric field is integrated along the channel. The voltage is higher, so that the voltage when the non-conduction is higher, and the collapse protection voltage when the non-conduction is higher than the prior art. In this embodiment, the gate 27 has the first conductivity type, and the sub-gate 27' has the second conductivity type. As a result, although the sub-gate 27' is in the on operation of the high-voltage element 200, that is, when the voltage of the gate 27 is higher than its threshold voltage, the sub-gate 27' will be non-conducting or partially conducting, so the sub-gate 27' For the drift region 22a immediately below, the on-state charge accumulation (accumulation) capability is low, thus causing the on-resistance of the high-voltage device 200 to decrease; however, the gate-drain capacitance is also reduced, so that the high-voltage device 200 is turned on. The transient response efficiency of time is improved, the operating speed of the high-voltage component 200 is increased, and the application range of the high-voltage component 200 is increased, and this does not affect the thickness of the drift oxide region or the collapse protection voltage.

In a preferred embodiment, as shown in FIGS. 2A and 2B, the sub-gate 27' and the gate 27 are connected by the conductive connection structure 25, and are not connected to each other. In a preferred embodiment, as shown in FIGS. 2A and 2B, the sub-gate 27' includes a conductive layer 271' and a spacer layer 272'. In a preferred embodiment, as shown in FIGS. 2A and 2B, the drift oxide region 24 is a completely connected structure and is not divided into different blocks.

Please refer to Figures 3A and 3B, which show the second embodiment of the present invention. 3A and 3B show a schematic cross-sectional view and a schematic top view of the high-voltage component 300, respectively. As shown in FIGS. 3A and 3B, the high-voltage device 300 includes: a semiconductor layer 31', a well region 32, an insulating structure 33, a drift oxide region 34, a body region 36, a gate 37, two sub-gates 37', and a source 38 And drain 39. The semiconductor layer 31' is formed on the substrate 31, and the semiconductor layer 31' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 3A, the same below), and has an upper surface 31a and a lower surface 31b opposite to each other. The substrate 31 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 31' is formed on the substrate 31 by, for example, an epitaxial step, or a part of the substrate 31 is used as the semiconductor layer 31'. The method of forming the semiconductor layer 31' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 3A and 3B, where the insulating structure 33 is formed on the upper surface 31a and connected to the upper surface 31a to define the operation area 33a (as indicated by the dashed frame in FIG. 3B). The insulating structure 33 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 34 is formed on the upper surface 31a and connected to the upper surface 31a, and is located on the drift region 32a (as indicated by the dashed frame in Figure 3A) in the operation region 33a and connected to the drift region 32a.

The well region 32 has the first conductivity type and is formed in the operation region 33a of the semiconductor layer 31'. In the vertical direction, the well region 32 is located under the upper surface 31a and connected to the upper surface 31a. The body region 36 has the second conductivity type and is formed in the well region 32 of the operation region 33a. In the vertical direction, the body region 36 is located under the upper surface 31a and connected to the upper surface 31a. The gate 37 is formed in the operating area 33a on the upper surface 31a of the semiconductor layer 31'. As seen from the top view, Fig. 3B, the gate 37 is approximately along the width direction (as shown in the solid arrow direction in Fig. 3B). As shown, the same below) is a rectangle extending from the top, and in the vertical direction, a part of the body region 36 is located directly below the gate 37 and connected to the gate 37 to provide a reverse current path for the high-voltage device 300 in the conduction operation. The conductive layer of the gate electrode 37 is doped with impurities of the first conductivity type and is of the first conductivity type, for example, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 3A and 3B. Two sub-gates 37' are formed directly above part of the drift region 32a and are located in the operating region 33a on the drift oxide region 34. As seen from Fig. 3B of the upper view, each sub-gate 37' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 37. And the sub-gate 37' spans the entire operating area 33a in the width direction. In the vertical direction, the sub-gate 37' is located on the drift oxidation region 34 and connected to the drift oxidation region 34. In this embodiment, the high-voltage component 300 includes, for example, two sub-gates 37'. According to the high-voltage component of the present invention, the high-voltage component 300 may also include one or another number of sub-gates 37'. The conductive layer of the sub-gate 37' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. In this embodiment, the sub-gate 37' and the gate 37 are not directly connected, and the two sub-gates 37' are electrically floating, for example. In other embodiments, at least one sub-gate 37' may also be electrically connected to the gate 37 or the source 38. The sub-gate 37' can also be electrically connected to the body region 36.

The source 38 and the drain 39 have the first conductivity type. In the vertical direction, the source 38 and the drain 39 are formed under the upper surface 31a and connected to the operation area 33a of the upper surface 31a, and the source 38 and the drain 39 are respectively located in the body region 36 below the gate 37 in the channel direction (as indicated by the dashed arrow direction in Figure 3B, the same below) and in the well region 32 on the side away from the body region 36, and in the channel direction Above, the drift region 32a is located between the drain 39 and the body region 36, separates the drain 39 and the body region 36, and is located in the well region 32 close to the upper surface 31a, and is used as a drift of the high-voltage element 300 in the conduction operation Current channel, as seen from the top view, Figure 3B, in the channel direction, the sub-gate 37' is between the gate 37 and the drain 39, and in the vertical direction, the source 38 and the drain 39 are located on the top The surface 31a is below and connected to the upper surface 31a. In this embodiment, the two sub-gates 37' are electrically floating, for example.

In this embodiment, the conductive layer of the gate 37 has the first conductivity type, and the conductive layers of the two sub-gates 37' both have the second conductivity type. In another embodiment, the conductive layer 37' of at least one sub-gate may also be a pure semiconductor structure, such as a pure polysilicon structure.

This embodiment is different from the first embodiment. In addition to the above, one point is that in the first embodiment, the drift oxide region 24 is a LOCOS structure, while in this embodiment, the drift oxide region 34 is a chemical Chemical vapor deposition (CVD) oxidation zone. The CVD oxide region is formed by the deposition step of the CVD process, which is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please refer to Figures 4A and 4B, which show the third embodiment of the present invention. 4A and 4B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage element 400. As shown in FIGS. 4A and 4B, the high-voltage element 400 includes: a semiconductor layer 41', a well region 42, an insulating structure 43, a drift oxide region 44, a conductive connection structure 45, a body region 46, a body electrode 46', a gate electrode 47, At least one sub-gate 47', a source 48, a metal silicide layer 48', and a drain 49. The semiconductor layer 41' is formed on the substrate 41, and the semiconductor layer 41' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 4A, the same below), and has a relatively upper surface 41a and a lower surface 41b. The substrate 41 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 41' is formed on the substrate 41 by, for example, an epitaxial step, or a part of the substrate 41 is used as the semiconductor layer 41'. The method of forming the semiconductor layer 41' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 4A and 4B, where the insulating structure 43 is formed on the upper surface 41a and connected to the upper surface 41a to define the operation area 43a (as indicated by the dashed frame in FIG. 4B). The insulating structure 43 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 44 is formed on the upper surface 41a and connected to the upper surface 41a, and is located on the drift region 42a (as indicated by the dashed frame in Figure 4A) in the operation region 43a and connected to the drift region 42a.

The well region 42 has the first conductivity type and is formed in the operation region 43a of the semiconductor layer 41'. In the vertical direction, the well region 42 is located under the upper surface 41a and connected to the upper surface 41a. The body region 46 has the second conductivity type and is formed in the well region 42 of the operation region 43a. In the vertical direction, the body region 46 is located under the upper surface 41a and connected to the upper surface 41a. The gate electrode 47 is formed in the operating area 43a on the upper surface 41a of the semiconductor layer 41'. From the top view, the gate electrode 47 is substantially along the width direction (as indicated by the solid arrow direction in Figure 4B, Same below) A rectangle extending from above, and in the vertical direction, a part of the body region 46 is located directly below the gate 47 and connected to the gate 47 to provide a reverse current channel for the high-voltage device 400 during the on-operation. The conductive layer of the gate electrode 47 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 4A and 4B. Two sub-gates 47' are formed directly above part of the drift region 42a and are located in the operating region 43a on the drift oxide region 44. As seen from Fig. 4B of the upper view, the sub-gate 47' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 47. And each sub-gate 47' spans the entire operating area 43a in the width direction. In the vertical direction, the sub-gate 47' is located on the drift oxide region 44 and connected to the drift oxide region 44. In this embodiment, the high-voltage element 400 includes two sub-gates 47', for example. The high-voltage component according to the present invention may include one or another number of multiple sub-gates 47'. In this embodiment, the sub-gate 47' and the gate 47 are not directly connected, and the two sub-gates 47' are electrically connected to the source 48 and the body region 46, for example, through the conductive connection structure 45 and the silicide layer 48'. And the body pole 46'. In other embodiments, at least one sub-gate 47' may also be electrically connected to the gate 47, or may be electrically floating. The metal silicide layer 48' is formed on the upper surface 41a connected to the body region 46 and the source electrode 48, for example, a metal such as cobalt or titanium, in a self-aligned process step, reacts with silicon atoms to form the metal silicide The layer 48' has a good conductive effect, which is well known to those with ordinary knowledge in the art, and will not be repeated here.

The source 48 and the drain 49 have the first conductivity type. In the vertical direction, the source 48 and the drain 49 are formed under the upper surface 41a and connected to the operation area 43a of the upper surface 41a, and the source 48 and the drain 49 are respectively located in the body area 46 below the outside of the gate 47 in the channel direction (as indicated by the dashed arrow direction in Figure 4B, the same below) and in the well area 42 on the side away from the body area 46, and in the channel direction Above, the drift region 42a is located between the drain 49 and the body region 46, separates the drain 49 and the body region 46, and is located in the well region 42 near the upper surface 41a, which serves as the drift of the high-voltage element 400 in the conduction operation Current channel, as seen from the top view in Figure 4B, in the channel direction, two sub-gates 47' are between the gate 47 and the drain 49, and in the vertical direction, the source 48 and the drain 49 Located under the upper surface 41a and connected to the upper surface 41a. The conductive connection structure 45 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here.

In this embodiment, the conductive layer of the gate 47 has the first conductivity type, and the conductive layer of the sub-gate 47' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 47' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the first embodiment is that the above two sub-gates 47' are electrically connected to the source 48 and the body region 46 and the body electrode 46', for example, via the conductive connection structure 45 and the silicide metal layer 48'. In addition, another point is that in the first embodiment, the drift oxide region 24 has a LOCOS structure, while in this embodiment, the drift oxide region 44 has a shallow trench isolation (STI) structure. The STI structure is well-known to those with ordinary knowledge in the field, and will not be repeated here.

Please refer to Figures 5A and 5B, which show the fourth embodiment of the present invention. Figures 5A and 5B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 500. As shown in FIGS. 5A and 5B, the high-voltage device 500 includes: a semiconductor layer 51', a well region 52, an insulating structure 53, a drift oxide region 54, a body region 56, a gate 57, a sub-gate 57', a source 58 and Drain 59. The semiconductor layer 51' is formed on the substrate 51, and the semiconductor layer 51' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 5A, the same below), and has an upper surface 51a and a lower surface 51b opposite to each other. The substrate 51 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 51' is formed on the substrate 51 by, for example, an epitaxial step, or a part of the substrate 51 is used as the semiconductor layer 51'. The method of forming the semiconductor layer 51' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 5A and 5B, where the insulating structure 53 is formed on the upper surface 51a and connected to the upper surface 51a to define the operation area 53a (as indicated by the dashed frame in FIG. 5B). The insulating structure 53 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 54 is formed on the upper surface 51a and connected to the upper surface 51a, and is located on the drift region 52a (as indicated by the dashed frame in Figure 5A) in the operation region 53a and connected to the drift region 52a.

The well region 52 has the first conductivity type and is formed in the operation region 53a of the semiconductor layer 51'. In the vertical direction, the well region 52 is located under the upper surface 51a and connected to the upper surface 51a. The body region 56 has the second conductivity type and is formed in the well region 52 of the operation region 53a. In the vertical direction, the body region 56 is located under the upper surface 51a and connected to the upper surface 51a. The gate 57 is formed in the operating area 53a on the upper surface 51a of the semiconductor layer 51'. From the top view, the gate 57 is substantially along the width direction (as indicated by the solid arrow direction in Figure 5B, The same below) is a rectangle extending from the top, and in the vertical direction, a part of the body region 56 is located directly below the gate 57 and connected to the gate 57 to provide a reverse current path for the high-voltage device 500 during the conduction operation. The conductive layer of the gate 57 is doped with impurities of the first conductivity type, and is of the first conductivity type, for example, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 5A and 5B. The sub-gate 57' is formed directly above part of the drift region 52a and is located in the operation region 53a on the drift oxide region 54. As seen from Fig. 5B of the upper view, the sub-gate 57' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 57. And the sub-gate 27' spans the entire operating area 23a in the width direction. In the vertical direction, the sub-gate 57' is located on the drift oxide region 54 and connected to the drift oxide region 54. In this embodiment, as shown in the figure, the high-voltage element 500 includes, for example, a sub-gate 57', which is directly connected to the gate 57. According to the high-voltage component of the present invention, the high-voltage component 500 may also include a plurality of sub-gates. The conductive layer of the sub-gate 57' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type.

The source 58 and the drain 59 have the first conductivity type. In the vertical direction, the source 58 and the drain 59 are formed under the upper surface 51a and connected to the operating area 53a of the upper surface 51a, and the source 58 and the drain 59 are respectively located in the body region 56 below the gate 57 in the channel direction (as indicated by the dashed arrow direction in Figure 5B, the same below) and in the well region 52 on the side away from the body region 56, and in the channel direction Above, the drift region 52a is located between the drain 59 and the body region 56, and separates the drain 59 and the body region 56, and is located in the well region 52 near the upper surface 51a, and is used as a drift of the high-voltage element 500 in the conduction operation The current channel, as seen from Figure 5B of the top view, in the channel direction, the sub-gate 57' is between the gate 57 and the drain 59, and in the vertical direction, the source 58 and the drain 59 are located on the top The surface 51a is below and connected to the upper surface 51a.

In this embodiment, the conductive layer of the gate 57 has the first conductivity type, and the conductive layer of the sub-gate 57' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 57' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the first embodiment is that in the first embodiment, the gate 27 and the sub-gate 27' are separated and not directly connected to each other; while in this embodiment, the sub-gate 27' And the gate 57 are directly connected to each other.

Please refer to Figures 6A and 6B, which show the fifth embodiment of the present invention. 6A and 6B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 600. As shown in FIGS. 6A and 6B, the high-voltage element 600 includes: a semiconductor layer 61', a well region 62, an insulating structure 63, a drift oxide region 64, a conductive connection structure 65, a body region 66, a gate 67, and a sub-gate 67' , Source 68 and drain 69. The semiconductor layer 61' is formed on the substrate 61, and the semiconductor layer 61' is in a vertical direction (as indicated by the direction of the dashed arrow in Figure 6A, the same below), and has an upper surface 61a and a lower surface 61b opposite to each other. The substrate 61 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 61' is formed on the substrate 61 by, for example, an epitaxial step, or a part of the substrate 61 is used as the semiconductor layer 61'. The method of forming the semiconductor layer 61' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 6A and 6B, where the insulating structure 63 is formed on the upper surface 61a and connected to the upper surface 61a to define the operation area 63a (as indicated by the dashed frame in FIG. 6B). The insulating structure 63 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 64 is formed on the upper surface 61a and connected to the upper surface 61a, and is located on the drift region 62a (as indicated by the dashed frame in Figure 6A) in the operation region 63a and connected to the drift region 62a.

The well region 62 has the first conductivity type and is formed in the operation region 63a of the semiconductor layer 61'. In the vertical direction, the well region 62 is located under the upper surface 61a and connected to the upper surface 61a. The body region 66 has the second conductivity type and is formed in the well region 62 of the operation region 63a. In the vertical direction, the body region 66 is located under the upper surface 61a and connected to the upper surface 61a. The gate 67 is formed in the operating area 63a on the upper surface 61a of the semiconductor layer 61'. From the top view, the gate 67 is substantially along the width direction (as indicated by the solid arrow direction in Figure 6B, The same below) is a rectangle extending from the top, and in the vertical direction, a part of the body region 66 is located directly under the gate 67 and connected to the gate 67 to provide a reverse current channel for the high-voltage device 600 during the on operation. The conductive layer of the gate 67 is doped with impurities of the first conductivity type, and is of the first conductivity type, for example, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 6A and 6B. The sub-gate 67' is formed directly above a portion of the drift region 62a, and is located in the operating region 63a on the drift oxide region 64. As seen from Fig. 6B of the upper view, the sub-gate 67' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 67. And the sub-gate 67' spans the entire operating area 63a in the width direction. In the vertical direction, the sub-gate 67' is located on the drift oxidation region 64 and connected to the drift oxidation region 64. In this embodiment, the high-voltage component 600 includes, for example, a sub-gate 67'. According to the high-voltage component of the present invention, the high-voltage component 600 may also include a plurality of sub-gates 67'. The conductive layer of the sub-gate 67' is a pure semiconductor structure. In this embodiment, the sub-gate 67' and the gate 67 are not directly connected, and are electrically connected to each other via the conductive connection structure 65. In other embodiments, the sub-gate 67' may also be electrically connected to the source 68. In a preferred embodiment, on the upper surface 61a connected to the body region 66 and the source electrode 68, there is a metal silicide layer (not shown, detailed later) for electrically connecting the body region 66 and the source electrode 68. The source 68; therefore, in this embodiment, the sub-gate 67' is also electrically connected to the body region 66. In another preferred embodiment, the sub-gate 67' may also be electrically floating.

The source 68 and the drain 69 have the first conductivity type. In the vertical direction, the source 68 and the drain 69 are formed under the upper surface 61a and connected to the operation area 63a of the upper surface 61a, and the source 68 and the drain 69 are respectively located in the body area 66 below the outside of the gate 67 in the channel direction (as indicated by the dashed arrow direction in Figure 6B, the same below) and in the well area 62 on the side away from the body area 66, and in the channel direction On the top, the drift region 62a is located between the drain 69 and the body region 66, separates the drain 69 and the body region 66, and is located in the well region 62 near the upper surface 61a, and is used as a drift of the high-voltage element 600 in the conduction operation The current channel, as seen from Figure 6B of the top view, in the channel direction, the sub-gate 67' is between the gate 67 and the drain 69, and in the vertical direction, the source 68 and the drain 69 are located on the top The surface 61a is below and connected to the upper surface 61a. The conductive connection structure 65 is above the gate 67 and the sub-gate 67', and electrically connects the gate 67 and the sub-gate 67', and the conductive connection structure 65 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here.

In this embodiment, the conductive layer of the gate 67 has the first conductivity type, and the conductive layer of the sub-gate 67' has a pure semiconductor structure.

This embodiment is different from the first embodiment in that, in the first embodiment, the conductive layer of the gate 27 has the first conductivity type, and the conductive layer of the sub-gate 27' has the second conductivity type. In this embodiment, the conductive layer of the gate 67 has the first conductivity type, and the conductive layer of the sub-gate 67' has a pure semiconductor structure, such as but not limited to a pure polysilicon structure.

Please refer to Figures 7A and 7B, which show the sixth embodiment of the present invention. 7A and 7B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 700. As shown in Figures 7A and 7B, the high-voltage element 700 includes: a semiconductor layer 71', a buried layer 71", a drift well 72, an insulating structure 73, a drift oxide 74, a conductive connection structure 75, a channel well 76, and a gate electrode 77. Sub-gate 77', source 78 and drain 79. The semiconductor layer 71' is formed on the substrate 71, and the semiconductor layer 71' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 7A, the same below) The upper surface has an upper surface 71a and a lower surface 71b. The substrate 71 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 71' is formed on the substrate 71 by, for example, an epitaxial step, or The part of the substrate 71 is used as the semiconductor layer 71'. The method of forming the semiconductor layer 71' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 7A and 7B, where the insulating structure 73 is formed on the upper surface 71a and connected to the upper surface 71a to define the operation area 73a (as indicated by the dashed frame in FIG. 7B). The insulating structure 73 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 74 is formed on the upper surface 71a and connected to the upper surface 71a, and is located on the drift region 72a (as indicated by the dashed frame in Figure 7A) in the operation region 73a and connected to the drift region 72a. In this embodiment, the operating area 73a defined by the insulating structure 73 has only one high-voltage element 700, but the present invention is not limited to this. The operating area 73a defined by the insulating structure 73 may also include a plurality of high-voltage elements, such as mirror images. The two high-voltage components arranged in the arrangement are well known to those with ordinary knowledge in the art, and will not be repeated here.

The drift well region 72 has the first conductivity type and is formed in the operation region 73a of the semiconductor layer 71'. In the vertical direction, the drift well region 72 is located under the upper surface 71a and connected to the upper surface 71a. The channel well area 76 has the second conductivity type and is formed in the operation area 73a under the upper surface 71a. In the vertical direction, the channel well area 76 is located under the upper surface 71a and connected to the upper surface 71a. The passage well area 76 and the drift well area 72 are adjacent in the direction of the passage (as indicated by the direction of the solid arrow in Figure 7A, the same below). The gate electrode 77 is formed in the operating area 73a on the upper surface 71a of the semiconductor layer 71'. From the top view, the gate electrode 77 is substantially along the width direction (as indicated by the solid arrow direction in Figure 7B, The same below) is a rectangle extending from the top, and in the vertical direction, a part of the channel well region 76 is located directly below the gate 77 and connected to the gate 77 to provide a reverse current channel for the high-voltage element 700 in the conduction operation. The conductive layer of the gate electrode 77 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 7A and 7B. The sub-gate 77' is formed directly above a portion of the drift region 72a, and is located in the operating region 73a on the drift oxide region 74. As seen from Figure 7B of the upper view, the sub-gate 77' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 77. And the sub-gate 77' spans the entire operating area 73a in the width direction. In the vertical direction, the sub-gate 77' is located on the drift oxide region 74 and connected to the drift oxide region 74. In this embodiment, the high-voltage element 700 includes, for example, a sub-gate 77'. According to the high-voltage component of the present invention, the high-voltage component 700 may also include a plurality of sub-gates 77'. The conductive layer of the sub-gate 77' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. In this embodiment, the sub-gate 77' and the gate 77 are not directly connected, and are electrically connected to each other via the conductive connection structure 75. In other embodiments, the sub-gate 77' may also be electrically connected to the source 78. In a preferred embodiment, on the upper surface 71a connected to the body region 76 and the source electrode 78, there is a metal silicide layer (not shown, such as the metal silicide layer 48' shown in FIG. 4A), It is used to electrically connect the body region 76 and the source electrode 78; therefore, in this embodiment, the sub-gate 77' is also electrically connected to the body region 76. In another preferred embodiment, the sub-gate 77' may also be electrically floating.

The source 78 and the drain 79 have the first conductivity type. In the vertical direction, the source 78 and the drain 79 are formed under the upper surface 71a and connected to the operation area 73a of the upper surface 71a, and the source 78 and the drain 79 are respectively located in the channel well region 76 below the gate 77 in the channel direction and in the drift well region 72 on the side away from the channel well region 76, and in the channel direction, the drift region 72a is located at the drain 79 and the channel well region 76 And separates the drain 79 and the body region 76, and is located in the drift well region 72 near the upper surface 71a, which is used as a drift current channel for the high-voltage element 700 in the conduction operation, and is viewed from the top view in FIG. 7B In the channel direction, the sub-gate 77' is between the gate 77 and the drain 79, and in the vertical direction, the source 78 and the drain 79 are located under the upper surface 71a and connected to the upper surface 71a. The conductive connection structure 75 is formed above the gate electrode 77 and the sub-gate 77' to electrically connect the gate electrode 77 and the sub-gate 77', and the conductive connection structure 75 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here. The buried layer 71" has the first conductivity type and is formed under the channel well region 76 in the vertical direction and connected to the channel well region 76, and the buried layer 71" is in the operation region 73a and completely covers the channel well region 76. In the vertical direction, the buried layer 71" is, for example, formed on both sides of the interface between the substrate 71 and the semiconductor layer 71', a part of the buried layer 71" is located in the substrate 71, and a part of the buried layer 71" is located in the semiconductor layer 71' to provide electrical The channel well area 76 and the base plate 71 are isolated.

In this embodiment, the conductive layer of the gate 77 has the first conductivity type, and the conductive layer of the sub-gate 77' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 77' can also be a pure semiconductor structure, such as a pure polysilicon structure.

In a preferred embodiment, as shown in FIGS. 7A and 7B, the sub-gate 77' and the gate 77 are connected by the conductive connection structure 75, and are not connected to each other. In a preferred embodiment, as shown in FIGS. 7A and 7B, the sub-gate 77' includes a conductive layer 771' and a sub-gate spacer layer 772'. In a preferred embodiment, as shown in FIGS. 7A and 7B, the drift oxide region 74 is a completely connected structure and is not divided into different blocks.

Please refer to Figures 8A and 8B, which show the seventh embodiment of the present invention. 8A and 8B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 800. As shown in Figures 8A and 8B, the high-voltage element 800 includes: a semiconductor layer 81', a buried layer 81", a drift well region 82, an insulating structure 83, a drift oxide region 84, a conductive connection structure 85, a channel well region 86, and a gate electrode 87. Sub-gate 87', source 88 and drain 89. The semiconductor layer 81' is formed on the substrate 81, and the semiconductor layer 81' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 8A, the same below) The upper surface has an upper surface 81a and a lower surface 81b. The substrate 81 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 81' is formed on the substrate 81 by, for example, an epitaxial step, or The part of the substrate 81 is used as the semiconductor layer 81'. The method of forming the semiconductor layer 81' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 8A and 8B, where the insulating structure 83 is formed on the upper surface 81a and connected to the upper surface 81a to define the operating area 83a (as indicated by the dashed frame in FIG. 8B). The insulating structure 83 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 84 is formed on the upper surface 81a and connected to the upper surface 81a, and is located on the drift region 82a (as indicated by the dashed frame in Figure 8A) in the operation region 83a and connected to the drift region 82a.

The drift well region 82 has the first conductivity type and is formed in the operation region 83a of the semiconductor layer 81'. In the vertical direction, the drift well region 82 is located under the upper surface 81a and connected to the upper surface 81a. The channel well area 86 has the second conductivity type and is formed in the operation area 83a under the upper surface 81a. In the vertical direction, the channel well area 86 is located under the upper surface 81a and connected to the upper surface 81a. The passage well area 86 and the drift well area 82 are adjacent in the direction of the passage (as indicated by the direction of the solid arrow in Figure 8A, the same below). The gate electrode 87 is formed in the operating area 83a on the upper surface 81a of the semiconductor layer 81'. From the top view, the gate electrode 87 is substantially along the width direction (as indicated by the solid arrow direction in Figure 8B, The same below) is a rectangle extending from above, and in the vertical direction, a part of the channel well region 86 is located directly below the gate electrode 87 and connected to the gate electrode 87 to provide a reverse current channel for the high-voltage element 800 in the conduction operation. The conductive layer of the gate electrode 87 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 8A and 8B. The sub-gate 87' is formed directly above part of the drift region 72a and is located in the operating region 83a on the drift oxide region 84. As seen from Fig. 8B of the upper view, the sub-gates 87' are substantially rectangular extending along the width direction and are arranged in parallel with the gates 87. And the sub-gate 77' spans the entire operating area 73a in the width direction. In the vertical direction, the sub-gate 87' is located on the drift oxidation region 84 and connected to the drift oxidation region 84. In this embodiment, the high-voltage element 800 includes, for example, two sub-gates 87'. According to the high-voltage component of the present invention, the high-voltage component 800 may also include one or other number of sub-gates. The conductive layer of the sub-gate 87' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. In this embodiment, the sub-gate 87' and the gate 87 are not directly connected, and are electrically connected to each other via the conductive connection structure 85. In other embodiments, the sub-gate 87' may also be electrically connected to the source 88. In a preferred embodiment, on the upper surface 81a connected to the body region 86 and the source electrode 88, there is a metal silicide layer (not shown, such as the metal silicide layer 48' shown in FIG. 4A), It is used to electrically connect the body region 86 and the source electrode 88; therefore, in this embodiment, the sub-gate 87' is also electrically connected to the body region 86. In another preferred embodiment, the sub-gate 87' may also be electrically floating.

The source 88 and the drain 89 have the first conductivity type. In the vertical direction, the source 88 and the drain 89 are formed under the upper surface 81a and connected to the operation area 83a of the upper surface 81a, and the source 88 and the drain 89 are respectively located in the channel well region 86 below the gate 87 in the channel direction and in the drift well region 82 on the side away from the channel well region 86, and in the channel direction, the drift region 82a is located at the drain 89 and the channel well region 86 And separates the drain 79 and the body region 76, and is located in the drift well region 82 near the upper surface 81a, which is used as a drift current channel for the high-voltage element 800 in the conduction operation, and is seen from the top view in FIG. 8B In the channel direction, the sub-gate 87' is between the gate 87 and the drain 89, and in the vertical direction, the source 88 and the drain 89 are located under the upper surface 81a and connected to the upper surface 81a. The conductive connection structure 85 is formed above the gate electrode 87 and the sub-gate 87' to electrically connect the gate electrode 87 and the sub-gate 87', and the conductive connection structure 85 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here. The buried layer 81" has the first conductivity type and is formed under the channel well region 86 and connected to the channel well region 86 in the vertical direction, and the buried layer 81" is in the operation region 83a and completely covers the channel well region 86 below. In the vertical direction, the buried layer 81" is formed, for example, on both sides of the interface between the substrate 81 and the semiconductor layer 81', a part of the buried layer 81" is located in the substrate 81, and a part of the buried layer 81" is located in the semiconductor layer 81' to provide electrical The channel well area 86 and the base plate 81 are isolated.

In this embodiment, the conductive layer of the gate electrode 87 has the first conductivity type, and the conductive layer of the sub-gate 87' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 87' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that in the sixth embodiment, the drift oxide region 74 is a LOCOS structure, while in this embodiment, the drift oxide region 84 is a chemical vapor deposition ( chemical vapor deposition, CVD) oxidation zone. The CVD oxide region is formed by the deposition step of the CVD process, which is well known to those with ordinary knowledge in the art, and will not be repeated here. This embodiment is different from the sixth embodiment. Another point is that in the sixth embodiment, the number of sub-gate 77' is one, while in this embodiment, the number of sub-gate 87' For two. This embodiment is different from the sixth embodiment. Another point is that, in the sixth embodiment, a part of the gate electrode 77 covers directly above the drift oxide region 74, while in this embodiment, the gate electrode 87 It does not cover directly above the drift oxidation region 84, and the sub-gate 87' is completely located above the drift oxidation region 84.

Please refer to Figures 9A and 9B, which show the eighth embodiment of the present invention. 9A and 9B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 900. As shown in FIGS. 9A and 9B, the high-voltage element 900 includes: a semiconductor layer 91', a buried layer 91", a drift well region 92, an insulating structure 93, a drift oxide region 94, a conductive connection structure 95, a channel well region 96, and a gate electrode 97. Two sub-gates 97', source 98 and drain 99. The semiconductor layer 91' is formed on the substrate 91, and the semiconductor layer 91' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 9A, the same below The upper surface has a relatively upper surface 91a and a lower surface 91b. The substrate 91 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 91' is formed on the substrate 91 by, for example, an epitaxial step, or The part of the substrate 91 is used as the semiconductor layer 91'. The method of forming the semiconductor layer 91' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 9A and 9B, where the insulating structure 93 is formed on the upper surface 91a and connected to the upper surface 91a to define the operation area 93a (as indicated by the dashed frame in FIG. 9B). The insulating structure 93 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 94 is formed on the upper surface 91a and connected to the upper surface 91a, and is located on and connected to the drift region 92a (as indicated by the dashed frame in Figure 9A) in the operation region 93a.

The drift well region 92 has the first conductivity type and is formed in the operation region 93a of the semiconductor layer 91'. In the vertical direction, the drift well region 92 is located under the upper surface 91a and connected to the upper surface 91a. The channel well region 96 has the second conductivity type and is formed in the operation region 93a under the upper surface 91a. In the vertical direction, the channel well region 96 is located under the upper surface 91a and connected to the upper surface 91a. The passage well area 96 and the drift well area 92 are adjacent to each other in the direction of the passage (as indicated by the direction of the solid arrow in Figure 9A, the same below). The gate 97 is formed in the operating area 93a on the upper surface 91a of the semiconductor layer 91'. From the top view, the gate 97 is substantially along the width direction (as indicated by the solid arrow direction in Figure 9B, The same below) is a rectangle extending from the top, and in the vertical direction, part of the channel well 96 is located directly below the gate 97 and connected to the gate 97 to provide a reverse current channel for the high-voltage element 900 in the conduction operation. The conductive layer of the gate electrode 97 is doped with impurities of the first conductivity type, and is of the first conductivity type, for example, but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 9A and 9B. The sub-gate 97' is formed directly above part of the drift region 72a and is located in the operating region 93a on the drift oxide region 94. As seen from Fig. 9B of the upper view, the sub-gate 97' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 97. And the sub-gate 97' spans the entire operating area 93a in the width direction. In the vertical direction, the sub-gate 97' is located on the drift oxidation region 94 and connected to the drift oxidation region 94. In this embodiment, the high-voltage element 900 includes two sub-gates 97', for example. According to the high-voltage component of the present invention, the high-voltage component 900 may also include one or other multiple sub-gates. The conductive layer of the sub-gate 97' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. In this embodiment, one of the sub-gate 97' is not directly connected to the gate 97, and the sub-gate 97' is electrically connected to the source 98 and the body region, for example, through the conductive connection structure 95 and the silicide layer 98'. 96 and the body electrode 96', and the other sub-gate 97' is electrically floating, for example. In other embodiments, at least one sub-gate 97' may also be electrically connected to the gate 97. The metal silicide layer 98' is formed on the upper surface 91a connected to the body region 96 and the source electrode 98. For example, a metal such as cobalt or titanium is used in a self-aligned process to react with silicon atoms to form a metal silicide. The layer 98' has a good conductive effect, which is well known to those with ordinary knowledge in the art, and will not be repeated here.

The source 98 and the drain 99 have the first conductivity type. In the vertical direction, the source 98 and the drain 99 are formed under the upper surface 91a and connected to the operation area 93a of the upper surface 91a, and the source 98 and the drain 99 are respectively located in the channel well region 96 below the gate 97 in the channel direction and in the drift well region 92 on the side away from the channel well region 96, and in the channel direction, the drift region 92a is located at the drain 99 and the channel well region 96 It separates the drain 99 and the body region 96, and is located in the drift well region 92 near the upper surface 91a, used as a drift current channel for the high-voltage element 900 in the conduction operation, and is seen from the top view, Figure 9B In the channel direction, the sub-gate 97' is between the gate 97 and the drain 99, and in the vertical direction, the source 98 and the drain 99 are located under the upper surface 91a and connected to the upper surface 91a. The conductive connecting structure 95 is electrically connected to the silicide metal layer 98' and the sub-gate 97' above the gate 97 and the sub-gate 97', and the conductive connecting structure 95 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here. The buried layer 91" has the first conductivity type and is formed under the channel well region 96 and connected to the channel well region 96 in the vertical direction, and the buried layer 91" is in the operation region 93a and completely covers the channel well region 96. In the vertical direction, the buried layer 91" is formed, for example, on both sides of the interface between the substrate 91 and the semiconductor layer 91', a part of the buried layer 91" is located in the substrate 91, and a part of the buried layer 91" is located in the semiconductor layer 91' to provide electrical The channel well 96 and the substrate 91 are isolated.

In this embodiment, the conductive layer of the gate 97 has the first conductivity type, and the conductive layer of the sub-gate 97' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 97' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the drift oxide region 74 is a LOCOS structure, while in this embodiment, the drift oxide region 94 is shallow trench insulation ( shallow trench isolation, STI) structure. The STI structure is well-known to those with ordinary knowledge in the field, and will not be repeated here. This embodiment is different from the sixth embodiment. Another point is that in the sixth embodiment, the number of sub-gates 77' is one, while in this embodiment, the number of sub-gates 97' is For two. This embodiment is different from the sixth embodiment. Another point is that in the sixth embodiment, the sub-gate 77' is electrically connected to the gate 77, while in this embodiment, one of the sub-gates The pole 97' is electrically connected to the source 98, the body electrode 96', and the body region 96, and the other sub-gate 97' is electrically floating.

Please refer to Figures 10A and 10B, which show the ninth embodiment of the present invention. 10A and 10B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 1000. As shown in Figures 10A and 10B, the high-voltage device 1000 includes: a semiconductor layer 101', a buried layer 101", a drift well region 102, an insulating structure 103, a drift oxide region 104, a conductive connection structure 105, a channel well region 106, and a gate electrode 107, sub-gate 107', source 108 and drain 109. The semiconductor layer 101' is formed on the substrate 101, and the semiconductor layer 101' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 10A, the same below) The upper surface has an upper surface 101a and a lower surface 101b. The substrate 101 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 101' is formed on the substrate 101 by, for example, an epitaxial step, or The part of the substrate 101 is used as the semiconductor layer 101'. The method of forming the semiconductor layer 101' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 10A and 10B, where the insulating structure 103 is formed on the upper surface 101a and connected to the upper surface 101a to define the operation area 103a (as indicated by the dashed frame in FIG. 10B). The insulating structure 103 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 104 is formed on the upper surface 101a and connected to the upper surface 101a, and is located on the drift region 102a (as indicated by the dashed frame in Figure 10A) in the operation region 103a and connected to the drift region 102a.

The drift well region 102 has the first conductivity type and is formed in the operation region 103a of the semiconductor layer 101'. In the vertical direction, the drift well region 102 is located under the upper surface 101a and connected to the upper surface 101a. The channel well region 106 has the second conductivity type and is formed in the operation region 103a under the upper surface 101a. In the vertical direction, the channel well region 106 is located under the upper surface 101a and connected to the upper surface 101a. The passage well area 106 and the drift well area 102 are adjacent to each other in the direction of the passage (as indicated by the direction of the solid arrow in Figure 10A, the same below). The gate electrode 107 is formed in the operating area 103a on the upper surface 101a of the semiconductor layer 101'. From the top view, the gate electrode 107 is roughly along the width direction (as indicated by the solid arrow direction in Figure 10B, The same below) is a rectangle extending from the top, and in the vertical direction, a part of the channel well region 106 is located directly below the gate 107 and connected to the gate 107 to provide a reverse current channel for the high-voltage device 1000 in the conduction operation. The conductive layer of the gate electrode 107 is doped with impurities of the first conductivity type, and is of the first conductivity type, for example, but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 10A and 10B. The sub-gate 107' is formed directly above part of the drift region 102a and is located in the operating region 103a on the drift oxide region 104. As seen from Fig. 10B of the upper view, the sub-gates 107' are substantially rectangular extending along the width direction and are arranged in parallel with the gates 107. And the sub-gate 107' spans the entire operating area 103a in the width direction. In the vertical direction, the sub-gate 107' is located on the drift oxide region 104 and connected to the drift oxide region 104. In this embodiment, the high-voltage element 1000 includes, for example, a sub-gate 107', and the sub-gate 107' and the gate 107 are directly connected to each other. The conductive layer of the sub-gate 107' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type.

The source 108 and the drain 109 have the first conductivity type. In the vertical direction, the source 108 and the drain 109 are formed under the upper surface 101a and connected to the operation area 103a of the upper surface 101a, and the source 108 and the drain 109 are respectively located in the channel well zone 106 below the gate 107 in the channel direction and in the drift well zone 102 on the side away from the channel well zone 106, and in the channel direction, the drift zone 102a is located at the drain 109 and the channel well zone 106 It separates the drain 109 from the body region 106, and is located in the drift well region 102 near the upper surface 101a, used as a drift current channel for the high-voltage element 1000 in the conduction operation, and is viewed from the top view of FIG. 10B In the channel direction, the sub-gate 107' is between the gate 107 and the drain 109, and in the vertical direction, the source 108 and the drain 109 are located under the upper surface 101a and connected to the upper surface 101a. The conductive connection structure 105 is formed above the gate 107 and the sub-gate 107', electrically connecting the gate 107 and the sub-gate 107', and the conductive connection structure 105 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here. The buried layer 101" has the first conductivity type and is formed under the channel well region 106 and connected to the channel well region 106 in the vertical direction, and the buried layer 101" is in the operation region 103a and completely covers the channel well region 106. In the vertical direction, the buried layer 101" is, for example, formed on both sides of the interface between the substrate 101 and the semiconductor layer 101', a part of the buried layer 101" is located in the substrate 101, and a part of the buried layer 101" is located in the semiconductor layer 101' to provide electrical The channel well region 106 and the substrate 101 are isolated.

In this embodiment, the conductive layer of the gate 107 has the first conductivity type, and the conductive layer of the sub-gate 107' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 107' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the sub-gate 77' and the gate 77 are not directly connected to each other; while in this embodiment, the sub-gate 107 'And the gate 107 are directly connected to each other.

Please refer to Figures 11A and 11B, which show the tenth embodiment of the present invention. 11A and 11B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage component 1100. As shown in Figures 11A and 11B, the high-voltage element 1100 includes: a semiconductor layer 111', a buried layer 111", a drift well 112, an insulating structure 113, a drift oxide 114, a conductive connection structure 115, a channel well 116, and a gate. 117, sub-gate 117', source 118, and drain 119. The semiconductor layer 111' is formed on the substrate 111, and the semiconductor layer 111' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 11A, the same below) The upper surface has an upper surface 111a and a lower surface 111b. The substrate 111 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 111' is formed on the substrate 111 by, for example, an epitaxial step, or The part of the substrate 111 is used as the semiconductor layer 111'. The method of forming the semiconductor layer 111' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 11A and 11B, where the insulating structure 113 is formed on the upper surface 111a and connected to the upper surface 111a to define the operation area 113a (as indicated by the dashed frame in FIG. 11B). The insulating structure 113 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 114 is formed on the upper surface 111a and connected to the upper surface 111a, and is located on the drift region 112a (as indicated by the dashed frame in Figure 11A) in the operation region 113a and connected to the drift region 112a.

The drift well region 112 has the first conductivity type and is formed in the operation region 113a of the semiconductor layer 111'. In the vertical direction, the drift well region 112 is located under the upper surface 111a and connected to the upper surface 111a. The channel well region 116 has the second conductivity type and is formed in the operation region 113a under the upper surface 111a. In the vertical direction, the channel well region 116 is located under the upper surface 111a and connected to the upper surface 111a. The passage well area 116 and the drift well area 112 are adjacent to each other in the direction of the passage (as indicated by the direction of the solid arrow in Figure 11A, the same below). The gate electrode 117 is formed in the operating area 113a on the upper surface 111a of the semiconductor layer 111'. From the top view, the gate electrode 117 is substantially along the width direction (as indicated by the solid arrow direction in Figure 11B, The same below) is a rectangle extending from the top, and in the vertical direction, a part of the channel well 116 is located directly below the gate electrode 117 and connected to the gate electrode 117 to provide a reverse current channel for the high-voltage component 1100 in the conduction operation. The conductive layer of the gate electrode 117 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Please continue to refer to FIGS. 11A and 11B. The sub-gate 117' is formed directly above part of the drift region 112a and is located in the operating region 113a on the drift oxide region 114. As seen from Fig. 11B of the upper view, the sub-gates 117' are substantially rectangular extending along the width direction and are arranged in parallel with the gates 117. And the sub-gate 117' spans the entire operating area 113a in the width direction. In the vertical direction, the sub-gate 117' is located on the drift oxide region 114 and connected to the drift oxide region 114. In this embodiment, the high-voltage component 1100 includes, for example, a sub-gate 117'. According to the high-voltage component of the present invention, the high-voltage component 1100 may also include a plurality of sub-gates. The conductive layer of the sub-gate 27' is a pure semiconductor structure, such as a pure polysilicon structure. In this embodiment, the sub-gate 117' and the gate 117 are not directly connected, and are electrically connected to each other via the conductive connection structure 115. In other embodiments, the sub-gate 117' may also be electrically connected to the source 118. In another preferred embodiment, the sub-gate 117' may also be electrically floating.

The source electrode 118 and the drain electrode 119 have the first conductivity type. In the vertical direction, the source electrode 118 and the drain electrode 119 are formed under the upper surface 111a and connected to the operation area 113a of the upper surface 111a, and the source electrode 118 and the drain electrode 118 119 are respectively located in the channel well zone 116 below the gate 117 in the channel direction and in the drift well zone 112 on the side away from the channel well zone 116, and in the channel direction, the drift zone 112a is located at the drain 119 and the channel well zone 116 It separates the drain 119 and the body region 116, and is located in the drift well region 112 near the upper surface 111a, used as a drift current channel for the high-voltage element 1100 in the conduction operation, and is seen from the top view in Figure 11B In the channel direction, the sub-gate 117' is between the gate 117 and the drain 119, and in the vertical direction, the source 118 and the drain 119 are located under the upper surface 111a and connected to the upper surface 111a. The conductive connection structure 115 is formed above the gate electrode 117 and the sub-gate 117' to electrically connect the gate electrode 117 and the sub-gate 117', and the conductive connection structure 115 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process are well known to those with ordinary knowledge in the art, and will not be repeated here. The buried layer 111" has the first conductivity type and is formed under the channel well region 116 in the vertical direction and is connected to the channel well region 116, and the buried layer 111" is in the operation region 113a and completely covers the channel well region 116. In the vertical direction, the buried layer 111" is formed, for example, on both sides of the interface between the substrate 111 and the semiconductor layer 111', a part of the buried layer 111" is located in the substrate 111, and a part of the buried layer 111" is located in the semiconductor layer 111'.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the sub-gate 77' is doped with impurities of the second conductivity type and is of the second conductivity type; Among them, the sub-gate 117' is a pure semiconductor structure, such as but not limited to a pure polysilicon structure.

Please refer to Figures 12A-12G, which show the eleventh embodiment of the present invention. Figures 12A-12G show a schematic cross-sectional view (Figure 12A, 12C, 12D, 12E, 12F, and 12G) or a schematic top view (Figure 12B) of the manufacturing method of the high-voltage component 200. As shown in FIGS. 12A and 12B, first, a semiconductor layer 21' is formed on the substrate 21. The semiconductor layer 21' is in the vertical direction (as indicated by the direction of the dashed arrow in FIG. 12A, the same below), with a relatively above Surface 21a and lower surface 21b. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21 by, for example, an epitaxial step, or a part of the substrate 21 is used as the semiconductor layer 21'. The method of forming the semiconductor layer 21' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIGS. 12A and 12B, and then, an insulating structure 23 and a drift oxide region 24 are formed on the upper surface 21a and connected to the upper surface 21a. The insulating structure 23 is used to define the operating area 23a (as indicated by the dashed box in Figure 12B). The insulating structure 23 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 24 is located on the drift region 22a in the operation region 23a and is connected to the drift region 22a. In this embodiment, the operating area 23a defined by the insulating structure 23 has only one high-voltage component 200, but the present invention is not limited to this. The operating area 23a defined by the insulating structure 23 may also include a plurality of high-voltage components, such as mirror images. The two high-voltage components arranged in the arrangement are well known to those with ordinary knowledge in the art, and will not be repeated here.

Next, referring to FIG. 12C, a well region 22 is formed in the operation region 23a of the semiconductor layer 21', and in the vertical direction, the well region 22 is located under the upper surface 21a and connected to the upper surface 21a. The well region 22 has the first conductivity type. For example, but not limited to ion implantation process steps, the first conductivity type impurities can be implanted into the operation area in the form of accelerated ions, as indicated by the dashed arrow in Figure 12C. 23a, to form a well 22.

Next, referring to FIG. 12D, the body region 26 is formed in the well region 22 of the operation region 23a, and in the vertical direction, the body region 26 is located under the upper surface 21a and connected to the upper surface 21a. The body region 26 has the second conductivity type. The step of forming the body region 26, for example, but not limited to, using a photoresist layer 26' formed by a photolithography process as a mask to dope the second conductivity type impurities into the well region 22, To form a body region 26. Among them, in this embodiment, for example, but not limited to, ion implantation process steps, the second conductivity type impurities are implanted into the well region 22 in the form of accelerated ions to form the body region 26.

Next, referring to Fig. 12E, the gate electrode 27 is formed in the operation area 23a on the upper surface 21a of the semiconductor layer 21'. The direction of the solid arrow in the figure indicates the direction of the arrow extending from the top, and in the vertical direction (as indicated by the direction of the dashed arrow in Figure 12E, the same below), part of the body area 26 is located at the gate 27 is directly below and connected to the gate 27 to provide a reverse current path for the high-voltage component 200 in the on-operation. The conductive layer of the gate electrode 27 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type. The method of forming the conductive layer of the first conductivity type, for example, can use ion implantation process steps to implant the first conductivity type impurities in the form of accelerated ions into the conductive layer of the gate 27 to form the first conductivity type. Conductive layer.

Please continue to refer to Figure 12E. For example, in the process steps of forming the gate 27 in part of the same process, including the deposition of pure semiconductor (such as but not limited to polysilicon) and the formation of a spacer layer, the sub-gate 27' is formed in the drift oxidation process. In the operation area 23a on the area 24. As seen from Figure 2B of the upper view, the sub-gates 27' are substantially rectangular extending along the width direction and are arranged in parallel with the gates 27. In the vertical direction, the sub-gate 27' is located on the drift oxidation region 24 and connected to the drift oxidation region 24. In this embodiment, the high-voltage component 200 includes, for example, a sub-gate 27'. The high-voltage component according to the present invention may include one or other plural sub-gates 27'. The conductive layer of the sub-gate 27' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. The method of forming the conductive layer of the second conductivity type, for example, can use the ion implantation process step to implant the second conductivity type impurities in the form of accelerated ions into the conductive layer of the sub-gate 27' to form the second conductive layer. Type of conductive layer.

Next, referring to FIG. 12F, in the vertical direction, a source 28 and a drain 29 are formed under the upper surface 21a and connected to the operation area 23a of the upper surface 21a, and the source 28 and the drain 29 are located at the gate respectively. 27 In the direction of the channel (as indicated by the direction of the solid arrow in Figure 12F, the same below) in the body region 26 and the well region 22 on the side away from the body region 26, and in the channel direction, the drift zone 22a is located between the drain 29 and the body region 26, in the well region 22 close to the upper surface 21a, and is used as a drift current channel for the high-voltage element 200 in the conduction operation, and it is seen from the top view and Figure 2B, in the channel direction Above, the sub-gate 27' is between the gate 27 and the drain 29, and in the vertical direction (as indicated by the direction of the dashed arrow in Figure 12F, the same below), the source 28 and the drain 29 are located The upper surface 21a is under and connected to the upper surface 21a. The source 28 and the drain 29 have the first conductivity type, and the steps of forming the source 28 and the drain 29, such as but not limited to using a photoresist layer 28' formed by a photolithography process as a mask, remove the first conductivity type impurities They are respectively doped into the body region 26 and the well region 22 to form the source 28 and the drain 29. Among them, in this embodiment, for example, but not limited to, ion implantation process steps, the first conductivity type impurities are implanted in the form of accelerated ions into the body region 26 and the well region 22 to form the source electrode 28 and the drain electrode. 29.

Next, referring to FIG. 12G, a conductive connecting structure 25 is formed to electrically connect the gate 27 and the sub-gate 27' above the gate 27 and the sub-gate 27', and the conductive connecting structure 25 is a conductor. For example, but not limited to, the steps of forming metal lines and conductive plugs in the process steps of semiconductor devices are used to form the conductive connection structure 25, which is well known to those with ordinary knowledge in the art. Do not repeat it.

In a preferred embodiment, as shown in FIG. 12G, the sub-gate 27' and the gate 27 are connected by the conductive connection structure 25, and are not directly connected to each other. In a preferred embodiment, as shown in FIG. 12G, the sub-gate 27' includes a conductive layer 271' and a spacer layer 272'. In a preferred embodiment, as shown in FIG. 12G, the drift oxide region 24 is a completely connected structure and is not divided into different blocks.

Please refer to Figures 13A-13F, which show the twelfth embodiment of the present invention. 13A-13F show a schematic cross-sectional view of the method of manufacturing the high-voltage component 700. As shown in Figure 13A, a semiconductor layer 71' is first formed on the substrate 71. The semiconductor layer 71' is in the vertical direction (as indicated by the direction of the dashed arrow in Figure 13A, the same below), and has a relatively upper surface 71a With the lower surface 71b. The substrate 71 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 71' is formed on the substrate 71 by, for example, an epitaxial step, or a part of the substrate 71 is used as the semiconductor layer 71'. The method of forming the semiconductor layer 71' is well known to those with ordinary knowledge in the art, and will not be repeated here.

Please continue to refer to FIG. 13A, and then, an insulating structure 73 is formed on the upper surface 71a and connected to the upper surface 71a to define the operation area 73a. The insulating structure 73 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. While forming the insulating structure 73, for example, the drift oxide region 74 is formed on the upper surface 71a and connected to the upper surface 71a by the same process steps, and is located in the drift region 72a in the operation region 73a (as shown by the dashed frame in Figure 13B). (Illustrated) on and connected to the drift region 72a. Then, in the vertical direction, a buried layer 71" is formed under the passage well area 76 and connected to the passage well area 76, and the buried layer 71" is in the operation area 73a and completely covers the passage well area 76. In the vertical direction, the buried layer 71" is, for example, formed on both sides of the interface between the substrate 71 and the semiconductor layer 71', a part of the buried layer 71" is located in the substrate 71, and a part of the buried layer 71" is located in the semiconductor layer 71'. The buried layer 71 "With the first conductivity type, for example, but not limited to ion implantation process steps, the first conductivity type impurities can be implanted into the substrate 71 in the form of accelerated ions to form the buried layer 71".

Next, referring to FIG. 13B, a drift well region 72 is formed in the operation region 73a of the semiconductor layer 71', and in the vertical direction, the drift well region 72 is located under the upper surface 71a and connected to the upper surface 71a. The drift well region 72 has the first conductivity type, and the steps of forming the drift well region 72, such as but not limited to using a photoresist layer 72' formed by a photolithography process as a mask, doping the semiconductor layer 71 with impurities of the first conductivity type 'In order to form a drift well area 72. In this embodiment, for example, but not limited to, ion implantation process steps, the second conductivity type impurities are implanted into the semiconductor layer 71' in the form of accelerated ions to form the drift well region 72.

Next, referring to FIG. 13C, the passage well area 76 is formed in the operation area 73a under the upper surface 71a, and in the vertical direction, the passage well area 76 is located under the upper surface 71a and connected to the upper surface 71a. The passage well area 76 and the drift well area 72 are adjacent to each other in the direction of the passage (as indicated by the direction of the solid arrow in Figure 13C, the same below). The channel well region 76 has the second conductivity type, and the step of forming the channel well region 76 is, for example, but not limited to, using a photoresist layer 76' formed by a photolithography process as a mask to dope the second conductivity type impurities into the semiconductor layer 71 'In order to form a channel well area 76. In this embodiment, for example, but not limited to, ion implantation process steps, the second conductivity type impurities are implanted into the semiconductor layer 71' in the form of accelerated ions to form the channel well region 76.

Next, referring to Figure 13D, a gate electrode 77 is formed in the operating area 73a on the upper surface 71a of the semiconductor layer 71'. From the top view, the gate electrode 77 is substantially along the width direction (as shown in Figure 7B). The direction of the solid arrow indicates the rectangle extending from the top, and in the vertical direction, part of the channel well area 76 is located directly below the gate 77 and connected to the gate 77 to provide the high-voltage element 700 in the conduction operation The reverse current channel. The conductive layer of the gate electrode 77 is doped with impurities of the first conductivity type and is of the first conductivity type, for example but not limited to a polysilicon structure doped with impurities of the first conductivity type. The method of forming the conductive layer of the first conductivity type, for example, can use the ion implantation process steps to implant the first conductivity type impurities in the form of accelerated ions into the conductive layer of the gate 77 to form the first conductivity type. Conductive layer.

Please continue to refer to FIG. 13D. For example, in the part of the same process steps for forming the gate 77, including the process steps of depositing pure semiconductor (such as but not limited to polysilicon) and forming a spacer layer, the sub-gate 77' is formed in the drift In the operation zone 73a on the oxidation zone 74. As seen from Figure 7B of the upper view, the sub-gate 77' is approximately a rectangle extending along the width direction and is arranged in parallel with the gate 77. In the vertical direction, the sub-gate 77' is located on the drift oxide region 74 and connected to the drift oxide region 74. In this embodiment, the high-voltage element 700 includes, for example, a sub-gate 77'. The high-voltage device according to the present invention may include one or other plural sub-gates 77'. The conductive layer of the sub-gate 77' is doped with impurities of the second conductivity type and is of the second conductivity type, for example but not limited to a polysilicon structure doped with impurities of the second conductivity type. The method of forming the second conductivity type conductive layer, for example, can use ion implantation process steps to implant the second conductivity type impurities in the form of accelerated ions into the conductive layer of the sub-gate 77' to form the second conductivity Type of conductive layer.

Next, referring to FIG. 13E, in the vertical direction, the source 78 and the drain 79 are formed to have the first conductivity type, and the source 78 and the drain 79 are under the upper surface 71a and connected to the operation area 73a of the upper surface 71a , And the source 78 and the drain 79 are respectively located in the channel well region 76 below the gate 77 outside the channel direction and in the drift well region 72 on the side away from the channel well region 76, and in the channel direction, the drift region 72a is located Between the drain 79 and the channel well region 76, in the drift well region 72 close to the upper surface 71a, it is used as a drift current channel for the high-voltage element 700 in the conduction operation, and it is seen from the top view, Figure 7B, in the channel direction Above, the sub-gate 77' is between the gate 77 and the drain 79, and in the vertical direction, the source 78 and the drain 79 are located under the upper surface 71a and connected to the upper surface 71a. The source electrode 78 and the drain electrode 79 have the first conductivity type, and the steps of forming the source electrode 78 and the drain electrode 79, such as but not limited to using a photoresist layer 78' formed by a photolithography process step as a mask, remove the first conductivity type impurity They are respectively doped into the channel well region 76 and the drift well region 72 to form a source 78 and a drain 79. Among them, in this embodiment, for example, but not limited to, ion implantation process steps, the first conductivity type impurities can be implanted in the channel well region 76 and the drift well region 72 in the form of accelerated ions to form the source electrode 78 and the drift well region 72. Dip pole 79.

Next, referring to FIG. 13F, a conductive connecting structure 75 is formed to electrically connect the gate 77 and the sub-gate 77' above the gate 77 and the sub-gate 77', and the conductive connecting structure 75 is a conductor. For example, but not limited to, the steps of forming metal lines and conductive plugs in the process steps of semiconductor devices are used to form the conductive connection structure 75, which is well known to those with ordinary knowledge in the art. Do not repeat it.

In a preferred embodiment, as shown in FIG. 13F, the sub-gate 77' and the gate 77 are connected by a conductive connection structure 75, and are not connected to each other. In a preferred embodiment, as shown in FIG. 13F, the sub-gate 77' includes a sub-gate conductive layer 771' and a sub-gate spacer layer 772'. In a preferred embodiment, as shown in FIG. 13F, the drift oxide region 74 is a completely connected structure and is not divided into different blocks.

FIG. 14A shows the electrical schematic diagram of the gate voltage of the transient response during the turn-on operation of the present invention and the prior art. According to Fig. 14A, the high-voltage component of the present invention has a shorter switching time and better transient response than the prior art. As shown in Figure 14A, the horizontal axis is time, in seconds, and the vertical axis is gate voltage, in volts. Taking the high-voltage component 200 of the first embodiment as an example, in the turning ON operation, compared with the prior art, the gate voltage rises faster according to the present invention. This is because the corresponding capacitance value is relative to The high-voltage component of the prior art drops, so that in the conduction operation, the gate voltage takes a relatively short time to reach the target voltage (for example, but not limited to 3.3V), so the transient response of the high-voltage component according to the present invention is improved.

FIG. 14B shows the electrical schematic diagram of the drain voltage of the transient response during the turn-on operation of the present invention and the prior art. As shown in Figure 14B, the high-voltage component of the present invention has a shorter switching time and better transient response than the prior art. As shown in Figure 14B, the horizontal axis is time, in seconds, and the vertical axis is drain voltage, in volts. Taking the high-voltage component 200 of the first embodiment as an example, in the turning ON operation, compared with the prior art, the drain voltage rises faster according to the present invention. This is because the corresponding capacitance value is relative to The high-voltage component of the prior art drops, so that in the conduction operation, the drain voltage takes a relatively short time to reach the target voltage (for example, but not limited to 12V), so the transient response of the high-voltage component according to the present invention is improved.

The present invention has been described above with respect to preferred embodiments, but the above descriptions are only for making it easier for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the device. For another example, the lithography technology is not limited to the photomask technology, and can also include electron beam lithography technology. All of these can be derived by analogy according to the teachings of the present invention. In addition, each described embodiment is not limited to a single application, and can also be applied in combination, for example, but not limited to combining the two embodiments. Therefore, the scope of the present invention should cover all the above and other equivalent changes. In addition, any implementation type of the present invention does not have to achieve all the objectives or advantages. Therefore, any item of the claimed patent scope should not be limited by this.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: high voltage components 11, 21, 31, 41, 51, 61, 71, 81, 91, 101, 111: substrate 11’,21’,31’,41’,51’,61’,71’,81’,91’,101’,111’: semiconductor layer 11a, 21a, 31a, 41a, 51a, 61a, 71a, 81a, 91a, 101a, 111a: upper surface 11b, 21b, 31b, 41b, 51b, 61b, 71b, 81b, 91b, 101b, 111b: bottom surface 12, 22, 32, 42, 52, 62: Well area 12a, 22a, 32a, 42a, 52a, 62a, 72a, 82a, 92a, 102a, 112a: drift zone 13,23,33,43,53,63,73,83,93,103,113: insulation structure 13a, 23a, 33a, 43a, 53a, 63a, 73a, 83a, 93a, 103a, 113a: operating area 14,24,34,44,54,64,74,84,94,104,114: drift oxide zone 15, 25, 35, 45, 55, 65, 75, 85, 95, 105, 115: conductive connection structure 16,26,36,46,56,66: body area 17,27,37,47,57,67,77,87,97,107,117: gate 17’,27’,37’,47’,57’,67’,77’,87’,97’,107’,117’: Sub-gate 18, 28, 38, 48, 58, 68, 78, 88, 98, 108, 118: source 19,29,39,49,59,69,79,89,99,109,119: drain 48’, 98’: Metal silicide layer 72, 82, 92, 102, 112: drift well area 76, 86, 96, 106, 116: channel well area 271,271’,771’: Conductive layer 272,272’,772’: Interval layer 273: Dielectric layer

1A and 1B respectively show a schematic cross-sectional view and a schematic top view of a prior art high-voltage component 100. Figures 2A and 2B show the first embodiment of the present invention. Figures 3A and 3B show the second embodiment of the present invention. Figures 4A and 4B show the third embodiment of the present invention. Figures 5A and 5B show the fourth embodiment of the present invention. Figures 6A and 6B show the fifth embodiment of the present invention. Figures 7A and 7B show the sixth embodiment of the present invention. Figures 8A and 8B show the seventh embodiment of the present invention. Figures 9A and 9B show the eighth embodiment of the present invention. Figures 10A and 10B show the ninth embodiment of the present invention. Figures 11A and 11B show the tenth embodiment of the present invention. Figures 12A-12G show the eleventh embodiment of the present invention. Figures 13A-13F show the twelfth embodiment of the present invention. FIG. 14A shows the electrical schematic diagram of the gate voltage of the transient response during the turn-on operation of the present invention and the prior art. FIG. 14B shows the electrical schematic diagram of the drain voltage of the transient response during the turn-on operation of the present invention and the prior art.

200: high voltage components

21: substrate

21’: Semiconductor layer

21a: upper surface

21b: lower surface

22: Well area

23: Insulation structure

23a: operating area

24: drift oxidation zone

25: Conductive connection structure

26: Body area

27: Gate

27’: Sub-gate

271,271’: Conductive layer

272,272’: Interval layer

273: Dielectric layer

28: Source

29: Dip pole

Claims (24)

A high-voltage component including: A semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; A drift oxide region formed on the upper surface and connected to the upper surface, and located on and connected to a drift region in an operation region; A well area having a first conductivity type, formed in the operation area of the semiconductor layer, the well area being located under the upper surface and connected to the upper surface; A body region having a second conductivity type formed in the well region of the operation region, the body region being located under the upper surface and connected to the upper surface; A gate is formed in the operation region on the upper surface of the semiconductor layer, and a part of the body region is located directly under the gate and connected to the gate to provide the high-voltage device with a turn-on operation. To current channel; At least one sub-gate is formed on the drift oxide region and is directly above at least part of the drift region. The sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the drift Oxidation zone; and A source and a drain having the first conductivity type, the source and the drain are formed under the upper surface and connected to the operation area of the upper surface, and the source and the drain are respectively located In the body region below the outside of the gate and in the well region on the side far from the body region, and in a channel direction, the drift region is located between the drain and the body region, near the upper surface In the well region, it is used as a drift current channel of the high-voltage element in the conduction operation, and as seen from the top view, the sub-gate is between the gate and the drain, and the source and the drain Pole located under the upper surface and connected to the upper surface; Wherein, the conductive layer of the gate has the first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure. The high-voltage device according to the first item of the patent application, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical vapor phase Deposition (chemical vapor deposition, CVD) oxidation zone. In the high-voltage component described in item 1 of the scope of patent application, at least one of the sub-gate and the gate are directly connected to each other. In the high-voltage component described in item 1 of the scope of patent application, at least one of the sub-gate and the gate are not directly connected to each other. The high-voltage device described in claim 1, wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes impurities doped with impurities of the second conductivity type The polysilicon structure. As for the high-voltage device described in item 1 of the scope of patent application, the sub-gate is electrically floating or electrically connected to the gate or the source. A method for manufacturing high-voltage components, including: Forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; Forming a drift oxide region on the upper surface and connected to the upper surface, and located on and connected to one of the drift regions in an operating region; Forming a well region in the operation region of the semiconductor layer, and the well region is located below and connected to the upper surface, and the well region has a first conductivity type; Forming a body region in the well region of the operation region, and the body region is located below the upper surface and connected to the upper surface, and the body region has a second conductivity type; A gate is formed in the operating region on the upper surface of the semiconductor layer, and a part of the body region is located directly under the gate and connected to the gate to provide the high-voltage device with an inversion in a turn-on operation Current channel At least one sub-gate is formed on the drift oxide region, and directly above at least part of the drift region, the sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the drift Oxidation zone; and A source and a drain are formed under the upper surface and connected to the operation area of the upper surface. The source and the drain have the first conductivity type and are respectively located below the outside of the gate In the body region and in the well region far away from the body region, and in a channel direction, the drift region is located in the interval between the drain and the body and in the well region close to the upper surface to serve as the high-voltage element In the turn-on operation, a drift current channel is viewed from the top view, the sub-gate is between the gate and the drain, and the source and the drain are located under the upper surface and connected to The upper surface Wherein, the conductive layer of the gate has the first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure. According to the method for manufacturing a high-voltage device described in claim 7, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical Chemical vapor deposition (CVD) oxidation zone. According to the method for manufacturing a high-voltage device described in item 7 of the scope of the patent application, at least one of the sub-gate and the gate are directly connected to each other. According to the manufacturing method of the high-voltage device described in item 7 of the scope of patent application, at least one of the sub-gate and the gate are not directly connected to each other. The method for manufacturing a high-voltage device as described in claim 7, wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes impurities of the second conductivity type Doped polysilicon structure. According to the manufacturing method of the high-voltage device described in item 7 of the scope of patent application, the sub-gate is electrically floating or electrically connected to the gate or the source. A high-voltage component including: A semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; A drift oxide region formed on the upper surface and connected to the upper surface, and located on and connected to a drift region in an operation region; A drift well region having a first conductivity type, formed in the operation region of the semiconductor layer under the upper surface, and the drift well region is located below the upper surface and connected to the upper surface; A channel well region having a second conductivity type, formed in the operation region below the upper surface, the channel well region and the drift well region are adjacent in a channel direction; A buried layer having the first conductivity type, formed under the channel well area and connected to the channel well area, and the buried layer is in the operation area and completely covers the channel well area; A gate is formed in the operation area on the upper surface of the semiconductor layer, and a part of the channel well area is located directly under the gate and connected to the gate to provide the high-voltage device in a conduction operation One reverse current channel; At least one sub-gate is formed on the drift oxide region and directly above at least a part of the drift region. The sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the Drift oxidation zone; and A source electrode and a drain electrode have the first conductivity type, and the source electrode and the drain electrode are formed under the upper surface and connected to the operation area of the upper surface, and the source electrode and the drain electrode are respectively Located in the channel well below the outside of the gate and in the drift well on the side far from the channel well, and in a channel direction, the drift zone is located between the drain and the channel well, close to The drift well region on the upper surface is used as a drift current channel of the high-voltage element in the conduction operation, and as seen from the top view, the sub-gate is between the gate and the drain; Wherein, the conductive layer of the gate has the first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure. The high-voltage device described in claim 13, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical vapor phase Deposition (chemical vapor deposition, CVD) oxidation zone. In the high-voltage device described in item 13 of the scope of patent application, at least one of the sub-gate and the gate are directly connected to each other. For the high-voltage component described in item 13 of the scope of patent application, at least one of the sub-gate and the gate are not directly connected to each other. The high-voltage device described in claim 13, wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes impurities doped with impurities of the second conductivity type The polysilicon structure. For the high-voltage device described in item 13 of the scope of patent application, the sub-gate is electrically floating or connected to the gate or the source. A method for manufacturing high-voltage components, including: Forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other; Forming a drift oxide region on the upper surface and connected to the upper surface, and located on and connected to one of the drift regions in an operating region; Forming a drift well region in the operation region of the semiconductor layer under the upper surface, and the drift well region is located below the upper surface and connected to the upper surface, and the drift well region has a first conductivity type; Forming a channel well region in the operating region below the upper surface, the channel well region having a second conductivity type and adjacent to the drift well region in a channel direction; Forming a buried layer under the channel well area and connected with the channel well area, and the buried layer is in the operation area and completely covers the channel well area, and the buried layer has the first conductivity type; A gate is formed in the operation area on the upper surface of the semiconductor layer, and a part of the channel well area is located directly under the gate and connected to the gate to provide the high-voltage element in a conduction operation Reverse current channel; At least one sub-gate is formed on the drift oxide region, and directly above at least part of the drift region, the sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the drift Oxidation zone; and A source and a drain are formed under the upper surface and connected to the operation area of the upper surface. The source and the drain have the first conductivity type and are respectively located below the outside of the gate In the channel well area and in the drift well area far from the channel well area, and in a channel direction, the drift area is located between the drain and the channel well area, in the drift well area close to the upper surface , Used as a drift current channel of the high-voltage component in the turn-on operation, and as seen from the top view, the sub-gate is between the gate and the drain; Wherein, the conductive layer of the gate has a first conductivity type, and the conductive layer of the sub-gate has a second conductivity type or a pure semiconductor structure. According to the method for manufacturing a high-voltage device described in the scope of patent application, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical Chemical vapor deposition (CVD) oxidation zone. According to the method for manufacturing a high-voltage device described in item 19 of the scope of patent application, at least one of the sub-gate and the gate are directly connected to each other. According to the method for manufacturing a high-voltage device described in item 19 of the scope of the patent application, at least one of the sub-gate and the gate are not directly connected to each other. The method for manufacturing a high-voltage device as described in claim 19, wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes impurities of the second conductivity type Doped polysilicon structure. The method for manufacturing a high-voltage device as described in item 19 of the scope of patent application, wherein the sub-gate is electrically floating or electrically connected to the gate or the source.

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