TWI770452B - High voltage device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a high voltage device and manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductive type, and a conductive layer of the sub-gate has a second conductive type or is an intrinsic semiconductor structure.

Description

High voltage component and method of making the same

The present invention relates to a high-voltage component and a manufacturing method thereof, in particular to a high-voltage component and a manufacturing method thereof capable of improving the transient response performance during turn-on operation.

1A and 1B respectively show a schematic cross-sectional view and a schematic top view of a conventional high-voltage device 100 . The so-called high-voltage components herein refer to semiconductor components whose voltages applied to the drain electrodes are higher than 5V during normal operation. Generally speaking, taking the high-voltage device 100 shown in FIGS. 1A and 1B as an example, there is a drift region 12a between the drain 19 and the body region 16 of the high-voltage device 100 (as indicated by the dotted line in FIG. 1A ). The pole 19 is separated from the body region 16, and the lateral length of the drift region 12a is adjusted according to the operating voltage required for normal operation. As shown in FIGS. 1A and 1B , the high voltage device 100 includes a well region 12 , an insulating structure 13 , a drift oxide region 14 , a body region 16 , a gate electrode 17 , a source electrode 18 , and a drain electrode 19 . The conductivity type of the well region 12 is N-type, which is formed on the substrate 11 , and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define the operation region 13 a as the main active region when the high-voltage device 100 operates. . The range of the operation area 13a is indicated by the thick black dashed box in Fig. 1B. As shown in FIG. 1A , a part of the gate electrode 17 is on the drift region 12 a and covers part of the drift oxide region 14 . In general, the thickness of the drift oxide region 14 is about 2,500 to 15,000 angstroms (Å), and the thickness of the gate oxide layer 173 in the gate 17 is about 20 Å to 500 Å. The thickness of the drift oxide region 14 is much higher than the thickness of the gate oxide layer 173, at least 5 times or more. The use of the thick drift oxide region 14 can block the high potential when the high voltage device 100 is not conducting, so that a relatively high electric field falls in the thick drift oxide region 14, so as to improve the non-conduction collapse protection of the high voltage device 100 Voltage. However, although the thick drift oxide region 14 increases the withstand voltage of the high-voltage device 100 (increases the non-conduction breakdown protection voltage), the on-resistance and gate-drain capacitance of the high-voltage device 100 are also relatively increased, resulting in The speed of operation is reduced, reducing the performance of the components.

In view of this, the present invention provides a high-voltage device and a manufacturing method thereof that can increase the operating speed and improve the transient response performance without affecting the thickness of the drift oxide region.

In one aspect, the present invention provides a high-voltage device, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other in a vertical direction; a drift oxide region, formed on the upper surface and connected to the upper surface, and located on a drift region in an operation region and connected to the drift region; a well region, having a first conductivity type, formed in the operation of the semiconductor layer In the region, and in the vertical direction, the well region is located under the upper surface and is connected to the upper surface; a body region, having a second conductivity type, is formed in the well region of the operation region, and is in the vertical direction direction, the body region is located under the upper surface and connected to the upper surface; a gate is formed in the operating region on the upper surface of the semiconductor layer, and part of the body region is located directly below the gate and connected at the gate to provide an inversion current path of the high-voltage element during a conduction operation; at least one sub-gate is formed on the drift oxide region, and at least part of the drift region is directly above the sub-gate The gate electrode is arranged in parallel with the gate electrode, and the sub-gate electrode is located on the drift oxide region and is connected to the drift oxide region; and a source electrode and a drain electrode have the first conductivity type, and the source electrode and the drain electrode are formed in The upper surface is below and connected to the operating region of the upper surface, and the source electrode and the drain electrode are respectively located in the body region below the outer portion of the gate electrode and in the well region away from the body region side, and In a channel direction, the drift region is located between the drain electrode and the body region, in the well region near the upper surface, and is used as a drift current channel of the high-voltage element in the conduction operation, and from the top Viewed from the view, the sub-gate is between the gate and the drain, and the source and the drain are at the same Under the upper surface and connected to the upper surface; wherein, the conductive layer of the gate electrode has the first conductivity type, and the conductive layer of the sub-gate electrode has the second conductivity type or is a pure semiconductor structure.

From another point of view, the present invention provides a method for manufacturing a high-voltage device, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; forming an insulating structure on the upper surface and connected to the upper surface to define an operation region; forming a drift oxide region on the upper surface and connected to the upper surface, and located on a drift region in the operation region and connected to the drift region; forming a drift region A well area is in the operation area of the semiconductor layer, and the well area is located below the upper surface and connected to the upper surface, the well area has a first conductivity type; a body area is formed in the well area of the operation area , and the body region is located below and connected to the upper surface, the body region has a second conductivity type; a gate is formed in the operation region on the upper surface of the semiconductor layer, and part of the body region is located in The gate is directly below and connected to the gate to provide an inversion current path for the high voltage element in a conducting operation; at least one sub-gate is formed on the drift oxide region, and at least part of the drift region is positive Above, the sub-gate is arranged in parallel with the gate, the sub-gate is located on the drift oxide region and connected to the drift oxide region; and a source electrode and a drain electrode are formed under the upper surface and connected to the upper surface In the operation region, the source electrode and the drain electrode have the first conductivity type, and are respectively located in the body region below the outer portion of the gate electrode and in the well region away from the body region side, and in a channel In the direction, the drift region is located between the drain electrode and the body, in the well region near the upper surface, and is used as a drift current channel of the high-voltage element during the conduction operation, and viewed from the top view, the The sub-gate is between the gate and the drain, and the source and the drain are located under the upper surface and are connected to the upper surface; wherein, the conductive layer of the gate has the first conductivity type, And the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure.

In another aspect, the present invention provides a high-voltage device, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; a drift oxide region formed on the upper surface and connected to the upper surface, and located on and connected to a drift region in an operating region in the drift region; a drift well region, having a first conductivity type, formed in the operation region of the semiconductor layer under the upper surface, and the drift well region is located under the upper surface and connected to the upper surface; a channel A well region, having the second conductivity type, is formed in the operating region below the upper surface, the channel well region and the drift well region adjoining in a channel direction; a buried layer, having a first conductivity type, is formed below the channel well region and connected to the channel well region, and the buried layer is in the operating region, completely covering the channel well region; a gate electrode is formed in the operating region on the upper surface of the semiconductor layer , a part of the channel well area is located directly below the gate electrode and is connected to the gate electrode to provide an inversion current channel for the high-voltage element in a conducting operation; at least one sub-gate is formed on the drift oxide region , and directly above at least part of the drift region, the sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected to the drift oxide region; and a source electrode and a drain electrode, with the first conductivity type, and the source electrode and the drain electrode are formed under the upper surface and connected in the operation region of the upper surface, and the source electrode and the drain electrode are respectively located at the outer portion of the gate electrode. In the channel well region and in the drift well region on the side away from the channel well region, and in a channel direction, the drift region is located between the drain electrode and the channel well region, in the drift well region near the upper surface , used as a drift current channel of the high-voltage element during the conduction operation, and viewed from the top view, the sub-gate is between the gate and the drain; wherein, the conductive layer of the gate has The first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or a pure semiconductor structure.

In another aspect, the present invention provides a method for manufacturing a high-voltage device, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; forming a drift oxide region on the upper surface and connected to the upper surface and located on a drift region in the operation region and connected to the drift region; a drift well region is formed in the operation region of the semiconductor layer under the upper surface, and the drift well region is located in the operation region of the semiconductor layer The upper surface is below and connected to the upper surface, the drift well region has a first conductivity type; a channel well region is formed in the operation region under the upper surface, the channel well region has the second conductivity type, and is connected with The drift well region is adjacent in a channel direction; a buried layer is formed below the channel well region and is adjacent to the channel well region area connection, and the buried layer is in the operation area, completely covering the channel well area, the buried layer has the first conductivity type; a gate is formed in the operation area on the upper surface of the semiconductor layer, partially The channel well is located directly below the gate, and is used for providing an inversion current channel of the high-voltage element during a conduction operation; at least one sub-gate is formed on the drift oxide region, and at least part of the drift region is positive Above, the sub-gate is located on the drift oxide region and connected to the drift oxide region; and a source electrode and a drain electrode are formed in the operation region under the upper surface, and the source electrode and the drain electrode have the first a conductivity type, and are located in the channel well region below the outside of the gate electrode and in the drift well region away from the channel well region side, respectively, and in a channel direction, the drift region is located in the drain electrode and the channel Between the well regions, in the drift well region close to the upper surface, it is used as a drift current path of the high-voltage element during the conduction operation, and from the top view, the sub-gate is between the gate and the gate. Between the drain electrodes; wherein, the conductive layer of the gate electrode has a first conductivity type, and the conductive layer of the sub-gate electrode has a second conductivity type or a pure semiconductor structure.

In a preferred embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (chemical vapor deposition) structure. deposition, CVD) oxidation zone.

In a preferred embodiment, at least one of the sub-gate and the gate are directly connected to each other.

In a preferred embodiment, at least one of the sub-gate and the gate are not directly connected to each other.

In a preferred embodiment, the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the sub-gate includes a polysilicon structure doped with impurities of the second conductivity type.

In a preferred embodiment, the sub-gate is electrically floating, or is electrically connected to the gate or the source.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: High Voltage Components

11, 21, 31, 41, 51, 61, 71, 81, 91, 101, 111: Substrates

11', 21', 31', 41', 51', 61', 71', 81', 91', 101', 111': semiconductor layer

11a, 21a, 31a, 41a, 51a, 61a, 71a, 81a, 91a, 101a, 111a: Upper surface

11b, 21b, 31b, 41b, 51b, 61b, 71b, 81b, 91b, 101b, 111b: lower surface

12, 22, 32, 42, 52, 62: Well block

12a, 22a, 32a, 42a, 52a, 62a, 72a, 82a, 92a, 102a, 112a: Drift Region

13, 23, 33, 43, 53, 63, 73, 83, 93, 103, 113: Insulation structure

13a, 23a, 33a, 43a, 53a, 63a, 73a, 83a, 93a, 103a, 113a: Operation area

14, 24, 34, 44, 54, 64, 74, 84, 94, 104, 114: Drift Oxidation Zones

15, 25, 35, 45, 55, 65, 75, 85, 95, 105, 115: Conductive connection structure

16,26,36,46,56,66: Ontology area

17,27,37,47,57,67,77,87,97,107,117: Gate

17', 27', 37', 47', 57', 67', 77', 87', 97', 107', 117': Sub-gate

18, 28, 38, 48, 58, 68, 78, 88, 98, 108, 118: Source

19,29,39,49,59,69,79,89,99,109,119: Drain

48', 98': silicide metal layer

72, 82, 92, 102, 112: Drift Wells

76, 86, 96, 106, 116: Access well area

271, 271', 771': Conductive layer

272, 272', 772': spacer layer

273: Dielectric Layer

1A and 1B respectively show a schematic cross-sectional view and a schematic top view of a prior art high-voltage device 100 .

Figures 2A and 2B show a first embodiment of the present invention.

Figures 3A and 3B show a second embodiment of the present invention.

Figures 4A and 4B show a third embodiment of the present invention.

Figures 5A and 5B show a fourth embodiment of the present invention.

Figures 6A and 6B show a fifth embodiment of the present invention.

Figures 7A and 7B show a sixth embodiment of the present invention.

Figures 8A and 8B show a seventh embodiment of the present invention.

Figures 9A and 9B show an eighth embodiment of the present invention.

Figures 10A and 10B show a ninth embodiment of the present invention.

Figures 11A and 11B show a tenth embodiment of the present invention.

Figures 12A-12G show an eleventh embodiment of the present invention.

Figures 13A-13F show a twelfth embodiment of the present invention.

FIG. 14A is an electrical schematic diagram of the gate voltage of the transient response during the turn-on operation of the present invention and the prior art.

FIG. 14B is an electrical schematic diagram of the drain voltage of the transient response during the turn-on operation of the present invention and the prior art.

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic, mainly intended to represent the process steps and the top-bottom order relationship between the layers, and the shapes, thicknesses and widths are not drawn to scale.

Please refer to FIGS. 2A and 2B, which show a first embodiment of the present invention. 2A and 2B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 200 . As shown in FIGS. 2A and 2B , the high voltage device 200 includes: a semiconductor layer 21 ′, a well region 22 , an insulating structure 23 , a drift oxide region 24 , a conductive connection structure 25 , a body region 26 , a gate 27 , and a sub-gate 27 ′ , source 28 and drain 29 . The semiconductor layer 21' is formed on the substrate 21, and the semiconductor layer 21' has opposite upper surfaces 21a and lower surfaces 21b in the vertical direction (as indicated by the dashed arrow direction in Fig. 2A, the same below). The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21 by, for example, an epitaxial step, or a part of the substrate 21 is used as the semiconductor layer 21'. The method of forming the semiconductor layer 21' is well known to those skilled in the art, and will not be described in detail here.

Please continue to refer to FIGS. 2A and 2B, wherein the insulating structure 23 is formed on the upper surface 21a and connected to the upper surface 21a to define the operation area 23a (as indicated by the dotted box in FIG. 2B). The insulating structure 23 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21a, and is located on and connected to the drift region 22a in the operation region 23a (as indicated by the dotted box in FIG. 2A). In this embodiment, the operating area 23a defined by the insulating structure 23 has only one high-voltage element 200, but the invention is not limited to this, and the operating area 23a defined by the insulating structure 23 may also include a plurality of high-voltage components, such as mirror images The arrangement of the two high-voltage components, etc., is well known to those with ordinary knowledge in the art, and will not be repeated here.

The well region 22 has the first conductivity type and is formed in the operation region 23a of the semiconductor layer 21', and in the vertical direction, the well region 22 is located under and connected to the upper surface 21a. The body region 26 has the second conductivity type and is formed in the well region 22 of the operation region 23a, and in the vertical direction, the body region 26 is located under and connected to the upper surface 21a. The gate electrode 27 is formed in the operating region 23a on the upper surface 21a of the semiconductor layer 21'. From the top view, the gate electrode 27 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 2B, The same below) is a rectangle extending upward, and in the vertical direction, a part of the body region 26 is located directly below the gate electrode 27 and is connected to the gate electrode 27 to provide an inversion current path of the high-voltage device 200 during the turn-on operation. The conductive layer 271 of the gate electrode 27 is doped with impurities of the first conductivity type and is of the first conductivity type, such as but not limited to a polysilicon structure with impurities of the first conductivity type.

Continuing to refer to FIGS. 2A and 2B , the sub-gate 27 ′ is formed just above a portion of the drift region 22 a and in the operating region 23 a on the drift oxide region 24 . As seen from the top view of FIG. 2B , the sub-gate electrodes 27 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 27 . And the sub-gate 27' spans the entire operating region 23a in the width direction. And in the vertical direction, the sub-gate 27' is located on the drift oxide region 24 and connected to the drift oxide region 24 . In this embodiment, the high-voltage element 200 includes, for example, a sub-gate 27'. According to the high-voltage device of the present invention, the high-voltage device 200 may also include a plurality of sub-gates 27'. The conductive layer 271 of the sub-gate 27' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. In this embodiment, the sub-gate 27' and the gate 27 are not directly connected, and are electrically connected to each other via the conductive connection structure 25. In other embodiments, the sub-gate 27' may also be electrically connected to the source 28. In a preferred embodiment, on the upper surface 21a connected to the body region 26 and the source electrode 28, there is a layer of silicide metal (not shown, described in detail later) for electrically connecting the body region 26 and the source electrode 28. source 28 ; thus, in such an embodiment, sub-gate 27 ′ is also electrically connected to body region 26 . In another preferred embodiment, the sub-gate 27' can also be electrically floating.

The source electrode 28 and the drain electrode 29 have the first conductivity type. In the vertical direction, the source electrode 28 and the drain electrode 29 are formed under the upper surface 21a and connected to the operation region 23a of the upper surface 21a, and the source electrode 28 and the drain electrode 29 are respectively located in the body region 26 below the outer portion of the gate 27 in the channel direction (as indicated by the dashed arrow direction in FIG. 2B, the same below) and in the well region 22 on the side away from the body region 26, and in the channel direction On the top, the drift region 22a is located between the drain electrode 29 and the body region 26, separates the drain electrode 29 and the body region 26, and is located in the well region 22 close to the upper surface 21a, and is used for the drift of the high voltage device 200 during the turn-on operation The current channel, and seen from the top view 2B, in the channel direction, the sub-gate 27' is between the gate 27 and the drain 29, and in the vertical direction, the source 28 and the drain 29 are located on top The surface 21a is below and connected to the upper surface 21a. The conductive connection structure 25 is above the gate electrode 27 and the sub-gate electrode 27', and electrically connects the gate electrode 27 and the sub-gate electrode 27', and the conductive connection structure 25 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here.

In this embodiment, the conductive layer of the gate electrode 27 has the first conductivity type, and the conductive layer of the sub-gate 27' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 27' can also be a pure semiconductor structure, such as a pure polysilicon structure.

It should be noted that the so-called inversion current channel refers to a region where an inversion layer is formed under the gate electrode 27 due to the voltage applied to the gate electrode 27 during the turn-on operation of the high-voltage device 200 to allow the turn-on current to pass through. , which is well known by common knowledge in the art, and will not be repeated here.

It should be noted that the so-called drift current channel refers to a region through which the on-current of the high-voltage element 200 drifts during the on-operation operation, which is well known in the art and will not be repeated here.

It should be noted that the upper surface 21a does not refer to a completely flat plane, but refers to a surface of the semiconductor layer 21'. In this embodiment, for example, the part of the upper surface 21a where the drift oxide region 24 is in contact with the upper surface 21a has a sunken part.

It should be noted that the gate electrode 27 includes a conductive layer 271 having conductivity, a dielectric layer 273 connected to the upper surface 21a, and a spacer layer 272 having electrical insulating properties; the sub-gate electrode 27' includes a conductive layer having conductivity 271 ′ and the spacer layer 272 ′ with electrical insulating properties are well known in the art and will not be repeated here.

It should be noted that the aforementioned "first conductivity type" and "second conductivity type" refer to the high-voltage MOS devices where impurities of different conductivity types are doped into the semiconductor constituent regions (such as but not limited to the aforementioned well regions, In the body region, source and drain regions, etc.), the semiconductor composition region becomes the first or second conductivity type (for example, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa ), wherein the first conductivity type and the second conductivity type are conductivity types that are electrically opposite to each other.

In addition, it should be noted that the so-called high-voltage MOS device refers to that the voltage applied to the drain electrode is higher than a specific voltage, such as 5V, and the lateral distance between the body region 26 and the drain electrode 29 (the length of the drift region) during normal operation. ) is adjusted according to the operating voltage it is subjected to during normal operation, so it can operate at the aforementioned higher specific voltage. These are all well known to those with ordinary knowledge in the art, and will not be repeated here.

It should be noted that, the number of sub-gates 27' is not limited to one as shown in the figure, but may also be plural. It should be noted that, as shown in FIGS. 2A and 2B , the sub-gate 27 ′ and the gate 27 are not directly connected, but are electrically connected through the conductive connection structure 25 . In another embodiment, the sub-gate 27 ′ and the gate 27 are electrically connected. The gate 27 can be directly connected. Here, the term "direct connection" means that the gate conductor layer 271 is in direct contact with the sub-gate conductor layer 271'.

It is worth noting that one of the technical features of the present invention over the prior art is that according to the present invention, taking the embodiment shown in FIGS. 2A and 2B as an example, when at least one sub-gate 27 ′ is formed in the drift oxide region 24, and arranged in parallel with the gate 27, when the high-voltage element 200 is not conducting, the edge of each sub-gate 27' along the width direction will have a relatively high electric field, so that the electric field is obtained after integrating along the channel. The voltage is higher, so the voltage when it is not conducting is higher, and the collapse protection voltage when it is not conducting is higher. The previous technology is high. In this embodiment, the gate electrode 27 has the first conductivity type, and the sub-gate electrode 27' has the second conductivity type. In this way, although the sub-gate 27 ′ is turned on when the high-voltage element 200 is turned on, that is, when the voltage of the gate 27 is higher than its threshold voltage, the sub-gate 27 ′ will not be turned on or partially turned on, so the sub-gate 27 ′ will be turned on. The on-charge accumulation capability of the drift region 22a directly below it is relatively low, thus causing the on-resistance of the high-voltage device 200 to decrease; however, it also reduces the gate-drain capacitance, so that the high-voltage device 200 operates when the high-voltage device 200 is turned on. The transient response performance is improved, the operation speed of the high-voltage device 200 is increased, and the application range of the high-voltage device 200 is increased, and this is without affecting the thickness of the drift oxide region and the breakdown protection voltage.

In a preferred embodiment, as shown in Figs. 2A and 2B, the sub-gate 27' and the gate 27 are connected by the conductive connection structure 25 and are not connected to each other. In a preferred embodiment, as shown in FIGS. 2A and 2B, the sub-gate 27' includes a conductive layer 271' and a spacer layer 272'. In a preferred embodiment, as shown in FIGS. 2A and 2B, the drift oxide region 24 is a completely connected structure and is not divided into different blocks.

Please refer to FIGS. 3A and 3B, which show a second embodiment of the present invention. 3A and 3B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 300 . As shown in FIGS. 3A and 3B , the high-voltage device 300 includes a semiconductor layer 31 ′, a well region 32 , an insulating structure 33 , a drift oxide region 34 , a body region 36 , a gate electrode 37 , two sub-gate electrodes 37 ′, and a source electrode 38 and drain 39. The semiconductor layer 31' is formed on the substrate 31, and the semiconductor layer 31' has opposite upper surfaces 31a and lower surfaces 31b in the vertical direction (as indicated by the dashed arrow direction in Fig. 3A, the same below). The substrate 31 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 31' is formed on the substrate 31 by, for example, an epitaxial step, or a part of the substrate 31 is used as the semiconductor layer 31'. The manner of forming the semiconductor layer 31' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 3A and 3B, wherein the insulating structure 33 is formed on and connected to the upper surface 31a to define the operation area 33a (as indicated by the dotted box in FIG. 3B). insulating structure 33 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and can also be a shallow trench isolation (STI) structure. The drift oxide region 34 is formed on the upper surface 31a and connected to the upper surface 31a, and is located on and connected to the drift region 32a in the operation region 33a (as indicated by the dotted box in FIG. 3A).

The well region 32 has the first conductivity type and is formed in the operation region 33a of the semiconductor layer 31', and in the vertical direction, the well region 32 is located under and connected to the upper surface 31a. The body region 36 has the second conductivity type, is formed in the well region 32 of the operation region 33a, and in the vertical direction, the body region 36 is located under and connected to the upper surface 31a. The gate electrode 37 is formed in the operation region 33a on the upper surface 31a of the semiconductor layer 31'. From the top view of Fig. 3B, the gate electrode 37 is substantially along the width direction (such as the direction of the solid arrow in Fig. 3B). As shown, the same below) is a rectangle extending upward, and in the vertical direction, a part of the body region 36 is located directly below the gate electrode 37 and is connected to the gate electrode 37 to provide an inversion current path of the high voltage device 300 during the turn-on operation. The conductive layer of the gate electrode 37 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Continuing to refer to FIGS. 3A and 3B , two sub-gates 37 ′ are formed just above part of the drift region 32 a and in the operating region 33 a on the drift oxide region 34 . From the top view of FIG. 3B , each sub-gate 37 ′ is substantially a rectangle extending along the width direction and is arranged in parallel with the gate 37 . And the sub-gate 37' spans the entire operating region 33a in the width direction. And in the vertical direction, the sub-gate 37' is located on the drift oxide region 34 and connected to the drift oxide region 34 . In this embodiment, the high-voltage element 300 includes, for example, two sub-gates 37'. According to the high-voltage device of the present invention, the high-voltage device 300 may also include a plurality of sub-gates 37' in one or other numbers. The conductive layer of the sub-gate 37' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. In this embodiment, the sub-gate 37' and the gate 37 are not directly connected, and the two sub-gates 37' are electrically floating, for example. in other embodiments Among them, at least one sub-gate 37' may also be electrically connected to the gate 37 or the source 38. The sub-gate 37' may also be electrically connected to the body region 36.

The source electrode 38 and the drain electrode 39 have the first conductivity type. In the vertical direction, the source electrode 38 and the drain electrode 39 are formed under the upper surface 31a and connected to the operation region 33a of the upper surface 31a, and the source electrode 38 and the drain electrode 39 are respectively located in the body region 36 below the outer portion of the gate 37 in the channel direction (as indicated by the dashed arrow direction in FIG. 3B, the same below) and in the well region 32 on the side away from the body region 36, and in the channel direction On the top, the drift region 32a is located between the drain electrode 39 and the body region 36, separates the drain electrode 39 and the body region 36, and is located in the well region 32 close to the upper surface 31a, and is used as the drift of the high voltage device 300 during the turn-on operation The current channel, and from the top view of FIG. 3B, in the channel direction, the sub-gate 37' is between the gate 37 and the drain 39, and in the vertical direction, the source 38 and the drain 39 are located on top The surface 31a is below and connected to the upper surface 31a. In this embodiment, the two sub-gates 37' are electrically floating, for example.

In this embodiment, the conductive layer of the gate electrode 37 has the first conductivity type, and the conductive layers of the two sub-gate electrodes 37' both have the second conductivity type. In another embodiment, the conductive layer 37' of at least one sub-gate may also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the first embodiment, in addition to the above, is that in the first embodiment, the drift oxide region 24 is a LOCOS structure, while in this embodiment, the drift oxide region 34 is a chemical Vapor deposition (chemical vapor deposition, CVD) oxidation zone. The CVD oxidation region is formed by the deposition step of the CVD process, which is well known to those skilled in the art and will not be described in detail here.

Please refer to FIGS. 4A and 4B, which show a third embodiment of the present invention. 4A and 4B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 400 . As shown in FIGS. 4A and 4B , the high-voltage device 400 includes: a semiconductor layer 41 ′, a well region 42 , an insulating structure 43 , a drift oxide region 44 , a conductive connection structure 45 , a body region 46 , a body electrode 46 ′, a gate electrode 47 , At least one sub-gate 47 ′, source 48 , metal silicide layer 48 ′ and drain 49 . The semiconductor layer 41' is formed on the substrate 41, and the semiconductor layer 41' is in the vertical direction (such as the The dashed arrows in Fig. 4A indicate the direction of the arrows, the same below), there are opposite upper surfaces 41a and lower surfaces 41b. The substrate 41 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 41' is formed on the substrate 41 by, for example, an epitaxial step, or a part of the substrate 41 is used as the semiconductor layer 41'. The method of forming the semiconductor layer 41' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 4A and 4B, wherein the insulating structure 43 is formed on the upper surface 41a and connected to the upper surface 41a to define the operation area 43a (as indicated by the dotted box in FIG. 4B). The insulating structure 43 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 44 is formed on the upper surface 41a and connected to the upper surface 41a, and is located on and connected to the drift region 42a in the operation region 43a (as indicated by the dotted box in FIG. 4A).

The well region 42 has the first conductivity type and is formed in the operation region 43a of the semiconductor layer 41', and in the vertical direction, the well region 42 is located under and connected to the upper surface 41a. The body region 46 has the second conductivity type and is formed in the well region 42 of the operation region 43a, and in the vertical direction, the body region 46 is located under and connected to the upper surface 41a. The gate electrode 47 is formed in the operation region 43a on the upper surface 41a of the semiconductor layer 41'. From the top view, the gate electrode 47 is approximately along the width direction (as indicated by the solid arrow direction in FIG. 4B, The same below) is a rectangle extending upward, and in the vertical direction, a part of the body region 46 is located directly below the gate electrode 47 and connected to the gate electrode 47 to provide an inversion current path of the high voltage device 400 during the conduction operation. The conductive layer of the gate electrode 47 is doped with impurities of the first conductivity type and is of the first conductivity type, such as but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Continuing to refer to FIGS. 4A and 4B , two sub-gates 47 ′ are formed directly above part of the drift region 42 a and in the operating region 43 a on the drift oxide region 44 . From the top view of FIG. 4B , the sub-gate electrodes 47 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 47 . And each sub-gate 47' spans the entire operating region 43a in the width direction. And in the vertical direction, the sub-gate 47' is located in the drift oxide region 44 and connected to the drift oxide region 44 . In this embodiment, the high-voltage element 400 includes, for example, two sub-gates 47'. The high voltage device according to the present invention may include one or other number of sub-gates 47'. In this embodiment, the sub-gate 47 ′ and the gate 47 are not directly connected, and the two sub-gates 47 ′ are electrically connected to the source 48 and the body region 46 , for example, through the conductive connection structure 45 and the metal silicide layer 48 ′. and body pole 46'. In other embodiments, at least one sub-gate 47' may also be electrically connected to the gate 47, or electrically floating. A metal silicide layer 48' is formed on the upper surface 41a connected to the body region 46 and the source electrode 48. For example, a metal such as cobalt or titanium is used in a self-aligned process to react with silicon atoms to form metal silicide The layer 48 ′ has a good conductive effect, which is well known to those with ordinary knowledge in the art, and will not be repeated here.

The source electrode 48 and the drain electrode 49 have the first conductivity type. In the vertical direction, the source electrode 48 and the drain electrode 49 are formed under the upper surface 41a and connected to the operation region 43a of the upper surface 41a, and the source electrode 48 and the drain electrode are connected to the operation region 43a of the upper surface 41a. 49 are respectively located in the body region 46 below the outer portion of the gate 47 in the channel direction (as indicated by the dashed arrow direction in FIG. 4B, the same below) and in the well region 42 on the side away from the body region 46, and in the channel direction On the top, the drift region 42a is located between the drain electrode 49 and the body region 46, separates the drain electrode 49 and the body region 46, and is located in the well region 42 close to the upper surface 41a, and is used as the drift of the high voltage device 400 during the turn-on operation The current channel, and from the top view of FIG. 4B, in the channel direction, the two sub-gate electrodes 47' are between the gate electrode 47 and the drain electrode 49, and in the vertical direction, the source electrode 48 and the drain electrode 49 Located below and connected to the upper surface 41a. The conductive connection structure 45 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here.

In this embodiment, the conductive layer of the gate electrode 47 has the first conductivity type, and the conductive layer of the sub-gate 47' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 47' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the first embodiment is that the two sub-gate electrodes 47' are electrically connected to the source electrode 48, the body region 46 and the body electrode 46', for example, through the conductive connection structure 45 and the metal silicide layer 48'. In addition, another point is that in the first embodiment, the drift oxide region 24 has a LOCOS structure, while in this embodiment, the drift oxide region 44 has a shallow trench isolation (STI) structure. The STI structure is well known to those skilled in the art and will not be described in detail here.

Please refer to FIGS. 5A and 5B, which show a fourth embodiment of the present invention. 5A and 5B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 500 . As shown in FIGS. 5A and 5B , the high-voltage device 500 includes: a semiconductor layer 51 ′, a well region 52 , an insulating structure 53 , a drift oxide region 54 , a body region 56 , a gate electrode 57 , a sub-gate electrode 57 ′, a source electrode 58 and Drain pole 59. The semiconductor layer 51' is formed on the substrate 51, and the semiconductor layer 51' has opposite upper surfaces 51a and lower surfaces 51b in the vertical direction (as indicated by the dashed arrow direction in Fig. 5A, the same below). The substrate 51 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 51' is formed on the substrate 51 by, for example, an epitaxial step, or a part of the substrate 51 is used as the semiconductor layer 51'. The method of forming the semiconductor layer 51' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 5A and 5B, wherein the insulating structure 53 is formed on the upper surface 51a and connected to the upper surface 51a to define the operation area 53a (as indicated by the dotted box in FIG. 5B). The insulating structure 53 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 54 is formed on the upper surface 51a and connected to the upper surface 51a, and is located on and connected to the drift region 52a in the operation region 53a (as indicated by the dotted box in FIG. 5A).

The well region 52 has the first conductivity type and is formed in the operation region 53a of the semiconductor layer 51', and in the vertical direction, the well region 52 is located under and connected to the upper surface 51a. The body region 56 has the second conductivity type, is formed in the well region 52 of the operation region 53a, and in the vertical direction, the body region 56 is located under and connected to the upper surface 51a. The gate electrode 57 is formed in the operation region 53a on the upper surface 51a of the semiconductor layer 51'. From the top view, the gate electrode 57 is generally along the width direction (such as the direction of the solid arrow in Fig. 5B). As shown, the same below) is a rectangle extending upward, and in the vertical direction, a portion of the body region 56 is located directly below the gate 57 and connected to the gate 57 to provide a reverse current path for the high-voltage device 500 during the conduction operation. The conductive layer of the gate 57 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure with impurities of the first conductivity type.

Continuing to refer to FIGS. 5A and 5B , the sub-gate 57 ′ is formed just above a portion of the drift region 52 a and in the operating region 53 a on the drift oxide region 54 . From the top view of FIG. 5B , the sub-gate electrodes 57 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 57 . And the sub-gate 27' spans the entire operating region 53a in the width direction. And in the vertical direction, the sub-gate 57' is located on the drift oxide region 54 and connected to the drift oxide region 54 . In this embodiment, as shown in the figure, the high-voltage element 500 includes, for example, a sub-gate 57', and the gate 57 is directly connected to each other. According to the high-voltage device of the present invention, the high-voltage device 500 may also include a plurality of sub-gates. The conductive layer of the sub-gate 57' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type.

The source electrode 58 and the drain electrode 59 have the first conductivity type. In the vertical direction, the source electrode 58 and the drain electrode 59 are formed under the upper surface 51a and connected to the operation region 53a of the upper surface 51a, and the source electrode 58 and the drain electrode 59 are respectively located in the body region 56 below the outer portion of the gate 57 in the channel direction (as indicated by the dashed arrow direction in FIG. 5B, the same below) and in the well region 52 on the side away from the body region 56, and in the channel direction On the top, the drift region 52a is located between the drain electrode 59 and the body region 56, and separates the drain electrode 59 and the body region 56, and is located in the well region 52 close to the upper surface 51a, and is used as the drift of the high voltage device 500 during the turn-on operation The current channel, and from the top view of FIG. 5B, in the channel direction, the sub-gate 57' is between the gate 57 and the drain 59, and in the vertical direction, the source 58 and the drain 59 are located on top The surface 51a is below and connected to the upper surface 51a.

In this embodiment, the conductive layer of the gate electrode 57 has the first conductivity type, and the conductive layer of the sub-gate 57' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 57' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the first embodiment is that, in the first embodiment, the gate 27 and the sub-gate 27' are separated and not directly connected to each other; in this embodiment, the sub-gate 27' is not directly connected to each other; The pole 57' is directly connected to the gate 57.

Please refer to FIGS. 6A and 6B, which show a fifth embodiment of the present invention. 6A and 6B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 600 . As shown in FIGS. 6A and 6B , the high voltage device 600 includes: a semiconductor layer 61 ′, a well region 62 , an insulating structure 63 , a drift oxide region 64 , a conductive connection structure 65 , a body region 66 , a gate 67 , and a sub-gate 67 ′ , source 68 and drain 69 . The semiconductor layer 61' is formed on the substrate 61, and the semiconductor layer 61' has opposite upper surfaces 61a and lower surfaces 61b in the vertical direction (as indicated by the dashed arrow direction in Fig. 6A, the same below). The substrate 61 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 61' is formed on the substrate 61 by, for example, an epitaxial step, or a part of the substrate 61 is used as the semiconductor layer 61'. The method of forming the semiconductor layer 61' is well known to those skilled in the art, and will not be described here.

Please continue to refer to FIGS. 6A and 6B, wherein the insulating structure 63 is formed on the upper surface 61a and connected to the upper surface 61a to define the operation area 63a (as indicated by the dotted box in FIG. 6B). The insulating structure 63 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 64 is formed on the upper surface 61a and connected to the upper surface 61a, and is located on and connected to the drift region 62a in the operation region 63a (as indicated by the dotted box in FIG. 6A).

The well region 62 has the first conductivity type and is formed in the operation region 63a of the semiconductor layer 61', and in the vertical direction, the well region 62 is located under and connected to the upper surface 61a. The body region 66 has the second conductivity type, is formed in the well region 62 of the operation region 63a, and in the vertical direction, the body region 66 is located under and connected to the upper surface 61a. The gate electrode 67 is formed in the operating region 63a on the upper surface 61a of the semiconductor layer 61'. From the top view, the gate electrode 67 is approximately along the width direction (as indicated by the solid arrow direction in FIG. 6B ). As shown, the same below) is a rectangle extending upward, and in the vertical direction, a part of the body region 66 is located directly below the gate 67 and connected to the gate 67 to provide a reverse current path for the high-voltage device 600 during the conduction operation. The conductive layer of the gate 67 is doped with impurities of the first conductivity type and is of the first conductivity type, such as but not limited to a polysilicon structure with impurities of the first conductivity type.

Continuing to refer to FIGS. 6A and 6B , the sub-gate 67 ′ is formed directly above a portion of the drift region 62 a and in the operating region 63 a on the drift oxide region 64 . From the top view of FIG. 6B , the sub-gate electrodes 67 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 67 . And the sub-gate 67' spans the entire operating region 63a in the width direction. And in the vertical direction, the sub-gate 67' is located on the drift oxide region 64 and connected to the drift oxide region 64 . In this embodiment, the high-voltage element 600 includes, for example, a sub-gate 67'. According to the high-voltage device of the present invention, the high-voltage device 600 may also include a plurality of sub-gates 67'. The conductive layer of the sub-gate 67' is a pure semiconductor structure. In this embodiment, the sub-gate 67' and the gate 67 are not directly connected, and are electrically connected to each other via the conductive connection structure 65. In other embodiments, the sub-gate 67' can also be electrically connected to the source 68. In a preferred embodiment, on the upper surface 61a connected to the body region 66 and the source electrode 68, there is a metal silicide layer (not shown, described in detail later) for electrically connecting the body region 66 and the source electrode 68. source 68 ; thus, sub-gate 67 ′ is also electrically connected to body region 66 in such an embodiment. In another preferred embodiment, the sub-gate 67' can also be electrically floating.

The source electrode 68 and the drain electrode 69 have the first conductivity type. In the vertical direction, the source electrode 68 and the drain electrode 69 are formed under the upper surface 61a and connected to the operation region 63a of the upper surface 61a, and the source electrode 68 and the drain electrode 69 are respectively located in the body region 66 below the outside of the gate 67 in the channel direction (as indicated by the dashed arrow direction in FIG. 6B, the same below) and in the well region 62 on the side away from the body region 66, and in the channel direction On the top, the drift region 62a is located between the drain electrode 69 and the body region 66, and separates the drain electrode 69 and the body region 66, and is located in the well region 62 close to the upper surface 61a, and is used for the drift of the high voltage device 600 during the turn-on operation The current channel, and from the top view of FIG. 6B, in the channel direction, the sub-gate 67' is between the gate 67 and the drain 69, and in the vertical direction, The source electrode 68 and the drain electrode 69 are located under and connected to the upper surface 61a. The conductive connection structure 65 is above the gate electrode 67 and the sub-gate electrode 67', and electrically connects the gate electrode 67 and the sub-gate electrode 67', and the conductive connection structure 65 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here.

In this embodiment, the conductive layer of the gate electrode 67 has the first conductivity type, and the conductive layer of the sub-gate electrode 67' is a pure semiconductor structure.

The difference between this embodiment and the first embodiment is that in the first embodiment, the conductive layer of the gate electrode 27 has the first conductivity type, and the conductive layer of the sub-gate 27' has the second conductivity type. In this embodiment, the conductive layer of the gate 67 has the first conductivity type, and the conductive layer of the sub-gate 67' is a pure semiconductor structure, such as but not limited to a pure polysilicon structure.

Please refer to FIGS. 7A and 7B, which show a sixth embodiment of the present invention. 7A and 7B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 700 . As shown in FIGS. 7A and 7B , the high voltage device 700 includes: a semiconductor layer 71 ′, a buried layer 71 ″, a drift well region 72 , an insulating structure 73 , a drift oxide region 74 , a conductive connection structure 75 , a channel well region 76 , a gate A pole 77 , a sub-gate 77 ′, a source 78 and a drain 79 . The semiconductor layer 71' is formed on the substrate 71, and the semiconductor layer 71' has opposite upper surfaces 71a and lower surfaces 71b in the vertical direction (as indicated by the dashed arrow direction in FIG. 7A, the same below). The substrate 71 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 71' is formed on the substrate 71 by, for example, an epitaxial step, or a part of the substrate 71 is used as the semiconductor layer 71'. The method of forming the semiconductor layer 71' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 7A and 7B, wherein the insulating structure 73 is formed on the upper surface 71a and connected to the upper surface 71a to define the operation area 73a (as indicated by the dotted box in FIG. 7B). The insulating structure 73 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and can also be a shallow trench isolation (STI) structure. A drift oxide region 74 is formed on the upper surface 71a on and connected to the upper surface 71a, and located on and connected to the drift region 72a in the operation region 73a (as indicated by the dashed box in FIG. 7A). In this embodiment, the operating area 73a defined by the insulating structure 73 has only one high-voltage element 700, but the invention is not limited to this. The operating area 73a defined by the insulating structure 73 may also include a plurality of high-voltage components, such as mirror images The arrangement of the two high-voltage components, etc., is well known to those with ordinary knowledge in the art, and will not be repeated here.

The drift well region 72 has the first conductivity type and is formed in the operation region 73a of the semiconductor layer 71', and in the vertical direction, the drift well region 72 is located under the upper surface 71a and connected to the upper surface 71a. The channel well region 76 has the second conductivity type, is formed in the operation region 73a below the upper surface 71a, and in the vertical direction, the channel well region 76 is located below the upper surface 71a and connected to the upper surface 71a. The channel well region 76 is adjacent to the drift well region 72 in the channel direction (as indicated by the direction of the solid arrow in FIG. 7A , the same below). The gate electrode 77 is formed in the operating region 73a on the upper surface 71a of the semiconductor layer 71'. From the top view, the gate electrode 77 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 7B, The same below) is a rectangle extending upward, and in the vertical direction, a part of the channel well region 76 is located directly below the gate electrode 77 and connected to the gate electrode 77 to provide an inversion current channel of the high voltage device 700 during the conduction operation. The conductive layer of the gate electrode 77 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Continuing to refer to FIGS. 7A and 7B , a sub-gate 77 ′ is formed just above a portion of the drift region 72 a and in the operating region 73 a above the drift oxide region 74 . From the top view of FIG. 7B , the sub-gate electrodes 77 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 77 . And the sub-gate 77' spans the entire operating region 73a in the width direction. And in the vertical direction, the sub-gate 77' is located on the drift oxide region 74 and connected to the drift oxide region 74 . In this embodiment, the high-voltage element 700 includes, for example, a sub-gate 77'. According to the high-voltage device of the present invention, the high-voltage device 700 may also include a plurality of sub-gates 77'. The conductive layer 771' of the sub-gate 77' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. In this embodiment, the sub-gate 77' is not directly connected to the gate 77, and are electrically connected to each other via the conductive connection structure 75 . In other embodiments, the sub-gate 77' may also be electrically connected to the source 78. In a preferred embodiment, on the upper surface 71a connected to the body region 76 and the source electrode 78, there is a metal silicide layer (not shown, such as the metal silicide layer 48' shown in FIG. 4A), It is used to electrically connect the body region 76 and the source electrode 78 ; therefore, in this embodiment, the sub-gate 77 ′ is also electrically connected to the body region 76 . In another preferred embodiment, the sub-gate 77' can also be electrically floating.

The source electrode 78 and the drain electrode 79 have the first conductivity type. In the vertical direction, the source electrode 78 and the drain electrode 79 are formed under the upper surface 71a and connected to the operation region 73a of the upper surface 71a, and the source electrode 78 and the drain electrode 79 are respectively located in the channel well region 76 below the gate 77 in the channel direction and in the drift well region 72 on the side away from the channel well region 76, and in the channel direction, the drift region 72a is located in the drain electrode 79 and the channel well region 76 between, and separates the drain electrode 79 and the body region 76, and is located in the drift well region 72 close to the upper surface 71a, which is used as a drift current path of the high-voltage device 700 during the turn-on operation. In the channel direction, the sub-gate 77' is between the gate 77 and the drain 79, and in the vertical direction, the source 78 and the drain 79 are located under the upper surface 71a and connected to the upper surface 71a. The conductive connection structure 75 is above the gate electrode 77 and the sub-gate electrode 77', and electrically connects the gate electrode 77 and the sub-gate electrode 77', and the conductive connection structure 75 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here. The buried layer 71 ″ has the first conductivity type and is formed below and connected to the channel well region 76 in the vertical direction. In the vertical direction, the buried layer 71 ″ is formed on both sides of the junction between the substrate 71 and the semiconductor layer 71 ′, for example, part of the buried layer 71 ″ is located in the substrate 71 , and part of the buried layer 71 ″ is located in the semiconductor layer 71 ′ to electrically The channel well region 76 is isolated from the substrate 71 .

In this embodiment, the conductive layer of the gate electrode 77 has the first conductivity type, and the conductive layer of the sub-gate 77' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 77' can also be a pure semiconductor structure, such as a pure polysilicon structure.

In a preferred embodiment, as shown in Figs. 7A and 7B, the sub-gate 77' and the gate 77 are connected by the conductive connection structure 75 and are not connected to each other. In a preferred embodiment, as shown in FIGS. 7A and 7B, the sub-gate 77' includes a conductive layer 771' and a spacer layer 772'. In a preferred embodiment, as shown in FIGS. 7A and 7B, the drift oxide region 74 is a completely connected structure and is not divided into different blocks.

Please refer to FIGS. 8A and 8B, which show a seventh embodiment of the present invention. 8A and 8B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 800 . As shown in FIGS. 8A and 8B , the high-voltage device 800 includes: a semiconductor layer 81 ′, a buried layer 81 ″, a drift well region 82 , an insulating structure 83 , a drift oxide region 84 , a conductive connection structure 85 , a channel well region 86 , a gate electrode 87. Two sub-gates 87', source 88 and drain 89. The semiconductor layer 81' is formed on the substrate 81, and the semiconductor layer 81' is in the vertical direction (as indicated by the dashed arrow direction in Figure 8A, the lower On the same), there are opposite upper surface 81a and lower surface 81b. The substrate 81 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 81 ′ is formed on the substrate 81 by, for example, an epitaxial step, Alternatively, a portion of the substrate 81 may be used as the semiconductor layer 81'. The method of forming the semiconductor layer 81' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 8A and 8B, wherein the insulating structure 83 is formed on the upper surface 81a and connected to the upper surface 81a to define the operation area 83a (as indicated by the dotted box in FIG. 8B). The insulating structure 83 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. A drift oxide region 84 is formed on and connected to the upper surface 81a, and is located on and connected to the drift region 82a in the operating region 83a (as indicated by the dashed box in FIG. 8A).

The drift well region 82 has the first conductivity type and is formed in the operation region 83a of the semiconductor layer 81', and in the vertical direction, the drift well region 82 is located under the upper surface 81a and connected to the upper surface 81a. The channel well region 86 has the second conductivity type and is formed in the operation region 83a below the upper surface 81a, and in the vertical direction, the channel well region 86 is located below the upper surface 81a and connected to the upper surface 81a. The channel well 86 and the drift well 82 are in the channel The direction (as indicated by the direction of the solid line arrow in Figure 8A, the same below) is adjacent to each other. The gate electrode 87 is formed in the operating region 83a on the upper surface 81a of the semiconductor layer 81'. From the top view, the gate electrode 87 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 8B, The same below) is a rectangle extending upward, and in the vertical direction, part of the channel well region 86 is located directly below the gate electrode 87 and connected to the gate electrode 87 to provide a reverse current channel of the high voltage element 800 during the conduction operation. The conductive layer of the gate 87 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure with impurities of the first conductivity type.

Continuing to refer to FIGS. 8A and 8B , a sub-gate 87 ′ is formed just above a portion of the drift region 82 a and in the operating region 83 a above the drift oxide region 84 . From the top view of FIG. 8B, the sub-gate 87' is substantially a rectangle extending along the width direction and is arranged in parallel with the gate 87. As shown in FIG. And the sub-gate 77' spans the entire operating region 73a in the width direction. And in the vertical direction, the sub-gate 87' is located on the drift oxide region 84 and connected to the drift oxide region 84 . In this embodiment, the high-voltage element 800 includes, for example, two sub-gates 87'. According to the high-voltage device of the present invention, the high-voltage device 800 may also include a plurality of sub-gates in one or other numbers. The conductive layer of the sub-gate 87' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. In this embodiment, the sub-gate 87' and the gate 87 are not directly connected, and are electrically connected to each other via the conductive connection structure 85. In other embodiments, the sub-gate 87' may also be electrically connected to the source 88. In a preferred embodiment, on the upper surface 81a connected to the body region 86 and the source electrode 88, there is a metal silicide layer (not shown, such as the metal silicide layer 48' shown in FIG. 4A), It is used to electrically connect the body region 86 and the source electrode 88 ; therefore, in this embodiment, the sub-gate 87 ′ is also electrically connected to the body region 86 . In another preferred embodiment, the sub-gate 87' can also be electrically floating.

The source electrode 88 and the drain electrode 89 have the first conductivity type. In the vertical direction, the source electrode 88 and the drain electrode 89 are formed under the upper surface 81a and connected to the operation region 83a of the upper surface 81a, and the source electrode 88 and the drain electrode 89 are respectively located in the channel well region 86 below the gate 87 in the channel direction and in the drift well region 82 on the side away from the channel well region 86, and in the channel direction, the drift region 82a is located in the drain electrode 89 and the channel well region 86 between, and divide The drain electrode 89 is separated from the body region 86, and is located in the drift well region 82 near the upper surface 81a, and is used as a drift current channel of the high voltage device 800 during the turn-on operation, and is viewed from the top view of FIG. 8B, in the channel direction On the top, the sub-gate 87 ′ is interposed between the gate 87 and the drain 89 , and in the vertical direction, the source 88 and the drain 89 are located under the upper surface 81 a and connected to the upper surface 81 a. The conductive connection structure 85 is above the gate electrode 87 and the sub-gate electrode 87', and electrically connects the gate electrode 87 and the sub-gate electrode 87', and the conductive connection structure 85 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here. The buried layer 81 ″ has the first conductivity type and is formed below and connected to the channel well region 86 in the vertical direction, and the buried layer 81 ″ is in the operation region 83 a and completely covers the channel well region 86 . In the vertical direction, the buried layer 81 ″ is formed on both sides of the junction between the substrate 81 and the semiconductor layer 81 ′, for example, part of the buried layer 81 ″ is located in the substrate 81 , and part of the buried layer 81 ″ is located in the semiconductor layer 81 ′ to electrically The channel well region 86 is isolated from the substrate 81 .

In this embodiment, the conductive layer of the gate electrode 87 has the first conductivity type, and the conductive layer of the sub-gate 87' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 87' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the drift oxide region 74 is a LOCOS structure, while in this embodiment, the drift oxide region 84 is a chemical vapor deposition (CVD) ( chemical vapor deposition, CVD) oxidation zone. The CVD oxidation region is formed by the deposition steps of the CVD process, which is well known to those skilled in the art, and will not be described in detail here. The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the number of sub-gates 77 ′ is one, while in this embodiment, the number of sub-gates 87 ′ for 2. The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, a part of the gate electrode 77 covers right above the drift oxide region 74 , while in this embodiment, the gate electrode 87 It does not cover directly above the drift oxide region 84 , and the sub-gate 87 ′ is completely located directly above the drift oxide region 84 .

Please refer to FIGS. 9A and 9B, which show an eighth embodiment of the present invention. 9A and 9B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 900 . As shown in FIGS. 9A and 9B , the high voltage device 900 includes: a semiconductor layer 91 ′, a buried layer 91 ″, a drift well region 92 , an insulating structure 93 , a drift oxide region 94 , a conductive connection structure 95 , a channel well region 96 , a gate electrode 97. Two sub-gates 97', source 98 and drain 99. The semiconductor layer 91' is formed on the substrate 91, and the semiconductor layer 91' is in the vertical direction (as indicated by the dashed arrow direction in Figure 9A, the same below). ), has opposite upper surface 91a and lower surface 91b. The substrate 91 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 91' is formed on the substrate 91 by, for example, an epitaxial step, or The part of the substrate 91 is used as the semiconductor layer 91'. The method of forming the semiconductor layer 91' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 9A and 9B, wherein the insulating structure 93 is formed on and connected to the upper surface 91a to define the operation area 93a (as indicated by the dotted box in FIG. 9B). The insulating structure 93 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. A drift oxide region 94 is formed on and connected to the upper surface 91a, and is located on and connected to the drift region 92a in the operation region 93a (as indicated by the dashed box in FIG. 9A).

The drift well region 92 has the first conductivity type and is formed in the operation region 93a of the semiconductor layer 91', and in the vertical direction, the drift well region 92 is located under the upper surface 91a and connected to the upper surface 91a. The channel well region 96 has the second conductivity type, is formed in the operation region 93a under the upper surface 91a, and in the vertical direction, the channel well region 96 is located under the upper surface 91a and connected to the upper surface 91a. The channel well area 96 is adjacent to the drift well area 92 in the channel direction (as indicated by the solid arrow direction in FIG. 9A , the same below). The gate electrode 97 is formed in the operating region 93a on the upper surface 91a of the semiconductor layer 91'. From the top view, the gate electrode 97 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 9B, The same below) is a rectangle extending upward, and in the vertical direction, part of the channel well region 96 is located directly below the gate electrode 97 and is connected to the gate electrode 97, so as to provide the high-voltage element 900 during conduction Inverting current channel in operation. The conductive layer of the gate 97 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure doped with impurities of the first conductivity type.

Continuing to refer to FIGS. 9A and 9B , a sub-gate 97 ′ is formed just above a portion of the drift region 92 a and in the operating region 93 a above the drift oxide region 94 . From the top view of FIG. 9B, the sub-gate 97' is substantially a rectangle extending along the width direction and is arranged in parallel with the gate 97. As shown in FIG. And the sub-gate 97' spans the entire operating region 93a in the width direction. And in the vertical direction, the sub-gate 97' is located on the drift oxide region 94 and connected to the drift oxide region 94 . In this embodiment, the high-voltage element 900 includes, for example, two sub-gates 97'. According to the high-voltage device of the present invention, the high-voltage device 900 may also include one or other number of sub-gates. The conductive layer of the sub-gate 97' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. In this embodiment, one of the sub-gates 97 ′ is not directly connected to the gate 97 , and the sub-gate 97 ′ is electrically connected to the source 98 and the body region via, for example, the conductive connection structure 95 and the metal silicide layer 98 ′. 96 and the body electrode 96', and the other sub-gate 97' is electrically floating, for example. In other embodiments, at least one sub-gate 97' may also be electrically connected to the gate 97. A metal silicide layer 98' is formed on the upper surface 91a connected to the body region 96 and the source electrode 98. For example, a metal such as cobalt or titanium is used in a self-aligned process to react with silicon atoms to form metal silicide The layer 98 ′ has good electrical conductivity, which is well known to those with ordinary knowledge in the art, and will not be repeated here.

The source electrode 98 and the drain electrode 99 have the first conductivity type. In the vertical direction, the source electrode 98 and the drain electrode 99 are formed under the upper surface 91a and connected to the operation region 93a of the upper surface 91a, and the source electrode 98 and the drain electrode 99 are respectively located in the channel well region 96 below the gate 97 in the channel direction and in the drift well region 92 on the side away from the channel well region 96, and in the channel direction, the drift region 92a is located in the drain electrode 99 and the channel well region 96 between, and separates the drain 99 and the body region 96, and is located in the drift well region 92 close to the upper surface 91a, which is used as a drift current path of the high-voltage device 900 during the turn-on operation. , in the channel direction, the sub-gate 97' is located between the gate 97 and the drain 99, and in the vertical direction, the source 98 and the drain 99 are located on top The surface 91a is below and connected to the upper surface 91a. The conductive connection structure 95 is above the gate electrode 97 and the sub-gate electrode 97', and electrically connects the metal silicide layer 98' and the sub-gate electrode 97', and the conductive connection structure 95 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here. The buried layer 91 ″ has the first conductivity type and is formed below and connected to the channel well region 96 in the vertical direction. In the vertical direction, the buried layer 91 ″ is formed on both sides of the junction between the substrate 91 and the semiconductor layer 91 ′, for example, part of the buried layer 91 ″ is located in the substrate 91 , and part of the buried layer 91 ″ is located in the semiconductor layer 91 ′ to electrically The channel well region 96 is isolated from the substrate 91 .

In this embodiment, the conductive layer of the gate electrode 97 has the first conductivity type, and the conductive layer of the sub-gate 97' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 97' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the drift oxide region 74 is a LOCOS structure, while in this embodiment, the drift oxide region 94 is a shallow trench insulation ( Shallow trench isolation, STI) structure. The STI structure is well known to those skilled in the art and will not be described in detail here. The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the number of sub-gates 77 ′ is one, while in this embodiment, the number of sub-gates 97 ′ for 2. The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the sub-gate 77 ′ and the gate 77 are electrically connected, and in this embodiment, one of the sub-gates The electrode 97' is electrically connected to the source electrode 98, the body electrode 96' and the body region 96, and the other sub-gate electrode 97' is electrically connected to floating.

Please refer to FIGS. 10A and 10B, which show a ninth embodiment of the present invention. FIGS. 10A and 10B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 1000 . As shown in FIGS. 10A and 10B , the high voltage device 1000 includes: a semiconductor layer 101 ′, a buried layer 101 ″, a drift well region 102 , an insulating structure 103 , a drift oxide region 104 , a conductive connection structure 105 , a channel well region 106 , a gate electrode 107. Sub-gate 107', The source electrode 108 and the drain electrode 109 . The semiconductor layer 101' is formed on the substrate 101, and the semiconductor layer 101' has opposite upper and lower surfaces 101a and 101b in the vertical direction (as indicated by the dashed arrows in Fig. 10A, the same below). The substrate 101 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 101' is formed on the substrate 101 by, for example, an epitaxial step, or a part of the substrate 101 is used as the semiconductor layer 101'. The method of forming the semiconductor layer 101' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIGS. 10A and 10B, wherein the insulating structure 103 is formed on the upper surface 101a and connected to the upper surface 101a to define the operation area 103a (as indicated by the dotted box in FIG. 10B). The insulating structure 103 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and can also be a shallow trench isolation (STI) structure. The drift oxide region 104 is formed on the upper surface 101a and connected to the upper surface 101a, and is located on the drift region 102a in the operation region 103a (as indicated by the dotted box in FIG. 10A) and connected to the drift region 102a.

The drift well region 102 has the first conductivity type and is formed in the operation region 103a of the semiconductor layer 101', and in the vertical direction, the drift well region 102 is located under the upper surface 101a and connected to the upper surface 101a. The channel well region 106 has the second conductivity type and is formed in the operation region 103a under the upper surface 101a, and in the vertical direction, the channel well region 106 is located under the upper surface 101a and connected to the upper surface 101a. The channel well area 106 is adjacent to the drift well area 102 in the channel direction (as indicated by the direction of the solid arrow in FIG. 10A , the same below). The gate electrode 107 is formed in the operating region 103a on the upper surface 101a of the semiconductor layer 101'. From the top view, the gate electrode 107 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 10B, The same below) is a rectangle extending upward, and in the vertical direction, part of the channel well region 106 is located directly below the gate 107 and connected to the gate 107 to provide an inversion current channel of the high-voltage device 1000 during the conduction operation. The conductive layer of the gate 107 is doped with impurities of the first conductivity type and is of the first conductivity type, such as but not limited to a polysilicon structure with impurities of the first conductivity type.

Please continue to refer to FIGS. 10A and 10B , the sub-gate 107 ′ is formed directly above part of the drift region 102 a and in the operating region 103 a on the drift oxide region 104 . From the top view of FIG. 10B , the sub-gate 107 ′ is substantially a rectangle extending along the width direction and is arranged in parallel with the gate 107 . And the sub-gate 107' spans the entire operating region 103a in the width direction. And in the vertical direction, the sub-gate 107' is located on the drift oxide region 104 and connected to the drift oxide region 104 . In this embodiment, the high-voltage element 1000 includes, for example, a sub-gate 107', and the sub-gate 107' and the gate 107 are directly connected to each other. The conductive layer of the sub-gate 107' is doped with impurities of the second conductivity type and is of the second conductivity type, such as, but not limited to, a polysilicon structure with impurities of the second conductivity type.

The source electrode 108 and the drain electrode 109 have the first conductivity type. In the vertical direction, the source electrode 108 and the drain electrode 109 are formed under the upper surface 101a and are connected to the operation region 103a of the upper surface 101a, and the source electrode 108 and the drain electrode 109 are respectively located in the channel well region 106 below the gate 107 in the channel direction and in the drift well region 102 on the side away from the channel well region 106, and in the channel direction, the drift region 102a is located in the drain electrode 109 and the channel well region 106 between, and separates the drain electrode 109 and the body region 106, and is located in the drift well region 102 close to the upper surface 101a, which is used as a drift current channel of the high-voltage device 1000 during the turn-on operation. In the channel direction, the sub-gate 107' is between the gate 107 and the drain 109, and in the vertical direction, the source 108 and the drain 109 are located under the upper surface 101a and connected to the upper surface 101a. The conductive connection structure 105 is above the gate electrode 107 and the sub-gate electrode 107', and electrically connects the gate electrode 107 and the sub-gate electrode 107', and the conductive connection structure 105 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here. The buried layer 101 ″ has the first conductivity type and is formed below and connected to the channel well region 106 in the vertical direction, and the buried layer 101 ″ is in the operation region 103 a and completely covers the channel well region 106 . In the vertical direction, the buried layer 101 ″ is formed on both sides of the junction between the substrate 101 and the semiconductor layer 101 ′, for example, part of the buried layer 101 ″ is located in the substrate 101 , and part of the buried layer 101 ″ is located in the semiconductor layer 101 ′ to electrically The channel well region 106 is isolated from the substrate 101 .

In this embodiment, the conductive layer of the gate electrode 107 has the first conductivity type, and the conductive layer of the sub-gate 107' has the second conductivity type. In another embodiment, the conductive layer of the sub-gate 107' can also be a pure semiconductor structure, such as a pure polysilicon structure.

The difference between this embodiment and the sixth embodiment is that in the sixth embodiment, the sub-gate 77 ′ and the gate 77 are not directly connected to each other; in this embodiment, the sub-gate 107 ' and the gate 107 are directly connected to each other.

Please refer to FIGS. 11A and 11B, which show a tenth embodiment of the present invention. 11A and 11B respectively show a schematic cross-sectional view and a schematic top view of the high-voltage device 1100 . As shown in FIGS. 11A and 11B , the high-voltage device 1100 includes: a semiconductor layer 111 ′, a buried layer 111 ″, a drift well region 112 , an insulating structure 113 , a drift oxide region 114 , a conductive connection structure 115 , a channel well region 116 , a gate electrode 117, sub-gate 117', source 118, and drain 119. The semiconductor layer 111' is formed on the substrate 111, and the semiconductor layer 111' is in the vertical direction (as indicated by the dashed arrow direction in Figure 11A, the same below) The upper surface 111a and the lower surface 111b are opposite to each other. The substrate 111 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 111' is formed on the substrate 111 by, for example, epitaxy, or The part of the substrate 111 is used as the semiconductor layer 111 ′. The method of forming the semiconductor layer 111 ′ is well known to those skilled in the art and will not be repeated here.

Please continue to refer to FIGS. 11A and 11B, wherein the insulating structure 113 is formed on the upper surface 111a and connected to the upper surface 111a to define the operation area 113a (as indicated by the dotted box in FIG. 11B). The insulating structure 113 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 114 is formed on the upper surface 111a and connected to the upper surface 111a, and is located on the drift region 112a in the operation region 113a (as indicated by the dotted box in FIG. 11A) and connected to the drift region 112a.

The drift well region 112 has the first conductivity type and is formed in the operation region 113a of the semiconductor layer 111', and in the vertical direction, the drift well region 112 is located under the upper surface 111a and connected to the upper surface 111a. The channel well region 116 has the second conductivity type and is formed in the operation region 113a under the upper surface 111a, and in the vertical direction, the channel well region 116 is located under the upper surface 111a and connected to the upper surface 111a. The channel well area 116 is adjacent to the drift well area 112 in the channel direction (as indicated by the solid arrow direction in FIG. 11A , the same below). The gate electrode 117 is formed in the operation region 113a on the upper surface 111a of the semiconductor layer 111'. From the top view, the gate electrode 117 is approximately along the width direction (as indicated by the direction of the solid arrow in FIG. 11B , The same below) is a rectangle extending upward, and in the vertical direction, part of the channel well region 116 is located directly below the gate electrode 117 and connected to the gate electrode 117 to provide an inversion current channel of the high voltage device 1100 during the conduction operation. The conductive layer of the gate electrode 117 is doped with impurities of the first conductivity type and is of the first conductivity type, such as but not limited to a polysilicon structure doped with impurities of the first conductivity type.

Continuing to refer to FIGS. 11A and 11B , the sub-gate 117 ′ is formed directly above part of the drift region 112 a and in the operating region 113 a on the drift oxide region 114 . From the top view of FIG. 11B , the sub-gate electrodes 117 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 117 . And the sub-gate 117' spans the entire operating region 113a in the width direction. And in the vertical direction, the sub-gate 117' is located on the drift oxide region 114 and connected to the drift oxide region 114 . In this embodiment, the high-voltage element 1100 includes, for example, a sub-gate 117'. According to the high-voltage device of the present invention, the high-voltage device 1100 may also include a plurality of sub-gates. The conductive layer of the sub-gate 27' is a pure semiconductor structure, such as a pure polysilicon structure. In this embodiment, the sub-gate 117 ″ and the gate 117 are not directly connected, and are electrically connected to each other via the conductive connection structure 115 . In other embodiments, the sub-gate 117 ′ can also be electrically connected to the source 118 . In another preferred embodiment, the sub-gate 117' can also be electrically floating.

The source electrode 118 and the drain electrode 119 have the first conductivity type. In the vertical direction, the source electrode 118 and the drain electrode 119 are formed under the upper surface 111a and are connected to the operation region 113a of the upper surface 111a, and the source electrode 118 is connected to the upper surface 111a. The drain 119 is located in the channel well 116 below the gate 117 in the channel direction and in the drift well 112 on the side away from the channel well 116, and in the channel direction, the drift region 112a is located between the drain 119 and the channel well Between the regions 116, and separates the drain 119 and the body region 116, and is located in the drift well region 112 close to the upper surface 111a, which is used as a drift current channel of the high voltage device 1100 during the turn-on operation, and is shown in Figure 11B from the top view It can be seen that in the channel direction, the sub-gate 117 ′ is between the gate 117 and the drain 119 , and in the vertical direction, the source 118 and the drain 119 are located under the upper surface 111 a and connected to the upper surface 111 a. The conductive connection structure 115 is above the gate electrode 117 and the sub-gate electrode 117', and electrically connects the gate electrode 117 and the sub-gate electrode 117', and the conductive connection structure 115 is a conductor. For example, but not limited to, metal lines and conductive plugs in the manufacturing process, which are well known to those skilled in the art, and will not be described in detail here. The buried layer 111 ″ has the first conductivity type and is formed below and connected to the channel well region 116 in the vertical direction. In the vertical direction, the buried layer 111" is formed on both sides of the junction between the substrate 111 and the semiconductor layer 111', for example, part of the buried layer 111" is located in the substrate 111, and part of the buried layer 111" is located in the semiconductor layer 111'.

The difference between this embodiment and the sixth embodiment is that, in the sixth embodiment, the conductive layer of the sub-gate 77 ′ is doped with impurities of the second conductivity type and is of the second conductivity type; In this embodiment, the conductive layer of the sub-gate 117 ′ is a pure semiconductor structure, such as, but not limited to, a pure polysilicon structure.

Please refer to Figures 12A-12G, which show an eleventh embodiment of the present invention. FIGS. 12A-12G are schematic cross-sectional views (FIGS. 12A, 12C, 12D, 12E, 12F, and 12G) or top-view schematic diagrams (FIG. 12B) of the manufacturing method of the high-voltage device 200 . As shown in Figs. 12A and 12B, a semiconductor layer 21' is firstly formed on the substrate 21. The semiconductor layer 21' is in the vertical direction (as indicated by the dashed arrow direction in Fig. 12A, the same below), with an opposite upper Surface 21a and lower surface 21b. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21 by, for example, an epitaxial step, or is based on A portion of the board 21 serves as the semiconductor layer 21'. The method of forming the semiconductor layer 21' is well known to those skilled in the art, and will not be described in detail here.

Please continue to refer to FIGS. 12A and 12B. Next, an insulating structure 23 and a drift oxide region 24 are formed on the upper surface 21a and connected to the upper surface 21a. The insulating structure 23 is used to define the operation area 23a (as indicated by the dotted box in FIG. 12B). The insulating structure 23 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure. The drift oxide region 24 is located on and connected to the drift region 22a in the operation region 23a. In this embodiment, the operating area 23a defined by the insulating structure 23 has only one high-voltage element 200, but the invention is not limited to this, and the operating area 23a defined by the insulating structure 23 may also include a plurality of high-voltage components, such as mirror images The arrangement of the two high-voltage components, etc., is well known to those with ordinary knowledge in the art, and will not be repeated here.

Next, referring to FIG. 12C, the well region 22 is formed in the operation region 23a of the semiconductor layer 21', and in the vertical direction, the well region 22 is located under the upper surface 21a and connected to the upper surface 21a. The well region 22 has a first conductivity type. For example, an ion implantation process step, such as but not limited to, can be used to implant impurities of the first conductivity type in the form of accelerated ions, as indicated by the dotted arrow in FIG. 12C, into the operation region. 23a to form the well region 22.

Next, referring to FIG. 12D, the body region 26 is formed in the well region 22 of the operation region 23a, and in the vertical direction, the body region 26 is located under the upper surface 21a and connected to the upper surface 21a. The body region 26 has the second conductivity type. The step of forming the body region 26 is, for example, but not limited to, using the photoresist layer 26 ′ formed by the lithography process as a mask, and doping impurities of the second conductivity type into the well region 22 , to form the body region 26 . In this embodiment, for example, but not limited to, an ion implantation process step can be used to implant impurities of the second conductivity type in the form of accelerated ions into the well region 22 to form the body region 26 .

Next, referring to FIG. 12E, a gate electrode 27 is formed in the operation region 23a on the upper surface 21a of the semiconductor layer 21'. As seen from the top view of FIG. 2B, the gate electrode 27 is approximately along the width direction (eg, FIG. 2B The direction of the solid line arrow in the figure is indicated by the direction of the arrow of the solid line, the same below) and the rectangle extending upward, and in the vertical direction (as indicated by the direction of the dotted line arrow in FIG. 12E, the same below), part of the body region 26 is located at the gate electrode 27 is directly below and connected to the gate electrode 27 to provide an inversion current path of the high-voltage element 200 during the conduction operation. The conductive layer 271' of the gate electrode 27 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure doped with impurities of the first conductivity type. The method of forming the conductive layer 271 ′ of the first conductivity type, for example, can use an ion implantation process step to implant impurities of the first conductivity type into the conductive layer 271 ′ of the gate electrode 27 in the form of accelerated ions to form the first conductivity type. A conductive layer of a conductivity type.

Please continue to refer to FIG. 12E, for example, in some of the same process steps of forming gate 27, including the process steps of depositing pure semiconductor (such as but not limited to polysilicon) and forming spacer layer, forming sub-gate 27' in drift oxidation In the operation area 23a above the area 24. As seen from the top view of FIG. 2B , the sub-gate electrodes 27 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 27 . And in the vertical direction, the sub-gate 27' is located on the drift oxide region 24 and connected to the drift oxide region 24 . In this embodiment, the high-voltage element 200 includes, for example, a sub-gate 27'. The high-voltage device according to the present invention may include one or other sub-gates 27'. The conductive layer of the sub-gate 27' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. The method for forming the conductive layer of the second conductivity type, for example, can utilize the ion implantation process step, implanting impurities of the second conductivity type in the form of accelerated ions into the conductive layer of the sub-gate 27 ′ to form the second conductivity type of conductive layer.

Next, referring to FIG. 12F, in the vertical direction, the source electrode 28 and the drain electrode 29 are formed under the upper surface 21a and connected to the operation region 23a of the upper surface 21a, and the source electrode 28 and the drain electrode 29 are respectively located at the gate electrode 27 in the channel direction (as indicated by the direction of the solid line arrow in FIG. 12F, the same below) in the body region 26 below the outside and in the well region 22 on the side away from the body region 26, and in the channel direction, the drift region 22a is at drain 29 Between the body region 26 and the well region 22 close to the upper surface 21a, it is used as a drift current channel of the high voltage element 200 during the conduction operation, and as seen from the top view 2B, in the channel direction, the sub-gate 27' is located between the gate electrode 27 and the drain electrode 29, and in the vertical direction (as indicated by the dashed arrow direction in FIG. 12F, the same below), the source electrode 28 and the drain electrode 29 are located under the upper surface 21a and parallel to each other. Connected to the upper surface 21a. The source electrode 28 and the drain electrode 29 have the first conductivity type, and the steps of forming the source electrode 28 and the drain electrode 29, such as but not limited to, use the photoresist layer 28' formed by the lithography process step as a mask to remove the impurities of the first conductivity type. The body region 26 and the well region 22 are respectively doped to form the source electrode 28 and the drain electrode 29 . In this embodiment, for example, but not limited to, ion implantation process steps can be used to implant impurities of the first conductivity type in the form of accelerated ions into the body region 26 and the well region 22 to form the source electrode 28 and the drain electrode 29.

Next, referring to FIG. 12G, a conductive connection structure 25 is formed to electrically connect the gate electrode 27 and the sub-gate electrode 27' above the gate electrode 27 and the sub-gate electrode 27', and the conductive connection structure 25 is a conductor. For example, but not limited to, the steps of forming metal lines and conductive plugs in the process steps of semiconductor devices are used to form the conductive connection structure 25, which is well known to those skilled in the art. I won't go into details.

In a preferred embodiment, as shown in FIG. 12G, the sub-gate 27' and the gate 27 are connected by the conductive connection structure 25, and are not directly connected to each other. In a preferred embodiment, as shown in FIG. 12G, the sub-gate 27' includes a conductive layer 271' and a spacer layer 272'. In a preferred embodiment, as shown in FIG. 12G, the drift oxide region 24 is a completely connected structure and is not divided into different blocks.

Please refer to Figures 13A-13F, which show a twelfth embodiment of the present invention. FIGS. 13A-13F show schematic cross-sectional views of a method of manufacturing a high voltage device 700 . As shown in FIG. 13A, first, a semiconductor layer 71' is formed on the substrate 71, and the semiconductor layer 71' has an opposite upper surface 71a in the vertical direction (as indicated by the dashed arrow direction in FIG. 13A, the same below). with the lower surface 71b. The substrate 71 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 71' is formed on the substrate 71 by, for example, an epitaxial step, or A portion of the substrate 71 is used as the semiconductor layer 71'. The method of forming the semiconductor layer 71' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIG. 13A. Next, an insulating structure 73 is formed on the upper surface 71a and connected to the upper surface 71a to define the operation area 73a. The insulating structure 73 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure, and can also be a shallow trench isolation (STI) structure. At the same time as the insulating structure 73 is formed, for example, a drift oxide region 74 is formed on the upper surface 71a and connected to the upper surface 71a by the same process steps, and is located in the drift region 72a in the operation region 73a (as indicated by the dotted box in FIG. 13B ) ) and connected to the drift region 72a. Next, in the vertical direction, a buried layer 71 ″ is formed under the channel well region 76 and connected to the channel well region 76 , and the buried layer 71 ″ is in the operation region 73 a and completely covers the channel well region 76 . In the vertical direction, the buried layer 71 ″ is formed on both sides of the junction between the substrate 71 and the semiconductor layer 71 ′, for example, part of the buried layer 71 ″ is located in the substrate 71 , and part of the buried layer 71 ″ is located in the semiconductor layer 71 ′. The buried layer 71 "Having the first conductivity type, for example, the first conductivity type impurities can be implanted in the substrate 71 in the form of accelerated ions by, for example, but not limited to, ion implantation process steps to form the buried layer 71".

Next, referring to FIG. 13B, a drift well region 72 is formed in the operation region 73a of the semiconductor layer 71', and in the vertical direction, the drift well region 72 is located under and connected to the upper surface 71a. The drift well region 72 has the first conductivity type. The steps of forming the drift well region 72 include, for example, but not limited to, using the photoresist layer 72 ′ as a mask to dope the first conductivity type impurities into the semiconductor layer 71 . ' to form the drift well region 72 . In this embodiment, for example, but not limited to, an ion implantation process step can be used to implant impurities of the second conductivity type in the form of accelerated ions into the semiconductor layer 71 ′ to form the drift well region 72 .

Next, referring to FIG. 13C, the channel well 76 is formed in the operation area 73a under the upper surface 71a, and in the vertical direction, the channel well 76 is located under the upper surface 71a and connected to the upper surface 71a. The channel well area 76 is adjacent to the drift well area 72 in the channel direction (as indicated by the solid arrow direction in FIG. 13C , the same below). The channel well region 76 has the second conductivity type, and the steps of forming the channel well region 76, such as but not limited to Using the photoresist layer 76' formed by the lithography process step as a mask, impurities of the second conductivity type are doped into the semiconductor layer 71' to form the channel well region 76. Wherein, in this embodiment, the second conductivity type impurities can be implanted in the semiconductor layer 71' in the form of accelerated ions by, for example, but not limited to, an ion implantation process step to form the channel well region 76.

Next, referring to FIG. 13D, the gate electrode 77 is formed in the operation region 73a on the upper surface 71a of the semiconductor layer 71'. From the top view, the gate electrode 77 is approximately along the width direction (as shown in FIG. 7B). The direction of the solid line arrow is indicated, the same below) a rectangle extending upward, and in the vertical direction, part of the channel well region 76 is located directly below the gate electrode 77 and is connected to the gate electrode 77, so as to provide the high-voltage element 700 in the conduction operation. The reverse current channel. The conductive layer of the gate electrode 77 is doped with impurities of the first conductivity type and is of the first conductivity type, such as, but not limited to, a polysilicon structure doped with impurities of the first conductivity type. The method of forming the conductive layer of the first conductivity type, for example, can use the ion implantation process step to implant the impurities of the first conductivity type into the conductive layer of the gate electrode 77 in the form of accelerated ions to form the first conductivity type. conductive layer.

Please continue to refer to FIG. 13D, for example, in some of the same process steps of forming the gate 77, including the process steps of depositing a pure semiconductor (such as but not limited to polysilicon) and forming a spacer layer, the formation of the sub-gate 77' is formed in the drift In the operation area 73a above the oxidation area 74. From the top view of FIG. 7B , the sub-gate electrodes 77 ′ are substantially rectangular extending along the width direction and are arranged in parallel with the gate electrodes 77 . And in the vertical direction, the sub-gate 77' is located on the drift oxide region 74 and connected to the drift oxide region 74 . In this embodiment, the high-voltage element 700 includes, for example, a sub-gate 77'. The high-voltage device according to the present invention may include one or other sub-gates 77'. The conductive layer 771' of the sub-gate 77' is doped with impurities of the second conductivity type and is of the second conductivity type, such as but not limited to a polysilicon structure with impurities of the second conductivity type. The method for forming the conductive layer 771' of the second conductivity type, for example, can use an ion implantation process step to implant impurities of the second conductivity type into the conductive layer 771' of the sub-gate 77' in the form of accelerated ions to A conductive layer 771' of the second conductivity type is formed.

Next, referring to FIG. 13E, in the vertical direction, the source electrode 78 and the drain electrode 79 are formed to have the first conductivity type, and the source electrode 78 and the drain electrode 79 are below the upper surface 71a and connected to the operation region 73a of the upper surface 71a. , and the source electrode 78 and the drain electrode 79 are respectively located in the channel well region 76 below the gate 77 in the channel direction and in the drift well region 72 on the side away from the channel well region 76, and in the channel direction, the drift region 72a is located in Between the drain electrode 79 and the channel well region 76, the drift well region 72 near the upper surface 71a is used as the drift current channel of the high voltage element 700 during the conduction operation, and as seen from the top view of FIG. 7B, in the channel direction On the top, the sub-gate 77 ′ is interposed between the gate 77 and the drain 79 , and in the vertical direction, the source 78 and the drain 79 are located under the upper surface 71 a and connected to the upper surface 71 a. The source electrode 78 and the drain electrode 79 have the first conductivity type, and the steps of forming the source electrode 78 and the drain electrode 79, such as but not limited to, use the photoresist layer 78' formed by the lithography process step as a mask to remove the impurities of the first conductivity type. Doping into the channel well region 76 and the drift well region 72 , respectively, forms a source electrode 78 and a drain electrode 79 . In this embodiment, for example, but not limited to, ion implantation process steps can be used to implant impurities of the first conductivity type in the form of accelerated ions into the channel well region 76 and the drift well region 72 to form the source electrode 78 and the drift well region 72 . Drain pole 79.

Next, referring to FIG. 13F, a conductive connection structure 75 is formed to electrically connect the gate electrode 77 and the sub-gate electrode 77' above the gate electrode 77 and the sub-gate electrode 77', and the conductive connection structure 75 is a conductor. For example, but not limited to, the steps of forming metal lines and conductive plugs in the process steps of semiconductor devices to form the conductive connection structure 75 are well known to those skilled in the art, and herein I won't go into details.

In a preferred embodiment, as shown in FIG. 13F, the sub-gate 77' and the gate 77 are connected by the conductive connection structure 75, and are not connected to each other. In a preferred embodiment, as shown in FIG. 13F, the sub-gate 77' includes a sub-gate conductive layer 771' and a sub-gate spacer layer 772'. In a preferred embodiment, as shown in FIG. 13F, the drift oxide region 74 is a completely connected structure and is not divided into different blocks.

FIG. 14A is an electrical schematic diagram of the gate voltage of the transient response during the turn-on operation of the present invention and the prior art. As shown in FIG. 14A, the high-voltage device of the present invention, compared with the prior art, It has shorter switching time and better transient response. As shown in Figure 14A, the horizontal axis is time, in seconds, and the vertical axis is gate voltage, in volts V. Taking the high-voltage device 200 of the first embodiment as an example, in the turning ON operation, compared with the prior art, the gate voltage according to the present invention rises faster, because the corresponding capacitance value is different from that of the prior art. The high voltage device of the prior art drops so that in turn-on operation, the gate voltage takes a relatively short time to reach the target voltage (eg, but not limited to, 3.3V), so the transient response of the high voltage device according to the present invention is improved.

FIG. 14B is an electrical schematic diagram of the drain voltage of the transient response during the turn-on operation of the present invention and the prior art. As shown in FIG. 14B , the high-voltage device of the present invention has a shorter switching time and better transient response than the prior art. As shown in Fig. 14B, the horizontal axis is time, and the unit is seconds; the vertical axis is the drain voltage, and the unit is volt V. Taking the high-voltage device 200 of the first embodiment as an example, in the turning ON operation, compared with the prior art, the drain voltage according to the present invention rises faster, because the corresponding capacitance value is different from that of the prior art. The high voltage device of the prior art drops so that in turn-on operation, the drain voltage takes a relatively short time to reach the target voltage (eg, but not limited to, 12V), so the transient response of the high voltage device according to the present invention is improved.

The present invention has been described above with respect to the preferred embodiments, but the above-mentioned descriptions are only intended to make it easy for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes will be devised by those skilled in the art. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the device; for another example, the lithography technology is not limited to the photomask technology, but also includes electron beam lithography technology. All of these can be derived by analogy according to the teachings of the present invention. In addition, each of the described embodiments is not limited to be applied individually, but can also be applied in combination, for example, but not limited to, the two embodiments are used together. Accordingly, the scope of the present invention should cover the above and all other equivalent changes. In addition, it is not necessary for any embodiment of the present invention to achieve all the purposes or advantages, and therefore the scope of the claimed patent should not be limited thereto.

200: High Voltage Components

21: Substrate

21': Semiconductor layer

21a: upper surface

21b: lower surface

22: Well area

23: Insulation structure

23a: Operation area

24: Drift oxide zone

25: Conductive connection structure

26: Ontology area

27: Gate

27': Sub-gate

271,271': Conductive layer

272,272': Spacer layer

273: Dielectric Layer

28: Source

29: Drain

Claims (8)

A high-voltage device, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; a drift oxide region formed on the upper surface and connected to the upper surface, and located at a A drift region in the operation region is on and connected to the drift region; a well region, having a first conductivity type, is formed in the operation region of the semiconductor layer, the well region is located under the upper surface and connected to the upper surface ; a body region having a second conductivity type formed in the well region of the operating region, the body region being located under and connected to the upper surface; a gate electrode formed on the upper surface of the semiconductor layer In the operating region on the surface, a part of the body region is located directly below the gate electrode and is connected to the gate electrode to provide an inversion current path for the high-voltage element in a conducting operation; at least one sub-gate is formed on the On the drift oxide region, and directly above at least part of the drift region, the sub-gate electrode is arranged in parallel with the gate electrode, and the sub-gate electrode is located on the drift oxide region and connected to the drift oxide region; and a source electrode and a drain electrode with the first conductivity type, the source electrode and the drain electrode are formed under the upper surface and connected in the operation region of the upper surface, and the source electrode and the drain electrode are respectively located between the gate electrodes In the body region below the exterior and in the well region on the side away from the body region, and in a channel direction, the drift region is located between the drain and the body region, in the well region near the upper surface, used as a drift current channel of the high-voltage element in the conduction operation, and viewed from the top view, the sub-gate is between the gate and the drain; Wherein, the conductive layer of the gate electrode has the first conductivity type, and the conductive layer of the sub-gate electrode has the second conductivity type or is a pure semiconductor structure; wherein the at least one sub-gate electrode and the gate electrode are different from each other Direct connection; wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of a first conductivity type, and the conductive layer of the at least one sub-gate includes a polysilicon structure doped with impurities of a second conductivity type, wherein the gate electrode The conductivity type is different from the conductivity type of the sub-gate; wherein the sub-gate is electrically floating, or is electrically connected to the source. The high voltage device as described in claim 1, wherein the drift oxide region comprises a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical vapor phase Deposition (chemical vapor deposition, CVD) oxide region. A high-voltage device manufacturing method, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; forming a drift oxide region on the upper surface and connected to the upper surface, and located in a A drift region in the operation region is on and connected to the drift region; a well region is formed in the operation region of the semiconductor layer, and the well region is located under the upper surface and connected to the upper surface, and the well region has a first a conductivity type; a body region is formed in the well region of the operation region, and the body region is located below the upper surface and connected to the upper surface, and the body region has a second conductivity type; A gate is formed in the operating region on the upper surface of the semiconductor layer, and a portion of the body region is located directly below the gate and connected to the gate to provide an inversion of the high-voltage element during a turn-on operation A current channel; at least one sub-gate is formed on the drift oxide region, and at least part of the drift region is directly above, the sub-gate is arranged in parallel with the gate, and the sub-gate is located on the drift oxide region and connected the drift oxide region; and a source electrode and a drain electrode are formed under the upper surface and connected in the operation region of the upper surface, the source electrode and the drain electrode have the first conductivity type and are respectively located in the gate In the body region below the outer portion of the pole and in the well region on the side away from the body region, and in a channel direction, the drift region is located between the drain electrode and the body region, in the well region near the upper surface, Used as a drift current channel of the high-voltage element in the conduction operation, and viewed from the top view, the sub-gate is between the gate and the drain; wherein, the conductive layer of the gate has the The first conductivity type, and the conductive layer of the sub-gate has the second conductivity type or is a pure semiconductor structure; wherein the at least one sub-gate and the gate are not directly connected to each other; wherein the conductive layer of the gate It includes a polysilicon structure doped with impurities of a first conductivity type, and the conductive layer of the at least one sub-gate includes a polysilicon structure doped with impurities of a second conductivity type, wherein the conductivity type of the gate electrode and the conductivity of the sub-gate electrode are different types; wherein the sub-gate is electrically floating, or is electrically connected to the source. The method for manufacturing a high-voltage device as described in claim 6, wherein the drift oxide region comprises a local oxidation of silicon (LOCOS) structure, a shallow trench insulation (shallow trench insulation) trench isolation, STI) structure or a chemical vapor deposition (chemical vapor deposition, CVD) oxide region. A high-voltage device, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; a drift oxide region formed on the upper surface and connected to the upper surface, and located at a One of the operating regions is on and connected to the drift region; a drift well region, having a first conductivity type, is formed in the operating region of the semiconductor layer under the upper surface, and the drift well region is located on the upper surface lower and connected to the upper surface; a channel well area with a second conductivity type formed in the operation area below the upper surface, the channel well area and the drift well area adjoining in a channel direction; a buried a layer with the first conductivity type, formed under the channel well region and connected to the channel well region, and the buried layer is in the operation region, completely covering the channel well region; a gate electrode is formed in the semiconductor layer In the operation region on the upper surface, a part of the channel well region is located directly below the gate electrode and is connected to the gate electrode for providing an inversion current channel of the high-voltage element in a conducting operation; at least one sub-channel a gate electrode, formed on the drift oxide region and directly above at least part of the drift region, the sub-gate electrode is arranged in parallel with the gate electrode, and the sub-gate electrode is located on the drift oxide region and connected to the drift oxide region ;as well as A source electrode and a drain electrode have the first conductivity type, and the source electrode and the drain electrode are formed under the upper surface and connected in the operation region of the upper surface, and the source electrode and the drain electrode are respectively In the channel well region below the outside of the gate and in the drift well region on the side away from the channel well region, and in the channel direction, the drift region is located between the drain electrode and the channel well region, close to The drift well region on the upper surface is used as a drift current channel of the high-voltage element during the conduction operation, and as seen from the top view, the sub-gate is between the gate and the drain; Wherein, the conductive layer of the gate electrode has the first conductivity type, and the conductive layer of the sub-gate electrode has the second conductivity type or is a pure semiconductor structure; wherein the at least one sub-gate electrode and the gate electrode are different from each other Direct connection; wherein the conductive layer of the gate includes a polysilicon structure doped with impurities of the first conductivity type, and the conductive layer of the at least one sub-gate includes a polysilicon structure doped with impurities of the second conductivity type, wherein the gate electrode The conductivity type is different from the conductivity type of the sub-gate; wherein the sub-gate is electrically floating, or is electrically connected to the source. The high voltage device as described in claim 11, wherein the drift oxide region comprises a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical vapor phase Deposition (chemical vapor deposition, CVD) oxide region. A high-voltage component manufacturing method, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an opposite upper surface and a lower surface; forming a drift oxide region on the upper surface and connected to the upper surface, and located on a drift region in an operation region and connected to the drift region; forming a drift well region on the upper surface of the semiconductor layer In the operation area, and the drift well area is located under the upper surface and connected to the upper surface, the drift well area has a first conductivity type; a channel well area is formed in the operation area under the upper surface, the channel well area The region has a second conductivity type and is adjacent to the drift well region in a channel direction; a buried layer is formed under the channel well region and connected to the channel well region, and the buried layer is in the operation region, completely Covering the channel well region, the buried layer has the first conductivity type; forming a gate electrode in the operation region on the upper surface of the semiconductor layer, part of the channel well region is located directly under the gate electrode and connected to the gate electrode The gate is used to provide an inversion current path of the high-voltage element during a conduction operation; at least one sub-gate is formed on the drift oxide region, and directly above at least part of the drift region, the sub-gate and the Gate electrodes are arranged in parallel, and the sub-gate electrode is located on the drift oxide region and connected to the drift oxide region; and a source electrode and a drain electrode are formed under the upper surface and connected to the operation region of the upper surface, The source electrode and the drain electrode have the first conductivity type, and are respectively located in the channel well region below the outside of the gate electrode and in the drift well region away from the channel well region side, and in the channel direction, The drift region is located between the drain electrode and the channel well region, in the drift well region near the upper surface, and is used as a drift current channel of the high-voltage element during the conduction operation, and viewed from the top view, The sub-gate is between the gate and the drain; wherein, the conductive layer of the gate has a first conductivity type, and the conductive layer of the sub-gate has a second conductivity type or is a pure semiconductor structure ; wherein the at least one sub-gate and the gate are not directly connected to each other; The conductive layer of the gate includes a polysilicon structure doped with impurities of a first conductivity type, and the conductive layer of the at least one sub-gate includes a polysilicon structure doped with impurities of a second conductivity type, wherein the conductivity type of the gate is Different from the conductivity type of the sub-gate; wherein the sub-gate is electrically floating, or is electrically connected to the source. The method for manufacturing a high voltage device as described in claim 16, wherein the drift oxide region comprises a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical Vapor deposition (chemical vapor deposition, CVD) oxidation zone.

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