US20010011742A1 - Semiconductor device having improved bias dependability and method of fabricating same - Google Patents
Semiconductor device having improved bias dependability and method of fabricating same Download PDFInfo
- Publication number
- US20010011742A1 US20010011742A1 US09/746,691 US74669100A US2001011742A1 US 20010011742 A1 US20010011742 A1 US 20010011742A1 US 74669100 A US74669100 A US 74669100A US 2001011742 A1 US2001011742 A1 US 2001011742A1
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- United States
- Prior art keywords
- polysilicon
- layer
- electrode
- semiconductor device
- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Definitions
- the present invention relates generally to semiconductor devices, and more specifically to an analog semiconductor devices having upper and lower polysilicon electrodes and a method of fabricating the semiconductor device.
- Analog metal-oxide-semiconductor transistors are composed of a gate formed on an oxide layer, and a source and a drain each being formed of upper and lower polysilicon electrodes and a capacitive element sandwiched therebetween. This capacitive element is required that a deviation from the specified capacitance value must be maintained in as small a range as possible under varying operating voltages.
- the lower polysilicon electrode and the gate are usually fabricated simultaneously. However, in the prior art transistor, the lower polysilicon electrode has no sufficient level of impurity dose to provide desired bias dependability. Thus there is a need to improve the bias dependability of a semiconductor device.
- a semiconductor device comprising a semiconductor substrate, an insulating layer on the substrate, the insulating layer having a gate insulating region, a lower polysilicon electrode on the insulating layer, a capacitive insulating layer on the lower polysilicon electrode, an upper polysilicon electrode on the capacitive insulating layer, and a polysilicon gate electrode on the gate insulating region, the gate electrode being of equal thickness to the lower polysilicon electrode.
- the lower polysilicon electrode is doped with an impurity of conductivity type identical to conductivity type of the polysilicon gate electrode.
- the present invention provides a method of fabricating a semiconductor device, comprising the steps of (a) forming a first insulating layer with a gate insulating region on a semiconductor substrate, (b) forming a first polysilicon layer on the first insulating layer and the gate insulating region, the first polysilicon layer having a first portion spaced from a second portion which contacts the gate insulating region, (c) doping an impurity into the first portion of the first polysilicon layer, the impurity having a conductivity type equal to conductivity type of the first polysilicon, (d) forming a second insulating layer on the first polysilicon layer, (e) forming a second polysilicon layer on the second insulating layer, (f) performing a first selective etching process so that a capacitive insulating layer and an upper polysilicon electrode are successively formed on the first portion of the first polysilicon layer and the second portion of the first polysilicon layer is exposed, and (
- FIGS. 1 to 8 are cross-sectional views of a semiconductor device of successive stages of the fabrication process of the present invention, wherein
- FIG. 1 illustrates the formation of a first insulating layer and a gate insulation layer on a semiconductor substrate and the deposition of a first polysilicon layer on the device
- FIG. 2 illustrates a first impurity doping process on a selected portion of the first polysilicon layer
- FIG. 3 illustrates the deposition of a second insulating layer on the first polysilicon layer
- FIG. 4 illustrates the deposition of a second polysilicon layer and a second impurity doping process on the second polysilicon layer
- FIGS. 5 and 6 illustrate a first etching process on a selected portion of the second polysilicon layer and the underlying second insulating layer
- FIGS. 7 and 8 illustrate a second etching process.
- FIGS. 1 to 8 a fabrication process of a semiconductor device according to the present invention is illustrated.
- a field oxide layer 2 is formed on a semiconductor substrate 1 as a device separator to a thickness of 200 to 500 nanometers.
- the device is coated with a polysilicon layer 4 with a thickness of 100 to 250 nanometers. A lower electrode and a gate will be formed from this polysilicon layer.
- photoresist 5 is used to provide ion implantation of phosphorous, whereby a polysilicon region selected for the lower electrode is doped with the impurity of the same conductivity type as the conductivity type of a polysilicon region to be selected as a gate electrode on the gate oxide layer 3 . If these polysilicon regions are of the N-type conductivity, the doping is continued until an impurity dose of 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 16 /cm 3 is attained. A highly doped polysilicon region 7 is thus formed. Note that phosphorous is of the same conductivity type as the conductivity type of a region above the gate oxide layer 3 .
- an oxide layer 8 is formed on the device to a thickness of 20 to 50 nanometers, as shown in FIG. 3.
- a polysilicon layer 14 of thickness 100 to 200 nanometers is grown on the oxide layer 8 and the polysilicon layer 14 is then doped with phosphorous in an ion implantation process. If the polysilicon layer 14 is of the N-type conductivity, the doping is continued until an impurity dose of 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 16 /cm 3 is reached.
- the polysilicon layer 14 and oxide layer 8 are selectively etched by using a photoresist 15 .
- a capacitive oxide layer 18 is formed on the highly doped polysilicon region 7 and a doped polysilicon layer 24 on the capacitive layer 18 , as shown in FIG. 6.
- the polysilicon layer 4 is selectively etched by using photoresists 25 and 26 so that the lower polysilicon electrode 10 and the gate 11 are formed as shown in FIG. 8.
- the bias dependability of the transistor of this invention is improved to 0.01%/volts to 0.03%/volts, as opposed to the dependability value of 03%/volts to 0.5%/volts of the prior art transistor in which the lower polysilicon electrode is not ion-injected with phosphorous.
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to semiconductor devices, and more specifically to an analog semiconductor devices having upper and lower polysilicon electrodes and a method of fabricating the semiconductor device.
- 2. Description of the Related Art
- Analog metal-oxide-semiconductor transistors are composed of a gate formed on an oxide layer, and a source and a drain each being formed of upper and lower polysilicon electrodes and a capacitive element sandwiched therebetween. This capacitive element is required that a deviation from the specified capacitance value must be maintained in as small a range as possible under varying operating voltages. The lower polysilicon electrode and the gate are usually fabricated simultaneously. However, in the prior art transistor, the lower polysilicon electrode has no sufficient level of impurity dose to provide desired bias dependability. Thus there is a need to improve the bias dependability of a semiconductor device.
- It is therefore an object of the present invention to provide a semiconductor device with a lower polysilicon electrode having an impurity dose that is sufficient to obtain desired bias dependability and a method of fabricating the semiconductor device.
- According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, an insulating layer on the substrate, the insulating layer having a gate insulating region, a lower polysilicon electrode on the insulating layer, a capacitive insulating layer on the lower polysilicon electrode, an upper polysilicon electrode on the capacitive insulating layer, and a polysilicon gate electrode on the gate insulating region, the gate electrode being of equal thickness to the lower polysilicon electrode. The lower polysilicon electrode is doped with an impurity of conductivity type identical to conductivity type of the polysilicon gate electrode.
- According to a further aspect, the present invention provides a method of fabricating a semiconductor device, comprising the steps of (a) forming a first insulating layer with a gate insulating region on a semiconductor substrate, (b) forming a first polysilicon layer on the first insulating layer and the gate insulating region, the first polysilicon layer having a first portion spaced from a second portion which contacts the gate insulating region, (c) doping an impurity into the first portion of the first polysilicon layer, the impurity having a conductivity type equal to conductivity type of the first polysilicon, (d) forming a second insulating layer on the first polysilicon layer, (e) forming a second polysilicon layer on the second insulating layer, (f) performing a first selective etching process so that a capacitive insulating layer and an upper polysilicon electrode are successively formed on the first portion of the first polysilicon layer and the second portion of the first polysilicon layer is exposed, and (g) performing a second selective etching process so that the first and second portions of the first polysilicon layer define a lower polysilicon electrode and a gate electrode, respectively.
- The present invention will be described in detail further with reference to the following drawings, in which:
- FIGS.1 to 8 are cross-sectional views of a semiconductor device of successive stages of the fabrication process of the present invention, wherein
- FIG. 1 illustrates the formation of a first insulating layer and a gate insulation layer on a semiconductor substrate and the deposition of a first polysilicon layer on the device,
- FIG. 2 illustrates a first impurity doping process on a selected portion of the first polysilicon layer;
- FIG. 3 illustrates the deposition of a second insulating layer on the first polysilicon layer;
- FIG. 4 illustrates the deposition of a second polysilicon layer and a second impurity doping process on the second polysilicon layer;
- FIGS. 5 and 6 illustrate a first etching process on a selected portion of the second polysilicon layer and the underlying second insulating layer; and
- FIGS. 7 and 8 illustrate a second etching process.
- Referring to FIGS.1 to 8, a fabrication process of a semiconductor device according to the present invention is illustrated.
- In FIG. 1, a
field oxide layer 2 is formed on asemiconductor substrate 1 as a device separator to a thickness of 200 to 500 nanometers. After forming agate oxide layer 3, the device is coated with apolysilicon layer 4 with a thickness of 100 to 250 nanometers. A lower electrode and a gate will be formed from this polysilicon layer. - In FIG. 2, photoresist5 is used to provide ion implantation of phosphorous, whereby a polysilicon region selected for the lower electrode is doped with the impurity of the same conductivity type as the conductivity type of a polysilicon region to be selected as a gate electrode on the
gate oxide layer 3. If these polysilicon regions are of the N-type conductivity, the doping is continued until an impurity dose of 1×1015/cm3 to 1×1016/cm3 is attained. A highly dopedpolysilicon region 7 is thus formed. Note that phosphorous is of the same conductivity type as the conductivity type of a region above thegate oxide layer 3. - After removing the photoresist5, an
oxide layer 8 is formed on the device to a thickness of 20 to 50 nanometers, as shown in FIG. 3. - In FIG. 4, a
polysilicon layer 14 of thickness 100 to 200 nanometers is grown on theoxide layer 8 and thepolysilicon layer 14 is then doped with phosphorous in an ion implantation process. If thepolysilicon layer 14 is of the N-type conductivity, the doping is continued until an impurity dose of 1× 1015/cm3 to 1×1016/cm3 is reached. - In FIG. 5, the
polysilicon layer 14 andoxide layer 8 are selectively etched by using aphotoresist 15. As a result, acapacitive oxide layer 18 is formed on the highlydoped polysilicon region 7 and a dopedpolysilicon layer 24 on thecapacitive layer 18, as shown in FIG. 6. - In FIG. 7, the
polysilicon layer 4 is selectively etched by usingphotoresists lower polysilicon electrode 10 and thegate 11 are formed as shown in FIG. 8. - The bias dependability of the transistor of this invention is improved to 0.01%/volts to 0.03%/volts, as opposed to the dependability value of 03%/volts to 0.5%/volts of the prior art transistor in which the lower polysilicon electrode is not ion-injected with phosphorous.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/043,466 US20020053707A1 (en) | 1999-12-22 | 2002-01-11 | Semiconductor device having improved bias dependability and method of fabricating same |
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JP11-364147 | 1999-12-22 | ||
JP36414799A JP2001185628A (en) | 1999-12-22 | 1999-12-22 | Semiconductor device and method of fabrication |
Related Child Applications (1)
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US10/043,466 Division US20020053707A1 (en) | 1999-12-22 | 2002-01-11 | Semiconductor device having improved bias dependability and method of fabricating same |
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US20010011742A1 true US20010011742A1 (en) | 2001-08-09 |
US6338997B2 US6338997B2 (en) | 2002-01-15 |
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US09/746,691 Expired - Fee Related US6338997B2 (en) | 1999-12-22 | 2000-12-21 | Method of fabricating semiconductor device having improved bias dependability |
US10/043,466 Abandoned US20020053707A1 (en) | 1999-12-22 | 2002-01-11 | Semiconductor device having improved bias dependability and method of fabricating same |
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US10/043,466 Abandoned US20020053707A1 (en) | 1999-12-22 | 2002-01-11 | Semiconductor device having improved bias dependability and method of fabricating same |
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JP (1) | JP2001185628A (en) |
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WO2002048689A1 (en) * | 2000-12-13 | 2002-06-20 | Institut D'optique Theorique Et Appliquee | Method for characterising a surface, and device therefor |
JP2002313932A (en) * | 2001-04-12 | 2002-10-25 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
JP2003224201A (en) | 2002-01-31 | 2003-08-08 | Mitsubishi Electric Corp | Semiconductor device and its fabricating method |
DE10338550A1 (en) * | 2003-08-19 | 2005-03-31 | Basf Ag | Transition metal complexes with carbene ligands as emitters for organic light-emitting diodes (OLEDs) |
KR100801076B1 (en) * | 2006-02-28 | 2008-02-11 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
KR20100076256A (en) * | 2008-12-26 | 2010-07-06 | 주식회사 동부하이텍 | Method of manufacturing a polysilicon-insulator-polysilicon |
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US6171901B1 (en) * | 1999-07-16 | 2001-01-09 | National Semiconductor Corporation | Process for forming silicided capacitor utilizing oxidation barrier layer |
US6156602A (en) * | 1999-08-06 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Self-aligned precise high sheet RHO register for mixed-signal application |
-
1999
- 1999-12-22 JP JP36414799A patent/JP2001185628A/en active Pending
-
2000
- 2000-12-21 US US09/746,691 patent/US6338997B2/en not_active Expired - Fee Related
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2002
- 2002-01-11 US US10/043,466 patent/US20020053707A1/en not_active Abandoned
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JP2001185628A (en) | 2001-07-06 |
US20020053707A1 (en) | 2002-05-09 |
US6338997B2 (en) | 2002-01-15 |
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Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YOSHIKAWA, KOICHI;REEL/FRAME:011404/0805 Effective date: 20001221 |
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