US20010010967A1 - Method for supressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping - Google Patents

Method for supressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping Download PDF

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US20010010967A1
US20010010967A1 US09/795,936 US79593601A US2001010967A1 US 20010010967 A1 US20010010967 A1 US 20010010967A1 US 79593601 A US79593601 A US 79593601A US 2001010967 A1 US2001010967 A1 US 2001010967A1
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nitrogen
gate dielectric
channel region
dielectric layer
plasma doping
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Wei-Wen Chen
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method of fabricating semiconductor device, and more particular to a method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping.
  • MOS metal-oxide-semiconductor
  • the manufacturing process begins by lightly doping a single crystalline silicon substrate with n-type or p-type species. Active areas of the substrate in which the transistors and other active devices will reside are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate that are filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon (LOCOS) structures. A gate dielectric layer (i.e., silicon dioxide) is then formed upon the substrate by thermally oxidizing the silicon-based substrate.
  • LOC local oxidation of silicon
  • a gate conductor is formed by depositing polysilicon upon the gate dielectric, followed by patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon gate conductor and source/drain regions arranged within the substrate on opposite sides of the gate conductor are concurrently doped with a high dosage of n-type or p-type dopants. If the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device.
  • the resistivity of the polysilicon gate conductor is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistance of the gate conductor is reduced to, in some instances, less than approximately 500 ohms/sq.
  • the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment.
  • the minimum depth of implantation is limited to between 200 .ANG. and 400 .ANG., because the energy of each ion is typically too large to permit a lesser depth of implantation.
  • Subsequent processing steps may require heating of the semiconductor topography.
  • a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor.
  • Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity.
  • boron which is commonly used to dope the polysilicon gate and the source/drain regions of a PMOS device undergoes fast diffusion. Unfortunately, boron readily migrates during heat treatment may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current.
  • the thickness of the gate dielectric layer is thinner than 20 ANG., and therefore, boron penetration effect is more significant. It is important to suppressing boron penetration through the gate dielectric layer into the device channel region that causes threshold voltage change and effects device operation.
  • the present invention provides a method of suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping, comprising the following steps.
  • a semiconductor substrate having a channel region is provided.
  • a pulsed nitrogen plasma doping step is then performed to dope nitrogen ions into the surface layer in the channel region.
  • a nitrogen annealing step is optionally performed after the pulsed nitrogen plasma doping step to enhance the doping result of nitrogen ions.
  • a thermal oxidation step is performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate.
  • an oxynitride containing thin film is formed over the channel region. Since the nitrogen ions doped in the surface layer in the channel region can produces a dense structure to provide barrier to effectively suppress boron penetrating through the gate dielectric layer into channel region, and therefore, electric property change of transistors causing from boron penetrating can be prevented
  • FIG. 1A- 1 D are schematic, cross-sectional views of one preferred embodiment of the present invention.
  • FIG. 2 is a schematic view of equipment structure of pulsed nitrogen plasma doping.
  • a semiconductor substrate 100 such as single crystal silicon substrate is provided.
  • a plurality of device isolations 102 are then formed in the substrate 100 to scheme location of transistors in active regions between device isolations 102 , wherein the active regions comprise channel regions of each transistor.
  • the device isolations 102 comprise the local oxidation of silicon (LOCOS) structures or shallow trench isolations (STI).
  • LOC local oxidation of silicon
  • STI shallow trench isolations
  • a pulsed nitrogen plasma doping step 104 is performed by utilizing nitrogen plasma to pulsed dope nitrogen ions into the surface layer in the active regions (comprising channel regions).
  • the pulsed nitrogen plasma doping of the present invention can get less doping depth, such as shallower than 50 ANG.
  • the nitrogen ions 106 doped into the substrate 100 are almost stay in the surface layer of the substrate 100 , and therefore, fewer damages are created on the substrate 100 . This is rewarding to maintain perfection of interface between the substrate 100 and the gate dielectric layer subsequently formed on the substrate 100 .
  • a photoresist layer may be formed on the substrate 100 to only expose the channel regions, and then the pulsed nitrogen plasma doping is sequently performed.
  • the pulsed nitrogen plasma doping is further described in detail in the following description.
  • FIG. 2 it is a schematic view of equipment structure of pulsed nitrogen plasma doping.
  • the reaction chamber in the equipment mainly comprises a lower electrode 202 and an upper electrode 204 , and a wafer 200 comprising the semiconductor substrate 100 is deposed and mounted on the lower electrode 202 .
  • a nitrogen containing gas such as nitrogen gas
  • nitrogen gas mixed with carrier gas such as argon
  • a nitrogen annealing step can be optionally performed to enhance doping resulting.
  • pure nitrogen gas i.e. purity is about 100%, is injected into the reaction chamber.
  • the nitrogen annealing step is performed to active the doped nitrogen ions 106 and recondition the wafer surface damaged in the doping step.
  • a thermal oxidation step 108 is then performed by utilizing traditional thermal oxidation, such as dry oxidation, to oxidize the silicon substrate 100 , and therefore a gate dielectric layer 110 comprising silicon dioxide is grew on the substrate 100 . Since the nitrogen ions 106 are doped into the surface layer of the substrate 100 prior to the thermal oxidation step 108 , an oxynitride layer is produced in the lower portion of the gate dielectric layer 110 . Therefore, the gate dielectric layer 100 is a commixed layer with oxide in the upper portion and oxynitride in the lower portion. Moreover, the thermal oxidation step 108 can recondition forward damages from nitrogen doping.
  • traditional thermal oxidation such as dry oxidation
  • the nitrogen annealing step is performed, a commixed structure with nitride, oxynitride, and oxide stacked in sequent is therefore formed. Since the lower oxynitride layer has closer and denser structure than the oxide layer, boron can be effectively defensed and therefore boron penetration can be suppressed.
  • PMOS transistor For example, a boron doped polysilicon layer is formed over the channel region 126 to serve as gate conductive layer 120 .
  • a gate spacer 122 is then formed on the sidewall of the gate conductive layer 120 , and a source/drain region 124 is formed on both sides of the gate conductive layer 120 . Since these are well known for the skills in the art, the present invention will not discuss in detail. Moreover, the technology in the present invention can also be applied to PMOS transistor relative device, such as complementary metal-oxide-semiconductor (CMOS) transistor.
  • CMOS complementary metal-oxide-semiconductor
  • the present invention discloses a method for suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping.
  • Nitrogen ions can be doped into extremely shallow surface layer to reduce damage caused from nitrogen doping by pulsed nitrogen plasma doping of the present invention to maintain perfection of interface between the substrate and the gate dielectric layer.
  • the gate dielectric layer of the present invention including oxynitride or nitride can produce closed and densed structure, and therefore can effectively defense boron penetating the gate dielectric layer into channel region to affect electrical properties of the transistors.

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Abstract

A method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. A pulsed nitrogen plasma doping process is utilized to dope nitrogen ions into the surface layer in the channel region of the semiconductor substrate. A thermal oxidation step is then performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate to avoid boron penetration effect accruing while a boron doped polysilicon layer is subsequently formed on the gate dielectric layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method of fabricating semiconductor device, and more particular to a method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. [0001]
    • BACKGROUND OF THE INVENTION
  • Fabrication of metal-oxide-semiconductor (MOS) transistors is well-known for the skills in the art. The manufacturing process begins by lightly doping a single crystalline silicon substrate with n-type or p-type species. Active areas of the substrate in which the transistors and other active devices will reside are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate that are filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon (LOCOS) structures. A gate dielectric layer (i.e., silicon dioxide) is then formed upon the substrate by thermally oxidizing the silicon-based substrate. A gate conductor is formed by depositing polysilicon upon the gate dielectric, followed by patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon gate conductor and source/drain regions arranged within the substrate on opposite sides of the gate conductor are concurrently doped with a high dosage of n-type or p-type dopants. If the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device. [0002]
  • The resistivity of the polysilicon gate conductor is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistance of the gate conductor is reduced to, in some instances, less than approximately 500 ohms/sq. In an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. However, the minimum depth of implantation is limited to between 200 .ANG. and 400 .ANG., because the energy of each ion is typically too large to permit a lesser depth of implantation. [0003]
  • Subsequent processing steps may require heating of the semiconductor topography. For example, a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity. For instance, boron which is commonly used to dope the polysilicon gate and the source/drain regions of a PMOS device undergoes fast diffusion. Unfortunately, boron readily migrates during heat treatment may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current. [0004]
  • Hence, while critical dimension is scaling down to 0.18 μm, the thickness of the gate dielectric layer is thinner than 20 ANG., and therefore, boron penetration effect is more significant. It is important to suppressing boron penetration through the gate dielectric layer into the device channel region that causes threshold voltage change and effects device operation. [0005]
    • SUMMARY OF THE INVENTION
  • The present invention provides a method of suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping, comprising the following steps. A semiconductor substrate having a channel region is provided. A pulsed nitrogen plasma doping step is then performed to dope nitrogen ions into the surface layer in the channel region. A nitrogen annealing step is optionally performed after the pulsed nitrogen plasma doping step to enhance the doping result of nitrogen ions. A thermal oxidation step is performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate. [0006]
  • According to the method of fabricating the gate dielectric layer of the present invention, an oxynitride containing thin film is formed over the channel region. Since the nitrogen ions doped in the surface layer in the channel region can produces a dense structure to provide barrier to effectively suppress boron penetrating through the gate dielectric layer into channel region, and therefore, electric property change of transistors causing from boron penetrating can be prevented [0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: [0008]
  • FIG. 1A-[0009] 1D are schematic, cross-sectional views of one preferred embodiment of the present invention; and
  • FIG. 2 is a schematic view of equipment structure of pulsed nitrogen plasma doping. [0010]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to FIG. 1A, a [0011] semiconductor substrate 100, such as single crystal silicon substrate is provided. A plurality of device isolations 102 are then formed in the substrate 100 to scheme location of transistors in active regions between device isolations 102, wherein the active regions comprise channel regions of each transistor. The device isolations 102 comprise the local oxidation of silicon (LOCOS) structures or shallow trench isolations (STI).
  • Referring to FIG. 1B, a pulsed nitrogen [0012] plasma doping step 104 is performed by utilizing nitrogen plasma to pulsed dope nitrogen ions into the surface layer in the active regions (comprising channel regions). Comparing to traditional ion implanting process, the pulsed nitrogen plasma doping of the present invention can get less doping depth, such as shallower than 50 ANG. The nitrogen ions 106 doped into the substrate 100 are almost stay in the surface layer of the substrate 100, and therefore, fewer damages are created on the substrate 100. This is rewarding to maintain perfection of interface between the substrate 100 and the gate dielectric layer subsequently formed on the substrate 100. In addition, if only the channel regions are needed to dope nitrogen ions 106, a photoresist layer may be formed on the substrate 100 to only expose the channel regions, and then the pulsed nitrogen plasma doping is sequently performed.
  • The pulsed nitrogen plasma doping is further described in detail in the following description. Referring to FIG. 2, it is a schematic view of equipment structure of pulsed nitrogen plasma doping. The reaction chamber in the equipment mainly comprises a [0013] lower electrode 202 and an upper electrode 204, and a wafer 200 comprising the semiconductor substrate 100 is deposed and mounted on the lower electrode 202. A nitrogen containing gas, such as nitrogen gas, is injected into the reaction chamber and flowed between the lower and upper electrode 202, 204. Likewise, nitrogen gas mixed with carrier gas, such as argon, can be injected into the reaction chamber to serve as reaction gas. A negative voltage is applied on the lower electrode 202 in accompany with a positive voltage applied on the upper electrode 204 to make nitrogen containing gas decompose to generate plasma 206 with positive nitrogen ions 208. The positive nitrogen ions 208 are then attracted with the negative lower electrode 202 and move forward to be implanted into the wafer 200. In the preferred embodiment, pulsed voltage is applied on the lower electrode 202 to control the plasma. The process parameters in the pulsed nitrogen plasma doping are controlled in the following ranges. The energy of pulsed nitrogen plasma doping is about 200-10000 eV, and the dosage is about 1E14-1E17/cm2. Suitable operating in accordance with other parameters, such as gas species, gas pressure, gas flow rate, voltage bias, distance between lower and upper electrode 202, 204, and reaction time, this can make better doping resulting.
  • After the pulsed nitrogen plasma doping, a nitrogen annealing step can be optionally performed to enhance doping resulting. At a temperature of about 800-1100° C., pure nitrogen gas, i.e. purity is about 100%, is injected into the reaction chamber. The nitrogen annealing step is performed to active the doped [0014] nitrogen ions 106 and recondition the wafer surface damaged in the doping step.
  • Referring to FIG. 1C, a thermal oxidation step [0015] 108 is then performed by utilizing traditional thermal oxidation, such as dry oxidation, to oxidize the silicon substrate 100, and therefore a gate dielectric layer 110 comprising silicon dioxide is grew on the substrate 100. Since the nitrogen ions 106 are doped into the surface layer of the substrate 100 prior to the thermal oxidation step 108, an oxynitride layer is produced in the lower portion of the gate dielectric layer 110. Therefore, the gate dielectric layer 100 is a commixed layer with oxide in the upper portion and oxynitride in the lower portion. Moreover, the thermal oxidation step 108 can recondition forward damages from nitrogen doping. If the nitrogen annealing step is performed, a commixed structure with nitride, oxynitride, and oxide stacked in sequent is therefore formed. Since the lower oxynitride layer has closer and denser structure than the oxide layer, boron can be effectively defensed and therefore boron penetration can be suppressed.
  • Referring to FIG. 1D, further processes are continued to complete PMOS transistor. For example, a boron doped polysilicon layer is formed over the [0016] channel region 126 to serve as gate conductive layer 120. A gate spacer 122 is then formed on the sidewall of the gate conductive layer 120, and a source/drain region 124 is formed on both sides of the gate conductive layer 120. Since these are well known for the skills in the art, the present invention will not discuss in detail. Moreover, the technology in the present invention can also be applied to PMOS transistor relative device, such as complementary metal-oxide-semiconductor (CMOS) transistor.
  • According to above description, the present invention discloses a method for suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping. Nitrogen ions can be doped into extremely shallow surface layer to reduce damage caused from nitrogen doping by pulsed nitrogen plasma doping of the present invention to maintain perfection of interface between the substrate and the gate dielectric layer. The gate dielectric layer of the present invention including oxynitride or nitride can produce closed and densed structure, and therefore can effectively defense boron penetating the gate dielectric layer into channel region to affect electrical properties of the transistors. [0017]
  • As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure. [0018]

Claims (23)

What is claimed is:
1. A method for suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping, comprising the steps of:
providing a semiconductor substrate having a channel region;
performing a pulsed nitrogen plasma doping step to dope nitrogen ions into the surface layer in the channel region; and
performing a thermal oxidation step to form a gate dielectric layer over the channel region of the semiconductor substrate.
2. The method according to
claim 1
, wherein the energy used in the pulsed nitrogen plasma doping step is about 200-1000 eV.
3. The method according to
claim 1
, wherein the dosage of nitrogen ions doped into the surface layer in the channel region is about 1E14-1E17/cm2.
4. The method according to
claim 1
, further comprising an annealing step after the pulsed nitrogen plasma doping step.
5. The method according to
claim 4
, wherein nitrogen is introduced in the annealing step.
6. The method according to
claim 5
, wherein the purity of the nitrogen is 100%.
7. The method according to
claim 4
, wherein the annealing step is at 800-1100° C.
8. The method according to
claim 1
, wherein the gate dielectric layer is a commixed layer of oxide and oxynitride.
9. A method for suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping, comprising the steps of:
providing a semiconductor substrate having a channel region;
performing a pulsed nitrogen plasma doping step to dope nitrogen ions into the surface layer in the channel region;
performing a nitrogen annealing step; and
performing a thermal oxidation step to form a gate dielectric layer over the channel region of the semiconductor substrate.
10. The method according to
claim 9
, wherein the energy used in the pulsed nitrogen plasma doping step is about 200-10000 eV.
11. The method according to
claim 9
, wherein the dosage of nitrogen ions doped into the surface layer in the channel region is about 1E14-1E17/cm2.
12. The method according to
claim 9
, wherein nitrogen is introduced in the nitrogen annealing step.
13. The method according to
claim 12
 wherein the purity of the nitrogen is 100%.
14. The method according to
claim 9
, wherein the annealing step is at 800-1100° C.
15. The method according to
claim 1
, wherein the gate dielectric layer is a commixed layer of oxide and oxynitride.
16. A method for fabricating a PMOS transistor, at least comprising the steps of:
providing a semiconductor substrate having a channel region;
performing a pulsed nitrogen plasma doping step to dope nitrogen ions into the surface layer in the channel region;
performing a thermal oxidation step to form a gate dielectric layer over the channel region of the semiconductor substrate;
forming a boron doped polysilicon layer over the channel region of the semiconductor substrate; and
forming a source/drain region in the semiconductor substrate and on both sides of the boron doped polysilicon layer.
17. The method according to
claim 16
, wherein the energy used in the pulsed nitrogen plasma doping step is about 200-10000 eV.
18. The method according to
claim 16
, wherein the dosage of nitrogen ions doped into the surface layer in the channel region is about 1E14-1B17/cm2.
19. The method according to
claim 16
, further comprising an annealing step after the pulsed nitrogen plasma doping step.
20. The method according to
claim 19
, wherein nitrogen is introduced in the annealing step.
21. The method according to
claim 20
, wherein the purity of the nitrogen is 100%.
22. The method according to
claim 19
, wherein the annealing step is at 800-1100° C.
23. The method according to
claim 16
, wherein the gate dielectric layer is a commixed layer of oxide and oxynitride.
US09/795,936 2000-01-30 2001-02-28 Method for suppressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping Expired - Lifetime US6432780B2 (en)

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US7033873B1 (en) * 2002-09-18 2006-04-25 Advanced Micro Devices, Inc. Methods of controlling gate electrode doping, and systems for accomplishing same
US20170018561A1 (en) * 2014-03-06 2017-01-19 The Regents Of The University Of Michigan Field effect transistor memory device

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US20020132457A1 (en) * 2001-03-13 2002-09-19 Macronix International Co., Ltd. Method for avoiding the ion penetration with the plasma doping
US20020197885A1 (en) * 2001-06-22 2002-12-26 Jack Hwang Method of making a semiconductor transistor by implanting ions into a gate dielectric layer thereof
KR100568859B1 (en) * 2003-08-21 2006-04-10 삼성전자주식회사 Method for manufacturing transistor of dynamic random access memory semiconductor
US9595444B2 (en) * 2015-05-14 2017-03-14 Sandisk Technologies Llc Floating gate separation in NAND flash memory
KR20220048690A (en) 2020-10-13 2022-04-20 삼성전자주식회사 Method for fabricating semiconductor device

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US6093661A (en) * 1999-08-30 2000-07-25 Micron Technology, Inc. Integrated circuitry and semiconductor processing method of forming field effect transistors

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US7033873B1 (en) * 2002-09-18 2006-04-25 Advanced Micro Devices, Inc. Methods of controlling gate electrode doping, and systems for accomplishing same
US20170018561A1 (en) * 2014-03-06 2017-01-19 The Regents Of The University Of Michigan Field effect transistor memory device
US9960175B2 (en) * 2014-03-06 2018-05-01 The Regents Of The University Of Michigan Field effect transistor memory device

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