US20010009297A1 - Bonding pad on a semiconductor chip - Google Patents
Bonding pad on a semiconductor chip Download PDFInfo
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- US20010009297A1 US20010009297A1 US09/800,574 US80057401A US2001009297A1 US 20010009297 A1 US20010009297 A1 US 20010009297A1 US 80057401 A US80057401 A US 80057401A US 2001009297 A1 US2001009297 A1 US 2001009297A1
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Definitions
- the present invention relates to a semiconductor chip, and more particularly, to a bonding pad on a semiconductor chip.
- MOS transistors are formed on a semiconductor chip
- the MOS transistors are connected by using multiple metallic interconnects. Contact of the metallic interconnects and the MOS transistors is avoided by depositing dielectric layers with a lower dielectric constant. This also reduces induced capacitance between them thus increasing the speed of signal transmission.
- a bonding pad will be formed in a predetermined area on the last dielectric layer as an interconnection area in a follow-up packaging process.
- FIG. 1 is a perspective view of the structure of a bonding pad 14 of a prior art semiconductor wafer 10 .
- the last layer of metallic interconnects is formed, and a metallic layer is formed as the bonding pad 14 in a predetermined area on the dielectric layer 12 .
- the semiconductor wafer 10 is then sectioned into individual chips for performing a following packaging process. If the dielectric constant of the dielectric layer 12 is too high, the speed of signal transmission between the dielectric layers 12 will be reduced. Therefore, the dielectric layer 12 is made of fluoride silicate glass (FSG) in the prior art with a low dielectric constant.
- FSG fluoride silicate glass
- FIG. 2 is a perspective view of the bonding pad 14 on a chip 15 connected to a metallic wire 18 .
- one side of the chip 15 is first fixed onto a baseplate 16 and one end of the metallic wire 18 is heated to form a metallic ball 17 . This allows bonding of the metallic wire 18 to the bonding pad 14 .
- the other end of the metallic wire 18 is dragged to and linked to a predetermined area of the baseplate 16 so that electronic signals of the chip 15 can be transmitted to external components.
- the dielectric layer 12 below the bonding pad 14 is made of flouride silicate glass (FSG) with a lower degree of hardness.
- FSG flouride silicate glass
- the metallic wire 18 is dragged across the surface of the baseplate 16 , or when the chip 15 is washed by performing a supersonic vibration process, the metallic ball 17 , bonding pad 14 and part of the dielectric layer 12 are peeled off from the surface of the chip 15 . This causes damage to the chip 15 and reduces reliability of packaging.
- the present invention provides a bonding pad on a semiconductor chip, the bonding pad being used to electrically connect an integrated circuit in the semiconductor chip with an external circuit.
- the semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting an integrated circuit (IC) in the semiconductor chip with an external circuit.
- IC integrated circuit
- the bonding pad can be firmly bonded to the surface of the semiconductor chip without peeling. Since the dielectric constant of the second dielectric layer is lower in the present invention, signal transmission speeds are not affected.
- FIG. 1 is a perspective view of the structure of a bonding pad of a prior art semiconductor wafer.
- FIG. 2 is a perspective view of the bonding pad in FIG. 1 on a chip connected to a metallic wire.
- FIG. 3 to FIG. 7 are perspective views of forming a bonding pad on a semiconductor wafer according to the present invention.
- FIG. 8 and FIG. 9 are perspective views of packaging a chip cut from the wafer in FIG. 3.
- FIG. 3 to FIG. 7 are perspective views of forming a bonding pad 26 on a semiconductor wafer 20 according to the present invention.
- the bonding pad 26 is used for electrically connecting integrated circuits on the semiconductor wafer 20 with external circuits.
- a uniform silicon dioxide (SiO 2 ) layer 21 is formed on the semiconductor wafer 20 , and photolithographic and etching processes are then performed to remove the silicon dioxide layer 21 outside of a predetermined area. This forms a first dielectric layer 22 as shown in FIG. 4.
- a flouride silicate glass (FSG) layer 23 is uniformly deposited on the semiconductor wafer 20 as shown in FIG. 5 followed by performing a chemical mechanical polishing (CMP) process to remove all the flouride silicate glass (FSG) in the predetermined area on the first dielectric layer 22 .
- CMP chemical mechanical polishing
- a second dielectric layer 24 is thus formed in close approximation to the sides of the first dielectric layer 22 as shown in FIG. 6.
- the dielectric constant and the degree of the hardness of the first dielectric layer 22 are both greater than those of the second dielectric layer 24 .
- the bonding pad 26 is formed on the first dielectric layer 22 at the same time the last layer of metal interconnects of the second dielectric layer 24 is prepared. As shown in FIG. 7, the bonding pad 26 comprises a titanium (Ti) glue layer 28 as its bottom layer, an aluminum alloy layer 30 on top of the glue layer 28 , and a titanium nitride (TiN) anti-reflection layer 32 on top of the aluminum alloy layer 30 .
- the aluminum alloy layer 30 is formed of aluminum and copper with more than 95% aluminum by weight.
- the aluminum alloy layer 30 can be made of aluminum (Al) copper (Cu) or alloy of aluminum.
- the semiconductor wafer 20 formed by the method of the present invention comprises a first dielectric layer 22 in a predetermined area on the semiconductor wafer 20 , a second dielectric layer 24 outside the predetermined area of the surface of the wafer 20 and a bonding pad 26 formed on the first dielectric layer 22 (FIG. 7).
- the first dielectric layer 22 is formed of silicon dioxide
- the second dielectric layer 24 is formed of flouride silicate glass (FSG).
- FSG flouride silicate glass
- the first dielectric layer 22 is harder and more durable than the dielectric layer 12 under the bonding pad 14 of the prior art. As such, the present invention dielectric layer 22 can withstand the stress exerted when connecting the metallic wire 18 with external circuits. This prevents peeling off of the bonding pad 26 from the dielectric layer 22 .
- FIG. 8 and FIG. 9 are perspective views of packaging a chip 80 cut from the wafer 20 .
- the manufacturing method for the bonding pad may also be used in “flip chip” processing.
- the chip 80 is cut from the semiconductor wafer 20 .
- a metallic lump 42 is formed on the bonding pad 26 of the chip 80 as shown in FIG. 8.
- the chip 80 is turned upside-down so that the melted metallic bump 42 contacts a baseplate 40 .
- the chip 80 is then fixed to the baseplate 40 by solidifying the metallic lump 42 .
- liquid epoxy 44 is injected into the gap between the chip 80 and the baseplate 40 followed by solidifying the epoxy 44 by baking, as shown in FIG. 9.
- the first dielectric layer under the bonding pad in present invention has increased hardness.
- the second dielectric layer, formed in areas not occupied by the first dielectric layer, has a lower dielectric constant.
Abstract
The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.
Description
- 1. Field of the invention
- The present invention relates to a semiconductor chip, and more particularly, to a bonding pad on a semiconductor chip.
- 2. Description of the Prior Art
- In a semiconductor process, when MOS transistors are formed on a semiconductor chip, the MOS transistors are connected by using multiple metallic interconnects. Contact of the metallic interconnects and the MOS transistors is avoided by depositing dielectric layers with a lower dielectric constant. This also reduces induced capacitance between them thus increasing the speed of signal transmission. When forming the last layer of metallic interconnects, a bonding pad will be formed in a predetermined area on the last dielectric layer as an interconnection area in a follow-up packaging process.
- Please refer to FIG. 1. FIG. 1 is a perspective view of the structure of a
bonding pad 14 of a priorart semiconductor wafer 10. After forming the lastdielectric layer 12 on thesemiconductor wafer 10, the last layer of metallic interconnects is formed, and a metallic layer is formed as thebonding pad 14 in a predetermined area on thedielectric layer 12. After an error-free electrical test is performed, thesemiconductor wafer 10 is then sectioned into individual chips for performing a following packaging process. If the dielectric constant of thedielectric layer 12 is too high, the speed of signal transmission between thedielectric layers 12 will be reduced. Therefore, thedielectric layer 12 is made of fluoride silicate glass (FSG) in the prior art with a low dielectric constant. - Please refer to FIG. 2. FIG. 2 is a perspective view of the
bonding pad 14 on achip 15 connected to ametallic wire 18. When performing a wire bonding process, one side of thechip 15 is first fixed onto abaseplate 16 and one end of themetallic wire 18 is heated to form ametallic ball 17. This allows bonding of themetallic wire 18 to thebonding pad 14. Next, the other end of themetallic wire 18 is dragged to and linked to a predetermined area of thebaseplate 16 so that electronic signals of thechip 15 can be transmitted to external components. Thedielectric layer 12 below thebonding pad 14 is made of flouride silicate glass (FSG) with a lower degree of hardness. Therefore, when themetallic wire 18 is dragged across the surface of thebaseplate 16, or when thechip 15 is washed by performing a supersonic vibration process, themetallic ball 17,bonding pad 14 and part of thedielectric layer 12 are peeled off from the surface of thechip 15. This causes damage to thechip 15 and reduces reliability of packaging. - It is therefore a primary objective of the present invention to provide a bonding pad on a semiconductor chip to solve the above mentioned problem.
- In a preferred embodiment, the present invention provides a bonding pad on a semiconductor chip, the bonding pad being used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting an integrated circuit (IC) in the semiconductor chip with an external circuit.
- It is an advantage of the present invention that by using a harder first dielectric layer, the bonding pad can be firmly bonded to the surface of the semiconductor chip without peeling. Since the dielectric constant of the second dielectric layer is lower in the present invention, signal transmission speeds are not affected.
- This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
- FIG. 1 is a perspective view of the structure of a bonding pad of a prior art semiconductor wafer.
- FIG. 2 is a perspective view of the bonding pad in FIG. 1 on a chip connected to a metallic wire.
- FIG. 3 to FIG. 7 are perspective views of forming a bonding pad on a semiconductor wafer according to the present invention.
- FIG. 8 and FIG. 9 are perspective views of packaging a chip cut from the wafer in FIG. 3.
- Please refer to FIG. 3 to FIG. 7. FIG. 3 to FIG. 7 are perspective views of forming a
bonding pad 26 on asemiconductor wafer 20 according to the present invention. Thebonding pad 26 is used for electrically connecting integrated circuits on thesemiconductor wafer 20 with external circuits. In FIG. 3, a uniform silicon dioxide (SiO2)layer 21 is formed on thesemiconductor wafer 20, and photolithographic and etching processes are then performed to remove thesilicon dioxide layer 21 outside of a predetermined area. This forms a firstdielectric layer 22 as shown in FIG. 4. - Then, a flouride silicate glass (FSG)
layer 23 is uniformly deposited on thesemiconductor wafer 20 as shown in FIG. 5 followed by performing a chemical mechanical polishing (CMP) process to remove all the flouride silicate glass (FSG) in the predetermined area on the firstdielectric layer 22. A seconddielectric layer 24 is thus formed in close approximation to the sides of the firstdielectric layer 22 as shown in FIG. 6. The dielectric constant and the degree of the hardness of the firstdielectric layer 22 are both greater than those of the seconddielectric layer 24. - The
bonding pad 26 is formed on the firstdielectric layer 22 at the same time the last layer of metal interconnects of the seconddielectric layer 24 is prepared. As shown in FIG. 7, thebonding pad 26 comprises a titanium (Ti) glue layer 28 as its bottom layer, analuminum alloy layer 30 on top of the glue layer 28, and a titanium nitride (TiN)anti-reflection layer 32 on top of thealuminum alloy layer 30. Thealuminum alloy layer 30 is formed of aluminum and copper with more than 95% aluminum by weight. Thealuminum alloy layer 30 can be made of aluminum (Al) copper (Cu) or alloy of aluminum. - In summary, the
semiconductor wafer 20 formed by the method of the present invention comprises a firstdielectric layer 22 in a predetermined area on thesemiconductor wafer 20, a seconddielectric layer 24 outside the predetermined area of the surface of thewafer 20 and abonding pad 26 formed on the first dielectric layer 22 (FIG. 7). The firstdielectric layer 22 is formed of silicon dioxide, the seconddielectric layer 24 is formed of flouride silicate glass (FSG). The firstdielectric layer 22 is harder and more durable than thedielectric layer 12 under thebonding pad 14 of the prior art. As such, the present inventiondielectric layer 22 can withstand the stress exerted when connecting themetallic wire 18 with external circuits. This prevents peeling off of thebonding pad 26 from thedielectric layer 22. - Please refer to FIG. 8 and FIG. 9. FIG. 8 and FIG. 9 are perspective views of packaging a
chip 80 cut from thewafer 20. The manufacturing method for the bonding pad may also be used in “flip chip” processing. In this scheme, thechip 80 is cut from thesemiconductor wafer 20. In the first step, ametallic lump 42 is formed on thebonding pad 26 of thechip 80 as shown in FIG. 8. Then, thechip 80 is turned upside-down so that the meltedmetallic bump 42 contacts abaseplate 40. Thechip 80 is then fixed to thebaseplate 40 by solidifying themetallic lump 42. Next,liquid epoxy 44 is injected into the gap between thechip 80 and thebaseplate 40 followed by solidifying theepoxy 44 by baking, as shown in FIG. 9. Internal stress occurs during baking of theepoxy 44 due to differences of the expansion coefficients of thechip 80,epoxy 44 andbaseplate 40. Depite this, thebonding pad 26 can withstand the stress due to the increased hardness of the firstdielectric layer 22. Therefore, peeling or rupture of the interface between thebonding pad 26 and the firstdielectric layer 22 is prevented. - In contrast to the prior art process of forming the bonding pad, the first dielectric layer under the bonding pad in present invention has increased hardness. The second dielectric layer, formed in areas not occupied by the first dielectric layer, has a lower dielectric constant. With the increased hardness of the first dielectric layer, the bonding pad can be more firmly bonded to the surface of the semiconductor chip and peeling can be prevented. Furthermore, The speed of signal transmission is not affected because the dielectric constant of the second dielectric layer is low.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (9)
1. A semiconductor chip comprising:
a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip;
a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer; and
a bonding pad positioned on the first dielectric layer for electrically connecting an integrated circuit (IC) in the semiconductor chip with an external circuit.
2. The semiconductor chip of wherein the method of forming the first dielectric layer comprises:
claim 1
forming a uniform dielectric layer by using a first dielectric material on the surface of the semiconductor chip; and
performing photolithographic and etching processes to remove the first dielectric material outside of the predetermined area to form the first dielectric layer.
3. The semiconductor chip of wherein the method of forming the second dielectric layer comprises:
claim 1
forming a uniform dielectric layer by using a second dielectric material on the surface of the semiconductor chip and the first dielectric layer; and
removing the second dielectric material from the surface of the first dielectric layer in the predetermined area to form the second dielectric layer outside the first dielectric layer.
4. The semiconductor chip of wherein the second dielectric material is removed from the surface of the first dielectric layer by performing a chemical mechanical polishing process.
claim 3
5. The semiconductor chip of wherein the dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.
claim 1
6. The semiconductor chip of wherein the first dielectric layer is formed of silicon dioxide, and the second dielectric layer is formed of fluoride silicate glass (FSG).
claim 1
7. The semiconductor chip of wherein the bonding pad is a metallic layer formed of aluminum (Al), copper (Cu) or alloy of aluminum.
claim 1
8. The semiconductor chip of wherein the alloy is formed of aluminum and copper with more than 95% of aluminum by weight.
claim 7
9. The semiconductor chip of wherein the bonding pad comprises a glue layer formed of titanium (Ti) positioned on the surface of the first dielectric layer, an aluminum alloy layer positioned on the glue layer, and an anti-reflection layer formed of titanium nitride (TiN) positioned on the aluminum alloy layer.
claim 1
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/800,574 US6388326B2 (en) | 1999-04-19 | 2001-03-08 | Bonding pad on a semiconductor chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/293,963 US6372621B1 (en) | 1999-04-19 | 1999-04-19 | Method of forming a bonding pad on a semiconductor chip |
US09/800,574 US6388326B2 (en) | 1999-04-19 | 2001-03-08 | Bonding pad on a semiconductor chip |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/293,963 Division US6372621B1 (en) | 1999-04-19 | 1999-04-19 | Method of forming a bonding pad on a semiconductor chip |
Publications (2)
Publication Number | Publication Date |
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US20010009297A1 true US20010009297A1 (en) | 2001-07-26 |
US6388326B2 US6388326B2 (en) | 2002-05-14 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/293,963 Expired - Fee Related US6372621B1 (en) | 1999-04-19 | 1999-04-19 | Method of forming a bonding pad on a semiconductor chip |
US09/800,574 Expired - Fee Related US6388326B2 (en) | 1999-04-19 | 2001-03-08 | Bonding pad on a semiconductor chip |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/293,963 Expired - Fee Related US6372621B1 (en) | 1999-04-19 | 1999-04-19 | Method of forming a bonding pad on a semiconductor chip |
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US (2) | US6372621B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070145604A1 (en) * | 2005-12-22 | 2007-06-28 | Advanced Semiconductor Engineering, Inc. | Chip structure and chip manufacturing process |
US20080197353A1 (en) * | 2007-02-21 | 2008-08-21 | Fujitsu Limited | Semiconductor device for which electrical test is performed while probe is in contact with conductive pad |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6737931B2 (en) | 2002-07-19 | 2004-05-18 | Agilent Technologies, Inc. | Device interconnects and methods of making the same |
JP3981089B2 (en) | 2004-02-18 | 2007-09-26 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4723197A (en) * | 1985-12-16 | 1988-02-02 | National Semiconductor Corporation | Bonding pad interconnection structure |
JPH077783B2 (en) * | 1988-03-18 | 1995-01-30 | 株式会社東芝 | Semiconductor device in which fine metal wires made of copper or copper alloy are arranged in electrical connection parts |
US5100503A (en) * | 1990-09-14 | 1992-03-31 | Ncr Corporation | Silica-based anti-reflective planarizing layer |
EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
US5795495A (en) * | 1994-04-25 | 1998-08-18 | Micron Technology, Inc. | Method of chemical mechanical polishing for dielectric layers |
US5661082A (en) * | 1995-01-20 | 1997-08-26 | Motorola, Inc. | Process for forming a semiconductor device having a bond pad |
US6317974B1 (en) * | 1997-10-09 | 2001-11-20 | Tessera, Inc. | Methods for creating wear resistant contact edges |
US6143638A (en) * | 1997-12-31 | 2000-11-07 | Intel Corporation | Passivation structure and its method of fabrication |
TW396524B (en) * | 1998-06-26 | 2000-07-01 | United Microelectronics Corp | A method for fabricating dual damascene |
US6086777A (en) * | 1998-07-02 | 2000-07-11 | Advanced Micro Devices, Inc. | Tantalum barrier metal removal by using CF4 /o2 plasma dry etch |
US6232238B1 (en) * | 1999-02-08 | 2001-05-15 | United Microelectronics Corp. | Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer |
-
1999
- 1999-04-19 US US09/293,963 patent/US6372621B1/en not_active Expired - Fee Related
-
2001
- 2001-03-08 US US09/800,574 patent/US6388326B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070145604A1 (en) * | 2005-12-22 | 2007-06-28 | Advanced Semiconductor Engineering, Inc. | Chip structure and chip manufacturing process |
US20080197353A1 (en) * | 2007-02-21 | 2008-08-21 | Fujitsu Limited | Semiconductor device for which electrical test is performed while probe is in contact with conductive pad |
Also Published As
Publication number | Publication date |
---|---|
US6388326B2 (en) | 2002-05-14 |
US6372621B1 (en) | 2002-04-16 |
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