US20010008685A1 - Method for forming a gold plating electrode a substrate based on the electrode forming method ,and a wire bonding method utilizing this electrode forming method. - Google Patents

Method for forming a gold plating electrode a substrate based on the electrode forming method ,and a wire bonding method utilizing this electrode forming method. Download PDF

Info

Publication number
US20010008685A1
US20010008685A1 US09/052,979 US5297998A US2001008685A1 US 20010008685 A1 US20010008685 A1 US 20010008685A1 US 5297998 A US5297998 A US 5297998A US 2001008685 A1 US2001008685 A1 US 2001008685A1
Authority
US
United States
Prior art keywords
gold layer
gold
electrode
substrate
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/052,979
Other versions
US6331347B2 (en
Inventor
Hiroshi Haji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/052,979 priority Critical patent/US6331347B2/en
Publication of US20010008685A1 publication Critical patent/US20010008685A1/en
Application granted granted Critical
Publication of US6331347B2 publication Critical patent/US6331347B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00Stock material or miscellaneous articles
    • Y10S428/901Printed circuit
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771Transition metal-base component
    • Y10T428/12861Group VIII or IB metal-base component
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771Transition metal-base component
    • Y10T428/12861Group VIII or IB metal-base component
    • Y10T428/12868Group IB metal-base component alternative to platinum group metal-base component [e.g., precious metal, etc.]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771Transition metal-base component
    • Y10T428/12861Group VIII or IB metal-base component
    • Y10T428/12889Au-base component
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771Transition metal-base component
    • Y10T428/12861Group VIII or IB metal-base component
    • Y10T428/12903Cu-base component
    • Y10T428/1291Next to Co-, Cu-, or Ni-base component
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • the present invention generally relates to a method for forming a gold plating electrode, a substrate based on the gold plating electrode forming method, and a wire bonding method utilizing the gold plating electrode forming method.
  • gold plating is used to form an electrode on a glass epoxy substrate and thus formed electrode is electrically connect with a chip through bonding of a wire.
  • gold plating must provide sufficient bondability, such as bonding strength, to a ball formed at a distal end of the wire.
  • the thickness of a gold layer formed by the gold plating needs to be as thick as 300 nanometer or more.
  • a principal object of the present invention is to provide a method for forming a novel and excellent gold plating electrode assuring sufficient bondability without requiring long processing time and expensive manufacturing costs, and to provide a substrate based on the above gold plating electrode forming method, and a wire bonding method utilizing this gold plating electrode forming method.
  • a first aspect of the present invention provides a novel and excellent method for forming a gold plating electrode comprising: a step of forming a circuit pattern on a substrate; a step of forming a nickel-containing barrier metal layer at a portion where an electrode of the circuit pattern is formed; a step of forming a gold layer on the barrier metal layer by plating; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone; and a step of removing the surface zone containing the nickel compound off the gold layer so as to expose a purified surface of the inside zone of the gold layer.
  • the surface zone containing the nickel compound is removed off by etching. It is preferable that the surface zone containing the nickel compound is removed off by a thickness of 3 to 10 nanometer.
  • the substrate is heated at a temperature of 150 to 200 centigrade for 5 to 60 minutes.
  • the gold layer is formed by plating so as to have a thickness in the range of 5 to 100 nanometer.
  • a second aspect of the present invention provides a substrate comprising: a circuit pattern formed on a surface of the substrate; a nickel-containing barrier metal layer formed at a portion where an electrode of the circuit pattern is formed; a gold layer formed on the barrier metal layer by plating, wherein the substrate is heated up to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer so that the fineness of a remaining part of the gold layer is enhanced at at least an inside zone immediately below the surface zone, and the surface zone containing the nickel compound is removed off so as to expose a purified surface of the inside zone of the gold layer.
  • a third aspect of the present invention provides a wire bonding method comprising: a step of forming a circuit pattern on a substrate, forming a nickel-containing barrier metal layer at a portion where an electrode of the circuit pattern is formed, and forming a gold layer on the barrier metal layer by plating, thereby forming an electrode on the substrate; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone; a step of removing the surface zone containing the nickel compound off the gold layer by etching to expose a purified surface of the inside zone of the gold layer; a step of applying an adhesive material on the substrate and die bonding a chip on the adhesive material; and a step of connecting an electrode of the chip to the electrode of the substrate via an electrically conductive wire.
  • a circuit pattern which is preferably a copper foil, is formed on a substrate.
  • a nickel-containing barrier metal layer is formed on the copper foil.
  • a gold layer is formed on the barrier metal layer by plating.
  • the substrate is heated up to cause nickel contained in the gold layer to move or shift toward a surface zone of the gold layer, so that nickel compound can be deposited or collected in the surface zone of the gold layer and, as a result, the fineness of the remaining part of the gold layer can be enhanced at at least the inside zone immediately below the surface zone.
  • FIG. 1A is a view showing a circuit pattern forming process of the electrode forming method in accordance with one embodiment of the present invention
  • FIG. 1B is a view showing a barrier metal layer forming process of the electrode forming method in accordance with one embodiment of the present invention
  • FIG. 1C is a view showing a gold layer forming process of the electrode forming method in accordance with one embodiment of the present invention
  • FIG. 1D is a view showing a before-heating condition of the electrode forming method in accordance with one embodiment of the present invention
  • FIG. 1E is a view showing an after-heating condition of the electrode forming method in accordance with one embodiment of the present invention.
  • FIG. 1F is a view showing a finally obtained electrode in accordance with one embodiment of the present invention.
  • FIG. 2 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained immediately after the formation of the gold plating electrode, in accordance with the one embodiment of the present invention
  • FIG. 3 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained after the heating operation, in accordance with the one embodiment of the present invention.
  • FIG. 4 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained after removal of nickel or nickel compound crowded in the surface zone, in accordance with the one embodiment of the present invention
  • FIG. 5 is a graph showing the ratio of nickel to gold in the gold plating electrode in accordance with the one embodiment of the present invention.
  • FIG. 6A is a view showing a bond applying step of an electronic component manufacturing method in accordance with the one embodiment of the present invention.
  • FIG. 6B is a view showing a chip mounting step of the electronic component manufacturing method in accordance with the one embodiment of the present invention.
  • FIG. 6C is a view showing a heating step of the electronic component manufacturing method in accordance with the one embodiment of the present invention.
  • FIG. 6D is a view showing a wire bonding step of the electronic component manufacturing method in accordance with the one embodiment of the present invention.
  • FIG. 6E is a view showing a sealing step of the electronic component manufacturing method in accordance with the one embodiment of the present invention.
  • FIGS. 2 through 4 are graphs showing Auger spectrum intensity of a surface zone of a gold plating electrode in accordance with one embodiment of the present invention.
  • FIG. 2 shows Auger spectrum intensity of the surface zone of a gold layer which is obtained immediately after a gold plating electrode is formed on a nickel-containing barrier metal layer by the electroless substitution plating.
  • a copper foil constituting a circuit pattern is formed on a substrate and the nickel-containing barrier metal layer is formed on this copper foil.
  • FIG. 2 it is found that a waveform A 1 indicating the presence of nickel or nickel compound clearly appears even immediately after the formation of gold plating.
  • FIG. 3 is Auger spectrum intensity obtained immediately after the substrate showed the Auger spectrum intensity of FIG. 2 is heated at 150° C. for 30 minutes.
  • a gold plating electrode is formed. Thereafter, an adhesive material is applied on the substrate, and a chip is die bonded thereon. Then, the substrate is heated under the conditions similar to the above-described conditions to harden the adhesive material and securely fix the chip on the substrate. Subsequently, the wire bonding operation is performed on the substrate.
  • the substrate having just finished the heating operation is in the same circumstances as the substrate to be immediately carried out the wire bonding operation thereon.
  • waveform A 2 indicating the presence of nickel or nickel compound has a large amplitude compared with the waveform A 1 of FIG. 2.
  • the amplitude difference between waveforms A 1 and A 2 proves the fact that nickel or nickel compound is deposited or collected in the surface zone of the gold layer in a concentrated manner by the heating operation performed before the wire bonding operation.
  • the inventor of the present application has tested the wire bonding formed on the gold plating electrode, (1) immediately after the gold plating electrode is formed and (2) immediately after the heating operation is performed, separately. According to the result of these trials, the resultant bonding is not satisfactory in the former case and too bad in the latter case.
  • FIG. 4 shows Auger spectrum intensity obtained after the surface zone of the gold layer showed the Auger spectrum intensity of FIG. 3 is removed off by a thickness of 5 nanometer by etching.
  • a resultant waveform A 3 indicates that nickel or nickel compound is no longer included. From the comparison between FIGS. 2 and 4, it is found that the removal of the surface zone is effective to enhance the fineness of gold enhance at the region slightly deeper than the surface zone, when it is compared with the fineness obtained immediately after the gold plating is formed.
  • the inventor of the present application has tested a wire bonding on the gold plating electrode after the surface zone containing nickel or nickel compound therein is removed off. According to the test result, an excellent bondability was attained. From this fact, it is confirmed that nickel or nickel compound concentrated in the surface zone of the gold layer worsened the bondability to the wire. In other words, by removing the nickel or nickel compound concentrated in the surface zone of the gold layer, it becomes possible to expose the highly purified gold layer located under the surface zone and improve the bondability to the wire. Moreover, a detailed study on binding energy revealed that the nickel compound crowded in the surface zone of the gold layer chiefly comprised Ni(OH) 2 , Ni 2 O 3 and NiO.
  • FIG. 5 shows the ratio of nickel to gold in each process of the gold plating electrode formation.
  • the inventor of the present application has conducted experiments on three kinds of gold layers, a 10-nanometer-thick gold layer (indicated by triangular marks), a 50-nanometer-thick gold layer (indicated by circular marks) and a 100-nanometer-thick gold layer (indicated by rectangular marks).
  • the ratio of nickel to gold in the surface zone of the gold layer is explicitly increased by the heating operation which is started immediately after finishing the plating under the above-described conditions.
  • the ratio of nickel to gold is extremely lowered after the surface zone containing the concentrated nickel or nickel compound is removed off the gold layer by etching.
  • the ratio of nickel to gold does not cause a substantial increase and thus remains at lower values. That is, removing the nickel or nickel compound concentrated in the surface zone from the gold layer by etching makes it possible to maintain an exposed surface having a higher ratio of gold even if the gold layer is later subjected to a continuous heating operation.
  • an excellent gold plating electrode can be fabricated by plating a gold layer at a thickness (for example, less than 100 nanometer) smaller than the plating thickness (300 nanometer or more) of a conventionally required gold layer. More specifically, a gold plating electrode is formed by plating (for example, by the electroless substitution plating), and is heated.. And then, the surface zone is removed off the main part of the gold layer by etching. Once the surface zone is removed off, the ratio of nickel to gold is no longer increased even if the gold layer is continuously heated, maintaining a higher fineness of gold at the exposed surface of the gold layer.
  • the inventor of the present application has reached the inventive concept to be realized as a method for forming a gold plating electrode and a related substrate based on this forming method.
  • FIGS. 1A to 1 F are views illustrating respective processes of the gold plating electrode forming method in accordance with one embodiment of the present invention.
  • a circuit pattern 2 a is formed on a surface of a substrate 1 using a copper foil having a thickness of 18 to 35 micrometer.
  • a nickel-containing barrier metal layer 2 b having a thickness of 3 to 5 micrometer is formed on the circuit pattern 2 a at a portion serving as an electrode.
  • a gold layer 2 c having a thickness of 10 to 100 nanometer is formed on the barrier metal layer 2 b by the electroless substitution plating (so-called flash plating).
  • the gold layer 2 c contains nickel or nickel compound which was originally contained in the barrier metal layer 2 b.
  • the electroless substitution plating used in this embodiment to form gold layer 2 c can be replaced by any other plating method, such as electro plating.
  • the electro plating is not desirable in that fine and complicated wiring is required and this fine and complicated wiring may interfere with the inherently required wiring of the circuit pattern or may cause undesirable antenna effects. Thus, it is recommendable to use the electroless substitution plating.
  • substrate 1 is heated, for example, at 150° C. for 30 minutes.
  • nickel or nickel compound existing in the gold layer 2 c moves toward and is deposited in a concentrated manner in the surface zone of the gold layer 2 c .
  • the surface zone is removed off the gold layer 2 c by a thickness of 3 to 10 nanometer, for example 5 nanometer, by etching.
  • etching Through this etching operation, almost all of nickel or nickel compound crowded near the surface of the gold layer 2 c can be removed off together with the surface zone.
  • an exposed surface of gold layer 2 c is a highly purified gold surface. Dry etching will be preferably used for the etching in this embodiment; however, it is needless to say that wet etching can be equivalently used.
  • substrate 1 is entered in and heated by a cure apparatus.
  • the ratio of nickel to gold is not substantially increased through this heating operation.
  • bondability can be maintained at satisfactory values.
  • the present invention is explained based on the above-described embodiment, it is possible to add various modifications to the above-described embodiments.
  • the above-described heating operation performed after the formation of gold layer 2 c on the barrier metal layer 2 b it will be desirable to set the heating temperature somewhere in the range of 150 to 200° C. and to set the heating time somewhere in the range of 5 to 60 minutes.
  • the substrate 1 can be replaced by a substrate made of other material, such as a ceramic substrate.
  • the present invention provides a method for forming a gold plating electrode comprising: a step of forming a circuit pattern on a substrate; a step of forming a nickel-containing barrier metal layer on the circuit pattern; a step of forming a gold layer on the barrier metal layer by plating; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone and depositing nickel or nickel compound in the surface zone of the gold layer; and a step of removing the surface zone containing the crowded nickel or nickel compound off the gold layer so as to expose a purified surface of the inside zone of the gold layer. Therefore, it becomes possible to form an excellent electrode having a satisfactory bondability to the wire by using a less amount of gold at low costs.

Abstract

A circuit pattern 2a, made of copper foil, is arranged on a substrate 1. A nickel-containing barrier metal layer 2b is formed on the circuit pattern 2a. A gold layer 2c is formed on the barrier metal layer 2b by electroless substitution plating. Then, substrate 1 is heated up to impel nickel contained in the gold layer 2c to move toward a surface zone of the gold layer 2c to deposit nickel compound in the surface zone of the gold layer 2c, thereby enhancing the fineness of a remaining part of the gold layer 2c at at least an inside zone immediately below the surface zone. Then, the surface zone containing the crowded nickel compound is removed off the gold layer 2c so as to expose a purified surface of the inside zone of the gold layer 2c. Therefore, it becomes possible to form an excellent electrode having satisfactory bondability to the wire by using a less amount of gold at low costs.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention generally relates to a method for forming a gold plating electrode, a substrate based on the gold plating electrode forming method, and a wire bonding method utilizing the gold plating electrode forming method. [0002]
  • 2. Prior Art [0003]
  • According to conventional technologies, it has been well known that gold plating is used to form an electrode on a glass epoxy substrate and thus formed electrode is electrically connect with a chip through bonding of a wire. In this case, gold plating must provide sufficient bondability, such as bonding strength, to a ball formed at a distal end of the wire. [0004]
  • From numerous experiences, it has been conventionally believed that the thickness of a gold layer formed by the gold plating needs to be as thick as 300 nanometer or more. To this end, it was usual to utilize the electro plating or electroless reduction plating to form a gold layer being sufficiently thick. [0005]
  • However, as well known to artisans, it takes an extremely long time until a growing gold layer reaches a required thickness when the gold layer is formed by the electro plating or electroless substitution plating, and the manufacturing cost must be expensive. [0006]
  • SUMMARY OF THE INVENTION
  • Accordingly, in view of above-described problems encountered in the prior art, a principal object of the present invention-is to provide a method for forming a novel and excellent gold plating electrode assuring sufficient bondability without requiring long processing time and expensive manufacturing costs, and to provide a substrate based on the above gold plating electrode forming method, and a wire bonding method utilizing this gold plating electrode forming method. [0007]
  • In order to accomplish this and other related objects, a first aspect of the present invention provides a novel and excellent method for forming a gold plating electrode comprising: a step of forming a circuit pattern on a substrate; a step of forming a nickel-containing barrier metal layer at a portion where an electrode of the circuit pattern is formed; a step of forming a gold layer on the barrier metal layer by plating; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone; and a step of removing the surface zone containing the nickel compound off the gold layer so as to expose a purified surface of the inside zone of the gold layer. [0008]
  • According to features of the preferred embodiments, the surface zone containing the nickel compound is removed off by etching. It is preferable that the surface zone containing the nickel compound is removed off by a thickness of 3 to 10 nanometer. The substrate is heated at a temperature of 150 to 200 centigrade for 5 to 60 minutes. The gold layer is formed by plating so as to have a thickness in the range of 5 to 100 nanometer. [0009]
  • A second aspect of the present invention provides a substrate comprising: a circuit pattern formed on a surface of the substrate; a nickel-containing barrier metal layer formed at a portion where an electrode of the circuit pattern is formed; a gold layer formed on the barrier metal layer by plating, wherein the substrate is heated up to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer so that the fineness of a remaining part of the gold layer is enhanced at at least an inside zone immediately below the surface zone, and the surface zone containing the nickel compound is removed off so as to expose a purified surface of the inside zone of the gold layer. [0010]
  • Furthermore, a third aspect of the present invention provides a wire bonding method comprising: a step of forming a circuit pattern on a substrate, forming a nickel-containing barrier metal layer at a portion where an electrode of the circuit pattern is formed, and forming a gold layer on the barrier metal layer by plating, thereby forming an electrode on the substrate; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer to deposit nickel compound in the surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone; a step of removing the surface zone containing the nickel compound off the gold layer by etching to expose a purified surface of the inside zone of the gold layer; a step of applying an adhesive material on the substrate and die bonding a chip on the adhesive material; and a step of connecting an electrode of the chip to the electrode of the substrate via an electrically conductive wire. [0011]
  • According to this novel and excellent gold plating electrode method. A circuit pattern, which is preferably a copper foil, is formed on a substrate. Next, a nickel-containing barrier metal layer is formed on the copper foil. Then, a gold layer is formed on the barrier metal layer by plating. Thereafter, the substrate is heated up to cause nickel contained in the gold layer to move or shift toward a surface zone of the gold layer, so that nickel compound can be deposited or collected in the surface zone of the gold layer and, as a result, the fineness of the remaining part of the gold layer can be enhanced at at least the inside zone immediately below the surface zone. [0012]
  • Through experiments conducted by an inventor of the present application, it was confirmed that nickel had surely moved from the barrier metal layer into the gold layer even immediately after the gold layer was formed by plating. Furthermore, it was confirmed that heating the substrate promoted or impelled the nickel in the gold layer to move into and deposit as nickel compound in the surface zone, enhancing the fineness of the gold layer at least the inside zone immediately below the surface zone to be sufficiently high to assure a satisfactory bondability to the wire. Accordingly, by removing the nickel compound crowded in the surface zone off the gold layer, it becomes possible to form an excellent gold electrode having high fineness and assuring a satisfactory bondability to the wire. [0013]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description which is to be read in conjunction with the accompanying drawings, in which: [0014]
  • FIG. 1A is a view showing a circuit pattern forming process of the electrode forming method in accordance with one embodiment of the present invention; [0015]
  • FIG. 1B is a view showing a barrier metal layer forming process of the electrode forming method in accordance with one embodiment of the present invention; [0016]
  • FIG. 1C is a view showing a gold layer forming process of the electrode forming method in accordance with one embodiment of the present invention; [0017]
  • FIG. 1D is a view showing a before-heating condition of the electrode forming method in accordance with one embodiment of the present invention; [0018]
  • FIG. 1E is a view showing an after-heating condition of the electrode forming method in accordance with one embodiment of the present invention; [0019]
  • FIG. 1F is a view showing a finally obtained electrode in accordance with one embodiment of the present invention; [0020]
  • FIG. 2 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained immediately after the formation of the gold plating electrode, in accordance with the one embodiment of the present invention; [0021]
  • FIG. 3 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained after the heating operation, in accordance with the one embodiment of the present invention; [0022]
  • FIG. 4 is a graph showing Auger spectrum intensity of the surface zone of the gold plating electrode, obtained after removal of nickel or nickel compound crowded in the surface zone, in accordance with the one embodiment of the present invention; [0023]
  • FIG. 5 is a graph showing the ratio of nickel to gold in the gold plating electrode in accordance with the one embodiment of the present invention; [0024]
  • FIG. 6A is a view showing a bond applying step of an electronic component manufacturing method in accordance with the one embodiment of the present invention; [0025]
  • FIG. 6B is a view showing a chip mounting step of the electronic component manufacturing method in accordance with the one embodiment of the present invention; [0026]
  • FIG. 6C is a view showing a heating step of the electronic component manufacturing method in accordance with the one embodiment of the present invention; [0027]
  • FIG. 6D is a view showing a wire bonding step of the electronic component manufacturing method in accordance with the one embodiment of the present invention; and [0028]
  • FIG. 6E is a view showing a sealing step of the electronic component manufacturing method in accordance with the one embodiment of the present invention. [0029]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Preferred embodiments of the present invention will be explained in greater detail hereinafter, with reference to the accompanying drawings. Identical parts are denoted by an identical reference numeral throughout views. [0030]
  • Prior to detailed explanation of steps consisting of a gold plating electrode forming method in accordance with one embodiment of the present invention, result of experiments conducted by the inventor of the present application will be first explained since it is believed that these experimental results will make clear the problem (i.e. insufficient bondability) of a conventional gold electrode formed by the electroless substitution plating. [0031]
  • FIGS. 2 through 4 are graphs showing Auger spectrum intensity of a surface zone of a gold plating electrode in accordance with one embodiment of the present invention. FIG. 2 shows Auger spectrum intensity of the surface zone of a gold layer which is obtained immediately after a gold plating electrode is formed on a nickel-containing barrier metal layer by the electroless substitution plating. In this case, a copper foil constituting a circuit pattern is formed on a substrate and the nickel-containing barrier metal layer is formed on this copper foil. According to the result of FIG. 2, it is found that a waveform A[0032] 1 indicating the presence of nickel or nickel compound clearly appears even immediately after the formation of gold plating.
  • Next, FIG. 3 is Auger spectrum intensity obtained immediately after the substrate showed the Auger spectrum intensity of FIG. 2 is heated at 150° C. for 30 minutes. [0033]
  • Here, the processing of the substrate conducted before and after the wire bonding operation will be explained briefly. First of all, a gold plating electrode is formed. Thereafter, an adhesive material is applied on the substrate, and a chip is die bonded thereon. Then, the substrate is heated under the conditions similar to the above-described conditions to harden the adhesive material and securely fix the chip on the substrate. Subsequently, the wire bonding operation is performed on the substrate. [0034]
  • Accordingly, the substrate having just finished the heating operation is in the same circumstances as the substrate to be immediately carried out the wire bonding operation thereon. [0035]
  • As shown in FIG. 3, it is understood that the waveform A[0036] 2 indicating the presence of nickel or nickel compound has a large amplitude compared with the waveform A1 of FIG. 2. The amplitude difference between waveforms A1 and A2 proves the fact that nickel or nickel compound is deposited or collected in the surface zone of the gold layer in a concentrated manner by the heating operation performed before the wire bonding operation.
  • The inventor of the present application has tested the wire bonding formed on the gold plating electrode, (1) immediately after the gold plating electrode is formed and (2) immediately after the heating operation is performed, separately. According to the result of these trials, the resultant bonding is not satisfactory in the former case and too bad in the latter case. [0037]
  • Furthermore, the inventor of the present application has investigated the condition of the gold plating electrode after the heating operation is finished. Still further, FIG. 4 shows Auger spectrum intensity obtained after the surface zone of the gold layer showed the Auger spectrum intensity of FIG. 3 is removed off by a thickness of 5 nanometer by etching. [0038]
  • As apparent from FIG. 4, a resultant waveform A[0039] 3 indicates that nickel or nickel compound is no longer included. From the comparison between FIGS. 2 and 4, it is found that the removal of the surface zone is effective to enhance the fineness of gold enhance at the region slightly deeper than the surface zone, when it is compared with the fineness obtained immediately after the gold plating is formed.
  • From the foregoing, it is concluded that the above-described heating operation is effective to deposit or collect almost all of nickel or nickel compound involved in the gold plating electrode into the surface zone in a concentrated or crowded manner. Hence, the fineness of gold can be enhanced in the inside zone of the gold layer deeper than the surface zone. [0040]
  • Furthermore, the inventor of the present application has tested a wire bonding on the gold plating electrode after the surface zone containing nickel or nickel compound therein is removed off. According to the test result, an excellent bondability was attained. From this fact, it is confirmed that nickel or nickel compound concentrated in the surface zone of the gold layer worsened the bondability to the wire. In other words, by removing the nickel or nickel compound concentrated in the surface zone of the gold layer, it becomes possible to expose the highly purified gold layer located under the surface zone and improve the bondability to the wire. Moreover, a detailed study on binding energy revealed that the nickel compound crowded in the surface zone of the gold layer chiefly comprised Ni(OH)[0041] 2, Ni2O3 and NiO.
  • FIG. 5 shows the ratio of nickel to gold in each process of the gold plating electrode formation. The inventor of the present application has conducted experiments on three kinds of gold layers, a 10-nanometer-thick gold layer (indicated by triangular marks), a 50-nanometer-thick gold layer (indicated by circular marks) and a 100-nanometer-thick gold layer (indicated by rectangular marks). [0042]
  • As shown in FIG. 5, the ratio of nickel to gold in the surface zone of the gold layer is explicitly increased by the heating operation which is started immediately after finishing the plating under the above-described conditions. On the other hand, the ratio of nickel to gold is extremely lowered after the surface zone containing the concentrated nickel or nickel compound is removed off the gold layer by etching. [0043]
  • Thereafter, even if the gold layer is heated continuously at 130° C., the ratio of nickel to gold does not cause a substantial increase and thus remains at lower values. That is, removing the nickel or nickel compound concentrated in the surface zone from the gold layer by etching makes it possible to maintain an exposed surface having a higher ratio of gold even if the gold layer is later subjected to a continuous heating operation. [0044]
  • Similar results are preferably obtained on any gold layer when its thickness is somewhere between 10 to 100 nanometer. These results show a remarkable progress compared with a conventional gold plating electrode forming method when such a conventional method needs a gold layer having a thickness of 300 nanometer or more which requires a significant long time and expensive costs to form. [0045]
  • As apparent from the foregoing description, it is confirmed that an excellent gold plating electrode can be fabricated by plating a gold layer at a thickness (for example, less than 100 nanometer) smaller than the plating thickness (300 nanometer or more) of a conventionally required gold layer. More specifically, a gold plating electrode is formed by plating (for example, by the electroless substitution plating), and is heated.. And then, the surface zone is removed off the main part of the gold layer by etching. Once the surface zone is removed off, the ratio of nickel to gold is no longer increased even if the gold layer is continuously heated, maintaining a higher fineness of gold at the exposed surface of the gold layer. [0046]
  • Taking the above-described experimental results into consideration, the inventor of the present application has reached the inventive concept to be realized as a method for forming a gold plating electrode and a related substrate based on this forming method. [0047]
  • FIGS. 1A to [0048] 1F are views illustrating respective processes of the gold plating electrode forming method in accordance with one embodiment of the present invention.
  • First of all, as illustrated in FIG. 1A, a [0049] circuit pattern 2 a is formed on a surface of a substrate 1 using a copper foil having a thickness of 18 to 35 micrometer. Next, as illustrated in FIG. 1B, a nickel-containing barrier metal layer 2 b having a thickness of 3 to 5 micrometer is formed on the circuit pattern 2 a at a portion serving as an electrode.
  • Next, as illustrated in FIG. 1C, a [0050] gold layer 2 c having a thickness of 10 to 100 nanometer is formed on the barrier metal layer 2 b by the electroless substitution plating (so-called flash plating). In this case, as illustrated in FIG. 1D, the gold layer 2 c contains nickel or nickel compound which was originally contained in the barrier metal layer 2 b.
  • The electroless substitution plating used in this embodiment to form [0051] gold layer 2 c can be replaced by any other plating method, such as electro plating. However, the electro plating is not desirable in that fine and complicated wiring is required and this fine and complicated wiring may interfere with the inherently required wiring of the circuit pattern or may cause undesirable antenna effects. Thus, it is recommendable to use the electroless substitution plating.
  • Next, [0052] substrate 1 is heated, for example, at 150° C. for 30 minutes. Through this heating operation, nickel or nickel compound existing in the gold layer 2 c moves toward and is deposited in a concentrated manner in the surface zone of the gold layer 2 c. Then, as illustrated in FIG. 1F, the surface zone is removed off the gold layer 2 c by a thickness of 3 to 10 nanometer, for example 5 nanometer, by etching. Through this etching operation, almost all of nickel or nickel compound crowded near the surface of the gold layer 2 c can be removed off together with the surface zone. Thus, an exposed surface of gold layer 2 c is a highly purified gold surface. Dry etching will be preferably used for the etching in this embodiment; however, it is needless to say that wet etching can be equivalently used.
  • Next, explained hereinafter with reference to FIGS. 6A through 6E is the processes for forming a wire bonding on the [0053] substrate 1 after the electrode 2 is formed on the substrate 1 in accordance with the present invention.
  • When the highly purified [0054] gold layer 2 c is exposed by removing the surface zone containing the crowded nickel compound off the gold layer 2 c by etching as described above, an adhesive material 3 is applied on the upper surface of substrate 1 between electrodes 2 (refer to FIG. 6A). Then, as illustrated in FIG. 6B, a chip 4 is die bonded on the applied adhesive material 3.
  • Subsequently, as illustrated in FIG. 6C, [0055] substrate 1 is entered in and heated by a cure apparatus. In this case, as explained previously, the ratio of nickel to gold is not substantially increased through this heating operation. Thus, bondability can be maintained at satisfactory values.
  • Next, as illustrated in FIG. 6D, the [0056] chip 4 and adjacent electrodes 2 are bonded via wires 5. Then, as illustrated in FIG. 6E, the assembly of chip 4, wires 5 and electrodes 2 is sealed by resin 6.
  • Although the present invention is explained based on the above-described embodiment, it is possible to add various modifications to the above-described embodiments. For example, regarding the above-described heating operation performed after the formation of [0057] gold layer 2 c on the barrier metal layer 2 b, it will be desirable to set the heating temperature somewhere in the range of 150 to 200° C. and to set the heating time somewhere in the range of 5 to 60 minutes. In summary, it is recommendable to perform the heating operation under the conditions which surely impel nickel contained in the gold layer 2 c to move into the surface zone of the gold layer 2 c. The substrate 1 can be replaced by a substrate made of other material, such as a ceramic substrate.
  • As apparent from the foregoing description, the present invention provides a method for forming a gold plating electrode comprising: a step of forming a circuit pattern on a substrate; a step of forming a nickel-containing barrier metal layer on the circuit pattern; a step of forming a gold layer on the barrier metal layer by plating; a step of heating the substrate to cause nickel contained in the gold layer to move toward a surface zone of the gold layer, thereby enhancing the fineness of a remaining part of the gold layer at at least an inside zone immediately below the surface zone and depositing nickel or nickel compound in the surface zone of the gold layer; and a step of removing the surface zone containing the crowded nickel or nickel compound off the gold layer so as to expose a purified surface of the inside zone of the gold layer. Therefore, it becomes possible to form an excellent electrode having a satisfactory bondability to the wire by using a less amount of gold at low costs. [0058]
  • As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiments as described are therefore intended to be only illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalents of such metes and bounds, are therefore intended to be embraced by the claims. [0059]

Claims (7)

What is claimed is:
1. A method for forming a gold plating electrode comprising:
a step of forming a circuit pattern on a substrate;
a step of forming a nickel-containing barrier metal layer at a portion where an electrode of said circuit pattern is formed;
a step of forming a gold layer on said barrier metal layer by plating;
a step of heating said substrate to cause nickel contained in said gold layer to move toward a surface zone of said gold layer to deposit nickel compound in said surface zone of said gold layer, thereby enhancing the fineness of a remaining part of said gold layer at at least an inside zone immediately below said surface zone; and
a step of removing said surface zone containing said nickel compound off said gold layer so as to expose a purified surface of said inside zone of said gold layer.
2. The method for forming a gold plating electrode defined by
claim 1
, wherein said surface zone containing said nickel compound is removed off by etching.
3. The method for forming a gold plating electrode defined by
claim 1
, wherein said surface zone containing said nickel compound is removed off by a thickness of 3 to 10 nanometer.
4. The method for forming a gold plating electrode defined by
claim 1
, wherein said substrate is heated at a temperature of 150 to 200 centigrade for 5 to 60 minutes.
5. The method for forming a gold plating electrode defined by
claim 1
, wherein said gold layer has a thickness of 5 to 100 nanometer when said gold layer is formed by said plating.
6. A substrate comprising:
a circuit pattern formed on a surface of said substrate;
a nickel-containing barrier metal layer formed at a portion where an electrode of said circuit pattern is formed;
a gold layer formed on said barrier metal layer by plating,
wherein said substrate is heated up to cause nickel contained in said gold layer to move toward a surface zone of said gold layer to deposit nickel compound in said surface zone of said gold layer so that the fineness of a remaining part of said gold layer is enhanced at at least an inside zone immediately below said surface zone, and said surface zone containing said nickel compound is removed off so as to expose a purified surface of said inside zone of said gold layer.
7. A wire bonding method comprising:
a step of forming a circuit pattern on a substrate, forming a nickel-containing barrier metal layer at a portion where an electrode of said circuit pattern is formed, and forming a gold layer on said barrier metal layer by plating, thereby forming an electrode on said substrate;
a step of heating said substrate to cause nickel contained in said gold layer to move toward a surface zone of said gold layer to deposit nickel compound in said surface zone of said gold layer, thereby enhancing the fineness of a remaining part of said gold layer at at least an inside zone immediately below said surface zone;
a step of removing said surface zone containing said nickel compound off said gold layer by etching to expose a purified surface of said inside zone of said gold layer;
a step of applying an adhesive material on said substrate and die bonding a chip on said adhesive material; and
a step of connecting an electrode of said chip to said electrode of said substrate via an electrically conductive wire.
US09/052,979 1995-02-20 1998-04-01 Method for forming a gold plating electrode a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method Expired - Lifetime US6331347B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/052,979 US6331347B2 (en) 1995-02-20 1998-04-01 Method for forming a gold plating electrode a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP7031223A JP3000877B2 (en) 1995-02-20 1995-02-20 Gold plated electrode forming method, substrate and wire bonding method
JP7-31223 1995-02-20
US08/604,072 US5767008A (en) 1995-02-20 1996-02-20 Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method
US09/052,979 US6331347B2 (en) 1995-02-20 1998-04-01 Method for forming a gold plating electrode a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/604,072 Division US5767008A (en) 1995-02-20 1996-02-20 Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method

Publications (2)

Publication Number Publication Date
US20010008685A1 true US20010008685A1 (en) 2001-07-19
US6331347B2 US6331347B2 (en) 2001-12-18

Family

ID=12325438

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/604,072 Expired - Lifetime US5767008A (en) 1995-02-20 1996-02-20 Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method
US09/052,979 Expired - Lifetime US6331347B2 (en) 1995-02-20 1998-04-01 Method for forming a gold plating electrode a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/604,072 Expired - Lifetime US5767008A (en) 1995-02-20 1996-02-20 Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method

Country Status (4)

Country Link
US (2) US5767008A (en)
JP (1) JP3000877B2 (en)
DE (1) DE19606074C2 (en)
GB (1) GB2297981B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040121080A1 (en) * 2002-10-17 2004-06-24 Robert Urscheler Method of producing a coated substrate

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245189B1 (en) 1994-12-05 2001-06-12 Nordson Corporation High Throughput plasma treatment system
JP3000877B2 (en) * 1995-02-20 2000-01-17 松下電器産業株式会社 Gold plated electrode forming method, substrate and wire bonding method
JPH1050751A (en) * 1996-07-30 1998-02-20 Kyocera Corp Method for bonding thin bonding wire
US5909633A (en) * 1996-11-29 1999-06-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronic component
JP3701138B2 (en) * 1999-04-23 2005-09-28 松下電器産業株式会社 Manufacturing method of electronic parts
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
US6972071B1 (en) 1999-07-13 2005-12-06 Nordson Corporation High-speed symmetrical plasma treatment system
JP3251930B2 (en) * 1999-11-02 2002-01-28 日東電工株式会社 Flexible wiring board
US6547946B2 (en) * 2000-04-10 2003-04-15 The Regents Of The University Of California Processing a printed wiring board by single bath electrodeposition
US6709522B1 (en) 2000-07-11 2004-03-23 Nordson Corporation Material handling system and methods for a multichamber plasma treatment system
WO2002031865A1 (en) 2000-10-13 2002-04-18 Emcore Corporation Method of making an electrode
US6841033B2 (en) * 2001-03-21 2005-01-11 Nordson Corporation Material handling system and method for a multi-workpiece plasma treatment system
DE10311031B4 (en) * 2003-03-13 2005-04-21 Siemens Ag Electrochemical sensor and method for its production
US6994918B2 (en) * 2003-08-12 2006-02-07 Johnson Morgan T Selective application of conductive material to circuit boards by pick and place
TWI262041B (en) * 2003-11-14 2006-09-11 Hitachi Chemical Co Ltd Formation method of metal layer on resin layer, printed wiring board, and production method thereof
JP2005244003A (en) * 2004-02-27 2005-09-08 Nitto Denko Corp Wiring circuit board
US7598119B2 (en) * 2007-03-12 2009-10-06 Texas Instruments Incorporated System and method for inhibiting and containing resin bleed-out from adhesive materials used in assembly of semiconductor devices
KR101426038B1 (en) * 2008-11-13 2014-08-01 주식회사 엠디에스 Printed circuit board and method of manufacturing the same
WO2010103941A1 (en) * 2009-03-09 2010-09-16 株式会社村田製作所 Flexible substrate
US8652649B2 (en) 2009-07-10 2014-02-18 Xtalic Corporation Coated articles and methods
US20120328904A1 (en) * 2011-06-23 2012-12-27 Xtalic Corporation Printed circuit boards and related articles including electrodeposited coatings
US8792214B1 (en) 2013-07-23 2014-07-29 Hutchinson Technology Incorporated Electrical contacts to motors in dual stage actuated suspensions

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781596A (en) * 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US4016050A (en) * 1975-05-12 1977-04-05 Bell Telephone Laboratories, Incorporated Conduction system for thin film and hybrid integrated circuits
US4068022A (en) * 1974-12-10 1978-01-10 Western Electric Company, Inc. Methods of strengthening bonds
US4442137A (en) * 1982-03-18 1984-04-10 International Business Machines Corporation Maskless coating of metallurgical features of a dielectric substrate
US4601424A (en) * 1985-05-17 1986-07-22 International Business Machines Corporation Stripped gold plating process
US5302492A (en) * 1989-06-16 1994-04-12 Hewlett-Packard Company Method of manufacturing printing circuit boards
JP2760107B2 (en) * 1989-12-07 1998-05-28 住友電気工業株式会社 Surface structure of ceramic substrate and method of manufacturing the same
JPH04359518A (en) * 1991-06-06 1992-12-11 Nec Corp Manufacture of semiconductor device
US5232873A (en) * 1992-10-13 1993-08-03 At&T Bell Laboratories Method of fabricating contacts for semiconductor devices
WO1994014190A1 (en) * 1992-12-10 1994-06-23 Kabushiki Kaisha Toyota Chuo Kenkyusho Surface structure for soldering and non-flux soldering method using the same
DE69433926T2 (en) * 1993-04-28 2005-07-21 Nichia Corp., Anan A semiconductor device of a gallium nitride III-V semiconductor compound
JP3000877B2 (en) * 1995-02-20 2000-01-17 松下電器産業株式会社 Gold plated electrode forming method, substrate and wire bonding method
US5909633A (en) * 1996-11-29 1999-06-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040121080A1 (en) * 2002-10-17 2004-06-24 Robert Urscheler Method of producing a coated substrate

Also Published As

Publication number Publication date
DE19606074C2 (en) 1998-12-03
GB2297981B (en) 1997-03-05
DE19606074A1 (en) 1996-08-22
GB9603568D0 (en) 1996-04-17
GB2297981A (en) 1996-08-21
US6331347B2 (en) 2001-12-18
US5767008A (en) 1998-06-16
JPH08227911A (en) 1996-09-03
JP3000877B2 (en) 2000-01-17

Similar Documents

Publication Publication Date Title
US6331347B2 (en) Method for forming a gold plating electrode a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method
DE10148120B4 (en) Electronic components with semiconductor chips and a system carrier with component positions and method for producing a system carrier
US6469260B2 (en) Wiring boards, semiconductor devices and their production processes
JP3010525B2 (en) Semiconductor package containing heat sink and surface treatment method of heat sink
KR100989007B1 (en) Semiconductor device and method of manufacturing same
DE102010000407B4 (en) A semiconductor package comprising a metal layer tape and method of making such a semiconductor package
KR20080111397A (en) Electronic device manufacturing method and electronic device
US8110752B2 (en) Wiring substrate and method for manufacturing the same
CN1547875A (en) Audio coding and decoding
US6853060B1 (en) Semiconductor package using a printed circuit board and a method of manufacturing the same
EP2061072A2 (en) Flip chip wafer, flip chip die and manufacturing processes thereof
US6919264B2 (en) Method for the solder-stop structuring of elevations on wafers
TWI228785B (en) Substrate, wiring board, substrate for semiconductor package, semiconductor device, semiconductor package and its manufacturing method
JP3349166B2 (en) Circuit board
US20030164303A1 (en) Method of metal electro-plating for IC package substrate
US6777314B2 (en) Method of forming electrolytic contact pads including layers of copper, nickel, and gold
JP3232959B2 (en) Substrate, substrate manufacturing method and wire bonding method
CN218867097U (en) Semiconductor structure and semiconductor package
JPH0363813B2 (en)
EP4184572A1 (en) Substrate-based package semiconductor device with side wettable flanks
DE102017211058B4 (en) Method for producing an electronic component and electronic component
KR100303354B1 (en) chip size package and method of fabricating the same
JPS60140737A (en) Manufacture of semiconductor device
US8497578B2 (en) Terminal face contact structure and method of making same
JPH05175408A (en) Material and method for mounting semiconductor element

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12