US20010005037A1 - Semiconductor device having a multilayer interconnection structure - Google Patents

Semiconductor device having a multilayer interconnection structure Download PDF

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US20010005037A1
US20010005037A1 US09/773,594 US77359401A US2001005037A1 US 20010005037 A1 US20010005037 A1 US 20010005037A1 US 77359401 A US77359401 A US 77359401A US 2001005037 A1 US2001005037 A1 US 2001005037A1
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film
refractive index
sio
insulation film
interlayer insulation
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Katsumi Kakamu
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Socionext Inc
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Fujitsu Ltd
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Definitions

  • the present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a low-dielectric interlayer insulation film suitable for high-speed operation, and a fabrication process thereof.
  • a multilayer interconnection structure for electrically interconnecting these active device elements.
  • a first-layer interconnection pattern is covered by a first-layer interlayer insulation film, and a second-layer interconnection pattern is provided on such a first-layer interlayer insulation film.
  • a second-layer interlayer insulation film covers the second-layer interconnection pattern thus formed on the first-layer interlayer insulation film.
  • FIGS. 1A and 1B show typical examples of conventional multilayer interconnection structure.
  • the multilayer interconnection structure 10 A is formed on a substrate 1 in which active device elements such as transistors are formed.
  • the substrate 1 further includes an interlayer insulation film covering the foregoing active devices.
  • an interconnection pattern 2 of Al or an Al-alloy there is formed an interconnection pattern 2 of Al or an Al-alloy, and an SiO 2 film 3 is formed on the substrate 1 typically by a plasma CVD process so as to cover the interconnection pattern 2 in conformity with the shape thereof.
  • a planarization film 4 typically of SOG such that the planarization film 4 covers the SiO 2 film 3 with a planarized top surface, and an SiO 2 film 5 is formed on the planarization film 4 by a plasma CVD process.
  • the interconnection pattern 2 on the substrate 1 is covered by a planarized interlayer insulation film 6 of SiO 2 formed by a high-density plasma CVD process, wherein the planarized interlayer insulation film 6 has a planarized top surface. Further, the planarized interlayer insulation film 6 is covered by an SiO 2 film 7 formed by a plasma CVD process.
  • the SiO 2 film 5 or the SiO 2 film 7 is covered by a passivation film of SiN.
  • the SiO 2 film 3 , 4 or 6 generally has a dielectric constant of 4.1 or more.
  • the problem of signal transmission delay appears conspicuously when the SiO 2 film 3 , 4 or 6 is used for the interlayer insulation film of ultra-fine semiconductor devices that are fabricated according to the submicron rules.
  • Another and more specific object of the present invention is to provide a semiconductor device having a multilayer interconnection structure using therein a low-dielectric interlayer insulation film of F-doped SiO 2 , wherein the adhesion of the F-doped SiO 2 interlayer insulation film is improved substantially and also the reliability of the semiconductor device.
  • Another object of the present invention is to provide a semiconductor device, comprising:
  • said multilayer interconnection structure comprising: an interconnection pattern; a F-doped interlayer insulation film covering said interconnection pattern; and a high-refractive index insulation film having a refractive index higher than a refractive index of said F-doped interlayer insulation film, said high-refractive index insulation film being disposed at least one of a top side and a bottom side of said F-doped interlayer insulation film.
  • Another object of the present invention is to provide a fabrication process of a semiconductor device having a multilayer interconnection structure, comprising the steps of:
  • the F ions released from the low-dielectric interlayer insulation film are absorbed by the high-refractive index insulation film that contains an excess amount of Si, by providing the high-refractive index insulation film adjacent to the F-containing, low-dielectric interlayer insulation film.
  • the problem of exfoliation of the low-dielectric interlayer insulation film is effectively suppressed.
  • FIGS. 1A and 1B are diagrams showing examples of conventional multilayer interconnection structure
  • FIG. 2 is a diagram showing the construction of a test piece used in the experiments constituting the basis of the present invention
  • FIG. 3 is a diagram showing the result of the experiments in the form of a table
  • FIG. 4 is a diagram showing the construction of another test piece
  • FIG. 5 is a diagram showing the result of the experiments conducted on the test piece of FIG. 4;
  • FIG. 6 is an FTIR spectrum of various SiO 2 films used in the experiment.
  • FIG. 7 is a diagram showing the construction of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 8 is a diagram showing the construction of a plasma CVD apparatus used in the present invention for forming a F-doped, low-dielectric SiO 2 film;
  • FIG. 9 is a diagram showing the construction of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 10 is a diagram showing the construction of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 11 is a diagram showing the construction of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 12 is a diagram showing the construction of a semiconductor device according to a fifth embodiment of the present invention.
  • test piece 20 A having a structure shown in FIG. 2 was subjected to a thermal annealing process in a nitrogen (N 2 ) atmosphere, and an examination was made on the test piece 20 A thus annealed with regard to the status of exfoliation of the interlayer insulation film.
  • the test piece 20 A includes a Si substrate 11 and an undoped SiO 2 film 12 formed on the Si substrate 11 by a high-density plasma CVD process with a thickness of about 800 nm.
  • the SiO 2 film 12 thus formed has a characteristic refractive index of about 1.46.
  • FIG. 2 there is further formed a F-doped SiO 2 film 13 on the undoped SiO 2 film 12 with a thickness of about 650 nm, wherein the F-doped SiO 2 film 13 is formed by a high-density plasma CVD process while using SiF 4 as the source material and has a dielectric constant of about 3.4.
  • TABLE II shows the actual condition used for forming the F-doped SiO 2 film 13 , wherein it will be noted that the deposition of the SiO 2 film 13 was made by an ICP (induction-coupled plasma) plasma CVD apparatus.
  • ICP plasma CVD substrate temperature 300-450° C. process vessel pressure 0.1-1.3 Pa high-frequency power 3.0-4.5 kW plasma density 10 ⁇ 10 9 cm 3 SiH 4 flow rate 5-30 cc/mm O 2 flow rate 200 cc/mm SiF 4 65-90 cc/mm
  • a cap layer 14 is formed by various methods, and an undoped SiO 2 film 15 similar to the undoped SiO 2 film 12 is formed on the cap layer 14 with the thickness of about 600 nm. Further, an SiN film 16 having a thickness of about 500 nm is formed on the SiO 2 film 15 .
  • the specimen 20 A thus formed was then subjected to a thermal annealing process at 400° C. in an N 2 atmosphere for various durations, for examination of exfoliation occurring therein.
  • the experiment A represents the result for the case in which the cap layer 14 was formed by an SiO 2 film having a refractive index of 1.46, wherein the SiO 2 film for the experiment A was formed in a parallel-plate plasma CVD apparatus while using SiH 4 , N 2 and N 2 O under the condition of TABLE 3 noted below.
  • TABLE III deposition apparatus parallel-plate type substrate temperature 300-450° C. process vessel pressure 300-350 Pa high-frequency power 1.1 kW SiH 4 flow rate 300 cc/mm N 2 O flow rate 9500 cc/mm N 2 flow rate 1500 cc/mm
  • TABLE I also shows the result of the experiment B, in which the cap layer 14 was formed of an SiO 2 film having a thickness of about 100 nm and a refractive index of about 1.49. It should be noted that the SiO 2 film of the experiment B was formed in a parallel-plate plasma CVD apparatus under the condition of TABLE IV below.
  • TABLE IV deposition apparatus parallel-plate type substrate temperature 300-450° C. process vessel pressure 200-300 Pa high-frequency power 1.0 kW SiH 4 flow rate 350 cc/mm N 2 O flow rate 9500 cc/mm N 2 flow rate 1500 cc/mm
  • experiment B did not show the exfoliation even when the test piece is subjected to the thermal annealing process for the duration of 180 minutes.
  • TABLE I also shows the result of the experiment C, in which the cap layer 14 was formed of an SiO 2 film having a thickness of about 100 nm and a refractive index of about 1.51. It should be noted that the SiO 2 film of the experiment C was formed in a parallel-plate plasma CVD apparatus under the condition of TABLE V below.
  • TABLE V deposition apparatus parallel-plate type substrate temperature 350-400° C. process vessel pressure 200-300 Pa high-frequency power 0.4 kW SiH 4 flow rate 150 cc/mm N 2 O flow rate 3800 cc/mm N 2 flow rate 3800 cc/mm
  • experiment C did not show the exfoliation even when the test piece was subjected to the thermal annealing process for the duration of 180 minutes.
  • TABLE I also shows the result of the experiments D-G, in which the cap layer 14 of SiO 2 was formed by a plasma CVD process that uses TEOS as a source material with the thickness of 100-400 nm, under the condition represented in TABLE VI.
  • the SiO 2 cap layer 14 thus formed had a refractive index of about 1.46.
  • TABLE VI deposition apparatus parallel-plate type substrate temperature 300-400° C. process vessel pressure 250-400 Pa high-frequency power 0.4 kW TEOS flow rate 2.1 cc/mm O 2 flow rate 9500 cc/mm
  • TABLE I also shows the result of the experiments H-I in which the cap layer 14 was formed of a composite film of an SiO 2 film and an SiON film, wherein the SiO 2 film was formed by the plasma CVD process that uses TEOS as the source material, while the SiON film was formed by a plasma CVD process under the condition noted in TABLE VII below.
  • the SiON film thus formed had a refractive index of about 1.58.
  • TABLE I also shows the result of the experiments J-L in which the cap layer 14 was formed of a composite film of an SiO 2 film and an SiON film, wherein the SiO 2 film was formed with a thickness of about 200 nm either by a plasma CVD process conducted under the condition of TABLE III or by a plasma CVD process under the condition of TABLE VI while using TEOS as the source material.
  • the SiO 2 film has a refractive index of about 1.46.
  • the SiON film on the other hand, was formed by a plasma CVD process under the condition noted in TABLE VIII below.
  • the SiON film thus formed had a refractive index of about 1.65.
  • TABLE VIII deposition apparatus parallel-plate type substrate temperature 300-350° C. process vessel pressure 350-450 Pa high-frequency power 220-250 W SiH 4 flow rate 40 cc/mm N 2 O flow rate 170 cc/mm N 2 flow rate 2000 cc/mm
  • the Si substrate 11 is covered with an underlying layer 12 A corresponding to the undoped SiO 2 film 12 of FIG. 2, and the F-doped SiO 2 film 13 is formed on the underlying layer 12 A with a thickness of about 600 nm under the condition represented in TABLE II. Further, the F-doped SiO 2 film 13 is covered with the cap layer 14 .
  • TABLE IX-represented in FIG. 5 shows the result of the annealing experiments conducted on the test piece 20 B of FIG. 4, wherein the annealing experiments were made at about 400° C. in an N 2 atmosphere.
  • the experiment M represents the case in which an undoped SiO 2 film is formed for the underlying layer 12 A by a plasma CVD process with a thickness of about 500 nm, under the condition explained previously with reference to TABLE III.
  • the F-doped SiO 2 film 13 was then formed on the layer 12 A under the condition of TABLE VI with a thickness of about 600 nm, and the cap layer 14 of SiN was formed on the F-doped SiO 2 film 13 with a thickness of about 30 nm by a plasma CVD process.
  • the SiN film constituting the cap-layer 14 had a refractive index of about 2.00.
  • an SiO 2 film having a refractive index of about 1.49 was formed on the F-doped SiO 2 film 13 as the cap layer 14 with a thickness of about 100 nm, under the condition explained with reference to TABLE IV.
  • the SiO 2 film thus formed was further covered by an SiN film formed under the condition of the experiment M with a thickness of about 30 nm.
  • the underlying layer 12 A and the cap layer 14 were formed of an SiN film, wherein the SiN film was formed with a thickness of about 30 nm by a plasma CVD process.
  • FIG. 6 shows the FTIR (Fourier transform infrared) absorption spectrum observed for a plasma-CVD SiO 2 film thus formed for-the cap layer 14 with a refractive index of 1.46 and for a plasma-CVD SiO 2 film thus formed with a refractive index of 1.51.
  • FIG. 6 it can be seen that there appears a strong absorption peak corresponding to the Si—O bond at the wavenumber of about 1100 cm ⁇ 1 for any of the SiO 2 film having the refractive index of 1.46 and the SiO 2 film having the refractive index of 1.51.
  • the SiO 2 film having the refractive index of 1.51 shows the existence of an absorption peak at the wavenumber of about 2200 cm ⁇ 1 corresponding to the Si—H bond and further an absorption peak at the wavenumber of about 3400 cm ⁇ 1 corresponding to the Si—OH bond.
  • the result of FIG. 6 indicates that the high-refractive index SiO 2 film contains therein an excessive amount of Si.
  • FIG. 7 shows the construction of a semiconductor device 30 having a multilayer interconnection structure according to a first embodiment of the present invention.
  • the semiconductor device 30 includes a Si substrate 31 and a CVD-SiO 2 film 32 formed on the substrate 31 so as to cover the active devices such as MOS transistors formed on the Si substrate 31 .
  • the CVD-SiO 2 film 32 carries thereon an interconnection pattern 33 of Al or an Al-alloy, wherein the interconnection pattern 33 is covered with an F-doped, low-dielectric SiO 2 film 34 formed by an ICP plasma CVD apparatus 40 to be described with reference to FIG. 8.
  • the SiO 2 film 34 typically has a dielectric constant in the range of 3.4-3.5.
  • the ICP plasma CVD apparatus 40 includes a process vessel 41 to which various gaseous source materials such as SiH 4 , SiF 4 , O 2 , and the like, are introduced together with a carrier gas of Ar, and the like, wherein the process vessel 41 includes therein a stage 42 adapted to hold a substrate 44 via an electrostatic chuck 43 .
  • various gaseous source materials such as SiH 4 , SiF 4 , O 2 , and the like
  • the stage 42 also includes a cooling mechanism 42 A for controlling the temperature of the substrate.
  • deposition of an SiO 2 film is conducted after the step of forming the interconnection pattern 33 by using the CVD apparatus 40 of FIG. 8 under the condition of TABLE II.
  • a F-doped SiO 2 film 34 A containing therein F with the amount of about 12 atomic percent such that the F-doped SiO 2 film 34 A covers the interconnection pattern 33 with a thickness of typically about 100 nm.
  • the F-doped SiO 2 film 34 A is formed to have little hygroscopicity while simultaneously satisfying the request of high F-concentration and a small dielectric constant, as low as about 3.4.
  • the present embodiment forms another F-doped SiO 2 film 34 B on the SiO 2 film 34 A by using the same ICP plasma CVD apparatus 40 of FIG. 8 but with a substrate biasing.
  • the high-frequency power source 45 is activated with a power of 1200 W.
  • the F-doped SiO 2 film 34 B is formed with a thickness of about 800 nm.
  • the SiO 2 film 34 B contains F with a concentration of about 8%.
  • F-content in the SiO 2 film it is possible to obtain a stable film quality and low hygroscopicity even when the SiO 2 film is formed under the presence of the substrate biasing. While it is true that the SiO 2 film 34 B has a dielectric constant slightly larger than that of the SiO 2 film 34 A because of the decreased F-content, the stray capacitance of the interlayer insulation film is still suppressed effectively, as the SiO 2 film 34 B does not make a direct contact with the interconnection pattern 33 .
  • the interlayer insulation film 34 B thus formed is further covered with a high-refractive index SiO 2 film 35 by forming the SiO 2 film in the parallel-plate plasma CVD under the condition of TABLE IV to have a thickness of typically about 100 nm.
  • the SiO 2 film 35 thus formed has a refractive index of 1.49 or higher and has a Si-enriched composition with respect to the stoichiometry composition of SiO 2 .
  • an SiN film 36 having a refractive index of about 2.0 is formed on the SiO 2 film 35 by the same parallel-plate plasma CVD apparatus.
  • the F ions released from the F-doped SiO 2 film 34 A or 34 B are captured by the high-refractive index SiO 2 film 35 as noted previously.
  • the problem of exfoliation of the SiN film 36 is effectively suppressed.
  • an SiO 2 film having a refractive index of 1.48 or higher may be used for the high-refractive index SiO 2 film 35 .
  • FIG. 9 shows the construction of a semiconductor device 50 having a multilayer interconnection structure formed by a dual damascene process according to a second embodiment of the present invention.
  • the semiconductor device 50 is constructed on a Si substrate 51 including diffusion regions 51 A and 51 B, wherein the substrate 51 is covered with an interlayer insulation film 52 of an undoped SiO 2 film corresponding to the SiO 2 film 12 of the structure 20 A of FIG. 2, and the interlayer insulation film 52 is formed with contact holes 52 A and 52 B exposing the diffusion regions 51 A and 51 B respectively. Further, there is formed a low-dielectric interlayer insulation film 53 of an F-doped SiO 2 film on th interlayer insulation film 52 , wherein the foregoing low-dielectric interlayer insulation film 53 is formed with interconnection grooves 53 A and 53 B respectively exposing the contact holes 52 A and 52 B.
  • the contact holes 52 A and 52 B are filled with W plugs 52 a and 52 b respectively, while the interconnection grooves 53 A and 53 B are filled respectively with Cu interconnection patterns 53 C and 53 D.
  • an SiN film 53 a used as an etching stopper, and the interlayer insulation film 53 is covered by a high-refractive index SiO 2 film 53 b corresponding to the high-refractive index SiO 2 film 35 and having a refractive index of preferably 1.49 or higher.
  • the W plugs 52 a and 52 b are formed by depositing a W layer on the interlayer insulation film 52 so as to fill the contact holes 52 A and 52 B, followed by a CMP process for removing any residual W layer remaining on the top surface of the interlayer insulation film 52 .
  • the Cu interconnection patterns 53 C and 53 D are formed by depositing a Cu layer on the interlayer insulation film 53 , more precisely on the high-refractive index SiO 2 film 53 b so as to fill the interconnection grooves 53 A and 53 B, followed by a CMP process-to remove the same from the top surface of the SiO 2 film 53 b.
  • interlayer insulation film 53 On the interlayer insulation film 53 , more precisely on the high-refractive index SiO 2 film 53 b , there is formed an interlayer insulation film 54 of F-doped SiO 2 , with an SiN etching stopper film 54 a interposed between the interlayer insulation film and the high-refractive index SiO 2 film 53 b . Further, the interlayer insulation film 54 thus formed is covered with a high-refractive index SiO 2 film 54 b similar to the SiO 2 film 53 b .
  • interlayer insulation film 54 there is further provided an interlayer insulation film 55 of F-doped SiO 2 , with the high-refractive index SiO 2 film 54 b and an SiN etching stopper film 55 a interposed between the interlayer insulation film 55 and the interlayer insulation film 54 . Further, the interlayer insulation film 55 is covered by a high-refractive index SiO 2 film 55 b similar to the high-refractive index SiO 2 film 53 b or 54 b.
  • interconnection grooves 55 A and 55 B there are formed interconnection grooves 55 A and 55 B while using the SiN film 55 a as an etching stopper.
  • contact holes 54 A and 54 B are formed in the interlayer insulation film 54 and further in the high-refractive index SiO 2 film 55 B by a dry etching process that is conducted while using the SiN film 55 a as a hard mask.
  • the contact holes 54 A and 54 B are formed so as to expose the SiN film 54 a , wherein the SiN film 54 a is further subjected to a dry etching process to expose the Cu interconnection patterns 53 C and 53 D at the contact holes 54 A and 54 B respectively.
  • the interlayer insulation film 55 more precisely the high-refractive index SiO 2 film 55 b is covered by a Cu layer deposited so as to fill the interconnection grooves 55 A and 55 B and the contact holes 54 A and 54 B, followed by a CMP process to remove the residual Cu layer remaining on the top surface of the high-refractive index SiO 2 film 55 b .
  • Cu interconnection patterns 55 C and 55 D are formed so as to fill the interconnection grooves 55 A and 55 B and so as to make a contact with the interconnection pattern 53 A or 53 B via the contact hole 54 A or 54 B.
  • a high-refractive index SiO 2 film such as the SiO 2 film 53 b or 54 b is formed adjacent to the F-doped low-dielectric SiO 2 film such as the SiO 2 film 53 , 54 or 55 so that the high-refractive index SiO 2 film 53 b or 54 b is interposed between the corresponding SiN film 54 a or 55 a .
  • the F ions released from the F-doped SiO 2 film 53 or 54 is captured by the high-refractive index SiO 2 film 53 b or 54 b , and the problem of accumulation of F under the SiN film 54 a or 55 a is successfully eliminated.
  • the semiconductor device 50 shows excellent reliability.
  • the semiconductor device 50 may be any of a logic integrated circuit and a memory integrated circuit such as a DRAM.
  • FIG. 10 shows the construction of a DRAM 60 according to a third embodiment of the present invention.
  • the DRAM 60 is constructed on a Si substrate 61 formed with a p-type well 62 , wherein the Si substrate 61 is also formed with a field oxide film 63 defining an active region.
  • the Si substrate 61 there are formed diffusion regions 61 A- 61 C of the n + -type in correspondence to the active region, and a gate electrode 64 A is formed on the substrate 61 so as to cover the channel region formed in the active region between the diffusion region 61 A and the diffusion region 61 B, with a gate insulation film (not shown) interposed between the substrate 61 and the gate electrode 64 A.
  • another gate electrode 64 B is formed on the substrate 61 so as to cover the channel region formed in the active region between the diffusion region 61 B and the diffusion region 61 C, with a gate insulation film (not shown) interposed between the substrate 61 and the gate electrode 64 B. Further, a word line WL similar to the gate electrode 64 A or 64 B extends over the field oxide film 63 .
  • Each of the gate electrodes 64 A and 64 B, and also the word line WL has a pair of side-wall insulation films on the respective side walls thereof, and is further covered by a thin insulation film 64 of SiN, and the like. Further, the insulation film 64 is covered by a planarizing insulation film 65 of CVD-SiO 2 , and the like, wherein the planarizing insulation film 65 is formed with a contact hole 65 A exposing the diffusion region 61 B. Further, there is formed a bit line electrode BL on the planarizing insulation film 65 by W or polysilicon, such that the bit line electrode BL makes a contact with the diffusion region 61 B at the contact hole 65 A.
  • bit line electrode BL is covered by a thin insulation film 66 of SiN, and the like, and a planarizing insulation film 67 of a CVD-SiO 2 film, and the like, is formed on the insulation film 66 . Further, the planarizing insulation film 67 is formed with contact holes 67 A and 67 B so as to expose the diffusion regions 61 A and 61 C, and memory cell capacitors C 1 and C 2 of the stacked-fin type are formed respectively in the contact holes 67 A and 67 B.
  • Each of the stacked-fin type capacitors C 1 and C 2 includes a polysilicon storage electrode that makes a contact with the diffusion region 61 A or 61 C at the contact hole 67 A or 67 B, and a capacitor insulation film covering the polysilicon storage electrode. Further, a polysilicon cell plate 68 covers the capacitor insulation film. The polysilicon cell plate 68 , in turn, is covered by a planarizing interlayer insulation film 69 .
  • interconnection pattern 70 On the planarizing interlayer insulation film 69 , there is formed an interconnection pattern 70 , wherein the interconnection pattern 70 includes a barrier layer 70 a having a Ti/TiN structure formed on the interlayer insulation film 69 , a conductor pattern 70 b of Al or an Al-alloy formed on the barrier layer 70 a , and an anti-reflection coating (ARC) 70 c of SiON, and the like, formed on the conductor pattern 70 b .
  • ARC anti-reflection coating
  • the interconnection pattern 70 is covered by an interlayer insulation film 71 of a F-doped, low-dielectric SiO 2 film formed on the planarizing interlayer insulation film 69 , wherein the interlayer insulation film 71 may contain F with a concentration of about 12 atomic percent and may have a dielectric constant of about 3.4.
  • the accumulation of F under the passivation film 73 is minimized by interposing the high-refractive index SiO 2 film 72 between the F-doped, low-dielectric interlayer insulation film 71 and the dense SiN passivation film 73 . Thereby, the exfoliation of the SiN passivation film 73 is effectively avoided.
  • FIG. 11 shows the construction of a semiconductor device 50 A according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
  • the semiconductor device 50 A is a modification of the semiconductor device 50 of FIG. 9 in that each of the F-doped SiO 2 films 53 , 54 and 55 has also an additional high-refractive index SiO 2 film 53 c , 54 c or 55 c , such that the additional high-refractive index SiO 2 film is formed at the bottom part of the F-doped SiO 2 film so as to intervene between the F-doped SiO 2 film and the SiN etching stopper layer thereon.
  • the additional high-refractive index SiO 2 film 53 c is interposed between the F-doped SiO 2 film 53 and the SiN film 53 a thereunder, the additional high-refractive index SiO 2 film 54 c is interposed between the F-doped SiO 2 film 54 and the underlying SiN etching stopper layer 54 a.
  • the SiN film 54 a or 55 a is sandwiched by a pair of high-refractive index SiO 2 film, such as the SiO 2 film 53 b and the SiO 2 film 54 c , and it becomes possible to interrupt the migration of the F ions to the SiN film from both the upward direction and the downward direction. Thereby, the accumulation of the F ions adjacent to the SiN film is effectively eliminated.
  • FIG. 12 shows the construction of a semiconductor device 50 B according to a fifth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
  • the semiconductor device 50 B is a modification of the semiconductor device 50 A of FIG. 11 in that there is added a further extra high-refractive index SiO 2 film between the F-doped SiO 2 film and the high-refractive index SiO 2 film at the top part of the F-doped SiO 2 film, such as an SiO 2 film 53 d , 54 d or 55 d .
  • the high-refractive index SiO 2 film 53 d is interposed between the F-doped SiO 2 film 53 and the high-refractive index SiO 2 film 53 b formed at the top part of the F-doped SiO 2 film 53 .

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Abstract

A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Description

    BACKGROUND OF THE INVENTION
  • The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a low-dielectric interlayer insulation film suitable for high-speed operation, and a fabrication process thereof. [0001]
  • In a semiconductor integrated circuit in which a number of active device elements, such as MOS transistors, are integrated on a common substrate, it is practiced to provide a multilayer interconnection structure for electrically interconnecting these active device elements. In a multilayer interconnection structure, a first-layer interconnection pattern is covered by a first-layer interlayer insulation film, and a second-layer interconnection pattern is provided on such a first-layer interlayer insulation film. Further, a second-layer interlayer insulation film covers the second-layer interconnection pattern thus formed on the first-layer interlayer insulation film. Further, there may be a third-layer interconnection pattern and a third-layer interlayer insulation film on the second-layer interlayer insulation film. [0002]
  • When such a multilayer interconnection structure is to be formed in a high-speed semiconductor integrated circuit such as a logic integrated circuit or a high-speed memory integrated circuit, it is desirable to reduce the dielectric constant of the insulation film constituting the interlayer insulation film as low as possible. This demand is particularly acute in the ultrafine semiconductor integrated circuits fabricated according to the design rule of 0.3 μm or stricter. It should be noted that such ultrafine semiconductor integrated circuits generally use four or more layers for the multilayer interconnection structure and the total length of the interconnection patterns therein inevitably becomes a very large value. [0003]
  • When a conventional insulation film such as SiO[0004] 2, which is formed by a parallel-plate plasma CVD process or by a high-temperature CVD process, or an SOG film which is formed by a spin-coating process, is to be used for the interlayer insulation film in such a multilayer interconnection structure, there arises a problem of increase in the impedance as a result of the electrostatic inductance between the interconnection patterns. It should be noted that such an increase in the impedance leads to the problems of response delay or increase of electrical power consumption.
  • In view of the shortcomings of the conventional interlayer insulation films, there has been a proposal to deposit a F-doped, low-dielectric SiO[0005] 2 film by a high-density plasma CVD process. The F-doped SiO2 film thus deposited may be subjected to a chemical mechanical polishing (CMP) process for planarization. In fact, it is possible to reduce the dielectric constant of the interlayer insulation film to 3.4-3.5 by adding F (fluorine) to the SiO2 interlayer insulation film.
  • FIGS. 1A and 1B show typical examples of conventional multilayer interconnection structure. [0006]
  • Referring to FIG. 1A showing an example multilayer interconnection structure [0007] 10A, it can be seen that the multilayer interconnection structure 10A is formed on a substrate 1 in which active device elements such as transistors are formed. The substrate 1 further includes an interlayer insulation film covering the foregoing active devices.
  • On the [0008] substrate 1, there is formed an interconnection pattern 2 of Al or an Al-alloy, and an SiO2 film 3 is formed on the substrate 1 typically by a plasma CVD process so as to cover the interconnection pattern 2 in conformity with the shape thereof. Further, there is formed a planarization film 4 typically of SOG, such that the planarization film 4 covers the SiO2 film 3 with a planarized top surface, and an SiO2 film 5 is formed on the planarization film 4 by a plasma CVD process.
  • In the example of FIG. 1B showing a multilayer interconnection structure [0009] 10B, on the other hand, the interconnection pattern 2 on the substrate 1 is covered by a planarized interlayer insulation film 6 of SiO2 formed by a high-density plasma CVD process, wherein the planarized interlayer insulation film 6 has a planarized top surface. Further, the planarized interlayer insulation film 6 is covered by an SiO2 film 7 formed by a plasma CVD process.
  • In any of the multilayer interconnection structures [0010] 10A and 10B of FIGS. 1A and 1B, the SiO2 film 5 or the SiO2 film 7 is covered by a passivation film of SiN.
  • In any of the conventional multilayer interconnection structures, the SiO[0011] 2 film 3, 4 or 6 generally has a dielectric constant of 4.1 or more. Thus, due to the effect of the stray capacitance, the problem of signal transmission delay appears conspicuously when the SiO2 film 3, 4 or 6 is used for the interlayer insulation film of ultra-fine semiconductor devices that are fabricated according to the submicron rules. Further, there arises a difficulty in increasing the clock speed in such ultra-fine semiconductor devices that uses the interlayer insulation film having a dielectric constant of 4.1 or more.
  • As noted already, it is possible to reduce the dielectric constant of the [0012] interlayer insulation film 3, 4 or 6 to the value of 3.4-3.5 by using SiO2 added with F. By using such a F-doped SiO2 film for the interlayer insulation film, it becomes possible to increase the operational speed of the ultra-fine semiconductor devices. However, such a F-doped SiO2 film has a drawback in that the adhesion of the SiO2 film to the interconnection pattern is insufficient and that the F-doped SiO2 film thus formed tends to cause an exfoliation.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated. [0013]
  • Another and more specific object of the present invention is to provide a semiconductor device having a multilayer interconnection structure using therein a low-dielectric interlayer insulation film of F-doped SiO[0014] 2, wherein the adhesion of the F-doped SiO2 interlayer insulation film is improved substantially and also the reliability of the semiconductor device.
  • Another object of the present invention is to provide a semiconductor device, comprising: [0015]
  • a substrate; [0016]
  • a multilayer interconnection structure formed on said substrate; [0017]
  • said multilayer interconnection structure comprising: an interconnection pattern; a F-doped interlayer insulation film covering said interconnection pattern; and a high-refractive index insulation film having a refractive index higher than a refractive index of said F-doped interlayer insulation film, said high-refractive index insulation film being disposed at least one of a top side and a bottom side of said F-doped interlayer insulation film. [0018]
  • Another object of the present invention is to provide a fabrication process of a semiconductor device having a multilayer interconnection structure, comprising the steps of: [0019]
  • covering an interconnection pattern with an interlayer insulation film containing therein F and having a first refractive index; and [0020]
  • forming a high-refractive insulation film on said interlayer insulation film, said high-refractive insulation film having a second refractive index higher than said first refractive index. [0021]
  • According to the present invention, the F ions released from the low-dielectric interlayer insulation film are absorbed by the high-refractive index insulation film that contains an excess amount of Si, by providing the high-refractive index insulation film adjacent to the F-containing, low-dielectric interlayer insulation film. Thereby, the problem of exfoliation of the low-dielectric interlayer insulation film is effectively suppressed. [0022]
  • Other objects and further features of the present invention will become apparent from the detailed description hereinafter when read in conjunction with the attached drawings. [0023]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A and 1B are diagrams showing examples of conventional multilayer interconnection structure; [0024]
  • FIG. 2 is a diagram showing the construction of a test piece used in the experiments constituting the basis of the present invention; [0025]
  • FIG. 3 is a diagram showing the result of the experiments in the form of a table; [0026]
  • FIG. 4 is a diagram showing the construction of another test piece; [0027]
  • FIG. 5 is a diagram showing the result of the experiments conducted on the test piece of FIG. 4; [0028]
  • FIG. 6 is an FTIR spectrum of various SiO[0029] 2 films used in the experiment;
  • FIG. 7 is a diagram showing the construction of a semiconductor device according to a first embodiment of the present invention; [0030]
  • FIG. 8 is a diagram showing the construction of a plasma CVD apparatus used in the present invention for forming a F-doped, low-dielectric SiO[0031] 2 film;
  • FIG. 9 is a diagram showing the construction of a semiconductor device according to a second embodiment of the present invention; [0032]
  • FIG. 10 is a diagram showing the construction of a semiconductor device according to a third embodiment of the present invention; [0033]
  • FIG. 11 is a diagram showing the construction of a semiconductor device according to a fourth embodiment of the present invention; and [0034]
  • FIG. 12 is a diagram showing the construction of a semiconductor device according to a fifth embodiment of the present invention. [0035]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Principle
  • Hereinafter, the principle of the present invention will be described with reference to FIGS. [0036] 2-5.
  • In the investigation that forms the basis of the present invention, the inventor of the present invention conducted a series of experiments on a [0037] multilayer interconnection structure 20A shown in FIG. 2 and obtained a result represented in FIG. 3 as TABLE I.
  • In the experiments, a [0038] test piece 20A having a structure shown in FIG. 2 was subjected to a thermal annealing process in a nitrogen (N2) atmosphere, and an examination was made on the test piece 20A thus annealed with regard to the status of exfoliation of the interlayer insulation film.
  • Referring to FIG. 2, the [0039] test piece 20A includes a Si substrate 11 and an undoped SiO2 film 12 formed on the Si substrate 11 by a high-density plasma CVD process with a thickness of about 800 nm. The SiO2 film 12 thus formed has a characteristic refractive index of about 1.46.
  • In the structure of FIG. 2, there is further formed a F-doped SiO[0040] 2 film 13 on the undoped SiO2 film 12 with a thickness of about 650 nm, wherein the F-doped SiO2 film 13 is formed by a high-density plasma CVD process while using SiF4 as the source material and has a dielectric constant of about 3.4. During the deposition process of the F-doped SiO2 film 13, no high-frequency biasing was applied to the substrate 11, as the use of such a high-frequency biasing during the deposition process of a F-doped SiO2 film tends to cause a deterioration in the hygroscopicity of the F-doped SiO2 film grown according to the high-density plasma CVD process. Because of this reason, it has been difficult to form the F-doped SiO2 film 13 to have a dielectric constant lower than about 3.6.
  • Following TABLE II shows the actual condition used for forming the F-doped SiO[0041] 2 film 13, wherein it will be noted that the deposition of the SiO2 film 13 was made by an ICP (induction-coupled plasma) plasma CVD apparatus.
    TABLE II
    deposition apparatus ICP plasma CVD
    substrate temperature 300-450° C.
    process vessel pressure 0.1-1.3 Pa
    high-frequency power 3.0-4.5 kW
    plasma density 10 × 109cm3
    SiH4 flow rate 5-30 cc/mm
    O2 flow rate 200 cc/mm
    SiF4 65-90 cc/mm
  • On the F-doped SiO[0042] 2 film 13, a cap layer 14 is formed by various methods, and an undoped SiO2 film 15 similar to the undoped SiO2 film 12 is formed on the cap layer 14 with the thickness of about 600 nm. Further, an SiN film 16 having a thickness of about 500 nm is formed on the SiO2 film 15.
  • The [0043] specimen 20A thus formed was then subjected to a thermal annealing process at 400° C. in an N2 atmosphere for various durations, for examination of exfoliation occurring therein.
    • EXPERIMENT A
  • Referring to TABLE I of FIG. 3, the experiment A represents the result for the case in which the [0044] cap layer 14 was formed by an SiO2 film having a refractive index of 1.46, wherein the SiO2 film for the experiment A was formed in a parallel-plate plasma CVD apparatus while using SiH4, N2 and N2O under the condition of TABLE 3 noted below.
    TABLE III
    deposition apparatus parallel-plate type
    substrate temperature 300-450° C.
    process vessel pressure 300-350 Pa
    high-frequency power 1.1 kW
    SiH4 flow rate 300 cc/mm
    N2O flow rate 9500 cc/mm
    N2 flow rate 1500 cc/mm
  • After the thermal annealing process conducted for the [0045] test piece 20A for the duration of 180 minutes, it was observed that there does occur an exfoliation in the SiN film 16. It should be noted that the SiN film 16 did not show such an exfoliation at the beginning of the annealing experiment.
    • EXPERIMENT B
  • TABLE I also shows the result of the experiment B, in which the [0046] cap layer 14 was formed of an SiO2 film having a thickness of about 100 nm and a refractive index of about 1.49. It should be noted that the SiO2 film of the experiment B was formed in a parallel-plate plasma CVD apparatus under the condition of TABLE IV below.
    TABLE IV
    deposition apparatus parallel-plate type
    substrate temperature 300-450° C.
    process vessel pressure 200-300 Pa
    high-frequency power 1.0 kW
    SiH4 flow rate 350 cc/mm
    N2O flow rate 9500 cc/mm
    N2 flow rate 1500 cc/mm
  • As represented in TABLE I, the experiment B did not show the exfoliation even when the test piece is subjected to the thermal annealing process for the duration of 180 minutes. [0047]
    • EXPERIMENT C
  • TABLE I also shows the result of the experiment C, in which the [0048] cap layer 14 was formed of an SiO2 film having a thickness of about 100 nm and a refractive index of about 1.51. It should be noted that the SiO2 film of the experiment C was formed in a parallel-plate plasma CVD apparatus under the condition of TABLE V below.
    TABLE V
    deposition apparatus parallel-plate type
    substrate temperature 350-400° C.
    process vessel pressure 200-300 Pa
    high-frequency power 0.4 kW
    SiH4 flow rate 150 cc/mm
    N2O flow rate 3800 cc/mm
    N2 flow rate 3800 cc/mm
  • As represented in TABLE I, the experiment C did not show the exfoliation even when the test piece was subjected to the thermal annealing process for the duration of 180 minutes. [0049]
    • EXPERIMENTS D-G
  • TABLE I also shows the result of the experiments D-G, in which the [0050] cap layer 14 of SiO2 was formed by a plasma CVD process that uses TEOS as a source material with the thickness of 100-400 nm, under the condition represented in TABLE VI. The SiO2 cap layer 14 thus formed had a refractive index of about 1.46.
    TABLE VI
    deposition apparatus parallel-plate type
    substrate temperature 300-400° C.
    process vessel pressure 250-400 Pa
    high-frequency power 0.4 kW
    TEOS flow rate 2.1 cc/mm
    O2 flow rate 9500 cc/mm
  • As represented in TABLE I, the experiments D-G showed an exfoliation of the [0051] SiN film 16 after 30 minutes from the start of the thermal annealing process.
    • EXPERIMENTS H-I
  • TABLE I also shows the result of the experiments H-I in which the [0052] cap layer 14 was formed of a composite film of an SiO2 film and an SiON film, wherein the SiO2 film was formed by the plasma CVD process that uses TEOS as the source material, while the SiON film was formed by a plasma CVD process under the condition noted in TABLE VII below. The SiON film thus formed had a refractive index of about 1.58.
    TABLE VII
    deposition apparatus parallel-plate type
    substrate temperature 300-350° C.
    process vessel pressure 350-450 Pa
    high- frequency power 220-250 W
    SiH4 flow rate 40 cc/mm
    N2O flow rate 170 cc/mm
    N2 flow rate 2000 cc/mm
  • As represented in TABLE I, the experiments H-I showed an exfoliation of the [0053] SiN film 16 after 90 minutes from the start of the thermal annealing process.
    • EXPERIMENTS J-L
  • TABLE I also shows the result of the experiments J-L in which the [0054] cap layer 14 was formed of a composite film of an SiO2 film and an SiON film, wherein the SiO2 film was formed with a thickness of about 200 nm either by a plasma CVD process conducted under the condition of TABLE III or by a plasma CVD process under the condition of TABLE VI while using TEOS as the source material. In any of these cases, the SiO2 film has a refractive index of about 1.46. The SiON film, on the other hand, was formed by a plasma CVD process under the condition noted in TABLE VIII below. The SiON film thus formed had a refractive index of about 1.65.
    TABLE VIII
    deposition apparatus parallel-plate type
    substrate temperature 300-350° C.
    process vessel pressure 350-450 Pa
    high-frequency power 220-250 W
    SiH4 flow rate 40 cc/mm
    N2O flow rate 170 cc/mm
    N2 flow rate 2000 cc/mm
  • As represented in TABLE I, the experiments J-L showed an exfoliation of the [0055] SiN film 16 after 180 minutes from the start of the thermal annealing process.
  • Further, the inventor of the present invention conducted a similar thermal annealing experiments for a [0056] test piece 20B having a construction shown in FIG. 4. In FIG. 4, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
  • Referring to FIG. 4, the Si substrate [0057] 11 is covered with an underlying layer 12A corresponding to the undoped SiO2 film 12 of FIG. 2, and the F-doped SiO2 film 13 is formed on the underlying layer 12A with a thickness of about 600 nm under the condition represented in TABLE II. Further, the F-doped SiO2 film 13 is covered with the cap layer 14.
  • TABLE IX-represented in FIG. 5 shows the result of the annealing experiments conducted on the [0058] test piece 20B of FIG. 4, wherein the annealing experiments were made at about 400° C. in an N2 atmosphere.
  • Referring to TABLE IX, the experiment M represents the case in which an undoped SiO[0059] 2 film is formed for the underlying layer 12A by a plasma CVD process with a thickness of about 500 nm, under the condition explained previously with reference to TABLE III. The F-doped SiO2 film 13 was then formed on the layer 12A under the condition of TABLE VI with a thickness of about 600 nm, and the cap layer 14 of SiN was formed on the F-doped SiO2 film 13 with a thickness of about 30 nm by a plasma CVD process. The SiN film constituting the cap-layer 14 had a refractive index of about 2.00.
  • In the experiment N, an SiO[0060] 2 film having a refractive index of about 1.49 was formed on the F-doped SiO2 film 13 as the cap layer 14 with a thickness of about 100 nm, under the condition explained with reference to TABLE IV. The SiO2 film thus formed was further covered by an SiN film formed under the condition of the experiment M with a thickness of about 30 nm.
  • In the experiment O, on the other hand, the [0061] underlying layer 12A and the cap layer 14 were formed of an SiN film, wherein the SiN film was formed with a thickness of about 30 nm by a plasma CVD process.
  • The result of TABLE IX shows that there occurs an exfoliation in the experiment M after a thermal annealing process conducted for 90 minutes. In the experiments N and O, no exfoliation was observed. [0062]
  • Summarizing above, in the experiments of TABLE I conducted on the [0063] specimen 20A, it was observed that exfoliation occurred always in the SiN film 16 which has a dense texture, wherein this result is interpreted such that the F-doped SiO2 film 13 releases F ions when the thermal annealing process is conducted and that the F ions thus released are accumulated under the dense SiN film 16. On the other hand, the result of the experiments B and C of TABLE I or the result of the experiment N of TABLE IX clearly shows that the problem of exfoliation is successfully avoided when a high-refractive index SiO2 film is formed adjacent to the F-doped SiO2 film 13 as the cap layer 14. This suggests that the F ions released from the F-doped SiO2 film 13 are captured by the high-refractive index SiO2 cap layer 14.
  • FIG. 6 shows the FTIR (Fourier transform infrared) absorption spectrum observed for a plasma-CVD SiO[0064] 2 film thus formed for-the cap layer 14 with a refractive index of 1.46 and for a plasma-CVD SiO2 film thus formed with a refractive index of 1.51.
  • Referring to FIG. 6, it can be seen that there appears a strong absorption peak corresponding to the Si—O bond at the wavenumber of about 1100 cm[0065] −1 for any of the SiO2 film having the refractive index of 1.46 and the SiO2 film having the refractive index of 1.51. On the other hand, it should be noted that the SiO2 film having the refractive index of 1.51 shows the existence of an absorption peak at the wavenumber of about 2200 cm−1 corresponding to the Si—H bond and further an absorption peak at the wavenumber of about 3400 cm−1 corresponding to the Si—OH bond. In other words, the result of FIG. 6 indicates that the high-refractive index SiO2 film contains therein an excessive amount of Si.
  • From the foregoing result of the FTIR spectrum of FIG. 6, it is interpreted that, in the experiment B or C of TABLE I or in the experiment N of TABLE IX, the excessive Si ions in the high-refractive index SiO[0066] 2 film capture the F ions that are released from the F-doped SiO2 film. In the spectrum of FIG. 6, it should also be noted that there is a shift in the absorption peak observed at the wavenumber of about 800 cm−1 in the SiO2 film having the refractive index of 1.46, such that the foregoing absorption peak is shifted to the wavenumber of about 900 cm−1 in the SiO2 film having the refractive index of 1.51.
  • Thus, according to the present invention, it becomes possible to avoid the problem of exfoliation of the interlayer insulation film or the passivation film constituting a multilayer interconnection structure, by disposing a high-refractive index SiO[0067] 2 film containing excess amount of Si adjacent to the F-doped SiO2 film and by causing the high-refractive index SiO2 film to absorb the F ions released from the F-doped SiO2 film.
    • First Embodiment
  • FIG. 7 shows the construction of a [0068] semiconductor device 30 having a multilayer interconnection structure according to a first embodiment of the present invention.
  • Referring to FIG. 7, the [0069] semiconductor device 30 includes a Si substrate 31 and a CVD-SiO2 film 32 formed on the substrate 31 so as to cover the active devices such as MOS transistors formed on the Si substrate 31.
  • The CVD-SiO[0070] 2 film 32 carries thereon an interconnection pattern 33 of Al or an Al-alloy, wherein the interconnection pattern 33 is covered with an F-doped, low-dielectric SiO2 film 34 formed by an ICP plasma CVD apparatus 40 to be described with reference to FIG. 8. The SiO2 film 34 typically has a dielectric constant in the range of 3.4-3.5.
  • Referring to FIG. 8, the ICP [0071] plasma CVD apparatus 40 includes a process vessel 41 to which various gaseous source materials such as SiH4, SiF4, O2, and the like, are introduced together with a carrier gas of Ar, and the like, wherein the process vessel 41 includes therein a stage 42 adapted to hold a substrate 44 via an electrostatic chuck 43. By introducing the foregoing gaseous source materials such as SiH4, SiF4 or O2 into the process vessel 41 and by energizing the substrate 44 by a high-frequency power source 45, and further by energizing a coil 41A outside-the process vessel 41 simultaneously by using another high-frequency power source 46, a high-density plasma is formed in the process vessel 41. It should be noted that the stage 42 also includes a cooling mechanism 42A for controlling the temperature of the substrate.
  • In the present embodiment, deposition of an SiO[0072] 2 film is conducted after the step of forming the interconnection pattern 33 by using the CVD apparatus 40 of FIG. 8 under the condition of TABLE II. Thereby, there is formed a F-doped SiO2 film 34A containing therein F with the amount of about 12 atomic percent such that the F-doped SiO2 film 34A covers the interconnection pattern 33 with a thickness of typically about 100 nm. By avoiding the use of substrate biasing in the step of forming the F-doped SiO2 film 34A, the F-doped SiO2 film 34A is formed to have little hygroscopicity while simultaneously satisfying the request of high F-concentration and a small dielectric constant, as low as about 3.4.
  • As the F-doped SiO[0073] 2 film 34A is formed without a substrate biasing, the step coverage over the interconnection pattern 33 by the SiO2 film 34 becomes inevitably poor. In view of the poor step coverage of the F-doped SiO2 film 34A, the present embodiment forms another F-doped SiO2 film 34B on the SiO2 film 34A by using the same ICP plasma CVD apparatus 40 of FIG. 8 but with a substrate biasing. Thus, during the deposition of the F-doped SiO2 film 34A, the high-frequency power source 45 is activated with a power of 1200 W. Typically, the F-doped SiO2 film 34B is formed with a thickness of about 800 nm.
  • During the deposition of the SiO[0074] 2 film 34B, the supply of SiF4 is reduced slightly such that the SiO2 film 34B thus formed contains F with a concentration of about 8%. By controlling the F-content in the SiO2 film within this level, it is possible to obtain a stable film quality and low hygroscopicity even when the SiO2 film is formed under the presence of the substrate biasing. While it is true that the SiO2 film 34B has a dielectric constant slightly larger than that of the SiO2 film 34A because of the decreased F-content, the stray capacitance of the interlayer insulation film is still suppressed effectively, as the SiO2 film 34B does not make a direct contact with the interconnection pattern 33.
  • In the [0075] structure 30 of FIG. 7, the interlayer insulation film 34B thus formed is further covered with a high-refractive index SiO2 film 35 by forming the SiO2 film in the parallel-plate plasma CVD under the condition of TABLE IV to have a thickness of typically about 100 nm. It should be noted that the SiO2 film 35 thus formed has a refractive index of 1.49 or higher and has a Si-enriched composition with respect to the stoichiometry composition of SiO2. Further, an SiN film 36 having a refractive index of about 2.0 is formed on the SiO2 film 35 by the same parallel-plate plasma CVD apparatus.
  • In the multilayer interconnection structure having such a structure, it should be noted that the F ions released from the F-doped SiO[0076] 2 film 34A or 34B are captured by the high-refractive index SiO2 film 35 as noted previously. Thereby, the problem of exfoliation of the SiN film 36, an example of which can be seen in the experiment B or C of TABLE I or in the experiment N of TABLE IX, is effectively suppressed. It should be noted that an SiO2 film having a refractive index of 1.48 or higher may be used for the high-refractive index SiO2 film 35.
    • Second Embodiment
  • FIG. 9 shows the construction of a [0077] semiconductor device 50 having a multilayer interconnection structure formed by a dual damascene process according to a second embodiment of the present invention.
  • Referring to FIG. 9, the [0078] semiconductor device 50 is constructed on a Si substrate 51 including diffusion regions 51A and 51B, wherein the substrate 51 is covered with an interlayer insulation film 52 of an undoped SiO2 film corresponding to the SiO2 film 12 of the structure 20A of FIG. 2, and the interlayer insulation film 52 is formed with contact holes 52A and 52B exposing the diffusion regions 51A and 51B respectively. Further, there is formed a low-dielectric interlayer insulation film 53 of an F-doped SiO2 film on th interlayer insulation film 52, wherein the foregoing low-dielectric interlayer insulation film 53 is formed with interconnection grooves 53A and 53B respectively exposing the contact holes 52A and 52B.
  • The contact holes [0079] 52A and 52B are filled with W plugs 52 a and 52 b respectively, while the interconnection grooves 53A and 53B are filled respectively with Cu interconnection patterns 53C and 53D. Between the interlayer insulation film 53 and the underlying interlayer insulation film 52, there is formed an SiN film 53 a used as an etching stopper, and the interlayer insulation film 53 is covered by a high-refractive index SiO2 film 53 b corresponding to the high-refractive index SiO2 film 35 and having a refractive index of preferably 1.49 or higher.
  • It should be noted that the W plugs [0080] 52 a and 52 b are formed by depositing a W layer on the interlayer insulation film 52 so as to fill the contact holes 52A and 52B, followed by a CMP process for removing any residual W layer remaining on the top surface of the interlayer insulation film 52. Similarly, the Cu interconnection patterns 53C and 53D are formed by depositing a Cu layer on the interlayer insulation film 53, more precisely on the high-refractive index SiO2 film 53 b so as to fill the interconnection grooves 53A and 53B, followed by a CMP process-to remove the same from the top surface of the SiO2 film 53 b.
  • On the [0081] interlayer insulation film 53, more precisely on the high-refractive index SiO2 film 53 b, there is formed an interlayer insulation film 54 of F-doped SiO2, with an SiN etching stopper film 54 a interposed between the interlayer insulation film and the high-refractive index SiO2 film 53 b. Further, the interlayer insulation film 54 thus formed is covered with a high-refractive index SiO2 film 54 b similar to the SiO2 film 53 b. On the interlayer insulation film 54, there is further provided an interlayer insulation film 55 of F-doped SiO2, with the high-refractive index SiO2 film 54 b and an SiN etching stopper film 55 a interposed between the interlayer insulation film 55 and the interlayer insulation film 54. Further, the interlayer insulation film 55 is covered by a high-refractive index SiO2 film 55 b similar to the high-refractive index SiO2 film 53 b or 54 b.
  • In the [0082] interlayer insulation film 55 and the high-refractive index SiO2 film 55 b, there are formed interconnection grooves 55A and 55B while using the SiN film 55 a as an etching stopper. Further, contact holes 54A and 54B are formed in the interlayer insulation film 54 and further in the high-refractive index SiO2 film 55B by a dry etching process that is conducted while using the SiN film 55 a as a hard mask. The contact holes 54A and 54B are formed so as to expose the SiN film 54 a, wherein the SiN film 54 a is further subjected to a dry etching process to expose the Cu interconnection patterns 53C and 53D at the contact holes 54A and 54B respectively.
  • The [0083] interlayer insulation film 55, more precisely the high-refractive index SiO2 film 55 b is covered by a Cu layer deposited so as to fill the interconnection grooves 55A and 55B and the contact holes 54A and 54B, followed by a CMP process to remove the residual Cu layer remaining on the top surface of the high-refractive index SiO2 film 55 b. As a result of the CMP process, Cu interconnection patterns 55C and 55D are formed so as to fill the interconnection grooves 55A and 55B and so as to make a contact with the interconnection pattern 53A or 53B via the contact hole 54A or 54B.
  • In the present embodiment, too, a high-refractive index SiO[0084] 2 film such as the SiO2 film 53 b or 54 b is formed adjacent to the F-doped low-dielectric SiO2 film such as the SiO2 film 53, 54 or 55 so that the high-refractive index SiO2 film 53 b or 54 b is interposed between the corresponding SiN film 54 a or 55 a. Thereby, the F ions released from the F-doped SiO2 film 53 or 54 is captured by the high-refractive index SiO2 film 53 b or 54 b, and the problem of accumulation of F under the SiN film 54 a or 55 a is successfully eliminated. Associated with the elimination of the problem of accumulation of F, the semiconductor device 50 shows excellent reliability. The semiconductor device 50 may be any of a logic integrated circuit and a memory integrated circuit such as a DRAM.
    • Third Embodiment
  • FIG. 10 shows the construction of a [0085] DRAM 60 according to a third embodiment of the present invention.
  • Referring to FIG. 8, the [0086] DRAM 60 is constructed on a Si substrate 61 formed with a p-type well 62, wherein the Si substrate 61 is also formed with a field oxide film 63 defining an active region. In the Si substrate 61, there are formed diffusion regions 61A-61C of the n+-type in correspondence to the active region, and a gate electrode 64A is formed on the substrate 61 so as to cover the channel region formed in the active region between the diffusion region 61A and the diffusion region 61B, with a gate insulation film (not shown) interposed between the substrate 61 and the gate electrode 64A. Similarly, another gate electrode 64B is formed on the substrate 61 so as to cover the channel region formed in the active region between the diffusion region 61B and the diffusion region 61C, with a gate insulation film (not shown) interposed between the substrate 61 and the gate electrode 64B. Further, a word line WL similar to the gate electrode 64A or 64B extends over the field oxide film 63.
  • Each of the [0087] gate electrodes 64A and 64B, and also the word line WL, has a pair of side-wall insulation films on the respective side walls thereof, and is further covered by a thin insulation film 64 of SiN, and the like. Further, the insulation film 64 is covered by a planarizing insulation film 65 of CVD-SiO2, and the like, wherein the planarizing insulation film 65 is formed with a contact hole 65A exposing the diffusion region 61B. Further, there is formed a bit line electrode BL on the planarizing insulation film 65 by W or polysilicon, such that the bit line electrode BL makes a contact with the diffusion region 61B at the contact hole 65A.
  • It should be noted that the bit line electrode BL is covered by a [0088] thin insulation film 66 of SiN, and the like, and a planarizing insulation film 67 of a CVD-SiO2 film, and the like, is formed on the insulation film 66. Further, the planarizing insulation film 67 is formed with contact holes 67A and 67B so as to expose the diffusion regions 61A and 61C, and memory cell capacitors C1 and C2 of the stacked-fin type are formed respectively in the contact holes 67A and 67B.
  • Each of the stacked-fin type capacitors C[0089] 1 and C2 includes a polysilicon storage electrode that makes a contact with the diffusion region 61A or 61C at the contact hole 67A or 67B, and a capacitor insulation film covering the polysilicon storage electrode. Further, a polysilicon cell plate 68 covers the capacitor insulation film. The polysilicon cell plate 68, in turn, is covered by a planarizing interlayer insulation film 69.
  • On the planarizing [0090] interlayer insulation film 69, there is formed an interconnection pattern 70, wherein the interconnection pattern 70 includes a barrier layer 70 a having a Ti/TiN structure formed on the interlayer insulation film 69, a conductor pattern 70 b of Al or an Al-alloy formed on the barrier layer 70 a, and an anti-reflection coating (ARC) 70 c of SiON, and the like, formed on the conductor pattern 70 b. The interconnection pattern 70 is covered by an interlayer insulation film 71 of a F-doped, low-dielectric SiO2 film formed on the planarizing interlayer insulation film 69, wherein the interlayer insulation film 71 may contain F with a concentration of about 12 atomic percent and may have a dielectric constant of about 3.4.
  • Further, in the [0091] DRAM 60 of FIG. 8, there is formed a high-refractive index SiO2 film 72 having a refractive index larger than about 1.48, preferably larger than about 1.49, on the interlayer insulation film 71, and a passivation film 73 of SiN is formed on the foregoing high-refractive index SiO2 film 72.
  • In the present embodiment, the accumulation of F under the [0092] passivation film 73 is minimized by interposing the high-refractive index SiO2 film 72 between the F-doped, low-dielectric interlayer insulation film 71 and the dense SiN passivation film 73. Thereby, the exfoliation of the SiN passivation film 73 is effectively avoided.
    • Fourth Embodiment
  • FIG. 11 shows the construction of a [0093] semiconductor device 50A according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
  • Referring to FIG. 11, the [0094] semiconductor device 50A is a modification of the semiconductor device 50 of FIG. 9 in that each of the F-doped SiO2 films 53, 54 and 55 has also an additional high-refractive index SiO2 film 53 c, 54 c or 55 c, such that the additional high-refractive index SiO2 film is formed at the bottom part of the F-doped SiO2 film so as to intervene between the F-doped SiO2 film and the SiN etching stopper layer thereon. For example, the additional high-refractive index SiO2 film 53 c is interposed between the F-doped SiO2 film 53 and the SiN film 53 a thereunder, the additional high-refractive index SiO2 film 54 c is interposed between the F-doped SiO2 film 54 and the underlying SiN etching stopper layer 54 a.
  • Thereby the [0095] SiN film 54 a or 55 a is sandwiched by a pair of high-refractive index SiO2 film, such as the SiO2 film 53 b and the SiO2 film 54 c, and it becomes possible to interrupt the migration of the F ions to the SiN film from both the upward direction and the downward direction. Thereby, the accumulation of the F ions adjacent to the SiN film is effectively eliminated.
    • Fifth Embodiment
  • FIG. 12 shows the construction of a [0096] semiconductor device 50B according to a fifth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
  • Referring to FIG. 12, the [0097] semiconductor device 50B is a modification of the semiconductor device 50A of FIG. 11 in that there is added a further extra high-refractive index SiO2 film between the F-doped SiO2 film and the high-refractive index SiO2 film at the top part of the F-doped SiO2 film, such as an SiO2 film 53 d, 54 d or 55 d. For example, the high-refractive index SiO2 film 53 d is interposed between the F-doped SiO2 film 53 and the high-refractive index SiO2 film 53 b formed at the top part of the F-doped SiO2 film 53.
  • By providing such an additional high-refractive index SiO[0098] 2 film 53 d, it becomes possible to completely block the migration of the F ions to the SiN film 54 a from the underlying F-doped SiO2 film 53. A similar effect is obtained for the additional high-refractive index SiO2 films 54 d and 55 d.
  • Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention. [0099]

Claims (11)

What is claimed is:
1. A semiconductor device, comprising:
a substrate;
an interconnection pattern formed above said substrate;
a F-doped interlayer insulation film covering said interconnection pattern; and
a high-refractive index insulation film having a refractive index higher than a refractive index of said F-doped interlayer insulation film, said high-refractive index insulation film being disposed at least one of a top side and a bottom side of said F-doped interlayer insulation film.
2. A semiconductor device as claimed in
claim 1
, wherein said high-refractive index insulation film comprises an SiO2 film containing therein an excess amount of Si.
3. A semiconductor device as claimed in
claim 1
, wherein said high-refractive index insulation film has a refractive index equal to or larger than about 1.48.
4. A semiconductor device as claimed in
claim 3
, wherein said high-refractive index insulation film has a refractive index equal to or larger than about 1.49.
5. A semiconductor device as claimed in
claim 1
, wherein said interlayer insulation film is covered by a passivation film.
6. A semiconductor device as claimed in
claim 1
, further including another high-refractive index insulation film adjacent to said high-refractive index insulation film, said another high-refractive index insulation film having a refractive index higher than said refractive index of said high-refractive index insulation film.
7. A semiconductor device as claimed in
claim 1
, wherein said F-doped interlayer insulation film includes a first layer having a first concentration level of F and a second layer formed on said first layer and having a second concentration level of F, said second concentration level being smaller than said first concentration level.
8. A method of fabricating a semiconductor device, comprising the steps of:
covering an interconnection pattern with an interlayer insulation film containing therein F and having a first refractive index; and
forming a high-refractive index insulation film on said interlayer insulation film, said high-refractive index insulation film having a second refractive index higher than said first refractive index.
9. A method as claimed in
claim 8
, wherein said step of forming said high-refractive index insulation film includes a plasma CVD process that forms an SiO2 film containing therein an excess amount of Si.
10. A method as claimed in
claim 8
, wherein said step of forming said interlayer insulation film containing therein F is conducted by a plasma CVD process.
11. A method as claimed in
claim 10
, wherein said step of forming-said interlayer insulation film includes: a first step of forming a first insulation film containing therein F under a condition of no substrate biasing; and a second step of forming a second insulation film containing therein F under a condition in which a substrate biasing is used.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187813A1 (en) * 2006-02-10 2007-08-16 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer
US20070190806A1 (en) * 2006-02-10 2007-08-16 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer fabricating method
US20120108059A1 (en) * 2008-08-05 2012-05-03 Rohm Co., Ltd. Method of manufacturing semiconductor device
CN104658967A (en) * 2013-11-21 2015-05-27 中芯国际集成电路制造(上海)有限公司 Semiconductor component and manufacturing method thereof

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057212A (en) * 2000-08-09 2002-02-22 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
US6501180B1 (en) * 2000-07-19 2002-12-31 National Semiconductor Corporation Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
KR100510743B1 (en) * 2000-12-30 2005-08-30 주식회사 하이닉스반도체 Method for fabricating insulation between wire and wire
JP2002252280A (en) 2001-02-26 2002-09-06 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US20020172880A1 (en) * 2001-03-01 2002-11-21 Dainippon Ink And Chemicals, Inc. Dry color toner for electrostatic image development
JP3780189B2 (en) 2001-09-25 2006-05-31 富士通株式会社 Semiconductor device manufacturing method and semiconductor device
US7208426B2 (en) * 2001-11-13 2007-04-24 Chartered Semiconductors Manufacturing Limited Preventing plasma induced damage resulting from high density plasma deposition
US6902960B2 (en) * 2002-11-14 2005-06-07 Sharp Laboratories Of America, Inc. Oxide interface and a method for fabricating oxide thin films
US6939792B1 (en) * 2003-03-28 2005-09-06 Cypress Semiconductor Corporation Low-k dielectric layer with overlying adhesion layer
US10553479B2 (en) 2017-02-16 2020-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with contact pad and fabrication method therefore
WO2019097573A1 (en) * 2017-11-14 2019-05-23 三菱電機株式会社 Semiconductor apparatus and method for manufacturing same
US11670559B2 (en) 2020-03-27 2023-06-06 Samsung Electronics Co., Ltd. Semiconductor device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62193265A (en) * 1986-02-20 1987-08-25 Toshiba Corp Manufacture of semiconductor device
JP3092185B2 (en) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 Method for manufacturing semiconductor device
JPH0555391A (en) * 1991-08-29 1993-03-05 Ricoh Co Ltd Forming method of interlayer insulating film and multilayer interconnection device
JP2901211B2 (en) * 1991-09-24 1999-06-07 松下電子工業株式会社 Method for manufacturing semiconductor device
JP3093429B2 (en) * 1992-04-28 2000-10-03 日本電気株式会社 Method for manufacturing semiconductor device
US5753564A (en) * 1992-11-24 1998-05-19 Sumitomo Metal Industries, Ltd. Method for forming a thin film of a silicon oxide on a silicon substrate, by BCR plasma
JP3381104B2 (en) 1994-10-27 2003-02-24 ソニー株式会社 Etching method for etching material to be etched containing F-containing material
JPH08148559A (en) * 1994-11-15 1996-06-07 Fujitsu Ltd Manufacture of semiconductor device with insulation film
JPH08148562A (en) 1994-11-18 1996-06-07 Oki Electric Ind Co Ltd Semiconductor device and its manufacture
US5804498A (en) * 1995-06-23 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making an underlayer to reduce pattern sensitivity of ozone-TEOS
JP3979687B2 (en) * 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド Method for improving film stability of halogen-doped silicon oxide films
KR100228348B1 (en) * 1996-06-28 1999-11-01 김영환 Semiconductor apparatus and its fabricating method
US5716890A (en) * 1996-10-18 1998-02-10 Vanguard International Semiconductor Corporation Structure and method for fabricating an interlayer insulating film
US6277730B1 (en) * 1998-02-17 2001-08-21 Matsushita Electronics Corporation Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers
TW441006B (en) * 1998-05-18 2001-06-16 United Microelectronics Corp Method of forming inter-metal dielectric layer
US6159872A (en) * 1998-09-03 2000-12-12 National Semiconductor Corporation F ion implantation into oxide films to form low-K intermetal dielectric
US6028013A (en) * 1999-05-06 2000-02-22 Vlsi Technology, Inc. Moisture repellant integrated circuit dielectric material combination

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187813A1 (en) * 2006-02-10 2007-08-16 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer
US20070190806A1 (en) * 2006-02-10 2007-08-16 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer fabricating method
US7662712B2 (en) * 2006-02-10 2010-02-16 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer fabricating method
US7755197B2 (en) 2006-02-10 2010-07-13 Macronix International Co., Ltd. UV blocking and crack protecting passivation layer
US20120108059A1 (en) * 2008-08-05 2012-05-03 Rohm Co., Ltd. Method of manufacturing semiconductor device
US8647984B2 (en) * 2008-08-05 2014-02-11 Rohm Co., Ltd. Method of manufacturing semiconductor device
CN104658967A (en) * 2013-11-21 2015-05-27 中芯国际集成电路制造(上海)有限公司 Semiconductor component and manufacturing method thereof

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US6211570B1 (en) 2001-04-03
TW425631B (en) 2001-03-11

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