US20010004132A1 - Method and an arrangement relating to chip carriers - Google Patents
Method and an arrangement relating to chip carriers Download PDFInfo
- Publication number
- US20010004132A1 US20010004132A1 US09/736,321 US73632100A US2001004132A1 US 20010004132 A1 US20010004132 A1 US 20010004132A1 US 73632100 A US73632100 A US 73632100A US 2001004132 A1 US2001004132 A1 US 2001004132A1
- Authority
- US
- United States
- Prior art keywords
- chip
- electrically
- thermally conductive
- dielectric layer
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present invention relates to methods and apparatus pertaining to microwave chip carriers.
- microwave chips are used for an increasing number of technical functions in microwave technology, such as amplifiers, mixers, frequency multipliers, etc., and it is not unusual to incorporate several functions in one single microwave chip.
- the microwave chips are less expensive, smaller and lighter in weight than traditional devices. Consequently, the microwave chip is well suited for use in many modern technical applications, for instance in aircraft electronics, radar, miniantennas, base stations, radio links, and so on.
- the microwave chip is constructed around a dielectric substrate that has semiconductor components disposed on its upper surface.
- the semiconductor components are normally connected with microstrip conductors (or coplanar conductors).
- the microstrip conductors include signal conductors disposed on the upper side of the substrate, and an electrically conductive element that is adapted to define an earth plane for the signal conductors on the underside of the substrate.
- the microwave chip is normally very small (about 2-10 (mm) 2 ) and thin (about 0.1 mm).
- the microwave chips are normally disposed on a chip carrier, said carrier normally including a carrier element in the form of a piece of material that has context-suitable properties.
- the microchip is mounted on a surface of the carrier element by means of an electrically conductive bonding substance, such as solder or glue.
- the carrier provides mechanical support for the chip.
- the carrier also enables heat to be conducted from the microwave chip to a cooling sink more effectively, for instance.
- the carrier also often forms an earth potential for the earth plane of the chip. Normally, the carrier is much larger than the chip, so as to provide space for elements required to connect the chip to peripheral equipment.
- the carrier element will preferably consist of material that will conduct heat and current effectively. Magnet carrying ferrite cylinders are often disposed on the carrier.
- the thermal expansion of the carrier element will also preferably be adapted to the thermal expansion of the microwave chip mounted on the carrier.
- Typical carrier element materials are, for instance, copper-tungsten (CuW), copper-molybdenum (CuMo) and aluminium-silicon carbide (AlSiC), these materials being suitable for microwave chips in gallium-arsenide; or aluminium-nitride (AlN), which is suitable for silicon microwave chips.
- the known technology for mounting microwave chips on chip carriers has certain drawbacks.
- the bonding substance forms an impedance which gives rise to an undesirable potential difference (earth fault) between the earth plane of the microwave chip and the earth potential of the carrier element.
- the materials used in chip carriers are often very expensive—it is not unusual for the chip carrier to cost up to 50% of the cost of the actual microwave chip.
- This high chip carrier cost has not earlier been considered a significant drawback, as the microwave chips obtain significant advantages in comparison with traditional techniques.
- the rapid development in technology and the increasing competition within this technical field, however, has meant that the high costs of the chip carriers must now be considered to constitute a burdensome drawback.
- the problem mainly addressed by the present invention resides in providing method and means that will enable microwave chips to be mounted on chip carriers in a manner that will reduce an earth fault between the microwave chip and a chip carrier to a minimum.
- the microwave chip is mounted on a chip carrier that includes an electrically and thermally conductive element in which a recess is provided relative to a surface of said element.
- the microwave chip is bonded or fastened to the surface of the electrically and thermally conductive element by means of a bonding substance that is disposed at least partially in the recess.
- the chip is positioned so that a chip earth plane will be level with the surface of the electrically and thermally conductive element. The distance between the earth plane and the surface is therefore very small, and consequently no earth fault will occur between the earth plane and said surface.
- an aim of the present invention is to enable microwave chips to be mounted on chip carriers so that no earth fault will occur, this aim being achieved with methods and arrangements according to the invention.
- a main advantage obtained when mounting chips in the aforesaid manner is that the occurrence of earth faults is avoided.
- Another advantage is that heat dissipation from the microwave chip is made more effective to some extent, due to the increase in the contact surface area between the bonding substance and the electrically and thermally conductive element provided by the recess.
- the electrically and thermally conductive element is comprised of a layer of copper or gold, as is preferred, the bonding substance will be solder or glue, for example.
- the present invention also addresses the further problem of providing a chip carrier that can be produced simply and inexpensively and that is also suitable for the aforesaid mounting process.
- a chip carrier that includes at least a first surface on which a dielectric layer is disposed such as to contribute in forming a pit on the first surface.
- An electrically and thermally conductive layer is arranged on the dielectric layer and in the pit such that the electrically and thermally conductive layer will obtain a surface in relation to which there is arranged a recess in connection with the pit.
- a further aim of the invention is therefore to provide a chip carrier which is suited to said mounting process and which can be produced readily and inexpensively, wherein the invention also includes a method of producing such a chip carrier.
- the carrier element may consist of a sheet of brass, aluminium or material that has similar properties and price.
- the dielectric layer is comprised, for instance, of photosensitive material that is laminated on the carrier element, wherewith the pit is suitably obtained by providing an opening in the dielectric layer.
- the opening, or cut-out, may be obtained by treating the dielectric layer photochemically.
- the electrically and thermally conductive layer may be comprised of copper or gold that has been panel-plated on top of the dielectric layer, for instance.
- the chip carrier is that it is suited to the aforesaid mounting process, and that it is relatively inexpensive and easy to manufacture.
- FIG. 1 is a cross-sectional view of an exemplifying embodiment of an inventive chip carrier adapted to carry a microwave chip.
- FIGS. 2 ( a - e ) are perspective views of the various stages in the manufacture of a chip carrier and illustrate mounting of microchips on the manufactured chip carrier.
- FIG. 1 is a cross-sectional view of an exemplifying embodiment of an inventive chip carrier 1 which is intended to carry a microchip 3 .
- the carrier 1 includes a carrier element 5 of relatively good thermal conductivity (about 80 W/mK and higher).
- the carrier element 5 of the illustrated embodiment comprises a metal plate, for instance made of brass, aluminium or some other relatively cheap metal alloy or metal.
- the carrier element 5 includes a generally planar surface 7 (the upper side of the element 5 shown in FIG. 1) on which there is disposed a layer 9 of dielectric material.
- the dielectric layer 9 includes a through-penetrating, rectangular aperture 8 which, together with the surface 7 of the carrier element, forms a pit 11 .
- a layer of material 13 that has a high electrically and thermally conductive capacity is disposed on top of the dielectric layer 9 .
- the electrically and thermally conductive material is, for instance, a metal that is suitable to this end, such as copper or gold.
- the layer 13 has a generally constant thickness and is also disposed in the pit 11 .
- the size, shape and depth of the recess 15 is determined by the size, shape and depth of the pit 11 and also by the thickness of the layer 13 .
- the microwave chip 3 includes a dielectric substance 3 a that has a first side (the upper side in FIG.
- a metal layer 3 c is disposed on a second side of the substrate 3 a , the underside in FIG. 1.
- the side of the metal layer 3 c that lies proximal to the component layer 3 b (the upper side in FIG. 1) defines an earth plane 3 b for the signal conductors in the component layer 3 b.
- the microwave chip 3 is fastened to the layer 13 by means of a bonding substance or fixing agent 19 , which may be solder or glue, for instance.
- the bonding substance 19 is disposed in the recess 15 and the microwave chip 3 is disposed in the recess such that the earth plane 3 d will lie level with the surface 17 of the layer 13 (its upper surface), in other words the earth plane 3 d lies in the same plane as the surface 17 .
- the earth plane 3 d is level with the surface 17 on the layer 13 , practically no earth fault will occur between the microwave chip 3 and the layer 13 , since any conductive path through the bonding substance 19 between the surface 17 and the earth plane 3 d will be very short. This is particularly beneficial in respect of microwave chips for high frequencies (frequencies of about 38 GHz and higher).
- the layer 13 forms a link in a heat dissipating cooling chain that effectively conducts heat away from the microwave chip 3 .
- cooling sinks such as cooling fins, cooling rods, coolant-filled channels or equivalent devices may be connected to the layer 13 or to the carrier element 5 , so as to further enhance the dissipation of heat from the microwave chip 3 .
- a sheet 23 of dielectric material is disposed on top of the layer 13 .
- Mask work, pads (i.e. solder for wire-bonding connection surfaces), decoupling capacitors and any other surface-mounted components (not shown) required to connect the microwave chip 3 electrically to surrounding equipment are disposed on the dielectric layer 23 .
- the dielectric layer 23 is adapted so that its upper surface will be level with the upper surface of the microwave chip 3 and therewith enable electrical connection of the microwave chip 3 to be achieved readily and inexpensively (minimises material consumption).
- the chip carrier 1 includes an block 25 which is let into the carrier element 5 beneath the pit 11 and secured to said element by means of glue, solder or some equivalent substance disposed on the underside and the edges of the block 25 .
- Epoxy resin and thermoplastic adhesives are suitable glues for securing the insert 25 .
- the block 25 is inserted so that one surface of the block (the upper side of the block 25 in FIG. 1) will form a part of the surface 7 on which the dielectric layer 9 is disposed.
- the block 25 is made of a material whose coefficient of thermal expansion corresponds generally to the coefficient of thermal expansion of the microwave chip 3 .
- the intention of the block 25 is to cause thermal expansion of the carrier 1 to accompany thermal expansion of the microwave chip 3 , so as to reduce the risk of harmful thermal stresses occurring in the microwave chip 3 .
- the block 25 is much larger than the pit 11 and the microwave chip 3 , and the dielectric layer 9 and the electrically and thermally conductive layer 13 are relatively thin, so that thermal expansion of the carrier 1 in an area around the microwave chip 3 will be determined essentially by the thermal expansion of the block 25 .
- the dielectric layer 9 and the electrically and thermally conductive layer 13 will suitably have thicknesses of about 20 ⁇ m.
- the coefficient of thermal expansion ⁇ of microwave chips typically lies in a range of from about 1 ppm/C.° to about 10 ppm/C.° ( ⁇ 3 ppm/C.° in the case of silicon chips while ⁇ 6.5 ppm/C.° in respect of gallium-arsenide chips).
- a copper-molybdenum alloy is a suitable choice of material for the block 25 , where the copper and molybdenum end-parts are selected so that the block 25 will obtain an appropriate coefficient of thermal expansion while taking into account the type of chip for which the carrier 1 is intended.
- the block 25 may alternatively have some other material composition, for instance an aluminium-silicon (AlSi), aluminium-nitride (AlN) or a copper-tungsten (CuW) composition.
- the block 25 is excluded and the whole of the carrier element 5 is, instead, made of a material whose coefficient of thermal expansion corresponds generally to the coefficient of thermal expansion of the microwave chip 3 . Because such materials are normally quite expensive, the embodiment of FIG. 1 that includes the block 25 is normally preferred from a cost aspect.
- FIGS. 2 are perspective views showing various stages in the manufacturing process.
- the method, or process is begun by selecting the carrier element 5 (see FIG. 2 a ) with the inserted block 25 .
- the method is continued by laminating the dielectric layer 9 on the planar surface 7 of the carrier element 5 (see FIG. 2 b ).
- the dielectric layer 7 is comprised of a photosensitive material, for instance the photosensitive epoxy varnish retailed by the company Cibas under the trade name Probilek.
- the photosensitive dielectric layer 7 is exposed on a surface where the opening or aperture 8 shall be obtained. Development is then effected so that the opening 8 , and therewith also the pit 11 , are formed (see FIG. 2 c ).
- the opening 8 can be obtained in some other way, for instance by laser treatment of the dielectric layer 9 (burning away the layer).
- the electrically and thermally conductive layer 13 is conveniently formed by metal plating, e.g. copper plating, the dielectric layer 9 and the pit 11 (see FIG. 2 d ).
- the recess 15 is therewith also obtained in the surface 17 (the upper side) of the electrically and thermally conductive layer 13 in connection with the pit 11 .
- the entire electrically and thermally conductive layer 13 is plated at once, with the aid of a so-called panel-plating process.
- the microwave chip 3 When mounting the microwave chip 3 (see FIG. 2 e ), the microwave chip 3 is fastened to the electrically and thermally conductive layer 13 with the aid of a bonding substance 19 disposed in the recess 15 . It is ensured at this stage that the earth plane 3 d of the microwave chip 3 is level with the surface 17 of the layer 13 .
- the chip carrier 1 can be used in mounting all forms of microwave chips. The higher the frequency, the more important it is to avoid earth faults, since the earth potential is then local and the distance to correct earth therefore of decisive significance.
- the carrier 1 is therefore particularly beneficial for mounting microwave chips for frequencies of from about 40 GHz and higher
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
- The present invention relates to methods and apparatus pertaining to microwave chip carriers.
- Large and heavy equipment, such as waveguides, mixers, amplifiers, etc., were often earlier used in microwave technology. However, developments in semiconductor technology have enabled microwave functions for frequencies of about 2 GHz and higher frequencies to be implemented at present with components on integrated microwave chips, for instance with the aid of semiconductor processing techniques and materials such as gallium-arsenide (GaAS) and silicon (Si). Microwave chips are used for an increasing number of technical functions in microwave technology, such as amplifiers, mixers, frequency multipliers, etc., and it is not unusual to incorporate several functions in one single microwave chip. The microwave chips are less expensive, smaller and lighter in weight than traditional devices. Consequently, the microwave chip is well suited for use in many modern technical applications, for instance in aircraft electronics, radar, miniantennas, base stations, radio links, and so on.
- The microwave chip is constructed around a dielectric substrate that has semiconductor components disposed on its upper surface. The semiconductor components are normally connected with microstrip conductors (or coplanar conductors). The microstrip conductors include signal conductors disposed on the upper side of the substrate, and an electrically conductive element that is adapted to define an earth plane for the signal conductors on the underside of the substrate. The microwave chip is normally very small (about 2-10 (mm)2) and thin (about 0.1 mm).
- The microwave chips are normally disposed on a chip carrier, said carrier normally including a carrier element in the form of a piece of material that has context-suitable properties. The microchip is mounted on a surface of the carrier element by means of an electrically conductive bonding substance, such as solder or glue.
- There are several reasons for mounting microwave chips on chip carriers. One reason is because the carrier provides mechanical support for the chip. The carrier also enables heat to be conducted from the microwave chip to a cooling sink more effectively, for instance. The carrier also often forms an earth potential for the earth plane of the chip. Normally, the carrier is much larger than the chip, so as to provide space for elements required to connect the chip to peripheral equipment.
- Thus, the carrier element will preferably consist of material that will conduct heat and current effectively. Magnet carrying ferrite cylinders are often disposed on the carrier. The thermal expansion of the carrier element will also preferably be adapted to the thermal expansion of the microwave chip mounted on the carrier. Typical carrier element materials are, for instance, copper-tungsten (CuW), copper-molybdenum (CuMo) and aluminium-silicon carbide (AlSiC), these materials being suitable for microwave chips in gallium-arsenide; or aluminium-nitride (AlN), which is suitable for silicon microwave chips.
- However, the known technology for mounting microwave chips on chip carriers has certain drawbacks. When the microwave chip is bonded to the carrier elements, the bonding substance forms an impedance which gives rise to an undesirable potential difference (earth fault) between the earth plane of the microwave chip and the earth potential of the carrier element. Furthermore, the materials used in chip carriers are often very expensive—it is not unusual for the chip carrier to cost up to 50% of the cost of the actual microwave chip. This high chip carrier cost has not earlier been considered a significant drawback, as the microwave chips obtain significant advantages in comparison with traditional techniques. The rapid development in technology and the increasing competition within this technical field, however, has meant that the high costs of the chip carriers must now be considered to constitute a burdensome drawback.
- The problem mainly addressed by the present invention resides in providing method and means that will enable microwave chips to be mounted on chip carriers in a manner that will reduce an earth fault between the microwave chip and a chip carrier to a minimum.
- In brief, this problem is solved in the following manner. The microwave chip is mounted on a chip carrier that includes an electrically and thermally conductive element in which a recess is provided relative to a surface of said element. The microwave chip is bonded or fastened to the surface of the electrically and thermally conductive element by means of a bonding substance that is disposed at least partially in the recess. The chip is positioned so that a chip earth plane will be level with the surface of the electrically and thermally conductive element. The distance between the earth plane and the surface is therefore very small, and consequently no earth fault will occur between the earth plane and said surface.
- Thus, an aim of the present invention is to enable microwave chips to be mounted on chip carriers so that no earth fault will occur, this aim being achieved with methods and arrangements according to the invention.
- Thus, a main advantage obtained when mounting chips in the aforesaid manner is that the occurrence of earth faults is avoided. Another advantage is that heat dissipation from the microwave chip is made more effective to some extent, due to the increase in the contact surface area between the bonding substance and the electrically and thermally conductive element provided by the recess.
- More explicitly, the aforesaid problem is solved in accordance with specific embodiments. For instance, if the electrically and thermally conductive element is comprised of a layer of copper or gold, as is preferred, the bonding substance will be solder or glue, for example.
- The present invention also addresses the further problem of providing a chip carrier that can be produced simply and inexpensively and that is also suitable for the aforesaid mounting process.
- In brief, this further problem is solved with a chip carrier that includes at least a first surface on which a dielectric layer is disposed such as to contribute in forming a pit on the first surface. An electrically and thermally conductive layer is arranged on the dielectric layer and in the pit such that the electrically and thermally conductive layer will obtain a surface in relation to which there is arranged a recess in connection with the pit.
- A further aim of the invention is therefore to provide a chip carrier which is suited to said mounting process and which can be produced readily and inexpensively, wherein the invention also includes a method of producing such a chip carrier.
- More explicitly, this further problem is solved by specific embodiments. For example, the carrier element may consist of a sheet of brass, aluminium or material that has similar properties and price. The dielectric layer is comprised, for instance, of photosensitive material that is laminated on the carrier element, wherewith the pit is suitably obtained by providing an opening in the dielectric layer. The opening, or cut-out, may be obtained by treating the dielectric layer photochemically. The electrically and thermally conductive layer may be comprised of copper or gold that has been panel-plated on top of the dielectric layer, for instance.
- The main advantages afforded by the chip carrier is that it is suited to the aforesaid mounting process, and that it is relatively inexpensive and easy to manufacture.
- The invention will now be described in further detail with reference to exemplifying embodiments thereof and also with reference to the accompanying drawings.
- FIG. 1 is a cross-sectional view of an exemplifying embodiment of an inventive chip carrier adapted to carry a microwave chip.
- FIGS.2(a-e) are perspective views of the various stages in the manufacture of a chip carrier and illustrate mounting of microchips on the manufactured chip carrier.
- FIG. 1 is a cross-sectional view of an exemplifying embodiment of an inventive chip carrier1 which is intended to carry a
microchip 3. The carrier 1 includes acarrier element 5 of relatively good thermal conductivity (about 80 W/mK and higher). Thecarrier element 5 of the illustrated embodiment comprises a metal plate, for instance made of brass, aluminium or some other relatively cheap metal alloy or metal. Thecarrier element 5 includes a generally planar surface 7 (the upper side of theelement 5 shown in FIG. 1) on which there is disposed alayer 9 of dielectric material. Thedielectric layer 9 includes a through-penetrating,rectangular aperture 8 which, together with thesurface 7 of the carrier element, forms apit 11. A layer ofmaterial 13 that has a high electrically and thermally conductive capacity is disposed on top of thedielectric layer 9. The electrically and thermally conductive material is, for instance, a metal that is suitable to this end, such as copper or gold. In the illustrated case, thelayer 13 has a generally constant thickness and is also disposed in thepit 11. There is therefore formed in a surface 17 (the upper side of thelayer 13 in FIG. 1) of the layer 13 arecess 15 in connection with thepit 11. The size, shape and depth of therecess 15 is determined by the size, shape and depth of thepit 11 and also by the thickness of thelayer 13. Themicrowave chip 3 includes adielectric substance 3 a that has a first side (the upper side in FIG. 1) on which there is disposed acomponent layer 3 b that includes semiconductor components and signal conductors (not shown) . Ametal layer 3 c is disposed on a second side of thesubstrate 3 a, the underside in FIG. 1. The side of themetal layer 3 c that lies proximal to thecomponent layer 3 b (the upper side in FIG. 1) defines anearth plane 3 b for the signal conductors in thecomponent layer 3 b. - The
microwave chip 3 is fastened to thelayer 13 by means of a bonding substance or fixingagent 19, which may be solder or glue, for instance. In the illustrated case, thebonding substance 19 is disposed in therecess 15 and themicrowave chip 3 is disposed in the recess such that theearth plane 3 d will lie level with thesurface 17 of the layer 13 (its upper surface), in other words theearth plane 3 d lies in the same plane as thesurface 17. When theearth plane 3 d is level with thesurface 17 on thelayer 13, practically no earth fault will occur between themicrowave chip 3 and thelayer 13, since any conductive path through thebonding substance 19 between thesurface 17 and theearth plane 3 d will be very short. This is particularly beneficial in respect of microwave chips for high frequencies (frequencies of about 38 GHz and higher). - Together with the
carrier element 5, thelayer 13 forms a link in a heat dissipating cooling chain that effectively conducts heat away from themicrowave chip 3. Alternatively, cooling sinks, such as cooling fins, cooling rods, coolant-filled channels or equivalent devices may be connected to thelayer 13 or to thecarrier element 5, so as to further enhance the dissipation of heat from themicrowave chip 3. When thebonding substance 19 is disposed in therecess 15, a slightly larger contact surface is obtained between the bondingsubstance 19 and the layer 13 (as compared with abonding substance 19 that is placed directly on thesurface 17 of thelayer 13, as in the case of conventional chip mounting processes), therewith increasing the dissipation of heat from themicrowave chip 3 to some extent. - A
sheet 23 of dielectric material is disposed on top of thelayer 13. Mask work, pads (i.e. solder for wire-bonding connection surfaces), decoupling capacitors and any other surface-mounted components (not shown) required to connect themicrowave chip 3 electrically to surrounding equipment are disposed on thedielectric layer 23. Thedielectric layer 23 is adapted so that its upper surface will be level with the upper surface of themicrowave chip 3 and therewith enable electrical connection of themicrowave chip 3 to be achieved readily and inexpensively (minimises material consumption). - The chip carrier1 includes an
block 25 which is let into thecarrier element 5 beneath thepit 11 and secured to said element by means of glue, solder or some equivalent substance disposed on the underside and the edges of theblock 25. Epoxy resin and thermoplastic adhesives are suitable glues for securing theinsert 25. However, it will preferably be ensured that the properties of the glue used will not have any deleterious effect on thedielectric layer 9. In the illustrated embodiment, theblock 25 is inserted so that one surface of the block (the upper side of theblock 25 in FIG. 1) will form a part of thesurface 7 on which thedielectric layer 9 is disposed. Theblock 25 is made of a material whose coefficient of thermal expansion corresponds generally to the coefficient of thermal expansion of themicrowave chip 3. The intention of theblock 25 is to cause thermal expansion of the carrier 1 to accompany thermal expansion of themicrowave chip 3, so as to reduce the risk of harmful thermal stresses occurring in themicrowave chip 3. In one preferred embodiment of the invention, theblock 25 is much larger than thepit 11 and themicrowave chip 3, and thedielectric layer 9 and the electrically and thermallyconductive layer 13 are relatively thin, so that thermal expansion of the carrier 1 in an area around themicrowave chip 3 will be determined essentially by the thermal expansion of theblock 25. Thedielectric layer 9 and the electrically and thermallyconductive layer 13 will suitably have thicknesses of about 20 μm. - The coefficient of thermal expansion α of microwave chips typically lies in a range of from about 1 ppm/C.° to about 10 ppm/C.° (α≈3 ppm/C.° in the case of silicon chips while α≈ 6.5 ppm/C.° in respect of gallium-arsenide chips). In this context, a copper-molybdenum alloy is a suitable choice of material for the
block 25, where the copper and molybdenum end-parts are selected so that theblock 25 will obtain an appropriate coefficient of thermal expansion while taking into account the type of chip for which the carrier 1 is intended. However, theblock 25 may alternatively have some other material composition, for instance an aluminium-silicon (AlSi), aluminium-nitride (AlN) or a copper-tungsten (CuW) composition. - In the case of an alternative to the embodiment of FIG. 1, the
block 25 is excluded and the whole of thecarrier element 5 is, instead, made of a material whose coefficient of thermal expansion corresponds generally to the coefficient of thermal expansion of themicrowave chip 3. Because such materials are normally quite expensive, the embodiment of FIG. 1 that includes theblock 25 is normally preferred from a cost aspect. - There will now be described by way of example an inventive method suitable for the manufacture of the chip carrier1 shown in FIG. 1. The method is described with reference to FIGS. 2(a-e), which are perspective views showing various stages in the manufacturing process.
- The method, or process, is begun by selecting the carrier element5 (see FIG. 2a) with the inserted
block 25. The method is continued by laminating thedielectric layer 9 on theplanar surface 7 of the carrier element 5 (see FIG. 2b). In a preferred embodiment of the invention, thedielectric layer 7 is comprised of a photosensitive material, for instance the photosensitive epoxy varnish retailed by the company Cibas under the trade name Probilek. Thephotosensitive dielectric layer 7 is exposed on a surface where the opening oraperture 8 shall be obtained. Development is then effected so that theopening 8, and therewith also thepit 11, are formed (see FIG. 2c). Alternatively, theopening 8 can be obtained in some other way, for instance by laser treatment of the dielectric layer 9 (burning away the layer). The electrically and thermallyconductive layer 13 is conveniently formed by metal plating, e.g. copper plating, thedielectric layer 9 and the pit 11 (see FIG. 2d). Therecess 15 is therewith also obtained in the surface 17 (the upper side) of the electrically and thermallyconductive layer 13 in connection with thepit 11. In a preferred embodiment of the invention, the entire electrically and thermallyconductive layer 13 is plated at once, with the aid of a so-called panel-plating process. - When mounting the microwave chip3 (see FIG. 2e), the
microwave chip 3 is fastened to the electrically and thermallyconductive layer 13 with the aid of abonding substance 19 disposed in therecess 15. It is ensured at this stage that theearth plane 3 d of themicrowave chip 3 is level with thesurface 17 of thelayer 13. - Manufacture of the chip carrier1 is both simple and inexpensive. Well known processes (lamination, photochemical treatment, panel-plating, etc.) suitable for mass production can be used in the manufacture. The inserted
block 25 enables the consumption of expensive material to be reduced, with no negative effect on the properties of the carrier 1. Standardised blocks are also available, therewith limiting costs still further as a result of avoiding special manufacture of the blocks. - The chip carrier1 can be used in mounting all forms of microwave chips. The higher the frequency, the more important it is to avoid earth faults, since the earth potential is then local and the distance to correct earth therefore of decisive significance. The carrier 1 is therefore particularly beneficial for mounting microwave chips for frequencies of from about 40 GHz and higher
Claims (28)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9904653A SE517916C2 (en) | 1999-12-17 | 1999-12-17 | Chip carriers, systems and procedures in the manufacture of chip carriers |
SE9904653-4 | 1999-12-17 | ||
SE9904653 | 1999-12-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010004132A1 true US20010004132A1 (en) | 2001-06-21 |
US6433423B2 US6433423B2 (en) | 2002-08-13 |
Family
ID=20418189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/736,321 Expired - Lifetime US6433423B2 (en) | 1999-12-17 | 2000-12-15 | Method and an arrangement relating to chip carriers |
Country Status (4)
Country | Link |
---|---|
US (1) | US6433423B2 (en) |
AU (1) | AU2240401A (en) |
SE (1) | SE517916C2 (en) |
WO (1) | WO2001045480A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6563198B1 (en) * | 2001-08-01 | 2003-05-13 | Lsi Logic Corporation | Adhesive pad having EMC shielding characteristics |
US6841736B2 (en) * | 2002-09-26 | 2005-01-11 | Motorola, Inc. | Current-carrying electronic component and method of manufacturing same |
US20070102826A1 (en) * | 2002-04-09 | 2007-05-10 | Infineon Technologies Ag | Electronic Component Having at Least One Semiconductor Chip and Flip-Chip Contacts, and Method for Producing the Same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7199305B2 (en) * | 2002-08-08 | 2007-04-03 | Nanoink, Inc. | Protosubstrates |
US8431438B2 (en) * | 2010-04-06 | 2013-04-30 | Intel Corporation | Forming in-situ micro-feature structures with coreless packages |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62229987A (en) * | 1986-03-31 | 1987-10-08 | Koito Mfg Co Ltd | Illuminator |
US5014114A (en) * | 1988-09-30 | 1991-05-07 | Harris Corporation | High speed, high density semiconductor memory package with chip level repairability |
US4990719A (en) * | 1989-07-13 | 1991-02-05 | Gte Products Corporation | Hermetically sealed chip carrier with metal cover having pre-poured glass window |
US5012386A (en) * | 1989-10-27 | 1991-04-30 | Motorola, Inc. | High performance overmolded electronic package |
GB9000264D0 (en) * | 1990-01-05 | 1990-03-07 | Int Computers Ltd | Circuit packaging |
US5258575A (en) * | 1990-05-07 | 1993-11-02 | Kyocera America, Inc. | Ceramic glass integrated circuit package with integral ground and power planes |
US5151769A (en) * | 1991-04-04 | 1992-09-29 | General Electric Company | Optically patterned RF shield for an integrated circuit chip for analog and/or digital operation at microwave frequencies |
US5783857A (en) * | 1996-07-25 | 1998-07-21 | The Whitaker Corporation | Integrated circuit package |
US6245442B1 (en) * | 1997-05-28 | 2001-06-12 | Kabushiki Kaisha Toyota Chuo | Metal matrix composite casting and manufacturing method thereof |
SE518572C2 (en) * | 1997-08-25 | 2002-10-22 | Ericsson Telefon Ab L M | Carrier element for a chip and chip module |
US6198163B1 (en) * | 1999-10-18 | 2001-03-06 | Amkor Technology, Inc. | Thin leadframe-type semiconductor package having heat sink with recess and exposed surface |
-
1999
- 1999-12-17 SE SE9904653A patent/SE517916C2/en not_active IP Right Cessation
-
2000
- 2000-11-30 AU AU22404/01A patent/AU2240401A/en not_active Abandoned
- 2000-11-30 WO PCT/SE2000/002394 patent/WO2001045480A1/en active Application Filing
- 2000-12-15 US US09/736,321 patent/US6433423B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6563198B1 (en) * | 2001-08-01 | 2003-05-13 | Lsi Logic Corporation | Adhesive pad having EMC shielding characteristics |
US20070102826A1 (en) * | 2002-04-09 | 2007-05-10 | Infineon Technologies Ag | Electronic Component Having at Least One Semiconductor Chip and Flip-Chip Contacts, and Method for Producing the Same |
US6841736B2 (en) * | 2002-09-26 | 2005-01-11 | Motorola, Inc. | Current-carrying electronic component and method of manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
US6433423B2 (en) | 2002-08-13 |
SE9904653D0 (en) | 1999-12-17 |
SE9904653L (en) | 2001-06-18 |
AU2240401A (en) | 2001-06-25 |
WO2001045480A1 (en) | 2001-06-21 |
SE517916C2 (en) | 2002-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5352926A (en) | Flip chip package and method of making | |
TW558921B (en) | Structure and method for fabrication of a leadless chip carrier with embedded inductor | |
US6156980A (en) | Flip chip on circuit board with enhanced heat dissipation and method therefor | |
US6455925B1 (en) | Power transistor package with integrated flange for surface mount heat removal | |
US7445968B2 (en) | Methods for integrated circuit module packaging and integrated circuit module packages | |
US7005734B2 (en) | Double-sided cooling isolated packaged power semiconductor device | |
US11114363B2 (en) | Electronic package arrangements and related methods | |
US20100019361A1 (en) | Multi Lead Frame Power Package | |
US6414847B1 (en) | Integral dielectric heatspreader | |
EP2398302B1 (en) | Semiconductor device | |
US5901042A (en) | Package and semiconductor device | |
US6433423B2 (en) | Method and an arrangement relating to chip carriers | |
US7586194B2 (en) | Semiconductor device having exposed heat dissipating metal plate | |
CN114762462A (en) | PCB for bare wafer mounting and processing method thereof | |
US20080036049A1 (en) | Stacked integration module and method for manufacturing the same | |
KR100957079B1 (en) | Power device with a plastic molded package and direct bonded substrate | |
JP2003204021A (en) | Substrate for semiconductor module | |
US11521921B2 (en) | Semiconductor device package assemblies and methods of manufacture | |
JP2833592B2 (en) | Semiconductor container | |
JP2856192B2 (en) | Semiconductor device | |
GB2307596A (en) | Radio communications module | |
TW432649B (en) | A heat sink | |
JPH04213863A (en) | Ic mounting package/carrier | |
KR20010057046A (en) | Package substrate having cavity | |
JP3022738B2 (en) | Multi-chip module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), SWEDEN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BERGSTEDT, LEIF;NILSSON, TORBJORN;REEL/FRAME:011371/0091;SIGNING DATES FROM 20001106 TO 20001107 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC (AS COLLATERA Free format text: LIEN;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:031866/0697 Effective date: 20131219 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION (AS COLLATE Free format text: SECURITY AGREEMENT;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:032167/0406 Effective date: 20131219 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CLUSTER LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TELEFONAKTIEBOLAGET L M ERICSSON (PUBL);REEL/FRAME:032326/0219 Effective date: 20131219 Owner name: OPTIS CELLULAR TECHNOLOGY, LLC, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CLUSTER LLC;REEL/FRAME:032326/0402 Effective date: 20131219 |
|
AS | Assignment |
Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:032786/0546 Effective date: 20140424 |
|
AS | Assignment |
Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE TO READ "SECURITY INTEREST" PREVIOUSLY RECORDED ON REEL 032786 FRAME 0546. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:033281/0216 Effective date: 20140424 |
|
AS | Assignment |
Owner name: OPTIS CELLULAR TECHNOLOGY, LLC, TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:HPS INVESTMENT PARTNERS, LLC;REEL/FRAME:039359/0916 Effective date: 20160711 |