US20010003373A1 - Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications - Google Patents
Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications Download PDFInfo
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- US20010003373A1 US20010003373A1 US09/225,278 US22527899A US2001003373A1 US 20010003373 A1 US20010003373 A1 US 20010003373A1 US 22527899 A US22527899 A US 22527899A US 2001003373 A1 US2001003373 A1 US 2001003373A1
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Definitions
- This invention relates in general to chip-on-board applications for integrated circuit dice, and in particular to devices and methods for electrically and thermally coupling to the backsides of dice in such applications.
- Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from semiconductor wafers, such as silicon wafers, on which multiple IC's have been fabricated. Most dice are packaged by attaching them to lead frames supported in plastic or ceramic packages, and the lead frames and packages are typically designed to conduct heat away from the dice in order to protect them from heat damage. Such packages are also typically designed to protect the dice from corrosion.
- COB chip-on-board
- PCB's printed circuit boards
- a liquid or gel encapsulant commonly referred to as a “glob top” is applied over the dice to protect them from corrosion.
- circuit traces 10 that widen near a die 12 and are directly attached to the surface 14 of a PCB 16 assist the PCB 16 in conducting significant amounts of heat away from the die 12 .
- circuit traces that widen sufficiently near dice to satisfactorily conduct heat away from the dice typically use an inordinately large amount of surface space on their associated PCB's.
- widened circuit traces can be difficult or impossible to implement in today's densely packed COB applications. Widened circuit traces can also lead to an undesirable increase in capacitive and inductive parasitics, which are highly undesirable for high-speed applications.
- thermally conductive PCB's are made with materials such as insulated aluminum, porcelainized steel, and ceramics that are superior in heat transfer characteristics than glass-epoxy. Because this technique is not applicable to the glass-epoxy PCB's used in the majority of COB applications, it is of limited utility.
- An inventive device for chip-on-board applications comprises a base, such as a printed circuit board (PCB) or a multi-chip module, that includes a conductive layer, such as a copper or other metallic plane, positioned on a surface of a supporting insulative substrate.
- An insulating layer overlies the surface of the conductive layer and defines at least one aperture in substantial registry with a localized region on the conductive layer on which a bare integrated circuit die is to be placed.
- the backside surface of the die is directly attached to the conductive plane in the localized region using a conductive die-attach material, such as a silver-filled epoxy, interposed between the conductive layer and the die.
- the inventive device thus can advantageously conduct heat away from the die by directly coupling the backside of the die to the conductive layer through the conductive die-attach material.
- the device can also conduct a substrate bias voltage to the backside of the die through the conductive layer and the die-attach material.
- the base includes multiple vertically-separated conductive layers, each layer having a localized region for conductive attachment to one of multiple bare integrated circuit dice. As a result, each of the dice may receive a different substrate bias voltage through its respective conductive layer.
- an electronic device in another embodiment, includes the base described above and an integrated circuit die, such as a Dynamic Random Access Memory (DRAM) die.
- an electronic system includes input, output, memory, and processor devices, and one or more of these devices includes the base described above.
- DRAM Dynamic Random Access Memory
- a system for conducting heat away from a die includes a thermally conductive interior PCB layer having a surface with an externally accessible die-attach region.
- a thermally conductive die-attach material directly attaches a backside surface of the die to the die-attach region to establish thermal conduction between the die and the thermally conductive layer.
- a system for supplying a substrate bias voltage to a die includes a substrate bias voltage generator and an electrically conductive layer inside a PCB for conducting the substrate bias voltage to an externally accessible die-attach region on the surface of the conductive layer.
- An electrically conductive die-attach material directly attaches a backside surface of the die to the die-attach region to conduct the substrate bias voltage to the backside surface of the die.
- FIG. 1 is an isometric view of a portion of a prior art printed circuit board that uses widened circuit traces near a directly attached (i.e., “on-board”) integrated circuit die to conduct heat away from the die;
- FIG. 2 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to a conductive layer of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between the conductive layer and the dice in accordance with the present invention;
- FIG. 3 is an isometric sectional view of the multi-chip module portion of FIG. 2 with an alternative substrate biasing arrangement
- FIG. 4 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to multiple conductive layers of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between each die and one of the conductive layers in accordance with the present invention
- FIG. 5 is a block diagram of an electronic system including the multi-chip module of FIG. 4.
- the present invention comprises a multi-chip module 20 that includes a plurality of integrated circuit dice 22 , each recessed in an aperture 23 in an insulating layer 24 of an insulative base 26 .
- the base 26 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB, the term PCB as employed herein including conductor-carrying substrates of silicon, ceramic, polymers and other materials known in the art.
- PCB printed circuit board
- the present invention will be described with respect to multi-chip module embodiments, it will be understood by those having skill in the field of this invention that the present invention is also applicable to single-die applications employing PCB's or other conductor-carrying bases.
- DRAM Dynamic Random Access Memory
- SIMM's Single In-line Memory Modules
- DIMM's Dual In-line Memory Modules
- memory cards as well as to processors and other dice commonly employed singly and in multi-chip assemblies on a variety of conductor-carrying substrates.
- Backsides (not shown) of the dice 22 are directly attached in a chip-on-board (COB) application to a conductive layer 28 of the base 26 using a conductive die-attach material 30 , such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive.
- a eutectic solder e.g., a gold/silver eutectic
- a metal-filled epoxy e.g., a silver-filled epoxy
- a conductive polyamide adhesive e.g., a conductive polyamide adhesive.
- the conductive layer 28 is positioned on a substrate 32 that may comprise one or more PCB layers.
- the conductive die-attach material and the conductive layer may be thermally conductive, electrically conductive, or preferably both, and that the conductive layer may comprise a wide variety of conductive materials, including copper, gold, and platinum. It should also be understood that there may be more than one vertically-superimposed conductive layer in a base and, consequently, that different dice may be attached to different conductive layers in the same base through apertures 23 extending to different depths of base 26 .
- Bond pads 34 on front- or active-side surfaces of the dice 22 are wire-bonded to signal traces 36 carried on a surface of the insulating layer 24 .
- the bond pads 34 may also be bonded to the signal traces 36 using tape-automated bonding (TAB) techniques, wherein the conductors are carried on a flexible dielectric film.
- the signal traces 36 may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. Further, it should be understood that, while the multi-chip module 20 of FIG.
- the present invention is equally applicable to COB applications in which there are multiple superimposed layers, such as insulating, conductive, or signal layers, between a conductive layer to which the backside of a die is directly attached and the signal layer to which the front-side of each die is bonded.
- a substrate bias voltage generator 38 can supply a substrate bias voltage V bb to the backsides (not shown) of the dice 22 through the conductive layer 28 .
- V bb the substrate bias voltage
- a supply voltage (commonly designated V cc ) ground potential (commonly designated V ss ), or electronic signal may be supplied to the dice 22 through the conductive layer 28 in place of the substrate bias voltage V bb .
- V cc a supply voltage
- V ss ground potential
- electronic signal may be supplied to the dice 22 through the conductive layer 28 in place of the substrate bias voltage V bb .
- the generator 38 is shown in FIG. 2 as applying a negative substrate bias voltage V bb to the conductive layer 28 , it should be understood that the generator 38 may instead provide a positive substrate bias voltage V bb to the layer 28 .
- the present invention also provides marginally greater physical protection for dice by positioning them within a protective aperture in the thin upper insulating layer 24 . Further, the present invention advantageously allows incrementally shorter bond wires to be used during die-bond because the front-side surfaces of the dice are slightly closer to the level of the signal traces to which they are bonded. While such advantages are relatively small, they are nonetheless significant.
- an alternative version of the multi-chip module 20 of FIG. 2 includes the substrate bias voltage generator 38 directly applying a bias between the conductive layer 28 and a conductive reference layer 41 .
- the reference layer 41 is shown in FIG. 3 as being grounded, it may be coupled to any voltage, particularly other reference voltages.
- the present invention also comprises a multi-chip module 40 that includes a plurality of integrated circuit dice 42 , each recessed in an aperture 43 in insulating layers 44 and 46 and a first conductive layer 48 of an insulative base 50 .
- the base 50 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB.
- Backsides (not shown) of the dice 42 are directly respectively attached in a chip-on-board (COB) application to the first conductive layer 48 and a second conductive layer 52 of the base 50 using a conductive die-attach material (not shown), such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive.
- the second conductive layer 52 is positioned on a substrate 54 that may comprise one or more PCB layers.
- the conductive die-attach material and the conductive layers may be thermally conductive, electrically conductive, or preferably both, and that the conductive layers may comprise a wide variety of conductive materials, including copper, gold, and platinum.
- Bond pads 56 on front- or active-side surfaces of the dice 42 are Tape-Automated Bonded (TAB) to signal traces 58 carried on a surface of the insulating layer 44 .
- TAB Tape-Automated Bonded
- the signal traces may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum.
- the flexible film (usually polyimide) of the TAB tape has been deleted for clarity.
- substrate bias voltage generators can supply a first substrate bias voltage V bb1 to the backside (not shown) of one of the dice 42 through the first conductive layer 48 and a second substrate bias voltage V bb2 to the backside (not shown) of the other of the dice 42 through the second conductive layer 52 .
- a supply voltage V cc , ground potential V ss , or electronic signal may be supplied to the dice 42 through the conductive layers 48 and 52 in place of the substrate bias voltages V bb1 and V bb2 .
- the substrate bias voltages V bb1 and V bb2 can be different voltages.
- the multi-chip module 40 of FIG. 4 can be incorporated into a memory device 60 of an electronic system 62 , such as a computer system, that includes an input device 64 and an output device 66 coupled to a processor device 68 .
- the multi-chip module 40 can alternatively be incorporated into the input device 64 , the output device 66 , or the processor device 68 .
- the multi-chip module (not shown) of FIG. 2 may be incorporated into the input device 64 , output device 66 , processor device 68 , or memory device 60 .
- the memory device 60 of FIG. 5 may comprise a DIMM, SIMM, memory card or any other memory die-carrying substrate.
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Abstract
An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.
Description
- This application is a divisional of application Ser. No. 08/870,614, filed Jun. 6, 1997, pending.
- 1. Field of the Invention
- This invention relates in general to chip-on-board applications for integrated circuit dice, and in particular to devices and methods for electrically and thermally coupling to the backsides of dice in such applications.
- 2. State of the Art
- Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from semiconductor wafers, such as silicon wafers, on which multiple IC's have been fabricated. Most dice are packaged by attaching them to lead frames supported in plastic or ceramic packages, and the lead frames and packages are typically designed to conduct heat away from the dice in order to protect them from heat damage. Such packages are also typically designed to protect the dice from corrosion.
- Some dice, however, are packaged in what are known as “chip-on-board” (COB) applications, in which the dice are directly attached to printed circuit boards (PCB's) or other known substrates using well-known die-attach techniques. In these applications, bond pads on one or more dice are connected to signal traces on the surfaces of PCB's or other substrates using wire, or tape-automated, bonding, and a liquid or gel encapsulant, commonly referred to as a “glob top,” is applied over the dice to protect them from corrosion. One such COB application is described in U.S. Pat. No. 5,497,027.
- Dice in COB applications typically generate more heat than their associated PCB's alone can satisfactorily conduct away. Consequently, certain techniques have been devised to assist in conducting heat away from dice in COB applications. In one such technique shown in FIG. 1, circuit traces10 that widen near a
die 12 and are directly attached to thesurface 14 of aPCB 16 assist thePCB 16 in conducting significant amounts of heat away from the die 12. Unfortunately, circuit traces that widen sufficiently near dice to satisfactorily conduct heat away from the dice typically use an inordinately large amount of surface space on their associated PCB's. As a result, widened circuit traces can be difficult or impossible to implement in today's densely packed COB applications. Widened circuit traces can also lead to an undesirable increase in capacitive and inductive parasitics, which are highly undesirable for high-speed applications. - Another technique for conducting heat away from dice in COB applications involves using thermally conductive PCB's in place of the more commonly used glass-epoxy PCB's. Thermally conductive PCB's are made with materials such as insulated aluminum, porcelainized steel, and ceramics that are superior in heat transfer characteristics than glass-epoxy. Because this technique is not applicable to the glass-epoxy PCB's used in the majority of COB applications, it is of limited utility.
- Therefore, there is a need in the art for a device and method for satisfactorily conducting heat away from dice that are directly attached to a variety of PCB's, including conventional, widely-utilized glass-epoxy PCB's, without degrading the electrical characteristics of the interconnecting circuitry in COB applications.
- An inventive device for chip-on-board applications comprises a base, such as a printed circuit board (PCB) or a multi-chip module, that includes a conductive layer, such as a copper or other metallic plane, positioned on a surface of a supporting insulative substrate. An insulating layer overlies the surface of the conductive layer and defines at least one aperture in substantial registry with a localized region on the conductive layer on which a bare integrated circuit die is to be placed. The backside surface of the die is directly attached to the conductive plane in the localized region using a conductive die-attach material, such as a silver-filled epoxy, interposed between the conductive layer and the die. The inventive device thus can advantageously conduct heat away from the die by directly coupling the backside of the die to the conductive layer through the conductive die-attach material. The device can also conduct a substrate bias voltage to the backside of the die through the conductive layer and the die-attach material.
- In a modified version of the base described above, the base includes multiple vertically-separated conductive layers, each layer having a localized region for conductive attachment to one of multiple bare integrated circuit dice. As a result, each of the dice may receive a different substrate bias voltage through its respective conductive layer.
- In another embodiment of the present invention, an electronic device includes the base described above and an integrated circuit die, such as a Dynamic Random Access Memory (DRAM) die. In still another embodiment, an electronic system includes input, output, memory, and processor devices, and one or more of these devices includes the base described above.
- In a further embodiment, a system for conducting heat away from a die includes a thermally conductive interior PCB layer having a surface with an externally accessible die-attach region. A thermally conductive die-attach material directly attaches a backside surface of the die to the die-attach region to establish thermal conduction between the die and the thermally conductive layer.
- In a still further embodiment of the present invention, a system for supplying a substrate bias voltage to a die includes a substrate bias voltage generator and an electrically conductive layer inside a PCB for conducting the substrate bias voltage to an externally accessible die-attach region on the surface of the conductive layer. An electrically conductive die-attach material directly attaches a backside surface of the die to the die-attach region to conduct the substrate bias voltage to the backside surface of the die.
- FIG. 1 is an isometric view of a portion of a prior art printed circuit board that uses widened circuit traces near a directly attached (i.e., “on-board”) integrated circuit die to conduct heat away from the die;
- FIG. 2 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to a conductive layer of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between the conductive layer and the dice in accordance with the present invention;
- FIG. 3 is an isometric sectional view of the multi-chip module portion of FIG. 2 with an alternative substrate biasing arrangement;
- FIG. 4 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to multiple conductive layers of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between each die and one of the conductive layers in accordance with the present invention; and
- FIG. 5 is a block diagram of an electronic system including the multi-chip module of FIG. 4.
- As shown in FIG. 2, the present invention comprises a
multi-chip module 20 that includes a plurality ofintegrated circuit dice 22, each recessed in anaperture 23 in aninsulating layer 24 of aninsulative base 26. Thebase 26 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB, the term PCB as employed herein including conductor-carrying substrates of silicon, ceramic, polymers and other materials known in the art. Although the present invention will be described with respect to multi-chip module embodiments, it will be understood by those having skill in the field of this invention that the present invention is also applicable to single-die applications employing PCB's or other conductor-carrying bases. It will also be understood that the present invention is applicable to memory dice, such as Dynamic Random Access Memory (DRAM) dice, packaged in Single In-line Memory Modules (SIMM's), Dual In-line Memory Modules (DIMM's), and memory cards, as well as to processors and other dice commonly employed singly and in multi-chip assemblies on a variety of conductor-carrying substrates. - Backsides (not shown) of the
dice 22 are directly attached in a chip-on-board (COB) application to aconductive layer 28 of thebase 26 using a conductive die-attach material 30, such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, theconductive layer 28 is positioned on asubstrate 32 that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layer may be thermally conductive, electrically conductive, or preferably both, and that the conductive layer may comprise a wide variety of conductive materials, including copper, gold, and platinum. It should also be understood that there may be more than one vertically-superimposed conductive layer in a base and, consequently, that different dice may be attached to different conductive layers in the same base throughapertures 23 extending to different depths ofbase 26. -
Bond pads 34 on front- or active-side surfaces of thedice 22 are wire-bonded tosignal traces 36 carried on a surface of the insulatinglayer 24. Of course, thebond pads 34 may also be bonded to thesignal traces 36 using tape-automated bonding (TAB) techniques, wherein the conductors are carried on a flexible dielectric film. Also, thesignal traces 36 may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. Further, it should be understood that, while themulti-chip module 20 of FIG. 2 is shown as having a singleinsulating layer 24 between theconductive layer 28 and thesignal traces 36, the present invention is equally applicable to COB applications in which there are multiple superimposed layers, such as insulating, conductive, or signal layers, between a conductive layer to which the backside of a die is directly attached and the signal layer to which the front-side of each die is bonded. - Because the present invention directly attaches the backsides of dice to a conductive layer, heat from the dice is advantageously conducted away from the dice through the conductive layer. Also, as shown in FIG. 2, a substrate
bias voltage generator 38 can supply a substrate bias voltage Vbb to the backsides (not shown) of thedice 22 through theconductive layer 28. As a result, there is no need for on-board substrate bias voltage generators (not shown) in thedice 22, and there is no need to supply the substrate bias voltage Vbb to thedice 22 throughbond pads 34 on their front-side surfaces. Of course, a supply voltage (commonly designated Vcc) ground potential (commonly designated Vss), or electronic signal may be supplied to thedice 22 through theconductive layer 28 in place of the substrate bias voltage Vbb. Also, although thegenerator 38 is shown in FIG. 2 as applying a negative substrate bias voltage Vbb to theconductive layer 28, it should be understood that thegenerator 38 may instead provide a positive substrate bias voltage Vbb to thelayer 28. - The present invention also provides marginally greater physical protection for dice by positioning them within a protective aperture in the thin upper
insulating layer 24. Further, the present invention advantageously allows incrementally shorter bond wires to be used during die-bond because the front-side surfaces of the dice are slightly closer to the level of the signal traces to which they are bonded. While such advantages are relatively small, they are nonetheless significant. - As shown in a sectional view in FIG. 3, an alternative version of the
multi-chip module 20 of FIG. 2 includes the substratebias voltage generator 38 directly applying a bias between theconductive layer 28 and aconductive reference layer 41. Of course, while thereference layer 41 is shown in FIG. 3 as being grounded, it may be coupled to any voltage, particularly other reference voltages. - As shown in FIG. 4, the present invention also comprises a
multi-chip module 40 that includes a plurality ofintegrated circuit dice 42, each recessed in anaperture 43 in insulatinglayers conductive layer 48 of aninsulative base 50. The base 50 may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB. - Backsides (not shown) of the
dice 42 are directly respectively attached in a chip-on-board (COB) application to the firstconductive layer 48 and a secondconductive layer 52 of the base 50 using a conductive die-attach material (not shown), such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, the secondconductive layer 52 is positioned on asubstrate 54 that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layers may be thermally conductive, electrically conductive, or preferably both, and that the conductive layers may comprise a wide variety of conductive materials, including copper, gold, and platinum. -
Bond pads 56 on front- or active-side surfaces of thedice 42 are Tape-Automated Bonded (TAB) to signaltraces 58 carried on a surface of the insulatinglayer 44. Of course, the signal traces may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. The flexible film (usually polyimide) of the TAB tape has been deleted for clarity. - Because the present invention directly attaches the backsides of dice to conductive layers, heat from the dice is advantageously conducted away from the dice through the conductive layers. Also, substrate bias voltage generators (not shown) can supply a first substrate bias voltage Vbb1 to the backside (not shown) of one of the
dice 42 through the firstconductive layer 48 and a second substrate bias voltage Vbb2 to the backside (not shown) of the other of thedice 42 through the secondconductive layer 52. As a result, there is no need for on-board substrate bias voltage generators in thedice 42, and there is no need to supply the substrate bias voltages Vbb1 and Vbb2 to thedice 42 throughbond pads 56 on their front-side surfaces. Of course, a supply voltage Vcc, ground potential Vss, or electronic signal may be supplied to thedice 42 through theconductive layers - As shown in FIG. 5, the
multi-chip module 40 of FIG. 4 can be incorporated into amemory device 60 of anelectronic system 62, such as a computer system, that includes aninput device 64 and anoutput device 66 coupled to aprocessor device 68. Of course, themulti-chip module 40 can alternatively be incorporated into theinput device 64, theoutput device 66, or theprocessor device 68. Alternatively, the multi-chip module (not shown) of FIG. 2 may be incorporated into theinput device 64,output device 66,processor device 68, ormemory device 60. Also, thememory device 60 of FIG. 5 may comprise a DIMM, SIMM, memory card or any other memory die-carrying substrate. - Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.
Claims (43)
1. A printed circuit board for chip-on-board applications, the printed circuit board comprising:
a first dielectric layer having a surface;
a conductive layer positioned on the surface of the first dielectric layer and including a die-mounting surface within a chip-attach area of the conductive layer for direct conductive attachment to a backside surface of a bare integrated circuit chip to establish at least one of electrical and thermal conduction between the conductive layer and the chip;
a second dielectric layer positioned on the conductive layer, the second dielectric layer having an aperture therein to define the chip-attach area of the conductive layer and to receive the bare integrated circuit chip; and
a layer of signal traces superimposed on the second dielectric layer in a substantially parallel relationship therewith, at least some of the traces including bond pads for electrical connection to a front-side surface of the chip.
2. The printed circuit board of , wherein the layer of signal traces is positioned on a surface of the second dielectric layer.
claim 1
3. The printed circuit board of , wherein a portion of the second dielectric layer aperture extends generally about a periphery of the chip-attach area of the conductive layer.
claim 1
4. The printed circuit board of , wherein the signal traces are selected from a group comprising copper, gold, and platinum.
claim 1
5. A multi-chip module comprising:
a supporting substrate having an insulative surface;
a conductive layer positioned on the insulative surface of the supporting substrate and having a surface with a plurality of localized die-attach areas thereon;
a plurality of bare integrated circuit dice each associated with one of the die-attach areas, each die having opposing front-side and backside surfaces, the front-side surface of each die having a plurality of bond pads thereon;
a conductive die-attach material interposed between each bare integrated circuit die and its associated die-attach area and directly attaching the backside surface of each die to its associated die-attach area to establish at least one of electrical and thermal conduction between each die and the conductive layer;
an insulating layer positioned on the surface of the conductive layer, the insulating layer having a plurality of apertures therein, each aperture in substantial registry with one of the attached bare integrated circuit dice;
a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having a plurality of conductor-devoid areas therein, each conductor-devoid area in substantial registry with one of the attached bare integrated circuit dice, the signal layer including a plurality of terminals; and
a plurality of conductors coupling the terminals of the signal layer to the bond pads on the front-side surfaces of the bare integrated circuit dice.
6. The multi-chip module of , wherein the signal layer comprises a plurality of signal traces.
claim 5
7. The multi-chip module of , wherein the signal layer terminals comprise bond pads.
claim 5
8. The multi-chip module of , wherein at least one of the bare integrated circuit dice comprises a dynamic random access memory die.
claim 5
9. The multi-chip module of , wherein the conductive die-attach material comprises a conductive epoxy.
claim 5
10. The multi-chip module of , wherein the conductive epoxy comprises a metal filled epoxy.
claim 9
11. The multi-chip module of , wherein the metal filled epoxy comprises a silver filled epoxy.
claim 10
12. The multi-chip module of , wherein the conductive die-attach material comprises a eutectic material.
claim 5
13. The multi-chip module of , wherein the eutectic material comprises a gold and silver eutectic material.
claim 12
14. The multi-chip module of , wherein the conductive die-attach material comprises a solder.
claim 5
15. The multi-chip module of , wherein the conductive die-attach material comprises a conductive polyamide.
claim 5
16. The multi-chip module of , wherein the conductive die-attach material comprises a thermally conductive die-attach material.
claim 5
17. The multi-chip module of , wherein the conductors comprise wire bond conductors.
claim 5
18. The multi-chip module of , wherein the conductors comprise TAB conductors.
claim 5
19. An electronic device comprising:
a supporting substrate having an insulative surface;
a conductive layer positioned on the insulative surface of the supporting substrate and including a surface with a localized die-attach area thereon;
a bare integrated circuit die having opposing front-side and backside surfaces, the front-side surface having a plurality of bond pads thereon;
a conductive die-attach material for directly attaching the backside surface of the bare integrated circuit die to the die-attach area on the surface of the conductive layer to establish at least one of electrical and thermal conduction between the die and the conductive layer;
an insulating layer positioned on the surface of the conductive layer, the insulating layer having an aperture therein in substantial registry with the attached bare integrated circuit die;
a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having an aperture therein in substantial registry with the attached bare integrated circuit die, the signal layer including a plurality of terminals; and
a plurality of conductors coupling the terminals of the signal layer to the bond pads on the front-side surface of the bare integrated circuit die.
20. The electronic device of , wherein the signal layer comprises a plurality of signal traces.
claim 19
21. The electronic device of , wherein the signal layer terminals comprise bond pads.
claim 19
22. The electronic device of , wherein the bare integrated circuit die comprises a dynamic random access memory die.
claim 19
23. The electronic device of , wherein the conductive die-attach material comprises a conductive epoxy.
claim 19
24. The electronic device of , wherein the conductive epoxy comprises a metal-filled epoxy.
claim 23
25. The electronic device of , wherein the metal-filled epoxy comprises a silver-filled epoxy.
claim 24
26. The electronic device of , wherein the conductive die-attach material comprises a thermally conductive die-attach material.
claim 19
27. The electronic device of , wherein the conductors comprise wire bond conductors.
claim 19
28. The electronic device of , wherein the conductors comprise tape-automated-bonding conductors.
claim 19
29. A system for conducting heat away from a bare integrated circuit die, the system comprising:
a thermally conductive layer positioned internally in a printed circuit board, the thermally conductive layer including a surface with an externally accessible localized die-attach region; and
a thermally conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the thermally conductive layer to establish thermal conduction between the die and the thermally conductive layer.
30. The system of , wherein the thermally conductive layer comprises a substantially continuous thermally conductive sheet.
claim 29
31. The system of , wherein the thermally conductive layer is also electrically conductive.
claim 29
32. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system comprising:
a substrate bias voltage generator for supplying the substrate bias voltage;
an electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator for conducting the substrate bias voltage, the electrically conductive layer including a surface with an externally accessible localized die-attach region; and
an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the electrically conductive layer to conduct the substrate bias voltage from the electrically conductive layer to the backside surface of the die.
33. The system of , wherein the electrically conductive die-attach material comprises a conductive epoxy.
claim 32
34. The system of , wherein the conductive epoxy comprises a metal-filled epoxy.
claim 33
35. The system of , wherein the metal-filled epoxy comprises a silver-filled epoxy.
claim 34
36. The system of , wherein the electrically conductive die-attach material comprises a eutectic material.
claim 32
37. The system of , wherein the eutectic material comprises a gold and silver eutectic material.
claim 36
38. The system of , wherein the electrically conductive die-attach material comprises a solder.
claim 32
39. The system of , wherein the electrically conductive die-attach material comprises a conductive polyamide.
claim 32
40. The system of , wherein the electrically conductive die-attach material is also a thermally conductive die-attach material.
claim 32
41. The system of , wherein the electrically conductive layer comprises a substantially continuous electrically conductive sheet.
claim 32
42. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system consisting essentially of:
a substrate bias voltage generator for supplying the substrate bias voltage;
an electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator for conducting the substrate bias voltage, the electrically conductive layer including a surface with an externally accessible localized die-attach region; and
an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the die-attach region on the surface of the electrically conductive layer to conduct the substrate bias voltage from the electrically conductive layer to the backside surface of the die.
43. A method of making a printed circuit board for supporting a bare integrated circuit die, the method comprising:
providing a supporting substrate having an insulative surface;
positioning a conductive layer on the insulative surface of the supporting substrate, the conductive layer having a surface with a localized region for direct conductive attachment to a backside surface of the bare integrated circuit die to establish at least one of electrical and thermal conduction between the conductive layer and the die; and
positioning an insulating layer on the conductive layer with an aperture in the insulating layer in substantial registry with the localized region on the surface of the conductive layer for receiving the bare integrated circuit die.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/225,278 US6339256B2 (en) | 1997-06-06 | 1999-01-05 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US09/652,407 US6299463B1 (en) | 1997-06-06 | 2000-08-31 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/870,614 US6064116A (en) | 1997-06-06 | 1997-06-06 | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US09/225,278 US6339256B2 (en) | 1997-06-06 | 1999-01-05 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
Related Parent Applications (1)
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US08/870,614 Division US6064116A (en) | 1997-06-06 | 1997-06-06 | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/652,407 Division US6299463B1 (en) | 1997-06-06 | 2000-08-31 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
Publications (2)
Publication Number | Publication Date |
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US20010003373A1 true US20010003373A1 (en) | 2001-06-14 |
US6339256B2 US6339256B2 (en) | 2002-01-15 |
Family
ID=25355778
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US08/870,614 Expired - Lifetime US6064116A (en) | 1997-06-06 | 1997-06-06 | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US09/225,278 Expired - Fee Related US6339256B2 (en) | 1997-06-06 | 1999-01-05 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US09/652,407 Expired - Fee Related US6299463B1 (en) | 1997-06-06 | 2000-08-31 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
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US09/652,407 Expired - Fee Related US6299463B1 (en) | 1997-06-06 | 2000-08-31 | Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
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US6064116A (en) | 2000-05-16 |
US6339256B2 (en) | 2002-01-15 |
US6299463B1 (en) | 2001-10-09 |
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