JPH0529779A - Heat-radiating mounting structure for semiconductor - Google Patents
Heat-radiating mounting structure for semiconductorInfo
- Publication number
- JPH0529779A JPH0529779A JP3185980A JP18598091A JPH0529779A JP H0529779 A JPH0529779 A JP H0529779A JP 3185980 A JP3185980 A JP 3185980A JP 18598091 A JP18598091 A JP 18598091A JP H0529779 A JPH0529779 A JP H0529779A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- heat
- ground conductor
- hole
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、テープキャリアを介し
て回路基板に接続する半導体チップの放熱実装構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat radiation mounting structure for a semiconductor chip connected to a circuit board via a tape carrier.
【０００２】電子機器の高機能化及び高密度実装化がま
すます進展するのに伴い、テープキャリアを介して半導
体チップを回路基板に接続してなる半導体集積回路は高
集積化され、信号処理速度も高速化してきている。半導
体集積回路の高集積化、高速化に伴って使用電力量が増
大しその発熱量も増加してきている。そのため、発熱し
た半導体チップの熱を効率よく放熱する実装構造が要望
されている。As electronic devices have become more highly functional and densely packaged, semiconductor integrated circuits in which a semiconductor chip is connected to a circuit board via a tape carrier have become highly integrated, resulting in high signal processing speed. Is also getting faster. Along with the higher integration and higher speed of semiconductor integrated circuits, the amount of power used and the amount of heat generated have increased. Therefore, there is a demand for a mounting structure that efficiently dissipates the generated heat of the semiconductor chip.
【０００３】[0003]
【従来の技術】従来は図６の実装側断面図に示すよう
に、テープキャリア12のインナリード12a を電極（図示
略）に接続した半導体チップ10は、フェースアップ状態
に（回路を含む電極形成面を上に）してアウタリード12
b を折り曲げフォーミングした後、回路基板11の予め、
図示しない半田ペーストをプリコートしたフットプリン
ト11a に熱圧着ボンディングしている。そして、半導体
チップ10の回路を含む電極形成面を耐湿性樹脂材13でコ
ーティングしている。2. Description of the Related Art Conventionally, as shown in a sectional view of a mounting side of FIG. 6, a semiconductor chip 10 in which an inner lead 12a of a tape carrier 12 is connected to an electrode (not shown) is placed in a face-up state (electrode formation including a circuit). Outer lead 12 with the side facing up)
After bending and forming b, the circuit board 11 is
It is thermocompression bonded to the footprint 11a pre-coated with a solder paste (not shown). The electrode forming surface including the circuit of the semiconductor chip 10 is coated with the moisture resistant resin material 13.
【０００４】半導体チップの放熱は、耐湿性樹脂材がコ
ーティングしてあっても、半導体チップを裸に近い状態
で実装しているため、他の樹脂封止形半導体装置に比べ
れば放熱が良く、発熱量の大きくないものでは別に補助
の放熱体を付加せずにそのままの状態で使用していた。As for the heat dissipation of the semiconductor chip, even if the semiconductor chip is coated with the moisture resistant resin material, the semiconductor chip is mounted in a nearly bare state, so that the heat dissipation is better than that of other resin-sealed semiconductor devices. For those that do not generate a large amount of heat, they were used as they were without adding an additional heat radiator.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな上記実装構造によれば、半導体チップの発熱量が増
加するに伴い放熱（冷却）が不十分になるという問題
や、放熱を良くするために半導体チップ上に補助の放熱
体を付加する場合、半導体チップ及びリード接合部に荷
重によるストレスが生じそれらを破壊してしまうといっ
た問題があった。However, according to the above mounting structure, in order to improve heat dissipation, there is a problem that heat dissipation (cooling) becomes insufficient as the heat generation amount of the semiconductor chip increases. When an auxiliary heat radiator is added on the semiconductor chip, there is a problem in that stress is applied to the semiconductor chip and the lead joint portion due to the load, and they are destroyed.
【０００６】上記問題点に鑑み、本発明は放熱をさらに
良くするとともに半導体チップの上に補助の放熱体を付
加する場合、半導体チップ及びリード接合部にストレス
の生じない半導体チップの放熱実装構造を提供すること
を目的とする。In view of the above problems, the present invention provides a heat dissipation mounting structure for a semiconductor chip in which stress is not generated in the semiconductor chip and the lead joint portion when heat dissipation is further improved and an auxiliary heat dissipation member is added on the semiconductor chip. The purpose is to provide.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体チップの放熱実装構造においては、
回路基板は実装面に接地レベルの内層にまで届き半導体
チップを入れるくぼみ穴を穿設し、該くぼみ穴の周辺を
含む内面に前記内層に接続する第１のグランド導体を形
成し、該くぼみ穴の第１のグランド導体に半導体チップ
を電極形成面を外側にしてダイボンディングするととも
にテープキャリアで回路接続するように構成する。In order to achieve the above object, in the heat dissipation mounting structure of the semiconductor chip of the present invention,
The circuit board is provided with a recessed hole which reaches the inner layer of the ground level and into which the semiconductor chip is inserted, and a first ground conductor which is connected to the inner layer is formed on the inner surface including the periphery of the recessed hole. The semiconductor chip is die-bonded to the first ground conductor with the electrode forming surface facing outside and is connected to the circuit by a tape carrier.
【０００８】[0008]
【作用】回路基板の実装面に接地レベルの内層にまで届
き半導体チップを入れるくぼみ穴を穿設し、該くぼみ穴
の周辺を含む内面に前記内層に接続する第１のグランド
導体を形成し、該くぼみ穴の第１のグランド導体に半導
体チップを電極形成面を外側にしてダイボンディングす
るとともにテープキャリアで回路接続することにより、
半導体チップの熱を第１のグランド導体を通して内層に
熱伝導し回路基板自体に熱拡散することができるため、
放熱をより良くすることができる。The mounting surface of the circuit board is provided with a recess hole that reaches the inner layer of the ground level and into which the semiconductor chip is inserted, and a first ground conductor connected to the inner layer is formed on the inner surface including the periphery of the recess hole. By die-bonding the semiconductor chip to the first ground conductor of the recessed hole with the electrode formation surface facing outward, and connecting the circuit with a tape carrier,
Since the heat of the semiconductor chip can be conducted to the inner layer through the first ground conductor and diffused to the circuit board itself,
The heat dissipation can be improved.
【０００９】[0009]
【実施例】以下、図面に示した実施例に基づいて本発明
の要旨を詳細に説明する。先ず、第１の実施例について
説明する。図１は第１の実施例を示す要部実装側断面図
で、図２(a),(b) は図１の回路基板の要部平面図及びそ
のＡ−Ａ断面図である。図２に示すように、多層の回路
基板１は実装面に接地レベルの内層1aにまで届き半導体
チップを入れるくぼみ穴（角穴）1bを穿設し、そのくぼ
み穴1bの周辺を含む内面に内層1aに接続する平面視正方
形の第１のグランド導体1b-1とその回り４辺に半導体チ
ップの電極に対応するフットプリント1cを配列備える。DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention will be described in detail below with reference to the embodiments shown in the drawings. First, the first embodiment will be described. FIG. 1 is a cross-sectional view of the main part mounting side showing the first embodiment, and FIGS. 2A and 2B are a plan view of the main part of the circuit board of FIG. As shown in FIG. 2, the multilayer circuit board 1 has a recessed hole (square hole) 1b which reaches the inner layer 1a at the ground level and into which a semiconductor chip is inserted, on the inner surface including the periphery of the recessed hole 1b. A first ground conductor 1b-1 having a square shape in plan view connected to the inner layer 1a, and footprints 1c corresponding to the electrodes of the semiconductor chip are arranged on four sides around the first ground conductor 1b-1.
【００１０】このくぼみ穴への半導体チップの実装はつ
ぎのように行う。即ち、図１に示したように、半導体チ
ップ10を、回路を含む電極形成面を外（上）側にしてく
ぼみ穴1bに入れ、底面にプリコートした導電性ペースト
２でダイボンディングするとともに、テープキャリア３
でインナリード3aは半導体チップ10の電極（図示略）
に、アウタリード3bは回路基板１のフットプリント1cに
熱圧着ボンディングする。The semiconductor chip is mounted in the recess hole as follows. That is, as shown in FIG. 1, the semiconductor chip 10 is put into the recessed hole 1b with the electrode forming surface including the circuit being the outside (upper) side, and die-bonded with the conductive paste 2 pre-coated on the bottom surface and the tape. Carrier 3
The inner leads 3a are electrodes of the semiconductor chip 10 (not shown).
The outer leads 3b are thermocompression bonded to the footprint 1c of the circuit board 1.
【００１１】テープキャリア３のインナリード3aとアウ
タリード3bとの間にはポリイミド樹脂テープなどからな
るサポートリング3cがありリード間のつなぎと第１のグ
ランド導体1b-1との短絡を防止する。半導体チップ10の
電極（図示略）及びフットプリント1cには予め、半田ペ
ースト（図示略）がプリコートしてある。そして、最後
に半導体チップ10の電極形成面にリード接合部を含め耐
湿性樹脂４を被着し構成する。A support ring 3c made of a polyimide resin tape or the like is provided between the inner lead 3a and the outer lead 3b of the tape carrier 3 to prevent a short circuit between the connection between the leads and the first ground conductor 1b-1. The electrodes (not shown) of the semiconductor chip 10 and the footprints 1c are pre-coated with solder paste (not shown). Then, finally, the moisture-resistant resin 4 including the lead bonding portion is adhered to the electrode formation surface of the semiconductor chip 10 to form a structure.
【００１２】このように構成することにより、半導体チ
ップの熱を第１のグランド導体を通して内層に熱伝導し
回路基板自体に熱拡散することができるため、放熱をよ
り良くすることができる。そのため、第１のグランド導
体及び内層の面積は最大限大きく取るのが望ましい。With this configuration, the heat of the semiconductor chip can be conducted to the inner layer through the first ground conductor and diffused to the circuit board itself, so that the heat radiation can be improved. Therefore, it is desirable to maximize the areas of the first ground conductor and the inner layer.
【００１３】つぎに、第２の実施例について説明する。
図３は第２の実施例を示す要部実装側断面図で、図４
(a),(b) は図３の回路基板の要部平面図及びそのＢ−Ｂ
断面図である。両図に図示するように第１の実施例と基
本的に同じ構成であるが、図３のように半導体チップ10
の電極形成面に第１の放熱体５を付加した点が異なる。
即ち、図４に示すように回路基板１は第１のグランド導
体1b-1の四隅を対角線上に延ばした先端に第１の放熱体
５の取付孔（図示略）に対応する取付用スルーホール1d
を穿設し、第１の放熱体５を固定ねじ６でナット6a止め
する。なお、半導体チップの電極形成面と第１の放熱体
との間には熱伝導を良くするためサーマルコンパウンド
や液体ヒートシンク、あるいは柔軟な放熱シートなどの
熱伝導性緩衝材７を介挿する。Next, a second embodiment will be described.
FIG. 3 is a sectional view of a main part mounting side showing a second embodiment.
(a), (b) is a plan view of the main part of the circuit board of FIG. 3 and its BB
FIG. As shown in both figures, the structure is basically the same as that of the first embodiment, but as shown in FIG.
The difference is that the first heat radiator 5 is added to the electrode forming surface.
That is, as shown in FIG. 4, the circuit board 1 has through holes for attachment corresponding to the attachment holes (not shown) of the first radiator 5 at the tips of the four corners of the first ground conductor 1b-1 extending diagonally. 1d
Then, the first heat radiator 5 is fixed to the nut 6a with the fixing screw 6. A thermal compound, a liquid heat sink, or a heat conductive cushioning material 7 such as a flexible heat radiating sheet is inserted between the electrode forming surface of the semiconductor chip and the first heat radiating body to improve heat conduction.
【００１４】この第２の構成によれば、半導体チップの
上に放熱体を付加しても回路基板に固定されているため
直接、重量は掛からず、緩衝材を介在し接触しているだ
けであるため、半導体チップ及びリード接合部に荷重に
よるストレスは生じず、また半導体チップの熱を内層か
らだけでなく、電極形成面から直接に熱伝導した第１の
放熱体からも放熱できるため、更に放熱を良くすること
ができる。According to the second structure, even if a heat radiator is added on the semiconductor chip, since it is fixed to the circuit board, the weight is not directly applied, and only the contact is made with the cushioning material interposed. Therefore, the stress due to the load is not generated in the semiconductor chip and the lead joint portion, and the heat of the semiconductor chip can be radiated not only from the inner layer but also from the first radiator radiating heat directly from the electrode formation surface. The heat dissipation can be improved.
【００１５】最後に、第３の実施例について説明する。
図５は第３の実施例を示す要部実装側断面図である。図
示するように第１の実施例と基本的に同じ構成である
が、第１のグランド導体1b-1に複数の熱伝導用スルーホ
ール1eで接続する第２のグランド導体1fを回路基板１の
実装反対面に備え、第２の実施例と同様に熱伝導性緩衝
材７を介挿して第２の放熱体８を搭載し第１の放熱体５
と固定ねじ６で共締めする。第２の放熱体８には図示し
ないねじ孔が立ててある。Finally, a third embodiment will be described.
FIG. 5 is a sectional view of the main part mounting side showing the third embodiment. As shown in the figure, it has basically the same configuration as that of the first embodiment, but the second ground conductor 1f connected to the first ground conductor 1b-1 by a plurality of through holes 1e for heat conduction is connected to the circuit board 1. The first radiator 5 is provided with the second radiator 8 mounted on the opposite surface of the mounting through the thermal conductive cushioning material 7 as in the second embodiment.
And the fixing screw 6 together. A screw hole (not shown) is formed in the second radiator 8.
【００１６】この第３の構成によれば、第２の実施例と
同様に半導体チップ及びリード接合部に荷重によるスト
レスは生じず、また第１のグランド導体→熱伝導用スル
ーホール→第２のグランド導体を通して第１の放熱体の
他に更に第２の放熱体からも放熱できるため尚一層に放
熱を良くすることができる。According to the third structure, as in the second embodiment, the stress due to the load is not generated in the semiconductor chip and the lead joint, and the first ground conductor → heat conduction through hole → second Since it is possible to dissipate heat not only from the first radiator but also from the second radiator through the ground conductor, the heat dissipation can be further improved.
【００１７】[0017]
【発明の効果】以上、詳述したように本発明によれば、
従来構成に比べて放熱をさらに良くするとともに半導体
チップの上に放熱体を付加しても半導体チップ及びリー
ド接合部にストレスの生じないため、半導体集積回路の
高集積化及び高速化を図ることができ、熱的信頼性の高
い半導体高集積回路を提供することができるといった産
業上極めて有用な効果を発揮する。As described above in detail, according to the present invention,
As compared with the conventional configuration, heat dissipation is further improved, and since stress is not generated in the semiconductor chip and the lead joint even if a heat radiator is added on the semiconductor chip, high integration and high speed of the semiconductor integrated circuit can be achieved. It is possible to provide a highly integrated semiconductor circuit with high thermal reliability, which is extremely useful in industry.
【図１】 本発明による第１の実施例を示す要部実装側
断面図FIG. 1 is a sectional view of a main part mounting side showing a first embodiment according to the present invention.
【図２】 図１の回路基板の要部平面図及びそのＡ−Ａ
断面図2 is a plan view of a main part of the circuit board of FIG. 1 and AA thereof.
Cross section
【図３】 本発明による第２の実施例を示す要部実装側
断面図FIG. 3 is a sectional view of a main part mounting side showing a second embodiment according to the present invention.
【図４】 図３の回路基板の要部平面図及びそのＢ−Ｂ
断面図FIG. 4 is a plan view of a main part of the circuit board of FIG. 3 and its BB.
Cross section
【図５】 本発明による第３の実施例を示す要部実装側
断面図FIG. 5 is a sectional view of a main part mounting side showing a third embodiment according to the present invention.
【図６】 従来技術による要部実装側断面図FIG. 6 is a sectional view of a main part mounting side according to a conventional technique.
１は回路基板 1aは内層 1bはくぼみ穴 1b-1は第１のグランド導体 1dは取付用スルーホール 1eは熱伝導用スルーホール 1fは第２のグランド導体 ３はテープキャリア ５は第１の放熱体 ７は熱伝導性緩衝材 ８は第２の放熱体 10は半導体チップ 1 is a circuit board 1a is the inner layer 1b hollow hole 1b-1 is the first ground conductor 1d is through hole for mounting 1e is a through hole for heat conduction 1f is the second ground conductor 3 is a tape carrier 5 is the first radiator 7 is a heat conductive cushioning material 8 is the second radiator 10 is a semiconductor chip
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山▲崎▼ 直哉 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yama ▲ Saki ▼ Naoya 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Within Fujitsu Limited
Claims (3)
層(1a)にまで届き半導体チップ(10)を入れるくぼみ穴(1
b)を穿設し、該くぼみ穴(1b)の周辺を含む内面に前記内
層(1a)に接続する第１のグランド導体(1b-1)を形成し、
該くぼみ穴(1b)の第１のグランド導体(1b-1)に半導体チ
ップ(10)を電極形成面を外側にしてダイボンディングす
るとともにテープキャリア(3) で回路接続してなること
を特徴とする半導体チップの放熱実装構造。1. The circuit board (1) has a recessed hole (1) which reaches a mounting surface to reach an inner layer (1a) at a ground level and into which a semiconductor chip (10) is inserted.
b) is formed, and a first ground conductor (1b-1) connected to the inner layer (1a) is formed on the inner surface including the periphery of the recessed hole (1b),
Characterized in that the semiconductor chip (10) is die-bonded to the first ground conductor (1b-1) of the recessed hole (1b) with the electrode formation surface facing outward, and is circuit-connected with the tape carrier (3). Heat dissipation mounting structure for semiconductor chips.
形成面に熱伝導性緩衝材(7) を介挿し密着させた第１の
放熱体(5) を、第１のグランド導体(1b-1)と内層(1a)と
を接続する取付用スルーホール(1d)に取着してなること
を特徴とする半導体チップの放熱実装構造。2. A first heat dissipation member (5) having a heat conductive cushioning material (7) interposed and closely attached to the electrode formation surface of the semiconductor chip (10) according to claim 1, A heat dissipation mounting structure for a semiconductor chip, characterized by being attached to a mounting through hole (1d) for connecting 1b-1) and an inner layer (1a).
面に第１のグランド導体(1b-1)に複数の熱伝導用スルー
ホール(1e)で接続する第２のグランド導体(1f)を備え、
該第２のグランド導体(1f)面に熱伝導性緩衝材(7) を介
挿し密着させた第２の放熱体(8) と第１の放熱体(5) と
で回路基板(1) を挟み共締めしてなることを特徴とする
半導体チップの放熱実装構造。3. The circuit board (1) according to claim 1, wherein the second ground conductor (1e) is connected to the first ground conductor (1b-1) by a plurality of through holes (1e) for heat conduction on the opposite surface of the mounting. 1f),
The circuit board (1) is composed of the second heat radiator (8) and the first heat radiator (5) which are closely attached to the surface of the second ground conductor (1f) by inserting a heat conductive cushioning material (7). A heat dissipation mounting structure for semiconductor chips, characterized in that they are tightened together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3185980A JPH0529779A (en) | 1991-07-25 | 1991-07-25 | Heat-radiating mounting structure for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3185980A JPH0529779A (en) | 1991-07-25 | 1991-07-25 | Heat-radiating mounting structure for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529779A true JPH0529779A (en) | 1993-02-05 |
Family
ID=16180253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3185980A Withdrawn JPH0529779A (en) | 1991-07-25 | 1991-07-25 | Heat-radiating mounting structure for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529779A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227780A (en) * | 2006-02-24 | 2007-09-06 | Alps Electric Co Ltd | Wiring structure of semiconductor component |
-
1991
- 1991-07-25 JP JP3185980A patent/JPH0529779A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227780A (en) * | 2006-02-24 | 2007-09-06 | Alps Electric Co Ltd | Wiring structure of semiconductor component |
| JP4685660B2 (en) * | 2006-02-24 | 2011-05-18 | アルプス電気株式会社 | Wiring structure of semiconductor parts |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |