US20010001506A1 - Method of forming contact openings - Google Patents
Method of forming contact openings Download PDFInfo
- Publication number
- US20010001506A1 US20010001506A1 US09/751,212 US75121200A US2001001506A1 US 20010001506 A1 US20010001506 A1 US 20010001506A1 US 75121200 A US75121200 A US 75121200A US 2001001506 A1 US2001001506 A1 US 2001001506A1
- Authority
- US
- United States
- Prior art keywords
- forming
- layer
- electronic component
- spacers
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates generally to a method of forming contact openings and to electronic components formed from the same and other methods.
- the fabrication of certain electronic components may require that contact openings be made to both the top surface of the respective wordlines and to substrate areas adjacent thereto.
- the prior art techniques have typically included separate photo patterning, and etching steps.
- the present method provides a convenient means by which contact openings to the top surface of the wordline, and adjacent node location can be provided in a single photo masking and etching step.
- FIG. 1 is a diagrammatic section of a semiconductor wafer shown at one processing step in accordance with the present invention.
- FIG. 2 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 1.
- FIG. 3 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 2.
- FIG. 4 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 3.
- FIG. 5 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 4.
- FIG. 6 is a diagrammatic section of the FIG. 1 wafer taken through a different plane from that depicted by FIGS. 1 - 5 , and corresponds in sequence to the processing depicted by FIG. 5.
- FIG. 7 is a diagrammatic section of the FIG. 1 wafer illustrated at an alternate processing step subsequent to that shown in FIG. 1.
- FIG. 8 is a diagrammatic section of the FIG. 1 wafer illustrated at an alternative processing step subsequent to that shown in FIG. 1.
- the invention provides methods for forming a contact opening to the top surface of an electronic component, and an adjacent node location in the same masking step, as well as an electronic component formed from the same methods.
- a semiconductive wafer in process is indicated generally by reference to numeral 10 .
- An electronic component or conductive line 12 having a main body 13 is provided, as shown.
- the electronic component or conductive line 12 is positioned over a gate oxide layer 14 .
- the electronic component 12 includes a layer of conductive material 16 , which is provided over the gate layer 14 , and which comprises polysilicon.
- a tungsten silicide layer 18 is provided over the polysilicon layer 16 .
- the tungsten silicide layer has an outwardly facing surface 20 which forms the top of the conductive line or electronic component 12 .
- the conductive line or electronic component 12 as provided, has a given photomasking target area identified by the line labeled 25 .
- An oxide layer 30 is formed over the top or outwardly facing surface 20 of the conductive line of electronic component 12 . Still further, a node location 40 in the form of a diffusion region is provided adjacent the conductive line or electronic component 12 .
- the node location may comprise LDD implants or boron halo implants which are not shown. As will be recognized, the node locations 40 has a given target area identified by the line labeled 45 .
- a disposable, sacrificial, first material layer 50 preferably comprising polysilicon is formed over the oxide layer 30 .
- an optional layer of nitride 60 having a thickness of approximately 100 Angstroms is formed over the disposable, sacrificial, first material layer.
- the nitride layer 60 serves to protect the underlying sacrificial first material layer from oxidation during reoxidation of the adjacent node location 40 .
- Each of the respective layers 16 , 18 , 30 , and 50 have substantially coplanar sidewalls 70 .
- a first pair of electrically insulative anisotropically etched nitride spacers 80 are formed in covering relation relative to the sidewalls 70 .
- the insulative spacers 80 have a portion 81 which is disposed outwardly relative to the top surface 20 of the conductive line or electronic component 12 .
- the sacrificial, or first material layer 50 is disposed in covering relation relative to the top surface 20 of the electronic component 12 , and is further positioned between the first pair of insulative spacers 80 .
- the conductive line or electronic component 12 is shown following the selective removal or etching of the sacrificial, or first layer of material 50 .
- the selective etching of the sacrificial layer 50 results in an elevational void 90 being formed, or otherwise defmed between the first pair of nitride spacers 80 .
- the conductive line or electronic component 12 is shown following the provision of a second nitride layer, which has been subsequently selectively etched to provide secondary, electrically insulative spacers 100 .
- the secondary spacers 100 are disposed, on the one hand, in opposing covering relation relative to the top surface 20 ; and on the other hand in partial covering relation relative to the first pair of nitride spacers 80 , and the underlying semiconductor wafer 10 .
- the secondary nitride spacers 100 include a first pair of nitride spacers 101 , which are disposed laterally, outwardly relative to the first pair of nitride spacers 80 ; and a second pair of nitride spacers 102 , which are disposed in partial covering relation relative to the top surface 20 of the conductive line 12 , and laterally inwardly relative to the first pair of nitride spacers 80 .
- optional n + and p + implants can be provided if desired. Further, it will be seen by a study of FIGS.
- a second layer of insulative material 120 preferably comprising BPSG, is provided in covering relation relative to the electronic component 12 , and the underlying semiconductor wafer 10 .
- FIGS. 5 and 6 are different parallel plane cross-sectional cuts. Following the provision of the insulative layer 120 , and in the same masking step, first and second contact openings 132 and 130 are provided, as desired, to the node location 40 (FIG. 5), and to the top surface 20 of the conductive line 12 respectively (FIG. 6).
- the provision of the secondary nitride spacers 101 and 102 allows for some misalignment of the respective contact openings 130 and 132 to the underlying node location 40 or top surface 20 .
- electrically conductive material 134 is provided therein.
- the present method for forming a contact opening 130 to an electronic component 12 includes forming an electronic component 12 , having a top surface 20 ; forming an electrically insulative spacer 102 in partial covering relation relative to the top surface 20 ; forming an insulating layer 120 over the spacer 102 and top surface 20 ; and selectively etching the insulative layer 120 relative to the spacer 102 to form a contact opening to the electronic component top surface 20 .
- FIG. 7 illustrates a misalignment of a contact mask to a node location
- FIG. 8 illustrates undesired misalignment but which is not as onerous as shown in FIG. 7.
- the second form of the invention includes a semiconductor wafer in process 10 and a conductive line or electronic component 12 positioned thereon.
- the conductive line or electronic component 12 has a construction similar to that earlier disclosed. More precisely, the electronic component 12 comprises a polysilicon layer 16 which is formed outwardly of a gate oxide layer 14 . Further, a tungsten silicide layer 18 is formed over the polysilicon layer 16 .
- the conductive line or electronic component 12 has a top surface 20 , and sidewalls 70 .
- a layer of nitride is formed over the conductive line 12 , and is subsequently, anisotropically etched to form the resulting nitride sidewall 140 spacers.
- the electrically insulative nitride sidewall spacers 140 are formed over the conductive sidewall surface 70 and project outwardly of the conductive line top conductive surface 20 .
- the resulting nitride sidewall spacers 140 define an elevational void 142 therebetween.
- a layer of oxide 144 (preferably Novellas or produced from decomposition of TEOS) is then formed over the top surface 20 of the electronic component and between the pair of nitride sidewall spacers 140 within void 142 .
- An electrically insulative layer 146 preferably comprising BPSG, is formed outwardly of the conductive line 12 and over the adjacent node location 40 . Thereafter, in the same masking step, a contact opening 148 is formed through the electrically insulative layer.
- the etching chemistry employed is selective relative to the nitride sidewall spacers 140 .
- the etching chemistry employed results in a lag time in the etch of material 144 , thereby permitting misalignment of the mask. Therefore, electrical contact to the top surface 20 of the underlying conductive line 12 is avoided.
- a method for forming a contact opening 148 of the present invention comprises providing a node location 40 to which electrical connection is to be made; forming a conductive line 12 adjacent the node location 40 , the conductive line 12 having top 20 and sidewall surfaces 70 ; forming an electrically insulative oxide 144 in covering relation relative to the top surface 20 of the conductive line 12 ; forming electrically insulative nitride sidewall spacers 140 over the conductive sidewall surfaces 70 ; the nitride sidewall spacers 140 projecting outwardly of the conductive line top conductive surface 20 , the electrically insulative oxide 144 positioned between the nitride sidewall spacers 140 ; forming an electrically insulative layer 146 outwardly of the conductive line 12 , and node location 40 ; and etching a contact opening 148 to the node location 40 through the electrically insulative layer 146 substantially selective relative to the nitride sidewall spacers 140 .
- the method of the prevent invention results in an electronic component 12 comprising a main body 13 having sidewalls 70 , and a top surface 20 ; a primary electrically insulative spacer 80 of a first material disposed in substantially covering relation relative to one of the sidewalls 70 of the electronic component 12 , the primary electrically insulative spacer extending above the top surface 20 of the electronic component; and a secondary electrically insulative spacer 102 formed laterally inwardly relative to the primary electrically insulative spacer 80 , the secondary insulative spacer 102 disposed in partial covering relation relative to the top surface 20 of the electronic component 12 .
- One aspect of the present invention relates to a method for forming first and second contact openings, comprising:
- a method for forming first and second contact openings comprises:
- Yet still another aspect of the present invention relates to a method for forming a contact opening comprising:
- Still another aspect of the present invention relates to a method for forming a contact opening comprising:
- Another aspect of the present invention relates to a method for forming a contact opening to an electronic component 12 , comprising:
- Still a further aspect of the present invention relates to a method for forming first and second contact openings comprising:
- Yet still another aspect of the present invention relates to an electronic component comprising:
- a main body 12 having sidewalls 70 and a top surface 20 ;
- a primary electrically insulative spacer 80 of a first material disposed in substantially covering relation relative to one of the sidewalls 70 of the electronic component 12 , the primary electrically insulative spacer 80 extending above the top surface of the electronic component 12 ;
- a secondary electrically insulative spacer 100 provided laterally inwardly relative to the primary electrically insulative spacer 80 , the secondary electrically insulative spacer 100 disposed in partial covering relation relative to the top surface 20 of the electronic component 12 .
Abstract
Description
- This invention relates generally to a method of forming contact openings and to electronic components formed from the same and other methods.
- As various electronic components such as DRAMS have increased in memory cell density, designers face a continuous challenge to provide contact openings to predetermined node locations, and to the top surface of conductive lines.
- Heretofore, so-called self-aligned contact openings are provided to node locations which are adjacent to wordlines, by first encapsulating the wordline in nitride spacers, and providing a nitride cap thereover. Once this is achieved, a silicon dioxide layer in the form of BPSG, is provided over the encapsulated wordline. Following the provision of the layer of BPSG, the contact opening is etched. In view of perceived shortcomings in the prior art techniques, the patterning and etching of the contact openings through the layer of BPSG to the node location, can be somewhat misaligned. To address this problem, an etching chemistry is provided which is selective to nitride and therefore the etching will stop on the nitride material which encapsulates the wordline.
- In addition to the foregoing, the fabrication of certain electronic components may require that contact openings be made to both the top surface of the respective wordlines and to substrate areas adjacent thereto. To make electrical contact to the top surface of wordlines, the prior art techniques have typically included separate photo patterning, and etching steps. The present method provides a convenient means by which contact openings to the top surface of the wordline, and adjacent node location can be provided in a single photo masking and etching step.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
- FIG. 1 is a diagrammatic section of a semiconductor wafer shown at one processing step in accordance with the present invention.
- FIG. 2 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 1.
- FIG. 3 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 2.
- FIG. 4 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 3.
- FIG. 5 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 4.
- FIG. 6 is a diagrammatic section of the FIG. 1 wafer taken through a different plane from that depicted by FIGS.1-5, and corresponds in sequence to the processing depicted by FIG. 5.
- FIG. 7 is a diagrammatic section of the FIG. 1 wafer illustrated at an alternate processing step subsequent to that shown in FIG. 1.
- FIG. 8 is a diagrammatic section of the FIG. 1 wafer illustrated at an alternative processing step subsequent to that shown in FIG. 1.
- The invention provides methods for forming a contact opening to the top surface of an electronic component, and an adjacent node location in the same masking step, as well as an electronic component formed from the same methods.
- This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
- Preferred embodiments of the present invention are collectively shown by the accompanying drawings as will become apparent from the continuing discussion.
- Referring first to FIG. 1, a semiconductive wafer in process is indicated generally by reference to
numeral 10. An electronic component orconductive line 12 having amain body 13 is provided, as shown. The electronic component orconductive line 12 is positioned over agate oxide layer 14. Theelectronic component 12 includes a layer ofconductive material 16, which is provided over thegate layer 14, and which comprises polysilicon. Atungsten silicide layer 18 is provided over thepolysilicon layer 16. The tungsten silicide layer has an outwardly facingsurface 20 which forms the top of the conductive line orelectronic component 12. The conductive line orelectronic component 12, as provided, has a given photomasking target area identified by the line labeled 25. - An
oxide layer 30 is formed over the top or outwardly facingsurface 20 of the conductive line ofelectronic component 12. Still further, anode location 40 in the form of a diffusion region is provided adjacent the conductive line orelectronic component 12. The node location may comprise LDD implants or boron halo implants which are not shown. As will be recognized, thenode locations 40 has a given target area identified by the line labeled 45. - A disposable, sacrificial,
first material layer 50 preferably comprising polysilicon is formed over theoxide layer 30. Still further, an optional layer ofnitride 60 having a thickness of approximately 100 Angstroms is formed over the disposable, sacrificial, first material layer. Thenitride layer 60 serves to protect the underlying sacrificial first material layer from oxidation during reoxidation of theadjacent node location 40. Each of therespective layers coplanar sidewalls 70. - Referring now to FIG. 2, a first pair of electrically insulative anisotropically etched
nitride spacers 80 are formed in covering relation relative to thesidewalls 70. Theinsulative spacers 80 have aportion 81 which is disposed outwardly relative to thetop surface 20 of the conductive line orelectronic component 12. The sacrificial, orfirst material layer 50 is disposed in covering relation relative to thetop surface 20 of theelectronic component 12, and is further positioned between the first pair ofinsulative spacers 80. - Referring now to FIG. 3, the conductive line or
electronic component 12 is shown following the selective removal or etching of the sacrificial, or first layer ofmaterial 50. The selective etching of thesacrificial layer 50 results in anelevational void 90 being formed, or otherwise defmed between the first pair ofnitride spacers 80. - Referring now to FIG. 4, the conductive line or
electronic component 12 is shown following the provision of a second nitride layer, which has been subsequently selectively etched to provide secondary, electricallyinsulative spacers 100. Thesecondary spacers 100 are disposed, on the one hand, in opposing covering relation relative to thetop surface 20; and on the other hand in partial covering relation relative to the first pair ofnitride spacers 80, and the underlying semiconductor wafer 10. Thesecondary nitride spacers 100 include a first pair ofnitride spacers 101, which are disposed laterally, outwardly relative to the first pair ofnitride spacers 80; and a second pair ofnitride spacers 102, which are disposed in partial covering relation relative to thetop surface 20 of theconductive line 12, and laterally inwardly relative to the first pair ofnitride spacers 80. Following the provisions of thesecondary spacers 100, optional n+and p+implants can be provided if desired. Further, it will be seen by a study of FIGS. 1 and 4, that the provision of thesecondary nitride spacers 102 increases the mask misalignment area for hitting thenode location 40 by the width ofspacers 102. It will be recognized, therefore, that misalignment of a subsequent mask for making contact to thenode location 40 in a dimension of less than or equal to the dimension of the width ofspacers 102, will not result in making electrical contact to the underlyingelectronic component 12. Further, it will also be recognized that thesecondary nitride spacers 101 provide an analogous added mask misalignment dimension equal to the width ofspacers 101 when targeting for thetop surface 20. - Referring now to FIGS.5, and 6, a second layer of
insulative material 120, preferably comprising BPSG, is provided in covering relation relative to theelectronic component 12, and theunderlying semiconductor wafer 10. FIGS. 5 and 6 are different parallel plane cross-sectional cuts. Following the provision of theinsulative layer 120, and in the same masking step, first andsecond contact openings top surface 20 of theconductive line 12 respectively (FIG. 6). As shown and discussed above, the provision of thesecondary nitride spacers respective contact openings underlying node location 40 ortop surface 20. Following the provision of theindividual contact openings conductive material 134 is provided therein. - As seen in FIG. 6, therefore, the present method for forming a
contact opening 130 to anelectronic component 12 includes forming anelectronic component 12, having atop surface 20; forming an electricallyinsulative spacer 102 in partial covering relation relative to thetop surface 20; forming aninsulating layer 120 over thespacer 102 andtop surface 20; and selectively etching theinsulative layer 120 relative to thespacer 102 to form a contact opening to the electroniccomponent top surface 20. - Referring now to FIGS. 7 and 8, a second alternate form of the invention is shown. FIG. 7 illustrates a misalignment of a contact mask to a node location, whereas FIG. 8 illustrates undesired misalignment but which is not as onerous as shown in FIG. 7. In particular, the second form of the invention, as seen in FIG. 7, includes a semiconductor wafer in
process 10 and a conductive line orelectronic component 12 positioned thereon. The conductive line orelectronic component 12 has a construction similar to that earlier disclosed. More precisely, theelectronic component 12 comprises apolysilicon layer 16 which is formed outwardly of agate oxide layer 14. Further, atungsten silicide layer 18 is formed over thepolysilicon layer 16. The conductive line orelectronic component 12 has atop surface 20, and sidewalls 70. - A layer of nitride is formed over the
conductive line 12, and is subsequently, anisotropically etched to form the resultingnitride sidewall 140 spacers. The electrically insulative nitride sidewall spacers 140 are formed over theconductive sidewall surface 70 and project outwardly of the conductive line topconductive surface 20. The resultingnitride sidewall spacers 140 define anelevational void 142 therebetween. A layer of oxide 144 (preferably Novellas or produced from decomposition of TEOS) is then formed over thetop surface 20 of the electronic component and between the pair ofnitride sidewall spacers 140 withinvoid 142. An electricallyinsulative layer 146, preferably comprising BPSG, is formed outwardly of theconductive line 12 and over theadjacent node location 40. Thereafter, in the same masking step, acontact opening 148 is formed through the electrically insulative layer. The etching chemistry employed is selective relative to thenitride sidewall spacers 140. The etching chemistry employed (RIE) results in a lag time in the etch ofmaterial 144, thereby permitting misalignment of the mask. Therefore, electrical contact to thetop surface 20 of the underlyingconductive line 12 is avoided. - Accordingly, a method for forming a
contact opening 148 of the present invention comprises providing anode location 40 to which electrical connection is to be made; forming aconductive line 12 adjacent thenode location 40, theconductive line 12 havingtop 20 and sidewall surfaces 70; forming anelectrically insulative oxide 144 in covering relation relative to thetop surface 20 of theconductive line 12; forming electrically insulativenitride sidewall spacers 140 over the conductive sidewall surfaces 70; thenitride sidewall spacers 140 projecting outwardly of the conductive line topconductive surface 20, theelectrically insulative oxide 144 positioned between thenitride sidewall spacers 140; forming an electricallyinsulative layer 146 outwardly of theconductive line 12, andnode location 40; and etching acontact opening 148 to thenode location 40 through theelectrically insulative layer 146 substantially selective relative to thenitride sidewall spacers 140. As seen in FIGS. 5 through 8, the method of the present invention provides a convenient means for making contact openings, in the same masking step, to both thenode location 40, and thetop surface 20 of the electronic component 11. - Still fuirther, the method of the prevent invention results in an
electronic component 12 comprising amain body 13 havingsidewalls 70, and atop surface 20; a primary electrically insulative spacer 80 of a first material disposed in substantially covering relation relative to one of thesidewalls 70 of theelectronic component 12, the primary electrically insulative spacer extending above thetop surface 20 of the electronic component; and a secondary electricallyinsulative spacer 102 formed laterally inwardly relative to the primary electricallyinsulative spacer 80, thesecondary insulative spacer 102 disposed in partial covering relation relative to thetop surface 20 of theelectronic component 12. - The invention as disclosed above is believed to be readily apparent and is briefly summarized at this point.
- One aspect of the present invention relates to a method for forming first and second contact openings, comprising:
- providing an
electronic component 12 having atop surface 20 on asemiconductive substrate 10, thesemiconductive substrate 10 having anode location 40 to which electrical contact is to be made; - forming a layer of
insulative material 120 in covering relation relative to theelectronic component 12; and - in the same masking step, forming the first contact opening132 through the layer of
insulative material 120 to thetop surface 20 of theelectronic component 12, and the second contact opening 130 through the layer ofinsulative material 120 to thenode location 40. - In accordance with another aspect of the present invention, a method for forming first and second contact openings comprises:
- providing an
electronic component 12 on asemiconductive substrate 10, theelectronic component 12 having asidewall 70 and atop surface 20, and the semiconductive substrate having anode location 40 to which electrical contact is to be made; - forming an
insulative spacer 80 on thesidewall 70 of theelectronic component 12, theinsulative spacer 80 having aportion 81 which is disposed outwardly relative to thetop surface 20 of theelectronic component 12; - forming a first layer of
material 50 in covering relation relative to thetop surface 20 of theelectronic component 12; - forming a second layer of
insulative material 120 in covering relation relative to theelectronic component 12 and thesemiconductive substrate 10; and - in the same masking step, forming the first contact opening132 through the second layer of
material 120 to thetop surface 20 of theelectronic component 12 and the second contact opening 130 through the second layer ofmaterial 120 to thenode location 40. - Yet still another aspect of the present invention relates to a method for forming a contact opening comprising:
- providing a
node location 40 on asemiconductive substrate 10 to which electrical contact is to be made; - forming an
electronic component 12 on thesemiconductive substrate 10 adjacent to thenode location 40, theelectronic component 12 havingsidewaUs 70 and atop surface 20; - forming a
first spacer 80 on at least one of thesidewalls 70 of theelectronic component 12; - forming a
second spacer 100 in partial covering relation relative to thetop surface 20 of theelectronic component 12; - forming an insulative layer of
material 120 over theelectronic component 12, the first andsecond spacers node location 40; and - selectively removing the
insulative layer 120 relative to the first andsecond spacers contact opening node location 40, or thetop surface 20 of theelectronic component 12. - Still another aspect of the present invention relates to a method for forming a contact opening comprising:
- providing a
node location 40 on asubstrate 10 to which electrical contact is to be made; - providing an
electronic component 12 on thesubstrate 10, and adjacent thenode location 40, theelectronic component 12 havingsidewalls 70 and an electrically conductivetop surface 20; - forming a
first spacer 80 on at least one of thesidewalls 70 of theelectronic component 12; - forming a
second spacer 100 in partial covering relation relative to thetop surface 20 of theelectronic component 12; - forming an insulative layer of
material 120 over theelectronic component 12, the first andsecond spacers node location 40; and - selectively removing the
insulative layer 120 relative to the first andsecond spacers contact opening 132 to the electrically conductivetop surface 20 of theelectronic component 12. - Another aspect of the present invention relates to a method for forming a contact opening to an
electronic component 12, comprising: - providing an
electronic component 12 having atop surface 20; - providing an electrically
insulative spacer 100 in partial covering relation relative to thetop surface 20; - providing an insulating
layer 120 over thespacer 100 and thetop surface 20; and - selectively removing the
insulative layer 120 relative to thespacer 100 to form acontact opening 132 to theelectronic component 12top surface 20. - Still a further aspect of the present invention relates to a method for forming first and second contact openings comprising:
- providing a
node location 40 to which electrical connection is to be made; - forming a
conductive line 12 adjacent thenode location 40, theconductive line 12 having conductive top 20 and sidewall surfaces 70; - forming a
first material layer 50 over theconductive line 12top surface 10; - forming electrically
insulative sidewall spacers 80 of a second material over the conductive sidewall surfaces 70, thesidewall spacers 70 projecting outwardly of theconductive line 12top surface 20, the electrically insulativefirst material 50 being provided between the sidewall spacers; - forming an electrically
insulative layer 120 outwardly of thenode location 40, the firstmaterial insulative layer 50, and secondmaterial sidewall spacers 80; and - in the same masking step, etching a first contact opening130 through the electrically insulative layer to the
node location 40, and a second contact opening 132 to the conductive line conductivetop surface 20, the etching being substantially selective relative to the second material of thesidewall spacers 80. - Yet still another aspect of the present invention relates to an electronic component comprising:
- a
main body 12 havingsidewalls 70 and atop surface 20; - a primary electrically insulative spacer80 of a first material disposed in substantially covering relation relative to one of the
sidewalls 70 of theelectronic component 12, the primary electrically insulative spacer 80 extending above the top surface of theelectronic component 12; and - a secondary electrically
insulative spacer 100 provided laterally inwardly relative to the primary electricallyinsulative spacer 80, the secondary electricallyinsulative spacer 100 disposed in partial covering relation relative to thetop surface 20 of theelectronic component 12. - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the Doctrine of Equivalents.
Claims (70)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/751,212 US6271126B2 (en) | 1998-07-31 | 2000-12-29 | Method of forming contact openings |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/127,577 US6140219A (en) | 1996-08-22 | 1998-07-31 | Method of forming contact openings |
US09/285,322 US6261948B1 (en) | 1998-07-31 | 1999-04-02 | Method of forming contact openings |
US09/751,212 US6271126B2 (en) | 1998-07-31 | 2000-12-29 | Method of forming contact openings |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/285,322 Division US6261948B1 (en) | 1998-07-31 | 1999-04-02 | Method of forming contact openings |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010001506A1 true US20010001506A1 (en) | 2001-05-24 |
US6271126B2 US6271126B2 (en) | 2001-08-07 |
Family
ID=22430817
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/285,322 Expired - Lifetime US6261948B1 (en) | 1998-07-31 | 1999-04-02 | Method of forming contact openings |
US09/751,212 Expired - Lifetime US6271126B2 (en) | 1998-07-31 | 2000-12-29 | Method of forming contact openings |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/285,322 Expired - Lifetime US6261948B1 (en) | 1998-07-31 | 1999-04-02 | Method of forming contact openings |
Country Status (1)
Country | Link |
---|---|
US (2) | US6261948B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014039166A1 (en) * | 2012-09-10 | 2014-03-13 | International Business Machines Corporation | Self-aligned contacts |
US9620619B2 (en) * | 2012-01-12 | 2017-04-11 | Globalfoundries Inc. | Borderless contact structure |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6586809B2 (en) * | 2001-03-15 | 2003-07-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
KR102167625B1 (en) * | 2013-10-24 | 2020-10-19 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
Family Cites Families (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4281448A (en) | 1980-04-14 | 1981-08-04 | Gte Laboratories Incorporated | Method of fabricating a diode bridge rectifier in monolithic integrated circuit structure utilizing isolation diffusions and metal semiconductor rectifying barrier diode formation |
US4936928A (en) | 1985-11-27 | 1990-06-26 | Raytheon Company | Semiconductor device |
US5272367A (en) | 1988-05-02 | 1993-12-21 | Micron Technology, Inc. | Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) |
JP2934325B2 (en) | 1990-05-02 | 1999-08-16 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5243219A (en) | 1990-07-05 | 1993-09-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having impurity diffusion region formed in substrate beneath interlayer contact hole |
US5104822A (en) | 1990-07-30 | 1992-04-14 | Ramtron Corporation | Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method |
US5206187A (en) | 1991-08-30 | 1993-04-27 | Micron Technology, Inc. | Method of processing semiconductor wafers using a contact etch stop |
US5166096A (en) | 1991-10-29 | 1992-11-24 | International Business Machines Corporation | Process for fabricating self-aligned contact studs for semiconductor structures |
JP3086747B2 (en) | 1992-05-07 | 2000-09-11 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JPH06140396A (en) | 1992-10-23 | 1994-05-20 | Yamaha Corp | Semiconductor device and manufacture thereof |
US5444003A (en) | 1993-06-23 | 1995-08-22 | Vlsi Technology, Inc. | Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure |
JP3219909B2 (en) | 1993-07-09 | 2001-10-15 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5372960A (en) | 1994-01-04 | 1994-12-13 | Motorola, Inc. | Method of fabricating an insulated gate semiconductor device |
US5429977A (en) | 1994-03-11 | 1995-07-04 | Industrial Technology Research Institute | Method for forming a vertical transistor with a stacked capacitor DRAM cell |
US5661053A (en) | 1994-05-25 | 1997-08-26 | Sandisk Corporation | Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
DE69431181D1 (en) | 1994-05-19 | 2002-09-19 | Cons Ric Microelettronica | Power integrated circuit ("PIC") and method of making the same |
US5710450A (en) | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
WO1996027901A1 (en) | 1995-03-07 | 1996-09-12 | Micron Technology, Inc. | Improved semiconductor contacts to thin conductive layers |
US5874359A (en) * | 1995-04-27 | 1999-02-23 | Industrial Technology Research Institute | Small contacts for ultra large scale integration semiconductor devices without separation ground rule |
US5547892A (en) | 1995-04-27 | 1996-08-20 | Taiwan Semiconductor Manufacturing Company | Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors |
EP0749156B1 (en) | 1995-05-23 | 1999-08-11 | Siemens Aktiengesellschaft | Semiconductor device with self-aligned contacts and method of fabrication |
JP3193845B2 (en) | 1995-05-24 | 2001-07-30 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
KR0155831B1 (en) | 1995-06-20 | 1998-12-01 | 김광호 | Fabrication method of semiconductor device |
US5899712A (en) | 1995-08-21 | 1999-05-04 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating silicon-on-insulator device |
US5960318A (en) | 1995-10-27 | 1999-09-28 | Siemens Aktiengesellschaft | Borderless contact etch process with sidewall spacer and selective isotropic etch process |
KR100206878B1 (en) | 1995-12-29 | 1999-07-01 | 구본준 | Process for fabricating semiconductor device |
US5686329A (en) | 1995-12-29 | 1997-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity |
KR0179806B1 (en) | 1995-12-30 | 1999-03-20 | 문정환 | Method of manufacturing semiconductor memory cell |
US5858832A (en) | 1996-03-11 | 1999-01-12 | Chartered Semiconduction Manufacturing Ltd. | Method for forming a high areal capacitance planar capacitor |
US5736441A (en) | 1996-03-15 | 1998-04-07 | United Microelectronics Corporation | High-capacitance dynamic random access memory cell and method for fabricating the same |
US5652174A (en) | 1996-05-20 | 1997-07-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors |
US5668021A (en) | 1996-06-04 | 1997-09-16 | Motorola, Inc. | Process for fabricating a semiconductor device having a segmented channel region |
US5612240A (en) | 1996-06-13 | 1997-03-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for making electrical connections to self-aligned contacts that extends beyond the photo-lithographic resolution limit |
US5811350A (en) | 1996-08-22 | 1998-09-22 | Micron Technology, Inc. | Method of forming contact openings and an electronic component formed from the same and other methods |
US5970360A (en) | 1996-12-03 | 1999-10-19 | Mosel Vitelic Inc. | DRAM cell with a roughened poly-Si electrode |
JP2925008B2 (en) | 1997-01-30 | 1999-07-26 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5930618A (en) | 1997-08-04 | 1999-07-27 | United Microelectronics Corp. | Method of Making High-K Dielectrics for embedded DRAMS |
JP3807836B2 (en) | 1997-11-28 | 2006-08-09 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method of semiconductor device |
US5895269A (en) | 1997-12-18 | 1999-04-20 | Advanced Micro Devices, Inc. | Methods for preventing deleterious punch-through during local interconnect formation |
KR100297711B1 (en) | 1998-07-20 | 2001-08-07 | 윤종용 | Method for fabricating mask ROM |
US6093609A (en) | 1998-11-18 | 2000-07-25 | United Microelectronics Corp. | Method for forming semiconductor device with common gate, source and well |
-
1999
- 1999-04-02 US US09/285,322 patent/US6261948B1/en not_active Expired - Lifetime
-
2000
- 2000-12-29 US US09/751,212 patent/US6271126B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620619B2 (en) * | 2012-01-12 | 2017-04-11 | Globalfoundries Inc. | Borderless contact structure |
WO2014039166A1 (en) * | 2012-09-10 | 2014-03-13 | International Business Machines Corporation | Self-aligned contacts |
US8853076B2 (en) | 2012-09-10 | 2014-10-07 | International Business Machines Corporation | Self-aligned contacts |
Also Published As
Publication number | Publication date |
---|---|
US6271126B2 (en) | 2001-08-07 |
US6261948B1 (en) | 2001-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5811350A (en) | Method of forming contact openings and an electronic component formed from the same and other methods | |
JP3398649B2 (en) | Method of doping gate conductors with dopants of different conductivity types | |
US6285073B1 (en) | Contact structure and method of formation | |
US7365400B2 (en) | Semiconductor device and method for manufacturing the same | |
US20040175919A1 (en) | Borderless contact structure and method of forming the same | |
US5811329A (en) | Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide | |
JPH1174508A (en) | Semiconductor device and its manufacture | |
US5939761A (en) | Method of forming a field effect transistor | |
US6501140B2 (en) | Transistor structures | |
US6297136B1 (en) | Method for fabricating an embedded semiconductor device | |
US6486516B1 (en) | Semiconductor device and a method of producing the same | |
US6271126B2 (en) | Method of forming contact openings | |
US20020028558A1 (en) | Method for forming gate electrode of MOS type transistor | |
US6753215B2 (en) | Methods for manufacturing semiconductor devices and semiconductor devices | |
US5986347A (en) | Processing methods of forming contact openings and integrated circuitry | |
US6221745B1 (en) | High selectivity mask oxide etching to suppress silicon pits | |
US6521517B1 (en) | Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer | |
KR100277905B1 (en) | Manufacturing Method of Semiconductor Memory Device | |
US20030203568A1 (en) | Semiconductor device manufacturing method and semiconductor device | |
US7259070B2 (en) | Semiconductor devices and methods for fabricating the same | |
JPH0897210A (en) | Semiconductor device and its manufacture | |
JPH09213949A (en) | Semiconductor device manufacturing method | |
JPH06244415A (en) | Semiconductor device and manufacture thereof | |
JPH088208A (en) | Formation method of contact hole in semiconductor element | |
JPH08139313A (en) | Manufacture of mis-fet |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |