US11967651B2 - Silicon carbide power diode device and fabrication method thereof - Google Patents

Silicon carbide power diode device and fabrication method thereof Download PDF

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US11967651B2
US11967651B2 US17/828,782 US202217828782A US11967651B2 US 11967651 B2 US11967651 B2 US 11967651B2 US 202217828782 A US202217828782 A US 202217828782A US 11967651 B2 US11967651 B2 US 11967651B2
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silicon carbide
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type regions
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US20220293800A1 (en
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Yonghong Tao
Zhidong Lin
Zhigao Peng
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Xiamen Sanan Integrated Circuit Co Ltd
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Xiamen Sanan Integrated Circuit Co Ltd
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Priority claimed from CN202021269885.2U external-priority patent/CN212725323U/en
Priority claimed from CN202010626793.3A external-priority patent/CN112038398B/en
Priority claimed from CN202010626798.6A external-priority patent/CN112038393B/en
Priority claimed from US16/928,373 external-priority patent/US11437525B2/en
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Priority to US17/828,782 priority Critical patent/US11967651B2/en
Assigned to XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD. reassignment XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, Zhidong, PENG, Zhigao, TAO, YONGHONG
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    • H01L29/872—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H01L29/1608—
    • H01L29/456—
    • H01L29/66143—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions

Definitions

  • the present invention relates to the technical field of semiconductor devices, and more particularly, to a silicon carbide power diode device and a method for manufacturing a silicon carbide power diode device.
  • SiC devices Compared with traditional Si-based devices, SiC devices have the characteristics of faster operating frequency, less operating loss, and higher operating temperature. As a representative device of SiC power devices, SiC diodes are widely used in power supplies, new energy vehicles and other fields.
  • SiC SBD Schottky Barrier Diode
  • SiC JBS Junction Barrier Schottky
  • SiC MPS Merged PiN Schottky
  • SiC MPS usually forms multiple P-type implanted regions in the active region, and ohmic contact metal is grown on each P-type implanted region, but due to the existing equipment (lithography machine) and etching process restrictions, in order to better etch the P-type implanted area and facilitate the growth of ohmic contact metal, it is necessary to appropriately increase the area of the P-type implanted area to achieve a better process window, otherwise an excessively high aspect ratio is difficult to carry out etch and metal growth and other etch related processes; and in order to ensure that the inrush current of the device is large enough and the current is stable enough, it is necessary to set up enough P-type injection regions, which directly leads to the reduction of the N-type conductive region and the forward voltage drop Increased, the device conduction loss increases. Therefore, in the case of ensuring the size of the N-type conductive region, there is a contradiction between the number requirements of the P-type injection region and the design direction of miniaturization.
  • the purpose of the present invention is to overcome the shortcomings of the current technology, to provide a silicon carbide power diode device and its preparation method, while ensuring that the MPS device has good forward surge capability and forward conduction characteristics, while avoiding the process of ohmic contact Process problems caused by narrow windows.
  • the technical solution of the present invention is as follows:
  • a silicon carbide power diode device includes at least:
  • SiC substrate SiC epitaxial layer, Disposed on the first surface of the SiC substrate, the SiC epitaxial layer is provided with an active region;
  • the Schottky metal layer is provided on the surface of the active area of the SiC epitaxial layer;
  • the first electrode layer is provided on the surface of the Schottky metal layer
  • the first ohmic contact metal layer is provided on the second surface of the SiC substrate;
  • the second electrode layer is provided on the surface of the first ohmic contact metal layer
  • the active region includes at least one or a plurality of first P-type regions, a plurality of second P-type regions, and an N-type region.
  • the first P-type region and the second P-type region are spaced apart; the surface of the first P-type region is provided with a A second ohmic contact metal layer, the second ohmic contact metal layer is located between the first P-type region and the Schottky metal layer, and the second P-type region is not provided with an ohmic contact metal layer.
  • the active area of the silicon carbide epitaxial layer is given the size of the first P-type region (including but not limited to the surface area) and then the size of the second P-type region (including but not limited to the surface area) is minimized and (Maximum size of N-type area including but not limited to surface area).
  • the size (including but not limited to the surface area) of the first P-type region given is wider than the size (including but not limited to the surface area) of the second P-type region (including but not limited to the width) settings.
  • the second ohmic contact metal layer completely covers the first P-type region.
  • the second ohmic contact metal layer is a bulk metal layer that does not completely cover the first P-type region.
  • the first P-type region and the second P-type region are both strip-shaped, and the width of the surface of any first P-type region is greater than the width of any second P-type region.
  • each first P-type region has the same width and is arranged at equal intervals.
  • the widths of the first P-type regions are not all the same.
  • the distance between the adjacent sides of the adjacent first P-type regions is the same, that is, the distance between the opposite sides of the first P-type region is the same between the adjacent first P-type regions.
  • the first P-type region and the second P-type region are block regions.
  • the plane area of the surface of any one first P-type region is larger than the plane area of the surface of any one second P-type region.
  • the first P-type region and the second P-type region are rectangular regions, trapezoidal regions, regular polygonal regions (such as regular hexagons), circular regions, irregular regions, or a combination thereof.
  • first P-type region and the second P-type region are a combination of stripe and block regions (for example, square regions).
  • At least one first P-type region is strip-shaped, and at least one second P-type region is a block region, and the plane area of the surface of the first P-type region is larger than the plane area of the surface of the second P-type region.
  • At least one first P-type region is a block region
  • at least one second P-type region is a bar shape, and the radial width of the surface of the first P-type region in any direction is greater than the surface width of the second P-type region.
  • the total planar area of the surface of the N-type region is 1 to 10 times the total planar area of the surface of the first P-type region and the surface of the second P-type region.
  • the value of the surface width of any first P-type region is 1-10 ⁇ m, and the number is ⁇ 2.
  • the surface width of any second P-type region is ⁇ 0.1 ⁇ m.
  • the first ohmic contact metal layer and the second ohmic contact metal layer are any one or a combination of Ti, Ni, Al, Au, Ta, or W.
  • the Schottky metal layer is any one or a combination of Ti, W, Ta, Ni, Mo or Pt.
  • a method for manufacturing a silicon carbide power diode device includes the following steps:
  • the surface of the first P-type region is completely covered or partially covered with a metal layer, and the surface of the second P-type region is not covered with a metal layer; through high-temperature annealing, a second ohmic contact metal layer is formed on the surface of the first P-type region
  • the SiC epitaxial surface is covered with a metal layer, which is annealed at high temperature to form a Schottky metal layer, and the first electrode layer is deposited on the Schottky metal layer.
  • step 2) the implantation area in the terminal area is also opened by etching, and ion implantation is performed in the implantation area of the terminal area; by activation (such as high temperature activation), the terminal area forms a terminal structure.
  • step 5 growing a first passivation layer on the surface of the terminal structure, forming a second passivation layer on the surface of the first passivation layer; etching to obtain the contact area of the first electrode layer; on the surface of the first ohmic contact metal layer A second electrode layer is deposited.
  • step 3) or step 5) further includes the steps of: covering a second layer of the SiC substrate with a metal layer, and forming a first ohmic contact metal layer on the second surface of the SiC substrate by high-temperature annealing, A second electrode layer is deposited on the surface of the first ohmic contact metal layer.
  • the high-temperature annealing process for forming the first ohmic contact metal layer and the second ohmic contact metal layer is 800° C. 1100° C. 1100° C., the time is 60 s-300 s; the high-temperature annealing process to form the Schottky metal layer, the temperature is 300° C.-500° C. time is 60 s-300 s.
  • the thickness of the first electrode layer is 25 ⁇ m; the thickness of the first passivation layer is 0.5 3 ⁇ m; and the thickness of the second electrode layer is 2-5 ⁇ m.
  • the first ohmic contact metal layer and the second ohmic contact metal layer are any one or a combination of Ti, Ni, Al, Au, Ta or W.
  • the Schottky metal layer is any one or a combination of Ti, W Ta, Ni, Mo or Pt.
  • the first P-type region and the second P-type region are both strip-shaped, and the surface area of any one first P-type region is larger than the surface area of any one second P-type region.
  • the first P-type region and the second P-type region are block regions, and the surface area of any one first P-type region is larger than the surface area of any one second P-type region.
  • the first P-type region and the second P-type region are a combination of strip and block regions; when the first P-type region is a strip and the second P-type region is a block region, the surface of the first P-type region The surface area of the first P-type region is larger than the surface area of the second P-type region; when the first P-type region is a block region and the second P-type region is a strip, the radial width of the first P-type region surface in any direction Second P-type surface width.
  • the silicon carbide power diode device of the present invention is provided with P-type regions of roughly two specifications.
  • the surface of the first P-type region with larger surface area and wider coverage is covered with ohmic contact metal, and the surface area with smaller surface area and narrower There is no ohmic contact metal on the surface of the second P-type region.
  • the current passes through the N-type region of the active region; under the condition of high current, the forward voltage of the diode rises, and the PiN diode barrier formed by the surface of the first P-type region covered by the ohmic contact is turned on. Current can pass through this area, thereby improving the surge current capability of the diode.
  • the preparation method of the silicon carbide power diode device of the present invention is used to prepare the silicon carbide power diode device of the present invention.
  • the N-type region of the diode is the region that conducts current.
  • the surface area of the P-type region is the same, the larger the surface area of the N-type region, the stronger the forward current capability of the diode.
  • the surface area of the N-type region is the same, the larger the area of the surface of the P-type region covered with the ohmic contact metal, the greater the surge capability of the diode.
  • the silicon carbide power diode device of the present invention uses two different specifications of P-type regions, the surface of the first P-type region with larger surface area and wider coverage is covered with ohmic metal, and the second P-type region with smaller surface area and narrower There is no ohmic contact metal on the surface of the zone.
  • the combination of the two can increase the current density of the diode and reduce the on-voltage drop while maintaining the same surge capacity of the diode.
  • FIG. 1 is a schematic structural diagram of an active region in Embodiment 1 (the second ohmic contact metal layer completely covers the first P-type region);
  • FIG. 2 is a schematic cross-sectional view of Embodiment 1 (the second ohmic contact metal layer completely covers the first P-type region);
  • FIG. 3 is a schematic structural diagram of an active region according to Embodiment 1 (the second ohmic contact metal layer is a bulk metal layer);
  • FIG. 4 is a schematic diagram of a structure of an active area of a reference example
  • FIG. 5 is a schematic cross-sectional view of a reference example
  • FIG. 6 is a schematic diagram comparing I-V characteristic curves of the present invention and a reference example
  • FIG. 7 is a schematic structural diagram of an active region in Embodiment 2.
  • FIG. 8 is a schematic structural diagram of an active region in Embodiment 3.
  • 10 is the SiC substrate
  • 20 is the SiC epitaxial layer
  • 21 is the active region
  • 22 is the first P-type region
  • 23 is the second P-type region
  • 24 is the N-type region
  • 25 is the terminal region
  • 26 is Terminal structure
  • 30 is Schottky metal layer
  • 40 is the first electrode layer
  • 50 is the first ohmic contact metal layer
  • 60 is the second electrode layer
  • 70 is the second ohmic contact metal layer
  • 81 is the first passivation layer
  • 82 is the second passivation layer.
  • the present invention provides a silicon carbide in order to solve the shortcomings of the existing MPS device of the prior art, such as the forward surge capability and the forward conduction characteristic, and the ohmic process window cannot be narrow enough (because the effect of ohmic metal deposition needs to be considered).
  • Power diode devices and their preparation methods, especially MPS devices to improve process compatibility, simplify process complexity, and achieve the characteristics of low forward voltage drop, high reverse voltage, and high surge current.
  • the silicon carbide power diode device of the present invention that is, an MPS device, at least includes:
  • the SiC epitaxial layer 20 is provided on the first surface of the SiC substrate 10 , and the SiC epitaxial layer 20 is provided with an active region 21 ;
  • the Schottky metal layer 30 is provided on the surface of the active region 21 of the SiC epitaxial layer 20 ;
  • the first electrode layer 40 is disposed on the surface of the Schottky metal layer 30 ;
  • the first ohmic contact metal layer 50 is provided on the second surface of the SiC substrate 10 ;
  • the second electrode layer 60 is disposed on the surface of the first ohmic contact metal layer 50 ;
  • the active region 21 includes a plurality of first P-type regions 22 , a plurality of second P-type regions 23 , and an N-type region 24 ; the surface of the first P-type region 22 is provided with a second ohmic contact metal layer 70 , that is, the first P-type region 22
  • the second ohmic contact metal layer 70 is an ohmic contact.
  • the second ohmic contact metal layer 70 is located between the first P-type region 22 and the Schottky metal layer 30 .
  • the second P-type region 23 is not provided with an ohmic contact metal layer. That is, it is directly covered by the Schottky metal layer 30 .
  • the active region of the SiC epitaxial layer 20 is given the size of the first P-type region 22 (including but not limited to the surface area), and then the size of the second P-type region 23 (including but not limited to the surface) is minimized Area, and maximize the size of the N-type region 24 (including but not limited to the surface area).
  • the size (including but not limited to the surface area) of the domain of the first P-type region 22 in a given setting is wider than the size (including but not limited to the surface area) of the domain of the second P-type region 23 (including but not limited to the surface area width).
  • the width of the second P-type region 23 may be implemented as narrow as possible, under the condition that the size of the active region 21 is fixed, the total planar area of the surface of the first P-type region 22 and the second P-type region 23 can be reduced, so that the planar area of the surface of the N-type region 24 increases. And therefore reduce forward voltage drop and improve forward conduction characteristic without increase total device area.
  • the size of the effective range for passing current within the range of the first P-type region 22 is actually determined by the size of the overlapping area between the first P-type region 22 and the second ohmic contact region 70 .
  • the shape of the second ohmic contact metal layer 70 can be diversified and good forward surge capability can be satisfied, while the second P-type region 23 can be as narrow as possible.
  • the size relation between the first P-type region 22 and the second P-type region 23 can be selected according to the following principle, that is, when the surface of any first P-type region 22 completely covers or partially covers the ohmic contact, Assuming that the surface of any one second P-type region 23 completely covers the ohmic contact, the amount of current passing through the first P-type region 22 must be greater than the second P-type region 23 .
  • the second ohmic contact metal layer 70 may be implemented to cover the first P-type region 22 beyond the range, or substantially coincide with the first P-type region 22 , or slightly smaller than the first P-type region 22 , or only cover the first Part of the P-type region 22 .
  • the first P-type region 22 and the second P-type region 23 are both strip-shaped, and the surface area of any first P-type region 22 is larger than the surface area of any second P-type regions 23 .
  • the first P-type region 22 and the second P-type region 23 are both strip-shaped, the length difference between the first P-type region 22 and the second P-type region 23 is small, the first P can be determined by expressing the width value The relationship between the difference in the planar areas of the surfaces of the type region 22 and the second P type region 23 .
  • the first P-type region 22 and the second P-type region 23 are placed alternatively to avoid the mutual influence of the heat generated by the adjacent second ohmic contact metal layer 70 due to operation, thereby affecting the overall heat dissipation of the device, causing instability of the devices.
  • the widths of the first P-type regions 22 are the same and are arranged at equal spacing; or, the widths of the first P-type regions 22 are not all the same, and the distance between opposite sides of the adjacent first P-type regions 22 is the same; furthermore, The heat generated by the second ohmic contact metal layer 70 due to operation is evenly distributed, which can improve heat dissipation, and can effectively controls the overall temperature rise to ensure the stability of the device.
  • the geometric center distance between adjacent first P-type regions 22 is 10 ⁇ m-300 ⁇ m.
  • first P-type region 22 and the second P-type region 23 may be implemented as rectangular strips, trapezoidal strips, regular hexagons, irregular strips (such as wedge-shaped or other irregular strips with long sides) or combination.
  • the second ohmic contact metal layer 70 completely covers the first P-type region 22 , and is implemented as a rectangular strip.
  • the second ohmic contact metal layer 70 is a block shaped metal layer which does not completely cover the first P-type region 22 . Every first p region is at least covered by one second ohmic contact metal layer 70 .
  • the center distance of the adjacent second ohmic contact metal layer 70 is 10 ⁇ m-300 ⁇ m; and the second ohmic contact metal layer 70 is uniformly arranged, which is in favor of uniform heat dissipation and can effectively control the overall temperature rise to ensure the stability of the device.
  • the total planar area of the surface of the N-type region 24 is 1 to 10 times of the total planar area of the first P-type region 22 and the second P-type region 23 .
  • the total planar area of the N-type region 24 is 3 times the total planar area of the first P-type region 22 and the second P-type region 23 .
  • the surface width value of any one first P-type region 22 is 1-10 ⁇ m
  • the number ⁇ 2 and the surface width value of any one second P-type region 23 is ⁇ 0.1 ⁇ m.
  • the SiC epitaxial layer 20 is further provided with a terminal region 25 , which surrounds the active region 21 , and a first passivation layer 81 is provided on the surface of the terminal region 25 , the first passivation The layer 81 covers the surface edge of the first electrode layer 40 . Further, the surface of the first passivation layer 81 covers the second passivation layer 82 .
  • the first passivation layer 81 is a dielectric layer made of silicon oxide or silicon nitride; the second passivation layer 82 is a PI layer made of polyimide.
  • the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 is any one or a combination of Ti, Ni, Al, Au, Ta, or W.
  • the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are Ti/Ni combined multilayers.
  • the Schottky metal layer 30 is any one or a combination of Ti, W, Ta, Ni, Mo or Pt. In this embodiment, the Schottky metal layer 30 is a multilayer metal of Ti/Ni/Ag combination.
  • the present invention has the same area as the active area 21 of the reference example and is provided with the same number of P-type regions.
  • the regions all cover the ohmic contact metal layer.
  • the plane area of the first P-type region 22 and the second P-type region 23 is smaller than the total plane area of the P-type region of the reference example, then the planar area of the N-type region 24 in this invention is larger than the planar area of the N-type region 24 of the reference example, and the present invention has better forward conduction characteristics than the reference example.
  • the P-type region and the N-type region 24 of the reference example can pass a large current.
  • the total planar area of the second ohmic contact metal layer 70 and the N-type region 24 from present invention can passing a large current, the present invention has the same forward surge capability as the reference example.
  • the reference example and the N-type region 24 of the present invention can both pass a small current. Since the plane area of the N-type region 24 of the present invention is larger than that of the reference example, the current density is higher, therefore the present invention has better forward conduction characteristics than the reference Examples.
  • the present invention under the condition of small current, the current passes through the N-type region of the active region; under the condition of large current, the forward voltage of the diode increases, and PiN diode barrier formed by the first P-type region covered with ohmic contacts is opened, and current can pass through this area, thereby improving the surge current capability of the diode.
  • first P-type region 22 and the second P-type region 23 are different.
  • the first P-type region 22 and the second P-type region 23 Area 23 is a block area.
  • the plane area of the surface of any first P-type region 22 is larger than the plane area of the surface of any one of the second P-type regions 23 .
  • the first P-type region 22 and the second P-type region 23 are rectangular regions, regular polygonal regions, circular regions, irregular regions, or a combination thereof, and the second ohmic contact metal layer 70 usually completely covers the first P-type region 22 , and the shape of the second ohmic contact metal layer 70 is in phase with the first P-type region 22 .
  • Embodiment 1 The difference between this embodiment and Embodiment 1 is that the shapes of the surfaces of the first P-type region 22 and the second P-type region 23 are different. As shown in FIG. 8 , in this embodiment, the first P-type region 22 and the second P-type region 23 The area 23 is a combination of stripe and block areas.
  • the surface area of the surface of the first P-type region 22 is larger than that of the second P-type region 23
  • the first P-type region 22 and the second P-type region 23 are rectangular strips, trapezoidal strips, irregular strips, rectangular regions, regular polygonal regions, circular regions, irregular regions, or a combination thereof, in this embodiment
  • the first P-type region 22 is a rectangular region
  • the second P-type region 23 is a rectangular strip
  • the second ohmic contact metal layer 70 usually completely covers the first P-type region 22 , and then the second ohmic contact metal layer 70
  • the shape is the same as the first P-type region 22 .
  • the invention also provides a method for preparing a silicon carbide power diode device, which is used for preparing the silicon carbide power diode device, and the steps are as follows:
  • a SiC epitaxial layer 20 having an N-type active region 21 is grown; specifically, an RCA cleaning process is performed on the SiC substrate 10 , and the SiC substrate 10 has a crystal form of 4 H-SiC and a thickness 350 ⁇ m, doping concentration is 1E19-1E20/cm3; using MOCVD, N-type SiC epitaxial layer 20 is grown on the first surface of N-type SiC substrate 10 , the thickness of SiC epitaxial layer 20 is 5-80 ⁇ m, the doping concentration is 1E14-5E16/cm3.
  • a protective film is deposited on the surface of the SiC epitaxial layer 20 , and the deposition method can be PVD or CVD. Dry etching is used to open a plurality of spaced-apart injection windows in the injection region of the terminal region 25 and the N-type active region 21 , Ion implantation is performed in the implantation regions of the terminal region 25 and the active region 21 ; after activation at high temperature, the terminal region 25 forms a terminal structure 26 , and the N-type active region 21 forms a plurality of spaced first P-type regions 22 and a plurality of second P-type area 23 ;
  • the second surface of the SiC substrate 10 is covered with a metal layer, and the surface of the first P-type region 22 is completely covered or partially covered with a metal layer, and the surface of the second P-type region is not covered with a metal layer;
  • a first ohmic contact metal layer 50 is formed on the second surface of the SiC substrate 10 , and a second ohmic contact metal layer 70 is formed on the surface of the first P-type region 22 ;
  • a metal layer is formed on the second surface of the SiC substrate 10 by deposition or sputtering, and a metal layer is formed on the first P-type region 22 by deposition or sputtering; forming the first ohmic contact metal layer 50 , the first The high-temperature annealing process of the two-ohm contact metal layer 70 , the temperature is 800° C.-1100° C., the time is 60 s-300 s;
  • a metal layer is covered on the surface of the SiC epitaxial layer 20 , and the Schottky metal layer 30 is formed by high-temperature annealing, and the first electrode layer 40 is deposited on the Schottky metal layer 30 ;
  • the first electrode layer 40 of 2-5 ⁇ m on the Schottky metal layer 30 as the anode electrode remove the Schottky metal layer 30 and the first electrode layer 40 covering the terminal structure 26 by the etching method (ie the preparation process In, the Schottky metal layer 30 and the first electrode layer 40 inevitably remain on the surface of the terminal structure 26 metal);
  • the preparation of the first ohmic contact metal layer 50 in step 3) can also be performed in step 5): the second electrode layer 60 in step 5) can be prepared in step 3) After the layer 50 is prepared continuously, it may also be performed at intervals with the preparation of the first ohmic contact metal layer 50 in step 3).
  • the doping concentration of the SiC substrate 10 is preferably 2E19/cm3; the thickness of the SiC epitaxial layer 20 is preferably 10 ⁇ m, and the doping concentration is preferably 1E16/cm3.
  • the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are preferably Ti/Ni combined multilayer metal; the process temperature is preferably 950° C., and the time is preferably 100 s;
  • the Schottky metal layer 30 is preferably Ti; the process temperature is preferably 450° C., and the time is preferably 100 s; the first electrode layer 40 is preferably Al, and the thickness is preferably 4 ⁇ m.
  • the first passivation layer 81 is preferably silicon oxide SiO2, the thickness is preferably 1.2 ⁇ m, the thickness of the second passivation layer 82 is preferably 5 ⁇ m; the second electrode layer 60 is preferably a combination of Ti/Ni/Ag For layer metal, the thickness is preferably 2 ⁇ m.
  • the silicon carbide power diode devices described in Embodiment 1, Embodiment 2, and Embodiment 3 can be prepared according to the structures described in Embodiment 1, Embodiment 2, and Embodiment 3.

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Abstract

A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 16/928,373 filed Jul. 14, 2020 entitled “Silicon Carbide Power Diode Device and Fabrication Method Thereof,” which claims priority to Chinese Invention Patent Application No. 202010626798.6 entitled “SILICON CARBIDE POWER DIODE DEVICE AND PREPARATION METHOD THEREOF” filed before China's National Intellectual Property Administration on Jul. 1, 2020, Chinese Utility Model Application No. 202021269885.2 entitled “SILICON CARBIDE MPS DEVICE” filed before China's National Intellectual Property Administration on Jul. 1, 2020, and Chinese Invention Application No. 202010626793.3 entitled “METHOD FOR PREPARING SILICON CARBIDE POWER DIODE DEVICE” filed before China's National Intellectual Property Administration on Jul. 1, 2020, the entire contents of each of which are incorporated herein by reference.
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
Not Applicable
BACKGROUND 1. Technical Field
The present invention relates to the technical field of semiconductor devices, and more particularly, to a silicon carbide power diode device and a method for manufacturing a silicon carbide power diode device.
2. Technical Background
Compared with traditional Si-based devices, SiC devices have the characteristics of faster operating frequency, less operating loss, and higher operating temperature. As a representative device of SiC power devices, SiC diodes are widely used in power supplies, new energy vehicles and other fields.
The forward voltage of SiC SBD (Schottky Barrier Diode) is low, and the operating frequency is fast. There is no reverse recovery time and loss of PiN diodes. However, due to its poor reverse blocking characteristics, the operating voltage can only be below 200V, which cannot be satisfied. Demand in the 650V/1200V high voltage field.
As an improved structure of SiC SBD, SiC JBS (Junction Barrier Schottky) adds a P-type implant in the active region on the basis of the SBD device structure. By adjusting parameters such as PN ratio, implanted doping concentration and dose, the leakage current can be greatly reduced, the reverse blocking characteristics of the JBS device can be improved, and the reliability of the device can also be improved. However, due to its poor surge capability and poor stability, JBS cannot meet customer needs in some outdoor surge-resistant lightning-resistant test environments.
SiC MPS (Merged PiN Schottky) is a new diode structure that combines the characteristics of JBS and PiN diodes. It forms an ohmic contact on the P-type implanted area of the active area. Under the condition of large current, the potential barrier of the PiN diode is turned on, which can further increase the inrush current of the device and meet the needs of higher-end fields.
In the prior art, SiC MPS usually forms multiple P-type implanted regions in the active region, and ohmic contact metal is grown on each P-type implanted region, but due to the existing equipment (lithography machine) and etching process restrictions, in order to better etch the P-type implanted area and facilitate the growth of ohmic contact metal, it is necessary to appropriately increase the area of the P-type implanted area to achieve a better process window, otherwise an excessively high aspect ratio is difficult to carry out etch and metal growth and other etch related processes; and in order to ensure that the inrush current of the device is large enough and the current is stable enough, it is necessary to set up enough P-type injection regions, which directly leads to the reduction of the N-type conductive region and the forward voltage drop Increased, the device conduction loss increases. Therefore, in the case of ensuring the size of the N-type conductive region, there is a contradiction between the number requirements of the P-type injection region and the design direction of miniaturization.
BRIEF SUMMARY
The purpose of the present invention is to overcome the shortcomings of the current technology, to provide a silicon carbide power diode device and its preparation method, while ensuring that the MPS device has good forward surge capability and forward conduction characteristics, while avoiding the process of ohmic contact Process problems caused by narrow windows.
The technical solution of the present invention is as follows:
A silicon carbide power diode device includes at least:
SiC substrate; SiC epitaxial layer, Disposed on the first surface of the SiC substrate, the SiC epitaxial layer is provided with an active region;
The Schottky metal layer is provided on the surface of the active area of the SiC epitaxial layer;
The first electrode layer is provided on the surface of the Schottky metal layer;
The first ohmic contact metal layer is provided on the second surface of the SiC substrate;
The second electrode layer is provided on the surface of the first ohmic contact metal layer;
The active region includes at least one or a plurality of first P-type regions, a plurality of second P-type regions, and an N-type region. The first P-type region and the second P-type region are spaced apart; the surface of the first P-type region is provided with a A second ohmic contact metal layer, the second ohmic contact metal layer is located between the first P-type region and the Schottky metal layer, and the second P-type region is not provided with an ohmic contact metal layer.
Among them, the active area of the silicon carbide epitaxial layer is given the size of the first P-type region (including but not limited to the surface area) and then the size of the second P-type region (including but not limited to the surface area) is minimized and (Maximum size of N-type area including but not limited to surface area).
Wherein, the size (including but not limited to the surface area) of the first P-type region given is wider than the size (including but not limited to the surface area) of the second P-type region (including but not limited to the width) settings.
Among them, the second ohmic contact metal layer completely covers the first P-type region.
The second ohmic contact metal layer is a bulk metal layer that does not completely cover the first P-type region.
The first P-type region and the second P-type region are both strip-shaped, and the width of the surface of any first P-type region is greater than the width of any second P-type region.
Wherein, each first P-type region has the same width and is arranged at equal intervals.
Among them, the widths of the first P-type regions are not all the same.
Wherein, the distance between the adjacent sides of the adjacent first P-type regions is the same, that is, the distance between the opposite sides of the first P-type region is the same between the adjacent first P-type regions.
Among them, the first P-type region and the second P-type region are block regions.
Wherein, the plane area of the surface of any one first P-type region is larger than the plane area of the surface of any one second P-type region.
The first P-type region and the second P-type region are rectangular regions, trapezoidal regions, regular polygonal regions (such as regular hexagons), circular regions, irregular regions, or a combination thereof.
Wherein, the first P-type region and the second P-type region are a combination of stripe and block regions (for example, square regions).
Wherein, at least one first P-type region is strip-shaped, and at least one second P-type region is a block region, and the plane area of the surface of the first P-type region is larger than the plane area of the surface of the second P-type region.
Wherein, at least one first P-type region is a block region, and at least one second P-type region is a bar shape, and the radial width of the surface of the first P-type region in any direction is greater than the surface width of the second P-type region.
The total planar area of the surface of the N-type region is 1 to 10 times the total planar area of the surface of the first P-type region and the surface of the second P-type region.
Among them, the value of the surface width of any first P-type region is 1-10 μm, and the number is ≥2.
Among them, the surface width of any second P-type region is ≥0.1 μm.
The first ohmic contact metal layer and the second ohmic contact metal layer are any one or a combination of Ti, Ni, Al, Au, Ta, or W.
Wherein, the Schottky metal layer is any one or a combination of Ti, W, Ta, Ni, Mo or Pt.
A method for manufacturing a silicon carbide power diode device includes the following steps:
1) growing an SiC epitaxial layer with an N-type active region on the first surface of the SiC substrate;
2) Deposit a protective film on the surface of the SiC epitaxial layer, open multiple spaced implantation windows in the N-type active area by etching, and perform ion implantation in the implantation window of the N-type active area; activated by high temperature, N-type The active region forms at least one first P-type region and a plurality of second P-type regions arranged at intervals;
3) The surface of the first P-type region is completely covered or partially covered with a metal layer, and the surface of the second P-type region is not covered with a metal layer; through high-temperature annealing, a second ohmic contact metal layer is formed on the surface of the first P-type region
4) The SiC epitaxial surface is covered with a metal layer, which is annealed at high temperature to form a Schottky metal layer, and the first electrode layer is deposited on the Schottky metal layer.
Among them, in step 2), the implantation area in the terminal area is also opened by etching, and ion implantation is performed in the implantation area of the terminal area; by activation (such as high temperature activation), the terminal area forms a terminal structure.
Among them, it also includes step 5) growing a first passivation layer on the surface of the terminal structure, forming a second passivation layer on the surface of the first passivation layer; etching to obtain the contact area of the first electrode layer; on the surface of the first ohmic contact metal layer A second electrode layer is deposited.
Wherein, step 3) or step 5) further includes the steps of: covering a second layer of the SiC substrate with a metal layer, and forming a first ohmic contact metal layer on the second surface of the SiC substrate by high-temperature annealing, A second electrode layer is deposited on the surface of the first ohmic contact metal layer.
Among them, the high-temperature annealing process for forming the first ohmic contact metal layer and the second ohmic contact metal layer is 800° C. 1100° C. 1100° C., the time is 60 s-300 s; the high-temperature annealing process to form the Schottky metal layer, the temperature is 300° C.-500° C. time is 60 s-300 s.
Among them, the thickness of the first electrode layer is 25 μm; the thickness of the first passivation layer is 0.5 3 μm; and the thickness of the second electrode layer is 2-5 μm.
Wherein, the first ohmic contact metal layer and the second ohmic contact metal layer are any one or a combination of Ti, Ni, Al, Au, Ta or W.
Wherein, the Schottky metal layer is any one or a combination of Ti, W Ta, Ni, Mo or Pt.
Among them, the first P-type region and the second P-type region are both strip-shaped, and the surface area of any one first P-type region is larger than the surface area of any one second P-type region.
Among them, the first P-type region and the second P-type region are block regions, and the surface area of any one first P-type region is larger than the surface area of any one second P-type region.
Among them, the first P-type region and the second P-type region are a combination of strip and block regions; when the first P-type region is a strip and the second P-type region is a block region, the surface of the first P-type region The surface area of the first P-type region is larger than the surface area of the second P-type region; when the first P-type region is a block region and the second P-type region is a strip, the radial width of the first P-type region surface in any direction Second P-type surface width.
The beneficial effects of the present invention are as follows:
The silicon carbide power diode device of the present invention is provided with P-type regions of roughly two specifications. The surface of the first P-type region with larger surface area and wider coverage is covered with ohmic contact metal, and the surface area with smaller surface area and narrower There is no ohmic contact metal on the surface of the second P-type region. Under the condition of small current, the current passes through the N-type region of the active region; under the condition of high current, the forward voltage of the diode rises, and the PiN diode barrier formed by the surface of the first P-type region covered by the ohmic contact is turned on. Current can pass through this area, thereby improving the surge current capability of the diode.
The preparation method of the silicon carbide power diode device of the present invention is used to prepare the silicon carbide power diode device of the present invention. Under low current conditions, the N-type region of the diode is the region that conducts current. In theory, under the premise that the surface area of the P-type region is the same, the larger the surface area of the N-type region, the stronger the forward current capability of the diode. Under high current conditions, theoretically, under the premise that the surface area of the N-type region is the same, the larger the area of the surface of the P-type region covered with the ohmic contact metal, the greater the surge capability of the diode. Therefore, how to choose between the forward current capability and the surge capability of the diode is the focus and difficulty of the device structure design. Due to semiconductor device and process capability issues, making ohmic metal contacts on each P-type implanted region requires too much precision in the etching process. In order to be compatible with the stability of the process and the type that can be mass-produced, the width of the surface of the P-type region covered with ohmic metal is greater than 0.3 um, so a part of the surface area of the N-type region is wasted. The silicon carbide power diode device of the present invention uses two different specifications of P-type regions, the surface of the first P-type region with larger surface area and wider coverage is covered with ohmic metal, and the second P-type region with smaller surface area and narrower There is no ohmic contact metal on the surface of the zone. The combination of the two can increase the current density of the diode and reduce the on-voltage drop while maintaining the same surge capacity of the diode.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic structural diagram of an active region in Embodiment 1 (the second ohmic contact metal layer completely covers the first P-type region);
FIG. 2 is a schematic cross-sectional view of Embodiment 1 (the second ohmic contact metal layer completely covers the first P-type region);
FIG. 3 is a schematic structural diagram of an active region according to Embodiment 1 (the second ohmic contact metal layer is a bulk metal layer);
FIG. 4 is a schematic diagram of a structure of an active area of a reference example;
FIG. 5 is a schematic cross-sectional view of a reference example;
FIG. 6 is a schematic diagram comparing I-V characteristic curves of the present invention and a reference example;
FIG. 7 is a schematic structural diagram of an active region in Embodiment 2;
FIG. 8 is a schematic structural diagram of an active region in Embodiment 3;
In the figure: 10 is the SiC substrate, 20 is the SiC epitaxial layer, 21 is the active region, 22 is the first P-type region, 23 is the second P-type region, 24 is the N-type region, 25 is the terminal region, 26 is Terminal structure, 30 is Schottky metal layer, 40 is the first electrode layer, 50 is the first ohmic contact metal layer, 60 is the second electrode layer, 70 is the second ohmic contact metal layer, 81 is the first passivation layer, 82 is the second passivation layer.
DETAILED DESCRIPTION
The present invention will be further described in detail below with reference to the drawings and embodiments.
The present invention provides a silicon carbide in order to solve the shortcomings of the existing MPS device of the prior art, such as the forward surge capability and the forward conduction characteristic, and the ohmic process window cannot be narrow enough (because the effect of ohmic metal deposition needs to be considered). Power diode devices and their preparation methods, especially MPS devices, to improve process compatibility, simplify process complexity, and achieve the characteristics of low forward voltage drop, high reverse voltage, and high surge current.
Example One
As shown in FIGS. 1 and 2 , the silicon carbide power diode device of the present invention, that is, an MPS device, at least includes:
SiC substrate 10;
The SiC epitaxial layer 20 is provided on the first surface of the SiC substrate 10, and the SiC epitaxial layer 20 is provided with an active region 21;
The Schottky metal layer 30 is provided on the surface of the active region 21 of the SiC epitaxial layer 20;
The first electrode layer 40 is disposed on the surface of the Schottky metal layer 30;
The first ohmic contact metal layer 50 is provided on the second surface of the SiC substrate 10;
The second electrode layer 60 is disposed on the surface of the first ohmic contact metal layer 50;
The active region 21 includes a plurality of first P-type regions 22, a plurality of second P-type regions 23, and an N-type region 24; the surface of the first P-type region 22 is provided with a second ohmic contact metal layer 70, that is, the first P-type region 22 The second ohmic contact metal layer 70 is an ohmic contact. The second ohmic contact metal layer 70 is located between the first P-type region 22 and the Schottky metal layer 30. The second P-type region 23 is not provided with an ohmic contact metal layer. That is, it is directly covered by the Schottky metal layer 30. Based on the structure that the second P-type region 22 is provided with the second ohmic contact metal layer 70 and the second P-type region 23 is not provided with the ohmic contact metal layer. Among them, the active region of the SiC epitaxial layer 20 is given the size of the first P-type region 22 (including but not limited to the surface area), and then the size of the second P-type region 23 (including but not limited to the surface) is minimized Area, and maximize the size of the N-type region 24 (including but not limited to the surface area). Moreover, the size (including but not limited to the surface area) of the domain of the first P-type region 22 in a given setting is wider than the size (including but not limited to the surface area) of the domain of the second P-type region 23 (including but not limited to the surface area width).
In the present invention, the width of the second P-type region 23 may be implemented as narrow as possible, under the condition that the size of the active region 21 is fixed, the total planar area of the surface of the first P-type region 22 and the second P-type region 23 can be reduced, so that the planar area of the surface of the N-type region 24 increases. And therefore reduce forward voltage drop and improve forward conduction characteristic without increase total device area. In the present invention, the size of the effective range for passing current within the range of the first P-type region 22 is actually determined by the size of the overlapping area between the first P-type region 22 and the second ohmic contact region 70. Based on the fact that the first P-type region 22 is sufficiently large, the shape of the second ohmic contact metal layer 70 can be diversified and good forward surge capability can be satisfied, while the second P-type region 23 can be as narrow as possible. In the present invention, the size relation between the first P-type region 22 and the second P-type region 23 can be selected according to the following principle, that is, when the surface of any first P-type region 22 completely covers or partially covers the ohmic contact, Assuming that the surface of any one second P-type region 23 completely covers the ohmic contact, the amount of current passing through the first P-type region 22 must be greater than the second P-type region 23.
During specific implementation, the second ohmic contact metal layer 70 may be implemented to cover the first P-type region 22 beyond the range, or substantially coincide with the first P-type region 22, or slightly smaller than the first P-type region 22, or only cover the first Part of the P-type region 22.
In this embodiment, the first P-type region 22 and the second P-type region 23 are both strip-shaped, and the surface area of any first P-type region 22 is larger than the surface area of any second P-type regions 23. When the first P-type region 22 and the second P-type region 23 are both strip-shaped, the length difference between the first P-type region 22 and the second P-type region 23 is small, the first P can be determined by expressing the width value The relationship between the difference in the planar areas of the surfaces of the type region 22 and the second P type region 23. In the present invention, the first P-type region 22 and the second P-type region 23 are placed alternatively to avoid the mutual influence of the heat generated by the adjacent second ohmic contact metal layer 70 due to operation, thereby affecting the overall heat dissipation of the device, causing instability of the devices.
In this embodiment, the widths of the first P-type regions 22 are the same and are arranged at equal spacing; or, the widths of the first P-type regions 22 are not all the same, and the distance between opposite sides of the adjacent first P-type regions 22 is the same; furthermore, The heat generated by the second ohmic contact metal layer 70 due to operation is evenly distributed, which can improve heat dissipation, and can effectively controls the overall temperature rise to ensure the stability of the device. In specific implementation, the geometric center distance between adjacent first P-type regions 22 is 10 μm-300 μm.
In specific implementation, the first P-type region 22 and the second P-type region 23 may be implemented as rectangular strips, trapezoidal strips, regular hexagons, irregular strips (such as wedge-shaped or other irregular strips with long sides) or combination. In this embodiment, the second ohmic contact metal layer 70 completely covers the first P-type region 22, and is implemented as a rectangular strip.
As another embodiment, as shown in FIG. 3 , the second ohmic contact metal layer 70 is a block shaped metal layer which does not completely cover the first P-type region 22. Every first p region is at least covered by one second ohmic contact metal layer 70. When the second ohmic contact metal layer 70 is a block shaped metal layer, the center distance of the adjacent second ohmic contact metal layer 70 is 10 μm-300 μm; and the second ohmic contact metal layer 70 is uniformly arranged, which is in favor of uniform heat dissipation and can effectively control the overall temperature rise to ensure the stability of the device.
In order to balance the good forward surge capability and forward conduction characteristics by the present invention, the total planar area of the surface of the N-type region 24 is 1 to 10 times of the total planar area of the first P-type region 22 and the second P-type region 23. Preferably, the total planar area of the N-type region 24 is 3 times the total planar area of the first P-type region 22 and the second P-type region 23. In addition, the surface width value of any one first P-type region 22 is 1-10 μm, the number≥2, and the surface width value of any one second P-type region 23 is ≥0.1 μm.
As an effective area defining the active region 21, the SiC epitaxial layer 20 is further provided with a terminal region 25, which surrounds the active region 21, and a first passivation layer 81 is provided on the surface of the terminal region 25, the first passivation The layer 81 covers the surface edge of the first electrode layer 40. Further, the surface of the first passivation layer 81 covers the second passivation layer 82. In this embodiment, the first passivation layer 81 is a dielectric layer made of silicon oxide or silicon nitride; the second passivation layer 82 is a PI layer made of polyimide.
In order to ensure good ohmic characteristics between the first ohmic contact metal layer 50 and the SiC substrate 10 and the second ohmic contact metal layer 70 and the first P-type region 22, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 is any one or a combination of Ti, Ni, Al, Au, Ta, or W. In this embodiment, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are Ti/Ni combined multilayers.
In order to ensure good Schottky characteristics between the Schottky metal and the N-type region 24, the Schottky metal layer 30 is any one or a combination of Ti, W, Ta, Ni, Mo or Pt. In this embodiment, the Schottky metal layer 30 is a multilayer metal of Ti/Ni/Ag combination.
Compared with the reference example based on the prior art (as shown in FIGS. 4 and 5 ), it is assumed that the present invention has the same area as the active area 21 of the reference example and is provided with the same number of P-type regions. The regions all cover the ohmic contact metal layer. In the present invention, only the first P-type region 22 covered with the second ohmic contact metal layer 70, and the second P-type region 23 covered with the second ohmic contact metal layer 70.
In the present invention, to guarantee the same forward surge capacity as the reference example, the plane area of the first P-type region 22 and the second P-type region 23 is smaller than the total plane area of the P-type region of the reference example, then the planar area of the N-type region 24 in this invention is larger than the planar area of the N-type region 24 of the reference example, and the present invention has better forward conduction characteristics than the reference example.
Through experiments, in the case of passing a large forward current, the P-type region and the N-type region 24 of the reference example can pass a large current. The total planar area of the second ohmic contact metal layer 70 and the N-type region 24 from present invention can passing a large current, the present invention has the same forward surge capability as the reference example.
In the case of passing a small forward current, the reference example and the N-type region 24 of the present invention can both pass a small current. Since the plane area of the N-type region 24 of the present invention is larger than that of the reference example, the current density is higher, therefore the present invention has better forward conduction characteristics than the reference Examples.
As shown in FIG. 6 , the present invention under the condition of small current, the current passes through the N-type region of the active region; under the condition of large current, the forward voltage of the diode increases, and PiN diode barrier formed by the first P-type region covered with ohmic contacts is opened, and current can pass through this area, thereby improving the surge current capability of the diode.
Example 2
The difference between this embodiment and the first embodiment is that the shapes of the surfaces of the first P-type region 22 and the second P-type region 23 are different. As shown in FIG. 7 , in this embodiment, the first P-type region 22 and the second P-type region 23 Area 23 is a block area. In the same way as the embodiment, in this embodiment, the plane area of the surface of any first P-type region 22 is larger than the plane area of the surface of any one of the second P-type regions 23.
During specific implementation, the first P-type region 22 and the second P-type region 23 are rectangular regions, regular polygonal regions, circular regions, irregular regions, or a combination thereof, and the second ohmic contact metal layer 70 usually completely covers the first P-type region 22, and the shape of the second ohmic contact metal layer 70 is in phase with the first P-type region 22.
The other parts are the same as the first embodiment.
Example 3
The difference between this embodiment and Embodiment 1 is that the shapes of the surfaces of the first P-type region 22 and the second P-type region 23 are different. As shown in FIG. 8 , in this embodiment, the first P-type region 22 and the second P-type region 23 The area 23 is a combination of stripe and block areas. The same as the embodiment, in this embodiment, when the first P-type region 22 is strip-shaped and the second P-type region 23 is a bulk region, the surface area of the surface of the first P-type region 22 is larger than that of the second P-type region 23 The planar area of the surface; when the first P-type region 22 is a block region and the second P-type region 23 is a strip, the radial width of the surface of the first P-type region 22 in any direction is larger than that of the second P-type region 23 Surface width.
During specific implementation, the first P-type region 22 and the second P-type region 23 are rectangular strips, trapezoidal strips, irregular strips, rectangular regions, regular polygonal regions, circular regions, irregular regions, or a combination thereof, in this embodiment In which, the first P-type region 22 is a rectangular region, and the second P-type region 23 is a rectangular strip; and the second ohmic contact metal layer 70 usually completely covers the first P-type region 22, and then the second ohmic contact metal layer 70 The shape is the same as the first P-type region 22.
The other parts are the same as the first embodiment.
Example 4
The invention also provides a method for preparing a silicon carbide power diode device, which is used for preparing the silicon carbide power diode device, and the steps are as follows:
1) On the first surface of the SiC substrate 10, a SiC epitaxial layer 20 having an N-type active region 21 is grown; specifically, an RCA cleaning process is performed on the SiC substrate 10, and the SiC substrate 10 has a crystal form of 4H-SiC and a thickness 350 μm, doping concentration is 1E19-1E20/cm3; using MOCVD, N-type SiC epitaxial layer 20 is grown on the first surface of N-type SiC substrate 10, the thickness of SiC epitaxial layer 20 is 5-80 μm, the doping concentration is 1E14-5E16/cm3.
2) A protective film is deposited on the surface of the SiC epitaxial layer 20, and the deposition method can be PVD or CVD. Dry etching is used to open a plurality of spaced-apart injection windows in the injection region of the terminal region 25 and the N-type active region 21, Ion implantation is performed in the implantation regions of the terminal region 25 and the active region 21; after activation at high temperature, the terminal region 25 forms a terminal structure 26, and the N-type active region 21 forms a plurality of spaced first P-type regions 22 and a plurality of second P-type area 23;
3) The second surface of the SiC substrate 10 is covered with a metal layer, and the surface of the first P-type region 22 is completely covered or partially covered with a metal layer, and the surface of the second P-type region is not covered with a metal layer; A first ohmic contact metal layer 50 is formed on the second surface of the SiC substrate 10, and a second ohmic contact metal layer 70 is formed on the surface of the first P-type region 22;
Wherein, a metal layer is formed on the second surface of the SiC substrate 10 by deposition or sputtering, and a metal layer is formed on the first P-type region 22 by deposition or sputtering; forming the first ohmic contact metal layer 50, the first The high-temperature annealing process of the two-ohm contact metal layer 70, the temperature is 800° C.-1100° C., the time is 60 s-300 s;
4) A metal layer is covered on the surface of the SiC epitaxial layer 20, and the Schottky metal layer 30 is formed by high-temperature annealing, and the first electrode layer 40 is deposited on the Schottky metal layer 30;
A high-temperature annealing process for forming a metal layer on the surface of the SiC epitaxial layer 20 by deposition or sputtering to form the Schottky metal layer 30 at a temperature of 300° C.-500° C. and a time of 60 s-300 s. Continue to deposit the first electrode layer 40 of 2-5 μm on the Schottky metal layer 30 as the anode electrode; remove the Schottky metal layer 30 and the first electrode layer 40 covering the terminal structure 26 by the etching method (ie the preparation process In, the Schottky metal layer 30 and the first electrode layer 40 inevitably remain on the surface of the terminal structure 26 metal);
5) Growth of 0.5-3 μm dielectric layer on the surface of the terminal structure 26 by CVD or PVD, as the first passivation layer 81, coating 2-5 μm Polyimide on the surface of the first passivation layer 81, as the second purification layer; by wet method or A dry etching method is used to etch the contact area of the first electrode layer 40; a 2-5 μm second electrode layer 60 is deposited on the surface of the first ohmic contact metal layer 50 as a cathode electrode.
In this embodiment, the preparation of the first ohmic contact metal layer 50 in step 3) can also be performed in step 5): the second electrode layer 60 in step 5) can be prepared in step 3) After the layer 50 is prepared continuously, it may also be performed at intervals with the preparation of the first ohmic contact metal layer 50 in step 3).
In step 1), the doping concentration of the SiC substrate 10 is preferably 2E19/cm3; the thickness of the SiC epitaxial layer 20 is preferably 10 μm, and the doping concentration is preferably 1E16/cm3.
In step 3), the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are preferably Ti/Ni combined multilayer metal; the process temperature is preferably 950° C., and the time is preferably 100 s;
In step 4), the Schottky metal layer 30 is preferably Ti; the process temperature is preferably 450° C., and the time is preferably 100 s; the first electrode layer 40 is preferably Al, and the thickness is preferably 4 μm.
In step 5), the first passivation layer 81 is preferably silicon oxide SiO2, the thickness is preferably 1.2 μm, the thickness of the second passivation layer 82 is preferably 5 μm; the second electrode layer 60 is preferably a combination of Ti/Ni/Ag For layer metal, the thickness is preferably 2 μm.
Based on the manufacturing method described in this embodiment, the silicon carbide power diode devices described in Embodiment 1, Embodiment 2, and Embodiment 3 can be prepared according to the structures described in Embodiment 1, Embodiment 2, and Embodiment 3.
The above embodiments are only used to illustrate the present invention, and are not intended to limit the present invention. As long as it is based on the technical essence of the present invention, changes, modifications, etc. to the above embodiments will fall within the scope of the claims of the present invention.

Claims (19)

What is claimed is:
1. A silicon carbide power diode device, comprising:
a silicon carbide substrate;
a silicon carbide epitaxial layer on a first surface of the silicon carbide substrate, the carbide epitaxial layer having an active region, and the active region having a surface away from the silicon carbide substrate;
a Schottky metal layer on the surface of the active region, the active region having an N-type region and a plurality of P-type regions, the N-type region extending from the surface of the active region toward the silicon carbide substrate, the P-type regions are spaced apart from each other in the N-type region, and extend to the surface of the active region; and
a plurality of ohmic contact layers on a surface of some of the P-type regions and set between the P-type regions and the Schottky metal layer;
wherein the plurality of P-type regions include a plurality of first P-type regions and a plurality of second P-type regions, wherein between neighboring ones of the first P-type regions there is at least one of the second P-type region, the ohmic contact layers being on the surface of the first P-type regions.
2. The silicon carbide power diode device of claim 1, wherein:
the first P-type regions are strip-shaped regions, block-shape regions, or a combination thereof;
the second P-type regions are strip-shaped regions and block-shape regions, or a combination thereof; and
the shape of the block-shape regions on the surface of the epitaxial layer are rectangular, trapezoidal, regular polygonal, circular, or a combination thereof.
3. The silicon carbide power diode device of claim 1, wherein on the surface of the epitaxial layer, a total surface area of the plurality of first P-type regions is larger than a total surface area of the plurality of second P-type regions.
4. The silicon carbide power diode device of claim 3, wherein on the surface of the epitaxial layer, a surface area of any one of the first P-type regions is larger than a surface area of any one of the second P-type regions.
5. The silicon carbide power diode device of claim 1, wherein on the surface of the epitaxial layer, a surface area of the N-type region is larger than a total surface area of the plurality of the P-type regions.
6. The silicon carbide power diode device of claim 1, wherein in the active region of the silicon carbide epitaxial layer, a total size of the plurality of first P-type regions is wider than a total size of the plurality of second P-type regions.
7. The silicon carbide power diode device of claim 1, wherein distances between neighboring first P-type regions are the same.
8. The silicon carbide power diode device of claim 7, wherein distances between facing sides of neighboring first P-type regions are the same.
9. The silicon carbide power diode device of claim 7, wherein shapes of the P-type regions on the surface of the epitaxial layer are the same.
10. The silicon carbide power diode device of claim 7, wherein shapes of the P-type regions on the surface of the epitaxial layer are a strip, trapezoidal or regular polygonal.
11. A silicon carbide power diode device, comprising:
a silicon carbide substrate;
a silicon carbide epitaxial layer on a first surface of the silicon carbide substrate, the carbide epitaxial layer having an active region and the active region having a surface away from the silicon carbide substrate, a N-type region and a plurality of P-type regions, the N-type region extending from a surface of the active region toward the SiC substrate, the P-type regions are spaced apart from each other in the N-type region and extend to the surface of the active region, and the plurality of P-type regions include a plurality of first P-type regions and a plurality of second P-type regions;
a plurality of ohmic contact metal layers on a surface of the first P-type regions; and
a Schottky metal layer, the Schottky metal layer covering a surface of the ohmic contact layers and a surface of the active region that without covering the ohmic metal layer.
12. The silicon carbide power diode device of claim 11, wherein each of the ohmic contact metal layers completely covers a surface of the corresponding first P-type region, the surface of the active region that without covering the ohmic metal layer includes a surface of the N-type region and a surface of the second P-type regions.
13. The silicon carbide power diode device of claim 11, wherein each of the ohmic contact metal layers partially covers a surface of the corresponding first P-type region, the surface the active region that without covering the ohmic metal layer includes a surface of the N-type region, a surface of the second P-type regions and a surface of each first p-type region without covering the ohmic metal layer.
14. The silicon carbide power diode device of claim 11 wherein at least some of the ohmic contact metal layers include a first portion completely covering a surface of the corresponding first P-type region and a second portion extending from the first portion and covering the N-type region neighboring the corresponding first P-type region, the surface of the active region that without covering the ohmic metal layer includes a surface of the second P-type regions, a surface of N-type region without covering the ohmic metal layer.
15. The silicon carbide power diode device of claim 11, wherein on a surface of the epitaxial layer, a surface area of the N-type region is larger than a total surface area of the plurality of the first P-type regions and the second P-type regions.
16. The silicon carbide power diode device of claim 11 wherein the ohmic contact metal layer is a block shaped metal layer.
17. The silicon carbide power diode device of claim 16, wherein distances between facing sides of neighboring first P-type regions are the same.
18. The silicon carbide power diode device of claim 16, wherein a center distance of neighboring ohmic contact metal layers is 10 μm-300 μm.
19. The silicon carbide power diode device of claim 15, wherein the ohmic contact metal layers are configured to be uniformly arranged on surfaces of the first P-type regions.
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Publication number Priority date Publication date Assignee Title
CN113257888A (en) * 2021-03-31 2021-08-13 华为技术有限公司 Power semiconductor device, packaging structure and electronic equipment
US11990553B2 (en) * 2022-03-31 2024-05-21 Leap Semiconductor Corp. Merged PiN Schottky (MPS) diode and method of manufacturing the same
CN115985934B (en) * 2022-10-27 2026-01-23 中国振华集团永光电子有限公司（国营第八七三厂） Schottky junction barrier diode with silicon carbide non-uniform mixed P+ structure and manufacturing method thereof

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10259373A1 (en) 2002-12-18 2004-07-15 Infineon Technologies Ag Schottky diode resisting overcurrent, with low blocking current, is formed with defined, differing spacings between regions of differing conduction type
US20080029838A1 (en) 2006-08-01 2008-02-07 Cree, Inc. Semiconductor devices including Schottky diodes with controlled breakdown and methods of fabricating same
CN101540283A (en) 2009-04-14 2009-09-23 西安电子科技大学 Method for manufacturing 4H-SiC PiN/schottky diode of field limiting ring structure
US20090289262A1 (en) 2008-05-21 2009-11-26 Cree, Inc. Junction barrier schottky diodes with current surge capability
US7851881B1 (en) 2008-03-21 2010-12-14 Microsemi Corporation Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode
US20120241762A1 (en) 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor device
JP2013084844A (en) 2011-10-12 2013-05-09 Showa Denko Kk Silicon carbide semiconductor device and manufacturing method thereof
JP2013120776A (en) 2011-12-06 2013-06-17 Showa Denko Kk Manufacturing method for silicon carbide semiconductor device
CN103534810A (en) 2011-05-18 2014-01-22 罗姆股份有限公司 Semiconductor device and method for producing same
US20140145289A1 (en) 2012-11-27 2014-05-29 Cree, Inc. Schottky structure employing central implants between junction barrier elements
US20140266403A1 (en) 2013-03-15 2014-09-18 Cree, Inc. Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same
US20150115285A1 (en) * 2012-04-27 2015-04-30 Fuji Electric Co., Ltd. Semiconductor device and fabrication method of semiconductor device
DE102013019851A1 (en) 2013-11-26 2015-05-28 Infineon Technologies Ag Schottky diode with reduced forward voltage
US9368650B1 (en) * 2015-07-16 2016-06-14 Hestia Power Inc. SiC junction barrier controlled schottky rectifier
US20160276442A1 (en) 2015-03-16 2016-09-22 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20180061951A1 (en) 2016-08-25 2018-03-01 Fuji Electric Co., Ltd. Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US20180190651A1 (en) 2017-01-04 2018-07-05 Infineon Technologies Ag Semiconductor Device and Corresponding Manufacturing Method
CN110571282A (en) 2019-08-01 2019-12-13 山东天岳电子科技有限公司 A kind of schottky diode and its manufacturing method
US20200091298A1 (en) 2018-09-19 2020-03-19 Kabushiki Kaisha Toshiba Semiconductor device
CN112038393A (en) 2020-07-01 2020-12-04 厦门市三安集成电路有限公司 Silicon carbide power diode device and preparation method thereof
CN112038398A (en) 2020-07-01 2020-12-04 厦门市三安集成电路有限公司 Preparation method of silicon carbide power diode device
CN212725323U (en) 2020-07-01 2021-03-16 厦门市三安集成电路有限公司 Silicon carbide MPS device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5408929B2 (en) * 2008-08-21 2014-02-05 昭和電工株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5542325B2 (en) * 2008-12-02 2014-07-09 昭和電工株式会社 Manufacturing method of semiconductor device
JP6287377B2 (en) * 2014-03-11 2018-03-07 住友電気工業株式会社 Wide band gap semiconductor device
JP6926869B2 (en) * 2017-09-13 2021-08-25 富士電機株式会社 Semiconductor device
JP6730237B2 (en) * 2017-09-19 2020-07-29 株式会社東芝 Semiconductor device

Patent Citations (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173801A1 (en) 2002-12-18 2004-09-09 Infineon Technologies Ag Schottky diode having overcurrent protection and low reverse current
US6861723B2 (en) 2002-12-18 2005-03-01 Infineon Technologies Ag Schottky diode having overcurrent protection and low reverse current
DE10259373A1 (en) 2002-12-18 2004-07-15 Infineon Technologies Ag Schottky diode resisting overcurrent, with low blocking current, is formed with defined, differing spacings between regions of differing conduction type
US20080029838A1 (en) 2006-08-01 2008-02-07 Cree, Inc. Semiconductor devices including Schottky diodes with controlled breakdown and methods of fabricating same
US7851881B1 (en) 2008-03-21 2010-12-14 Microsemi Corporation Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode
CN103633150A (en) 2008-05-21 2014-03-12 克里公司 Junction barrier schottky diodes with current surge capability
JP5537545B2 (en) 2008-05-21 2014-07-02 クリー インコーポレイテッド Junction-type barrier Schottky diode with current surge capability
US20090289262A1 (en) 2008-05-21 2009-11-26 Cree, Inc. Junction barrier schottky diodes with current surge capability
EP2289105A1 (en) 2008-05-21 2011-03-02 Cree, Inc. Junction barrier schottky diodes with current surge capability
CN102084487A (en) 2008-05-21 2011-06-01 克里公司 Junction Barrier Schottky Diode with Current Surge Capability
JP2011521471A (en) 2008-05-21 2011-07-21 クリー インコーポレイテッド Junction-type barrier Schottky diode with current surge capability
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
EP2816608A2 (en) 2008-05-21 2014-12-24 Cree, Inc. Junction barrier schottky diodes with current surge capability
US20120273802A1 (en) 2008-05-21 2012-11-01 Qingchun Zhang Junction barrier schottky diodes with current surge capability
JP2014150286A (en) 2008-05-21 2014-08-21 Cree Inc Junction type barrier schottky diode with current surge capability
WO2009142721A1 (en) 2008-05-21 2009-11-26 Cree, Inc. Junction barrier schottky diodes with current surge capability
US20140077228A1 (en) 2008-05-21 2014-03-20 Cree, Inc. Junction barrier schottky diodes with current surge capability
US8653534B2 (en) 2008-05-21 2014-02-18 Cree, Inc. Junction Barrier Schottky diodes with current surge capability
JP5926316B2 (en) 2008-05-21 2016-05-25 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． Junction-type barrier Schottky diode with current surge capability
CN101540283A (en) 2009-04-14 2009-09-23 西安电子科技大学 Method for manufacturing 4H-SiC PiN/schottky diode of field limiting ring structure
US20120241762A1 (en) 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor device
CN103534810A (en) 2011-05-18 2014-01-22 罗姆股份有限公司 Semiconductor device and method for producing same
US9548353B2 (en) 2011-05-18 2017-01-17 Rohm Co., Ltd. Wide band-gap semiconductor device including schotky electrode and method for producing same
JP2013084844A (en) 2011-10-12 2013-05-09 Showa Denko Kk Silicon carbide semiconductor device and manufacturing method thereof
JP2013120776A (en) 2011-12-06 2013-06-17 Showa Denko Kk Manufacturing method for silicon carbide semiconductor device
US20150115285A1 (en) * 2012-04-27 2015-04-30 Fuji Electric Co., Ltd. Semiconductor device and fabrication method of semiconductor device
US9831355B2 (en) 2012-11-27 2017-11-28 Cree, Inc. Schottky structure employing central implants between junction barrier elements
KR101764038B1 (en) 2012-11-27 2017-08-01 크리, 인코포레이티드 Schottky diodes and method of manufacturing the same
KR20150089054A (en) 2012-11-27 2015-08-04 크리, 인코포레이티드 Schottky diodes and method of manufacturing the same
EP2926377A1 (en) 2012-11-27 2015-10-07 Cree, Inc. Schottky diodes and method of manufacturing the same
JP2016502763A (en) 2012-11-27 2016-01-28 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． Schottky diode and method of manufacturing Schottky diode
US9318624B2 (en) 2012-11-27 2016-04-19 Cree, Inc. Schottky structure employing central implants between junction barrier elements
US20140145289A1 (en) 2012-11-27 2014-05-29 Cree, Inc. Schottky structure employing central implants between junction barrier elements
JP6425659B2 (en) 2012-11-27 2018-11-21 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． Schottky diode and method of manufacturing Schottky diode
US20160211387A1 (en) 2012-11-27 2016-07-21 Cree, Inc. Schottky structure employing central implants between junction barrier elements
US20140266403A1 (en) 2013-03-15 2014-09-18 Cree, Inc. Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same
DE102013019851A1 (en) 2013-11-26 2015-05-28 Infineon Technologies Ag Schottky diode with reduced forward voltage
US9859383B2 (en) 2013-11-26 2018-01-02 Infineon Technologies Ag Schottky diode with reduced forward voltage
CN104681637A (en) 2013-11-26 2015-06-03 英飞凌科技股份有限公司 Schottky Diode With Reduced Forward Voltage
US20150144966A1 (en) 2013-11-26 2015-05-28 Infineon Technologies Ag Schottky diode with reduced forward voltage
US9748342B2 (en) 2015-03-16 2017-08-29 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20160276442A1 (en) 2015-03-16 2016-09-22 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US9368650B1 (en) * 2015-07-16 2016-06-14 Hestia Power Inc. SiC junction barrier controlled schottky rectifier
US20180061951A1 (en) 2016-08-25 2018-03-01 Fuji Electric Co., Ltd. Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US20180190651A1 (en) 2017-01-04 2018-07-05 Infineon Technologies Ag Semiconductor Device and Corresponding Manufacturing Method
DE102017100109A1 (en) 2017-01-04 2018-07-05 Infineon Technologies Ag SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
JP2018110234A (en) 2017-01-04 2018-07-12 インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ Semiconductor device and manufacturing method thereof
US20200091298A1 (en) 2018-09-19 2020-03-19 Kabushiki Kaisha Toshiba Semiconductor device
CN110571282A (en) 2019-08-01 2019-12-13 山东天岳电子科技有限公司 A kind of schottky diode and its manufacturing method
CN112038393A (en) 2020-07-01 2020-12-04 厦门市三安集成电路有限公司 Silicon carbide power diode device and preparation method thereof
CN112038398A (en) 2020-07-01 2020-12-04 厦门市三安集成电路有限公司 Preparation method of silicon carbide power diode device
CN212725323U (en) 2020-07-01 2021-03-16 厦门市三安集成电路有限公司 Silicon carbide MPS device

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
1st Office Action for CN202010626793; Jun. 15, 2022.
1st Office Action for CN2020106267986; Jun. 15, 2022.
2nd Office Action for CN202010626793; Jul. 25, 2022.
2nd Office Action for CN2020106267986; Oct. 12, 2022.
European Search Report and Written Opinion for Application Serial No. EP21182970; dated Nov. 11, 2021.
Losee, P. A.; Zhu, L.; Chow, T. P.; Bhat, I. B.; Gutmann, R. J.; "Degraded Blocking Performance of 4H-SiC Rectifiers under High dV/dt Conditions"; Proceedings of the 17th International Symposium on Power Semiconductor Devices & IC's in Santa Barbara, CA, USA; May 23-26, 2005.
PCT International Search Report & Written Opinion for PCT/CN2021/103440; dated Sep. 21, 2021.
Search Report for CN202010626793; Jun. 8, 2022.
Search Report for CN2020106267986; Jun. 10, 2022.

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