US11923849B1 - Frequency divider for non-overlapping clock signals - Google Patents

Frequency divider for non-overlapping clock signals Download PDF

Info

Publication number
US11923849B1
US11923849B1 US17/899,564 US202217899564A US11923849B1 US 11923849 B1 US11923849 B1 US 11923849B1 US 202217899564 A US202217899564 A US 202217899564A US 11923849 B1 US11923849 B1 US 11923849B1
Authority
US
United States
Prior art keywords
clock signal
input
latch
gate
overlapping clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/899,564
Other versions
US20240072807A1 (en
Inventor
Nagarjuna NALLAM
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to US17/899,564 priority Critical patent/US11923849B1/en
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NALLAM, Nagarjuna
Priority to PCT/US2023/030977 priority patent/WO2024049691A2/en
Publication of US20240072807A1 publication Critical patent/US20240072807A1/en
Application granted granted Critical
Publication of US11923849B1 publication Critical patent/US11923849B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H03K21/026—Input circuits comprising logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H03K21/023—Input circuits comprising pulse shaping or differentiating circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H03K21/10—Output circuits comprising logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/425—Out-of-phase gating or clocking signals applied to counter stages using bistables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • This application relates to frequency dividers, and more particularly, to a frequency divider that generates non-overlapping clock signals.
  • non-overlapping clock signals In a plurality of non-overlapping clock signals, only one of the clock signals will be in a binary true state at any given time. This binary true state may be a power supply voltage in a binary-high convention or ground in a binary-low convention. Regardless of the binary-high (or low) convention, non-overlapping clock signals have many uses in electronic systems. For example, modern receivers may use passive mixers that are driven by a plurality N of non-overlapping clock signals, N being a plural positive integer. However, the generation of non-overlapping clock signals typically consumes substantial power and may suffer from excessive phase noise.
  • a frequency divider for the generation of non-overlapping clock signals that includes: a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises: a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and wherein an output terminal of the 2-input logic gate in each preceding stage in the series is coupled to a first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein an output terminal of the 2-input logic gate in the Nth stage is coupled to a first input terminal of the 3-input logic gate in the first stage.
  • a frequency divider includes: a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal; a plurality of N latches, wherein N is a plural positive integer greater than two; a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals; and a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the
  • a frequency divider includes: a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal; a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth of the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater; and a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.
  • a method of frequency division includes: dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%; and processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
  • FIG. 1 A is a circuit diagram of a divide-by-3 frequency divider in accordance with an aspect of the disclosure.
  • FIG. 1 B is a timing diagram for the clock signals of FIG. 1 A .
  • FIG. 1 C is an alternative circuit diagram of the divide-by-3 frequency divider of FIG. 1 A .
  • FIG. 2 A is a circuit diagram of a divide-by-4 frequency divider in accordance with an aspect of the disclosure.
  • FIG. 2 B is a timing diagram for the clock signals of FIG. 2 A .
  • FIG. 3 is a timing diagram illustrating a time difference between three example overlapping clock signals in accordance with an aspect of the disclosure.
  • FIG. 4 is a circuit diagram for a divide-by-N frequency divider in which N is odd in accordance with an aspect of the disclosure.
  • FIG. 5 is a circuit diagram for a divide-by-N frequency divider in which N is even in accordance with an aspect of the disclosure.
  • FIG. 6 is a flowchart for an example method of operation for a divide-by-N frequency divider in accordance with an aspect of the disclosure.
  • FIG. 7 illustrates some example electronic devices including a frequency divider in accordance with an aspect of the disclosure.
  • a frequency divider is provided that divides an input clock signal according to a positive integer N into a plurality of 2N non-overlapping clock signals, where N is three or greater.
  • the input clock signal cycles at a frequency f with a period T.
  • Each non-overlapping clock signal thus has a frequency of f/N and a period of N*T.
  • each non-overlapping clock signal is deemed to be “asserted” when the non-overlapping clock signal is in a binary true state, regardless of whether the binary true state is represented using a binary-high or a binary-low convention. In implementations in which a binary-high convention is used, each non-overlapping clock signal is thus asserted by being charged to a power supply voltage.
  • each non-overlapping clock signal is asserted by being discharged to ground. Regardless of which convention is used, each non-overlapping clock signal is asserted for just T/2 in each period of N*T.
  • the input clock signal has a 50% duty cycle so that it is also asserted to T/2 in in each period of T.
  • the frequency divider also divides the input clock signal into a plurality of 2N overlapping clock signals, each having a duty cycle of 50%.
  • each overlapping clock signal has a frequency of f/N and a period of N*T.
  • each overlapping clock signal is asserted in one-half of its period, which equals NT/2. Since the assertion time for each non-overlapping clock signal is T/2, this non-overlapping assertion time is 1/Nth the assertion time for each overlapping clock signal.
  • the duty cycle of each non-overlapping clock signal is thus 50%/N.
  • the 2N overlapping clock signals may be deemed to be arranged from a first overlapping clock signal to a 2Nth overlapping clock signals.
  • an ith overlapping clock signal is timed so as to be delayed by T/2 with respect to an (i ⁇ 1)th overlapping clock signal, where i is an integer ranging from 2 to 2N.
  • the first overlapping clock signal is delayed by T/2 with respect to the 2Nth overlapping clock signal.
  • the frequency divider includes a plurality of N set-reset latches. Each latch produces a corresponding pair of the overlapping clock signals.
  • the latches may be deemed to be arranged serially, from a first latch to an Nth latch. With respect to this order, an ith latch produces an (i+1)th overlapping clock signal and an ((i+1)+N)th overlapping clock signal, where i is an integer ranging from 1 to (N ⁇ 1).
  • the Nth latch produces the first overlapping clock signal and an (N+1)th overlapping clock signal.
  • each latch Since each latch is a set-reset latch, each latch has a reset input terminal and a set input terminal. When an ith latch is set by an assertion of a voltage of its set input terminal, it asserts the (i+1)th overlapping clock signal. Similarly, when an ith latch is reset by an assertion of a voltage of its reset input terminal, it asserts the (i+(N+1))th overlapping clock signal. Given the time delay of T/2 from one overlapping clock signal to the next, the pair of overlapping clock signals produced by each latch will have a time difference of NT/2. When set, the Nth latch asserts the (N+1)th overlapping clock signal. Similarly, the Nth latch asserts the first overlapping clock signal when reset.
  • each latch is controlled by a corresponding three-input logic gate. Since there are N latches, there are N corresponding three-input logic gates to control the setting of the N latches. Similarly, there are N corresponding three-input logic gates to the control the resetting of the N latches. Each latch thus couples to a first three-input logic gate that drives the latch's set terminal and couples to a second three-input logic gate that drives the latch's reset terminal. There is thus a plurality of N three-input first logic gates and a plurality of N three-input second logic gates.
  • each three-input first and second logic gate is a 3-input NOR gate, but it will be appreciated that a 3-input NAND gate may also be used in alternative implementations.
  • Each 3-input logic gate produces a corresponding one of the 2N non-overlapping clock signals.
  • first latch 125 When set by an assertion of a set (S) terminal, first latch 125 asserts the E 2 clock signal and resets (de-asserts) an E 5 clock signal. Conversely when reset by an assertion of a reset (R) terminal, first latch 125 asserts the E 5 clock signal and resets the E 2 clock signal.
  • the E 2 and E 5 clock signal are thus complements of each other. Since each successive E clock signal is delayed by T/2, the E 5 clock signal is delayed by 3T/2 with respect to the E 2 clock signal.
  • second latch 130 asserts the E 3 clock signal and resets the E 6 clock signal when set. Second latch 130 also resets the E 3 clock signal and asserts the E 6 clock signal when reset.
  • the E 3 and E 6 clock signals are thus complements of each other.
  • third latch 135 asserts an E 4 clock signal and resets the E 1 clock signal when set. Finally, third latch 135 asserts the E 1 clock signal and resets the E 4 clock signal when reset.
  • the E 1 and E 4 clock signal are thus complements of each other. More generally, each latch produces a complementary pair of overlapping clock signals.
  • Each 3-input NOR gate produces or outputs a corresponding non-overlapping clock signal. There are thus 6 non-overlapping clock signals produced by frequency divider 100 .
  • the non-overlapping clock signals are designated by a letter P and a corresponding index.
  • frequency divider 100 produces six P clock signals ranging from a P 1 clock signal to a P 6 clock signal.
  • each successive non-overlapping clock signal is delayed by T/2 with respect to a preceding non-overlapping clock signal.
  • a P 2 clock signal is thus delayed by T/2 with respect to the P 1 clock signal.
  • a P 3 clock signal is delayed by T/2 with respect to the P 2 clock signal
  • a P 4 clock signal is delayed by T/2 with respect to the P 3 clock signal
  • the P 6 clock signal is delayed by T/2 with respect to a P 5 clock signal.
  • each latch Since the setting and resetting of each latch controls the production of each latch's pair of overlapping clock signals, the overlapping clock signals from any given latch are complementary.
  • the E 2 and E 5 clock signal produced by first latch 125 are complements of each other.
  • the E 2 and E 5 clock signals are still accurate to refer to the E 2 and E 5 clock signals as overlapping clock signals.
  • the E 2 clock signal overlaps with every other E clock signal except the E 5 clock signal.
  • the E 5 clock signal overlaps with every other E clock signal except the E 2 clock signal.
  • each latch produces a complementary pair of E signals that overlap with all the remaining E clock signals.
  • Frequency divider 100 thus functions to divide the clkn and clkp input clock signals in frequency by a divisor N using a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals, where N equals 3.
  • each successive E clock signal Given the T/2 delay of each successive E clock signal with respect to its preceding E clock signal, each successive E clock signal will have an overlap of T with the preceding clock signal in which both E clock signals are in a binary false state (which is ground in a binary-high convention) in this divide-by-3 implementation.
  • the E 2 clock signal has such an overlap of T with the E 1 clock signal.
  • the NOR gates exploit this T overlap by gating each successive E clock signal with the preceding E clock signal with a gating clock signal selected from a positive input clock signal (clkp) and a negative input clock signal (clkn) as produced by a differential clock source 120 .
  • NOR gate 155 NORs the E 1 clock signal with the E 2 clock signal and with the clkp input clock signal to produce the P 2 clock signal to drive the reset input terminal of the second latch 130 .
  • this gating is: without the gating by the selected input clock signal, the E 1 and E 2 clock signals will both be in a binary zero state for T in each of their periods since the E 2 clock signal is delayed by T/2 with respect to the E 1 clock signal. An output signal from NOR gate 155 would then pulse high during this T-long stretch of time in which both the E 1 and the E 2 clock signals are in the binary zero state.
  • frequency divider 100 could not produce non-overlapping clock signals if each non-overlapping clock signal had an assertion time of T. But when gated by one of the input clock signals, the output signal from NOR gate 155 can form the desired non-overlapping P 2 clock signal.
  • frequency divider 100 itself not only produces the E clock signals (the overlapping clock signals) but also the P clock signals (the non-overlapping clock signals). The result is a significant reduction in semiconductor die space to implement frequency divider 100 .
  • frequency divider 100 may be readily modified as explained herein to accommodate any desired even or odd value of N.
  • frequency divider 100 reduces power consumption as compared to the use of a separate combinational logic circuit. Yet another advantage of frequency divider 100 is reduced phase noise in the E and P clock signals.
  • the remaining set and reset input terminals for the latches in frequency divider 100 are coupled to corresponding 3-input NOR gates that NORs the appropriate E clock signals (a pair of E signals having a time delay between them of T/2) with the appropriate gating clock.
  • Which one of the clkp or clkn input clock signals that is used to gate the NOR gate output depends upon which P clock signal is being generated.
  • a 3-input NOR gate 145 produces the P 1 clock signal to drive the reset input terminal of first latch 125 through a NOR of the E 1 clock signal, the E 6 clock signal, and the clkn input clock signal. Note that the clkp input clock signal could also have been selected.
  • NOR gate 155 is gated by the clkp input clock signal since NOR gate 145 is gated by the clkn input clock signal.
  • NOR gate 165 NORs generates the P 3 clock signal to drive the reset terminal of third latch 135 through a NOR of the E 2 and E 3 clock signals and the clkn input clock signal.
  • the clkn and clkp input clock signals are alternately provided to the inputs of the series of NOR gates 145 - 170 .
  • NOR gate 150 NORs the E 3 clock signal with an E 4 clock signal and also with the clkp input clock signal to produce the P 4 clock signal to control the setting of first latch 125 .
  • NOR gate 150 is gated by the complement of the input clock signal that gates NOR gate 145 . This is because of the T/2 delay between each successive non-overlapping clock signal and its preceding non-overlapping clock signal. In this case, the P 4 clock signal is thus delayed by 3T/2 with respect to the P 1 clock signal. If NOR gate 150 were instead gated by the clkn input clock signal, the P 4 clock signal would then overlap with P 3 .
  • NOR gate 150 By gating NOR gate 150 with the clkp input clock signal, the desired non-overlapping time shift is achieved.
  • NOR gate 160 NORs the E 5 and E 4 clock signals with the clkn input clock signal to produce the P 5 clock signal to control the setting of second latch 130 .
  • NOR gate 170 NORs the E 6 and E 5 clock signals with the clkp input clock signal to produce the P 6 clock signal to control the setting of third latch 135 .
  • Each latch may be implemented using a cross-coupled pair of logic gates (e.g., NAND gates, NOR gates, etc.)
  • each latch is formed using a cross-coupled pair of NOR gates 110 and 115 as shown for an example cross-coupled-NOR gate latch 105 .
  • a corresponding E clock signal produced at a Q output terminal will then be asserted when the set input terminal (S) of latch 110 is asserted.
  • a corresponding E clock signal produced at a QB output terminal will then be asserted when the reset input terminal (R) of latch 110 is asserted.
  • the latches in frequency divider 100 may instead be produced using a pair of cross-coupled NAND gates in alternative implementations.
  • the resulting timing of the E and P clock signals in frequency divider 100 as controlled by the clkp and clkn input clock signals is shown in FIG. 1 B .
  • the E 1 clock signal begins a cycle at a time t 0 by rising from ground to a power supply voltage as triggered by corresponding edge in one of the input clock signals.
  • the rising edge of the clkp input clock signal triggers the rising edge of the E 1 clock signal.
  • the rising edge of the clkn input clock signal may be used to trigger the rising edge of the E 1 clock signal.
  • the E 2 clock signal With the rising edge of the E 1 clock signal occurring at time to, the E 2 clock signal thus has a rising edge at a time t 1 that is T/2 after time t 0 since each successive E clock signal is delayed by T/2 with respect to the preceding E clock signal.
  • the E 3 clock signal has a rising edge at a time t 2 that is T/2 after time t 1 .
  • the E 4 clock signal has a rising edge at a time t 3 that is T/2 after time t 2 whereas the E 5 clock signal has a rising edge at a time t 4 that is T/2 after time t 3 .
  • the E 6 clock signal has a rising edge at a time t 5 that is T/2 after time t 4 .
  • the E clock period is N*T, which is 3T in this divide-by-3 implementation.
  • the E 1 clock signal thus begins another cycle at a time t 6 that is T/2 after time t 5 and 3T after time t 0 .
  • Each E clock signal in a divide-by-three implementation thus has a period that 3 times the period T of the input clock signals.
  • Clock signals E 1 and E 6 are both in a binary zero state from time t 3 to time t 5 .
  • the clkn input clock signal is a binary zero from time t 4 to time t 5 so that is when NOR gate 145 asserts the P 1 clock signal.
  • the P 1 clock signal assertion resets first latch 125 so that the E 5 clock signal has a rising edge at time t 3 .
  • the E 2 and E 1 clock signals are both in a binary zero state from time t 4 to time t 6 .
  • the clkp input clock signal is a binary zero from time t 5 to time t 6 so that is when NOR gate 155 asserts the P 2 clock signal.
  • the P 2 clock signal assertion resets second latch 130 so that the E 6 clock signal has a rising edge at time t 5 .
  • the E 2 and E 3 clock signals are both in a binary zero state from time t 5 to a time t 7 that is T/2 after time t 6 .
  • the clkn input clock signal is a binary zero from time t 6 to time t 7 so that is when NOR gate 165 asserts the P 3 clock signal.
  • the P 3 clock signal assertion resets third latch 135 so that the clock signal E 1 has a rising edge at time t 7 .
  • Clock signals E 3 and E 4 are both in a binary zero state from time t 6 to a time t 8 that is T/2 after time t 7 .
  • the input clock signal clkp is a binary zero from time t 7 to time t 8 so that is when NOR gate 150 asserts the P 4 clock signal.
  • the P 4 clock signal assertion sets first latch 125 so that the E 3 clock signal has a rising edge at time t 7 .
  • Clock signals E 5 and E 4 are both in a binary zero state from time t 7 to a time t 9 that is T/2 after time t 8 .
  • the input clock signal clkn is a binary zero from time t 8 to time t 9 so that is when NOR gate 160 asserts the P 5 clock signal.
  • the P 5 clock signal assertion sets second latch 130 so that the E 3 clock signal has a rising edge at time t 8 .
  • clock signals E 6 and E 5 are both in a binary zero state from time t 8 to a time t 10 that is T/2 after time t 9 .
  • the input clock signal clkp is a binary zero from time t 9 to time t 10 so that is when NOR gate 170 asserts the P 6 clock signal.
  • the P 6 clock signal assertion sets third latch 135 so that the clock signal E 4 has a rising edge at time t 9 .
  • Clock signal P 1 will then begin a new cycle (not illustrated) at time t 10 .
  • each latch being implemented using a pair of cross-coupled 2-input NOR gates as discussed with regard to latch 105 , it may be seen that the resulting 3-input NOR gates and 2-input NOR gates form a plurality of 2N (in this case, six) stages arranged in a serial ring, each stage including a corresponding 3-input NOR gate and a corresponding 2-input NOR gate.
  • frequency divider 100 may be illustrated as shown in FIG. 1 C including an example stage 180 .
  • NOR gate 155 is driving the reset input terminal of second latch 130 with the P 2 clock signal.
  • NOR gate 130 -A the corresponding NOR gate in second latch 130 having an input terminal coupled to the output terminal of NOR gate 155 is designated as NOR gate 130 -A.
  • NOR gate 130 -A is cross-coupled with a NOR gate 130 -B that outputs the E 6 clock signal.
  • NOR gates 130 -A and 130 -B form the second latch 130 of FIG. 1 A .
  • the output terminal of NOR gate 130 -A couples to an input terminal of NOR gate 165 to drive NOR gate 165 with the E 3 clock signal.
  • NOR gate 165 forms another stage with a NOR gate 135 -A from third latch 135 .
  • NOR gate 165 NORs the E 3 and E 2 clock signals with the clkn input clock signal to output the P 3 clock signal.
  • NOR gate 135 -A is cross coupled with a NOR gate 135 -B to form the third latch 135 of FIG. 1 A .
  • NOR gate 125 -A is cross coupled with a NOR gate 125 -B to form the first latch 125 of FIG. 1 A .
  • FIGS. 1 A and 1 C demonstrates the equivalence of the two representations of frequency divider 100 . Thus, the remaining elements of FIG. 1 C will not be discussed further.
  • frequency divider 100 is just one implementation for a specific value of N (in this case, 3). But the principles from frequency divider 100 may be generalized to produce a frequency divider for an arbitrary integer divisor N that is greater than 3.
  • Each latch controls a corresponding pair of the E clock signals. But note that the period of the E clock signals for frequency divider 400 is now 4T such that each E clock signal is in a binary zero state (or binary high state) for 2T each clock cycle. Since the gating at the 3-input NOR gates exploits pairs of E signals that have a T overlap, each 3-input NOR gate in frequency divider 200 does not process successive pairs of E signals as was done in frequency divider 100 . In particular, each 3-input NOR gate in frequency divider 100 processes a pair of E clock signals in which one of the E clock signals is delayed by T/2 with respect to the other. But in frequency divider 200 , each 3-input NOR gate processes a pair of E clock signals in which one of the E clock signals is delayed by T with respect to the other. In this fashion, the T overlap for the mutual binary-zero state is achieved.
  • the structure of frequency divider 200 will now be further explained in conjunction with the timing diagram for frequency divider 200 that is shown in FIG. 2 B .
  • the E 1 clock signal has a rising edge at a time t 0 .
  • the E 2 clock signal has a rising edge at a time t 1 that is T/2 after time t 0
  • the E 3 clock signal has a rising edge at a time t 2 that is T/2 after time t 1 , and so on.
  • the E 4 clock signal rising edge is at a time t 3
  • the E 5 clock signal rising edge is at a time t 4
  • the E 6 clock signal rising edge is at a time t 5
  • the E 7 clock signal rising edge is at a time t 6
  • the E 8 clock signal rising edge is at a time t 7 .
  • Each E clock signal may be paired with another E clock signal to form a pair of E clock signals that have an overlap of T in which both E clock signals are in the binary-zero state.
  • the E 1 and E 7 clock signals have this overlap of T such that both signals are a binary zero from time t 4 to time t 6 .
  • a NOR gate 225 that NORs the E 1 and E 7 clock signals with the clkn input clock signal will then assert the P 1 clock signal at time t 5 .
  • the assertion of the P 1 clock signal resets first latch 205 so that clock signal E 6 has the rising edge at time t 5 .
  • the E 2 and E 8 clock signals have an overlap of T such that both signals are a binary zero from time t 5 to time t 7 .
  • a NOR gate 235 that NORs the E 2 and E 8 clock signals with the clkp input clock signal will then assert the P 2 clock signal at time t 6 .
  • the assertion of the P 2 clock signal resets second latch 210 so that clock signal E 7 has a rising edge at time t 6 .
  • the E 1 and E 3 clock signals have an overlap of T such that both signals are a binary zero from time t 6 to a time t 8 that is T/2 after time t 7 .
  • a NOR gate 245 that NORs the E 1 and E 3 clock signals with the clkn input clock signal will then assert the P 3 clock signal at time t 7 .
  • the assertion of the P 3 clock signal resets third latch 215 so that clock signal E 8 has a rising edge at time t 7 .
  • E 2 and E 4 clock signals have an overlap of T such that both signals are a binary zero from time t 7 to a time t 9 that is T/2 after time t 8 .
  • a NOR gate 255 that NORs the E 2 and E 4 clock signals with the clkp input clock signal will then assert the P 4 clock signal at time t 8 .
  • the assertion of the P 3 clock signal resets fourth latch 220 so that clock signal E 1 has a rising edge at time t 8 .
  • the E 3 and E 5 clock signals have an overlap of T such that both signals are a binary zero from time t 8 to a time t 10 that is T/2 after time t 9 .
  • a NOR gate 230 that NORs the E 3 and E 5 clock signals with the clkn input clock signal will then assert the P 5 clock signal from time t 9 to time t 10 .
  • the assertion of the P 5 clock signal sets first latch 205 so that clock signal E 2 has a rising edge at time t 9 .
  • NOR gate 240 that NORs the E 6 and E 4 clock signals with the clkp input clock signal will then assert the P 6 clock signal from time t 10 to a time t 11 that is T/2 after time t 10 .
  • the assertion of the P 6 clock signal sets second latch 210 so that the E 3 clock signal has a rising edge at time t 10 .
  • NOR gate 250 that NORs the E 7 and E 5 clock signals with the clkn input clock signal will then assert the P 7 clock signal from time t 11 to a time t 12 that is T/2 after time tn.
  • the assertion of the P 7 clock signal sets third latch 215 so that the E 4 clock signal has a rising edge at time t 11 .
  • NOR gate 260 that NORs the E 6 and E 8 clock signals with the clkp input clock signal will then assert the P 8 clock signal from time t 12 to a time t 13 that is T/2 after time t 12 .
  • the assertion of the P 8 clock signal sets fourth latch 220 so that the E 5 clock signal has a rising edge at time t 12 .
  • a comparison of frequency dividers 100 and 200 demonstrates a general pattern for values of odd N and values of even N.
  • the latches may be deemed to be arranged from a first latch to an Nth latch.
  • a first N of the plurality of 2N P clock signals may also be deemed to have the same arrangement, from the P 1 clock signal to a PN clock signal.
  • each latch is reset by the corresponding P clock signal.
  • the P 1 clock signal resets the first latch
  • the P 2 clock signal resets the second latch, and so on such that the PN clock signal resets the Nth latch.
  • a second N of the P clock signals that ranges from a P(N+1) clock signal to a P 2 N clock signal controls the setting of the latches.
  • the P(N+1) clock signal thus sets the first latch
  • a P(N+2) clock signal sets the second latch
  • so on such that the P 2 N clock signal sets the Nth latch.
  • the plurality of 2N E clock signals may also be deemed to form a first half that ranges from the E 1 clock signal to an EN clock signal and to form a second half that ranges from an E(N+1) clock signal to an E 2 N clock signal.
  • the first half are processed by the 3-input NOR gates that control the resetting of the latches.
  • a 3-input NOR gate that controls the resetting of a first latch processes the E 1 clock signal.
  • a 3-input NOR gate that controls the resetting of a second latch processes the E 2 clock signal, and so on such that a 3-input NOR gate that controls the resetting of an Nth latch processes the EN clock signal.
  • Each of these resetting NOR gates also processes a E clock signal that has a T overlap with the other E clock signal being processed.
  • the selection of this E clock signal depends upon the divisor N. For example, consider the E 1 clock signal shown in FIG. 3 . Regardless of the value of the divisor N, the corresponding frequency divider that divides by the divisor N will generate an E 1 clock signal. As already discussed, each successive E clock signal is delayed by T/2 with respect to its preceding E clock signal. There is thus an E 2 clock signal (not shown) that is delayed by T/2 with respect to the E 1 clock signal, and so on. An E(N+1) clock signal will thus have a rising edge at the falling edge of the E 1 clock signal. This is true because the half period of each E clock signal is NT/2.
  • Each half period may thus be divided into N parts of T/2 each.
  • the E(N+1) clock signal will thus have its rising edge at a delay of NT/2 from the rising edge of the E 1 clock signal.
  • the E clock signal that is T delayed from the E(N+1) clock signal is selected. Since T is two half input clock cycles, such an E clock signal is the second E clock signal subsequent to the E(N+1) clock signal.
  • the E(N+3) clock signal will provide the desired T overlap with the E 1 clock signal, regardless of whether N is odd or even.
  • a 3-input NOR gate that controls the resetting of the first latch and that processes the E 1 clock signal will then also process the E(N+3) clock signal.
  • Analogous reasoning shows that the resetting 3-input NOR for each successive latch is indexed by 1 from this resetting of the first latch.
  • the 3-input NOR gate that controls the resetting of the second latch will process E 2 and the E(N+4) clock signal, and so on. Should this indexing lead to a value that is greater than 2N, a modulo-2N value is taken.
  • the indexing without any modulus being taken leads to the 3-input NOR gate that controls the resetting of the Nth latch to process the EN clock signal and an E(2N+2) clock signal. Since (2N+2) is greater than 2N, the modulo-2N value is taken, which is 2.
  • the resetting of the Nth latch is controlled by a NOR of the EN clock signal, the E 2 clock signal, and one of the input clock signals.
  • the resetting of the latches for an odd divisor N may thus be generalized as shown in FIG. 4 for a frequency divisor 400 .
  • a NOR gate 425 NORs the E 1 clock signal and the E(N+3) clock signal with one of the input clock signals to generate the P 1 clock signal to reset the first latch 405 .
  • the clkn input clock signal is selected although the clkp input clock signal may be selected for alternative implementations.
  • the selection of the input clock signal for the gating of NOR gate 425 determines the input clock selection for all the remaining latch resetting and latch setting NOR gates.
  • first latch 405 In response to being reset, first latch 405 asserts the E(N+2) clock signal and resets the E 2 clock signal.
  • a NOR gate 435 NORs the E(N+4) and E 2 clock signals with the clkp input clock signal to produce the P 2 clock signal.
  • the clkp input clock signal is selected because the P 2 clock signal is delayed by T/2 with respect to the P 1 clock signal.
  • the second latch 410 asserts the E(N+3) clock signal and resets the E 3 clock signal.
  • a NOR gate 445 NORs the E(N+5) and E 3 clock signals with the clkn input clock signal to produce the P 3 clock signal.
  • the third latch 415 asserts the E(N+4) clock signal and resets the E 4 clock signal.
  • an ith latch i being between 1 and less than or equal to 2N
  • NOR gate that NORs the E(i) clock signal with the E(i+N+2) clock signal along with the appropriate input clock signal to produce the Pi clock signal.
  • the ith latch asserts the E(i+N+1) clock signal and resets the E(i+1) clock signal.
  • a modulo-2N value is taken of (i+N+1) if it exceeds 2N.
  • This general pattern is true for the Nth latch 420 because it is reset by a NOR gate that NORs the EN clock signal.
  • the E(i+N+2) clock signal is E 2 when i is N.
  • the Nth latch 420 is reset by a NOR gate 455 that NORs E 2 with EN.
  • the Nth latch 420 asserts the E 1 clock signal and resets the E(N+1) clock signal.
  • the gating clock for NOR gate 455 is of the same polarity as selected for the gating of NOR gate 425 because there is an odd number of latches. Since the clkn input clock signal was processed by NOR gate 425 , this same input clock signal is also processed by NOR gate 455 .
  • Each latch is set by a 3-input NOR gate that NORs the E signal with the same index plus N as the latch.
  • first latch 405 is reset by a NOR gate 430 that NORs the E(N+1) clock signal.
  • the corresponding E signal that has an overlap of T with an ith E clock signal is E(i+N+2).
  • NOR gate 430 NORs the E(N+1) and E 3 clock signals to produce the P(N+1) clock signal.
  • NOR gate 430 is gated by the clkp input clock signal.
  • first latch 405 asserts the E 2 clock signal and resets the E(N+2) clock signal.
  • the setting of each successive latch is controlled by a NOR of a pair of E clock signals whose indices are incremented by one with respect to the pair of E clock signal for the preceding latch.
  • a NOR gate 440 that produces the P(N+2) clock signal to set the second latch 410 functions to NOR the E 4 clock signal with the E(N+2) clock signal and the clkp input clock signal.
  • second latch 410 In response to being set, second latch 410 asserts the E 3 clock signal and resets the E(N+3) clock signal.
  • a NOR gate 450 that produces the P(N+3) clock signal to set the third latch 415 functions to NOR the E 5 clock signal with the E(N+3) clock signal and the clkn input clock signal.
  • the third latch 410 In response to being set, the third latch 410 asserts the E 4 clock signal and resets the E(N+4) clock signal.
  • a NOR gate 460 asserts the P 2 N clock signal to control the setting of the Nth latch 420 . To produce the P 2 N clock signal, NOR gate 460 NORs the E 2 N and E(N+2) clock signals with the clkn input clock signal.
  • frequency divider 500 With respect to the use of an even divisor N, an example frequency divider 500 is shown in FIG. 5 . It may be seen that the same selection of E clock signals occurs for the 3-input NOR gates in frequency divider 500 as was discussed for frequency divider 400 . Like frequency divider 400 , frequency divider 500 has N latches arranged from a first latch 505 to an Nth latch 520 . A NOR gate 525 that resets the first latch with the P 1 clock signal NORs the E 1 and E(N+3) clock signals with the clkn input clock signal as discussed with regard to NOR gate 425 . Similarly, a NOR gate 535 NORs the E 2 and E(N+4) clock signals to reset a second latch 510 with the P 2 clock signal.
  • NOR gate 535 is thus the equivalent of NOR gate 435 .
  • NOR gate 545 NORs the E(N+5) and E 3 clock signals to reset a third latch 515 with the P 3 clock signal. But since there an even number of latches, the Nth latch 520 is reset by NOR gate 555 that is gated by the clkp input clock signal. In contrast, NOR gate 455 is gated by the clkn input clock signal.
  • the setting of the latches in frequency divider 500 is also analogous to the setting of the latches in frequency divider 400 .
  • a NOR gate 530 NORs the E 3 and E(N+1) clock signal to control the setting of the first latch 505 with the P(N+1) clock signal.
  • the gating of NOR gate 530 is controlled by the clkn input clock signal since the clkp input clock signal gates the setting of the Nth latch 520 .
  • the setting of the second latch 510 by a NOR gate 540 is thus gated by the clkp input clock signal.
  • the setting of the third latch 515 by a NOR gate 550 is gated by the clkn input clock signal.
  • the setting of the Nth latch 520 by a NOR gate 560 is gated by the clkp input clock signal.
  • the setting and resetting NOR gates of frequency divider 500 are NORing the same E clock signals as discussed analogously for frequency divider 400 .
  • the method includes an act 600 of dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%.
  • the division of the input clock signals to form the plurality of E clock signals as discussed with respect to FIGS. 1 A, 2 A, 4 , and 5 is an example of act 600 .
  • the method also includes an act 605 of processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
  • the processing by the 3-input logic gates of FIGS. 1 A, 2 A, 4 , and 5 to form the P clock signals is an example of act 605 .
  • a frequency divider as disclosed herein may be incorporated in any suitable mobile device or electronic system.
  • a cellular telephone 700 , a laptop computer 705 , and a tablet PC 710 may all include a frequency divider in accordance with the disclosure.
  • Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with a frequency divider constructed in accordance with the disclosure.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

Description

TECHNICAL FIELD
This application relates to frequency dividers, and more particularly, to a frequency divider that generates non-overlapping clock signals.
BACKGROUND
In a plurality of non-overlapping clock signals, only one of the clock signals will be in a binary true state at any given time. This binary true state may be a power supply voltage in a binary-high convention or ground in a binary-low convention. Regardless of the binary-high (or low) convention, non-overlapping clock signals have many uses in electronic systems. For example, modern receivers may use passive mixers that are driven by a plurality N of non-overlapping clock signals, N being a plural positive integer. However, the generation of non-overlapping clock signals typically consumes substantial power and may suffer from excessive phase noise.
SUMMARY
A frequency divider is provided for the generation of non-overlapping clock signals that includes: a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises: a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and wherein an output terminal of the 2-input logic gate in each preceding stage in the series is coupled to a first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein an output terminal of the 2-input logic gate in the Nth stage is coupled to a first input terminal of the 3-input logic gate in the first stage.
In addition, a frequency divider is provided that includes: a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal; a plurality of N latches, wherein N is a plural positive integer greater than two; a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals; and a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the second output terminal, a corresponding non-overlapping clock signal from a second plurality of N non-overlapping clock signals.
In addition, a frequency divider is provided that includes: a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal; a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth of the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater; and a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.
Finally, a method of frequency division is provided that includes: dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%; and processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
These and other advantageous features may be better appreciated through the following detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a circuit diagram of a divide-by-3 frequency divider in accordance with an aspect of the disclosure.
FIG. 1B is a timing diagram for the clock signals of FIG. 1A.
FIG. 1C is an alternative circuit diagram of the divide-by-3 frequency divider of FIG. 1A.
FIG. 2A is a circuit diagram of a divide-by-4 frequency divider in accordance with an aspect of the disclosure.
FIG. 2B is a timing diagram for the clock signals of FIG. 2A.
FIG. 3 is a timing diagram illustrating a time difference between three example overlapping clock signals in accordance with an aspect of the disclosure.
FIG. 4 is a circuit diagram for a divide-by-N frequency divider in which N is odd in accordance with an aspect of the disclosure.
FIG. 5 is a circuit diagram for a divide-by-N frequency divider in which N is even in accordance with an aspect of the disclosure.
FIG. 6 is a flowchart for an example method of operation for a divide-by-N frequency divider in accordance with an aspect of the disclosure.
FIG. 7 illustrates some example electronic devices including a frequency divider in accordance with an aspect of the disclosure.
Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figure.
DETAILED DESCRIPTION
A frequency divider is provided that divides an input clock signal according to a positive integer N into a plurality of 2N non-overlapping clock signals, where N is three or greater. The input clock signal cycles at a frequency f with a period T. Each non-overlapping clock signal thus has a frequency of f/N and a period of N*T. In the following discussion, each non-overlapping clock signal is deemed to be “asserted” when the non-overlapping clock signal is in a binary true state, regardless of whether the binary true state is represented using a binary-high or a binary-low convention. In implementations in which a binary-high convention is used, each non-overlapping clock signal is thus asserted by being charged to a power supply voltage. Conversely, in implementations in which a binary-low convention is used, each non-overlapping clock signal is asserted by being discharged to ground. Regardless of which convention is used, each non-overlapping clock signal is asserted for just T/2 in each period of N*T. The input clock signal has a 50% duty cycle so that it is also asserted to T/2 in in each period of T.
The frequency divider also divides the input clock signal into a plurality of 2N overlapping clock signals, each having a duty cycle of 50%. Like the non-overlapping clock signals, each overlapping clock signal has a frequency of f/N and a period of N*T. Given the 50% duty cycle, each overlapping clock signal is asserted in one-half of its period, which equals NT/2. Since the assertion time for each non-overlapping clock signal is T/2, this non-overlapping assertion time is 1/Nth the assertion time for each overlapping clock signal. The duty cycle of each non-overlapping clock signal is thus 50%/N.
The 2N overlapping clock signals may be deemed to be arranged from a first overlapping clock signal to a 2Nth overlapping clock signals. With respect to this order or arrangement, an ith overlapping clock signal is timed so as to be delayed by T/2 with respect to an (i−1)th overlapping clock signal, where i is an integer ranging from 2 to 2N. The first overlapping clock signal is delayed by T/2 with respect to the 2Nth overlapping clock signal. To form these 2N overlapping clock signals having this staggered or progressive time-delay relationship, the frequency divider includes a plurality of N set-reset latches. Each latch produces a corresponding pair of the overlapping clock signals. The latches may be deemed to be arranged serially, from a first latch to an Nth latch. With respect to this order, an ith latch produces an (i+1)th overlapping clock signal and an ((i+1)+N)th overlapping clock signal, where i is an integer ranging from 1 to (N−1). The Nth latch produces the first overlapping clock signal and an (N+1)th overlapping clock signal.
Since each latch is a set-reset latch, each latch has a reset input terminal and a set input terminal. When an ith latch is set by an assertion of a voltage of its set input terminal, it asserts the (i+1)th overlapping clock signal. Similarly, when an ith latch is reset by an assertion of a voltage of its reset input terminal, it asserts the (i+(N+1))th overlapping clock signal. Given the time delay of T/2 from one overlapping clock signal to the next, the pair of overlapping clock signals produced by each latch will have a time difference of NT/2. When set, the Nth latch asserts the (N+1)th overlapping clock signal. Similarly, the Nth latch asserts the first overlapping clock signal when reset.
The set input terminal of each latch is controlled by a corresponding three-input logic gate. Since there are N latches, there are N corresponding three-input logic gates to control the setting of the N latches. Similarly, there are N corresponding three-input logic gates to the control the resetting of the N latches. Each latch thus couples to a first three-input logic gate that drives the latch's set terminal and couples to a second three-input logic gate that drives the latch's reset terminal. There is thus a plurality of N three-input first logic gates and a plurality of N three-input second logic gates.
The following discussion will assume that each three-input first and second logic gate is a 3-input NOR gate, but it will be appreciated that a 3-input NAND gate may also be used in alternative implementations. Each 3-input logic gate produces a corresponding one of the 2N non-overlapping clock signals. An example frequency divider 100 in which N equals 3 is shown in FIG. 1A. Since the frequency division is by 3, there are three latches including a first latch 125, a second latch 130, and a third latch 135. With N being 3, there are 2N=6 overlapping clock signals, each designated by E and its index. A first overlapping clock signal is thus designated as E1, a second overlapping clock signal is designated as E2, a third overlapping clock signal is designated as E3, and so on such that a sixth overlapping clock signal is designated as E6.
When set by an assertion of a set (S) terminal, first latch 125 asserts the E2 clock signal and resets (de-asserts) an E5 clock signal. Conversely when reset by an assertion of a reset (R) terminal, first latch 125 asserts the E5 clock signal and resets the E2 clock signal. The E2 and E5 clock signal are thus complements of each other. Since each successive E clock signal is delayed by T/2, the E5 clock signal is delayed by 3T/2 with respect to the E2 clock signal. Similarly, second latch 130 asserts the E3 clock signal and resets the E6 clock signal when set. Second latch 130 also resets the E3 clock signal and asserts the E6 clock signal when reset. The E3 and E6 clock signals are thus complements of each other. In addition, third latch 135 asserts an E4 clock signal and resets the E1 clock signal when set. Finally, third latch 135 asserts the E1 clock signal and resets the E4 clock signal when reset. The E1 and E4 clock signal are thus complements of each other. More generally, each latch produces a complementary pair of overlapping clock signals.
Each latch has its set terminal voltage controlled by a corresponding 3-input NOR gate. Similarly, each latch has its reset terminal voltage controlled by another corresponding 3-input NOR gate. Since there are N latches, there are thus 2N=6 3-input NOR gates for the setting and resetting of the N latches. Each 3-input NOR gate produces or outputs a corresponding non-overlapping clock signal. There are thus 6 non-overlapping clock signals produced by frequency divider 100. The non-overlapping clock signals are designated by a letter P and a corresponding index. In particular, frequency divider 100 produces six P clock signals ranging from a P1 clock signal to a P6 clock signal. Like the overlapping clock signals, each successive non-overlapping clock signal is delayed by T/2 with respect to a preceding non-overlapping clock signal. A P 2 clock signal is thus delayed by T/2 with respect to the P1 clock signal. Similarly, a P3 clock signal is delayed by T/2 with respect to the P2 clock signal, a P4 clock signal is delayed by T/2 with respect to the P3 clock signal, and so on such that the P6 clock signal is delayed by T/2 with respect to a P5 clock signal.
Since the setting and resetting of each latch controls the production of each latch's pair of overlapping clock signals, the overlapping clock signals from any given latch are complementary. For example, the E2 and E5 clock signal produced by first latch 125 are complements of each other. Although there is thus no overlap between the E2 and E5 clock signals, note that is still accurate to refer to the E2 and E5 clock signals as overlapping clock signals. For example, the E2 clock signal overlaps with every other E clock signal except the E5 clock signal. Similarly, the E5 clock signal overlaps with every other E clock signal except the E2 clock signal. More generally, each latch produces a complementary pair of E signals that overlap with all the remaining E clock signals. Frequency divider 100 thus functions to divide the clkn and clkp input clock signals in frequency by a divisor N using a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals, where N equals 3.
Given the T/2 delay of each successive E clock signal with respect to its preceding E clock signal, each successive E clock signal will have an overlap of T with the preceding clock signal in which both E clock signals are in a binary false state (which is ground in a binary-high convention) in this divide-by-3 implementation. For example, the E2 clock signal has such an overlap of T with the E1 clock signal. The NOR gates exploit this T overlap by gating each successive E clock signal with the preceding E clock signal with a gating clock signal selected from a positive input clock signal (clkp) and a negative input clock signal (clkn) as produced by a differential clock source 120. For example, a 3-input NOR gate 155 NORs the E1 clock signal with the E2 clock signal and with the clkp input clock signal to produce the P2 clock signal to drive the reset input terminal of the second latch 130. Note how advantageous this gating is: without the gating by the selected input clock signal, the E1 and E2 clock signals will both be in a binary zero state for T in each of their periods since the E2 clock signal is delayed by T/2 with respect to the E1 clock signal. An output signal from NOR gate 155 would then pulse high during this T-long stretch of time in which both the E1 and the E2 clock signals are in the binary zero state. Note that frequency divider 100 could not produce non-overlapping clock signals if each non-overlapping clock signal had an assertion time of T. But when gated by one of the input clock signals, the output signal from NOR gate 155 can form the desired non-overlapping P2 clock signal.
In that regard, it is known to construct a frequency divider from a serially arranged set of flip-flops. Such a serially arranged set of flip-flops may produce the equivalent of the overlapping clock signals with a 50% duty cycle. But a separate combinational logic circuit would then be needed to process the overlapping clock signals from such a frequency divider to obtain the non-overlapping clock signals. In sharp contrast, frequency divider 100 itself not only produces the E clock signals (the overlapping clock signals) but also the P clock signals (the non-overlapping clock signals). The result is a significant reduction in semiconductor die space to implement frequency divider 100. In addition, frequency divider 100 may be readily modified as explained herein to accommodate any desired even or odd value of N. Moreover, frequency divider 100 reduces power consumption as compared to the use of a separate combinational logic circuit. Yet another advantage of frequency divider 100 is reduced phase noise in the E and P clock signals.
The remaining set and reset input terminals for the latches in frequency divider 100 are coupled to corresponding 3-input NOR gates that NORs the appropriate E clock signals (a pair of E signals having a time delay between them of T/2) with the appropriate gating clock. Which one of the clkp or clkn input clock signals that is used to gate the NOR gate output depends upon which P clock signal is being generated. For example, a 3-input NOR gate 145 produces the P1 clock signal to drive the reset input terminal of first latch 125 through a NOR of the E1 clock signal, the E6 clock signal, and the clkn input clock signal. Note that the clkp input clock signal could also have been selected. But whatever input clock signal is selected, that determines the input clock signal selection for the NOR gate producing the subsequent P clock signal. Thus, NOR gate 155 is gated by the clkp input clock signal since NOR gate 145 is gated by the clkn input clock signal. Similarly, a 3-input NOR gate 165 NORs generates the P3 clock signal to drive the reset terminal of third latch 135 through a NOR of the E2 and E3 clock signals and the clkn input clock signal. In sum, the clkn and clkp input clock signals are alternately provided to the inputs of the series of NOR gates 145-170.
The setting of the latches is controlled by an analogous 3-input NOR gate. For example, a 3-input NOR gate 150 NORs the E3 clock signal with an E4 clock signal and also with the clkp input clock signal to produce the P4 clock signal to control the setting of first latch 125. Note that NOR gate 150 is gated by the complement of the input clock signal that gates NOR gate 145. This is because of the T/2 delay between each successive non-overlapping clock signal and its preceding non-overlapping clock signal. In this case, the P4 clock signal is thus delayed by 3T/2 with respect to the P1 clock signal. If NOR gate 150 were instead gated by the clkn input clock signal, the P4 clock signal would then overlap with P3. But by gating NOR gate 150 with the clkp input clock signal, the desired non-overlapping time shift is achieved. Similarly, a NOR gate 160 NORs the E5 and E4 clock signals with the clkn input clock signal to produce the P5 clock signal to control the setting of second latch 130. Finally, a NOR gate 170 NORs the E6 and E5 clock signals with the clkp input clock signal to produce the P6 clock signal to control the setting of third latch 135.
Each latch may be implemented using a cross-coupled pair of logic gates (e.g., NAND gates, NOR gates, etc.) In one implementation, each latch is formed using a cross-coupled pair of NOR gates 110 and 115 as shown for an example cross-coupled-NOR gate latch 105. A corresponding E clock signal produced at a Q output terminal will then be asserted when the set input terminal (S) of latch 110 is asserted. Similarly, a corresponding E clock signal produced at a QB output terminal will then be asserted when the reset input terminal (R) of latch 110 is asserted. Note that the latches in frequency divider 100 may instead be produced using a pair of cross-coupled NAND gates in alternative implementations.
The resulting timing of the E and P clock signals in frequency divider 100 as controlled by the clkp and clkn input clock signals is shown in FIG. 1B. The E1 clock signal begins a cycle at a time t0 by rising from ground to a power supply voltage as triggered by corresponding edge in one of the input clock signals. In this implementation, the rising edge of the clkp input clock signal triggers the rising edge of the E1 clock signal. In alternative implementations, the rising edge of the clkn input clock signal may be used to trigger the rising edge of the E1 clock signal. With the rising edge of the E1 clock signal occurring at time to, the E2 clock signal thus has a rising edge at a time t1 that is T/2 after time t0 since each successive E clock signal is delayed by T/2 with respect to the preceding E clock signal. Similarly, the E3 clock signal has a rising edge at a time t2 that is T/2 after time t1. The E4 clock signal has a rising edge at a time t3 that is T/2 after time t2 whereas the E5 clock signal has a rising edge at a time t4 that is T/2 after time t3. Similarly, the E6 clock signal has a rising edge at a time t5 that is T/2 after time t4. The E clock period is N*T, which is 3T in this divide-by-3 implementation. The E1 clock signal thus begins another cycle at a time t6 that is T/2 after time t5 and 3T after time t0. Each E clock signal in a divide-by-three implementation thus has a period that 3 times the period T of the input clock signals.
The resetting of the latches and the corresponding assertions of clock signals P1, P2, and P3 will be discussed first. Clock signals E1 and E6 are both in a binary zero state from time t3 to time t5. The clkn input clock signal is a binary zero from time t4 to time t5 so that is when NOR gate 145 asserts the P1 clock signal. The P1 clock signal assertion resets first latch 125 so that the E5 clock signal has a rising edge at time t3. Similarly, the E2 and E1 clock signals are both in a binary zero state from time t4 to time t6. The clkp input clock signal is a binary zero from time t5 to time t6 so that is when NOR gate 155 asserts the P2 clock signal. The P2 clock signal assertion resets second latch 130 so that the E6 clock signal has a rising edge at time t5. The E2 and E3 clock signals are both in a binary zero state from time t5 to a time t7 that is T/2 after time t6. The clkn input clock signal is a binary zero from time t6 to time t7 so that is when NOR gate 165 asserts the P3 clock signal. The P3 clock signal assertion resets third latch 135 so that the clock signal E1 has a rising edge at time t7.
The setting of the latches and the corresponding assertions of clock signals P4, P5, and P6 will now be discussed. Clock signals E3 and E4 are both in a binary zero state from time t6 to a time t8 that is T/2 after time t7. The input clock signal clkp is a binary zero from time t7 to time t8 so that is when NOR gate 150 asserts the P4 clock signal. The P4 clock signal assertion sets first latch 125 so that the E3 clock signal has a rising edge at time t7. Clock signals E5 and E4 are both in a binary zero state from time t7 to a time t9 that is T/2 after time t8. The input clock signal clkn is a binary zero from time t8 to time t9 so that is when NOR gate 160 asserts the P5 clock signal. The P5 clock signal assertion sets second latch 130 so that the E3 clock signal has a rising edge at time t8. Finally, clock signals E6 and E5 are both in a binary zero state from time t8 to a time t10 that is T/2 after time t9. The input clock signal clkp is a binary zero from time t9 to time t10 so that is when NOR gate 170 asserts the P6 clock signal. The P6 clock signal assertion sets third latch 135 so that the clock signal E4 has a rising edge at time t9. Clock signal P1 will then begin a new cycle (not illustrated) at time t10.
With each latch being implemented using a pair of cross-coupled 2-input NOR gates as discussed with regard to latch 105, it may be seen that the resulting 3-input NOR gates and 2-input NOR gates form a plurality of 2N (in this case, six) stages arranged in a serial ring, each stage including a corresponding 3-input NOR gate and a corresponding 2-input NOR gate. For example, frequency divider 100 may be illustrated as shown in FIG. 1C including an example stage 180. Referring back to FIG. 1A, note that NOR gate 155 is driving the reset input terminal of second latch 130 with the P2 clock signal. With the latches being implemented by cross-coupled 2-input NOR gates as shown for latch 105, the corresponding NOR gate in second latch 130 having an input terminal coupled to the output terminal of NOR gate 155 is designated as NOR gate 130-A. NOR gate 130-A is cross-coupled with a NOR gate 130-B that outputs the E6 clock signal. NOR gates 130-A and 130-B form the second latch 130 of FIG. 1A. The output terminal of NOR gate 130-A couples to an input terminal of NOR gate 165 to drive NOR gate 165 with the E3 clock signal.
NOR gate 165 forms another stage with a NOR gate 135-A from third latch 135. As already discussed, NOR gate 165 NORs the E3 and E2 clock signals with the clkn input clock signal to output the P3 clock signal. NOR gate 135-A is cross coupled with a NOR gate 135-B to form the third latch 135 of FIG. 1A. Similarly, a NOR gate 125-A is cross coupled with a NOR gate 125-B to form the first latch 125 of FIG. 1A. A comparison of FIGS. 1A and 1C demonstrates the equivalence of the two representations of frequency divider 100. Thus, the remaining elements of FIG. 1C will not be discussed further.
It will be appreciated that frequency divider 100 is just one implementation for a specific value of N (in this case, 3). But the principles from frequency divider 100 may be generalized to produce a frequency divider for an arbitrary integer divisor N that is greater than 3. For example, a frequency divider 200 shown in FIG. 2A divides the input clock signals clkp and clkn by four (N=4) to produce a plurality of 8 overlapping clock signals (E1 through E8) and a plurality of 8 non-overlapping clock signals (P1 through P8). Since N is four, frequency divider 200 has a serial arrangement of four latches formed by a first latch 205, a second latch 210, a third latch 215, and a fourth latch 220. Each latch controls a corresponding pair of the E clock signals. But note that the period of the E clock signals for frequency divider 400 is now 4T such that each E clock signal is in a binary zero state (or binary high state) for 2T each clock cycle. Since the gating at the 3-input NOR gates exploits pairs of E signals that have a T overlap, each 3-input NOR gate in frequency divider 200 does not process successive pairs of E signals as was done in frequency divider 100. In particular, each 3-input NOR gate in frequency divider 100 processes a pair of E clock signals in which one of the E clock signals is delayed by T/2 with respect to the other. But in frequency divider 200, each 3-input NOR gate processes a pair of E clock signals in which one of the E clock signals is delayed by T with respect to the other. In this fashion, the T overlap for the mutual binary-zero state is achieved.
The structure of frequency divider 200 will now be further explained in conjunction with the timing diagram for frequency divider 200 that is shown in FIG. 2B. The E1 clock signal has a rising edge at a time t0. The E2 clock signal has a rising edge at a time t1 that is T/2 after time t0, the E3 clock signal has a rising edge at a time t2 that is T/2 after time t1, and so on. For example, the E4 clock signal rising edge is at a time t3, the E5 clock signal rising edge is at a time t4, the E6 clock signal rising edge is at a time t5, the E7 clock signal rising edge is at a time t6, and the E8 clock signal rising edge is at a time t7. Each E clock signal may be paired with another E clock signal to form a pair of E clock signals that have an overlap of T in which both E clock signals are in the binary-zero state. For example, the E1 and E7 clock signals have this overlap of T such that both signals are a binary zero from time t4 to time t6.
The resetting of the latches will be discussed first followed by a discussion of the setting of the latches. A NOR gate 225 that NORs the E1 and E7 clock signals with the clkn input clock signal will then assert the P1 clock signal at time t5. The assertion of the P1 clock signal resets first latch 205 so that clock signal E6 has the rising edge at time t5. The E2 and E8 clock signals have an overlap of T such that both signals are a binary zero from time t5 to time t7. A NOR gate 235 that NORs the E2 and E8 clock signals with the clkp input clock signal will then assert the P2 clock signal at time t6. The assertion of the P2 clock signal resets second latch 210 so that clock signal E7 has a rising edge at time t6. The E1 and E3 clock signals have an overlap of T such that both signals are a binary zero from time t6 to a time t8 that is T/2 after time t7. A NOR gate 245 that NORs the E1 and E3 clock signals with the clkn input clock signal will then assert the P3 clock signal at time t7. The assertion of the P3 clock signal resets third latch 215 so that clock signal E8 has a rising edge at time t7. Finally, the E2 and E4 clock signals have an overlap of T such that both signals are a binary zero from time t7 to a time t9 that is T/2 after time t8. A NOR gate 255 that NORs the E2 and E4 clock signals with the clkp input clock signal will then assert the P4 clock signal at time t8. The assertion of the P3 clock signal resets fourth latch 220 so that clock signal E1 has a rising edge at time t8.
With regard to the setting of the latches, the E3 and E5 clock signals have an overlap of T such that both signals are a binary zero from time t8 to a time t10 that is T/2 after time t9. A NOR gate 230 that NORs the E3 and E5 clock signals with the clkn input clock signal will then assert the P5 clock signal from time t9 to time t10. The assertion of the P5 clock signal sets first latch 205 so that clock signal E2 has a rising edge at time t9. Similarly, a NOR gate 240 that NORs the E6 and E4 clock signals with the clkp input clock signal will then assert the P6 clock signal from time t10 to a time t11 that is T/2 after time t10. The assertion of the P6 clock signal sets second latch 210 so that the E3 clock signal has a rising edge at time t10. In addition, a NOR gate 250 that NORs the E7 and E5 clock signals with the clkn input clock signal will then assert the P7 clock signal from time t11 to a time t12 that is T/2 after time tn. The assertion of the P7 clock signal sets third latch 215 so that the E4 clock signal has a rising edge at time t11. Finally, a NOR gate 260 that NORs the E6 and E8 clock signals with the clkp input clock signal will then assert the P8 clock signal from time t12 to a time t13 that is T/2 after time t12. The assertion of the P8 clock signal sets fourth latch 220 so that the E5 clock signal has a rising edge at time t12.
A comparison of frequency dividers 100 and 200 demonstrates a general pattern for values of odd N and values of even N. For example, the latches may be deemed to be arranged from a first latch to an Nth latch. A first N of the plurality of 2N P clock signals may also be deemed to have the same arrangement, from the P1 clock signal to a PN clock signal. Regardless of whether the divisor N is odd or even, each latch is reset by the corresponding P clock signal. For example, the P1 clock signal resets the first latch, the P2 clock signal resets the second latch, and so on such that the PN clock signal resets the Nth latch. Similarly, a second N of the P clock signals that ranges from a P(N+1) clock signal to a P2N clock signal controls the setting of the latches. The P(N+1) clock signal thus sets the first latch, a P(N+2) clock signal sets the second latch, and so on such that the P2N clock signal sets the Nth latch.
The plurality of 2N E clock signals may also be deemed to form a first half that ranges from the E1 clock signal to an EN clock signal and to form a second half that ranges from an E(N+1) clock signal to an E2N clock signal. The first half are processed by the 3-input NOR gates that control the resetting of the latches. For example, a 3-input NOR gate that controls the resetting of a first latch processes the E1 clock signal. Similarly, a 3-input NOR gate that controls the resetting of a second latch processes the E2 clock signal, and so on such that a 3-input NOR gate that controls the resetting of an Nth latch processes the EN clock signal. Each of these resetting NOR gates also processes a E clock signal that has a T overlap with the other E clock signal being processed. The selection of this E clock signal depends upon the divisor N. For example, consider the E1 clock signal shown in FIG. 3 . Regardless of the value of the divisor N, the corresponding frequency divider that divides by the divisor N will generate an E1 clock signal. As already discussed, each successive E clock signal is delayed by T/2 with respect to its preceding E clock signal. There is thus an E2 clock signal (not shown) that is delayed by T/2 with respect to the E1 clock signal, and so on. An E(N+1) clock signal will thus have a rising edge at the falling edge of the E1 clock signal. This is true because the half period of each E clock signal is NT/2. Each half period may thus be divided into N parts of T/2 each. The E(N+1) clock signal will thus have its rising edge at a delay of NT/2 from the rising edge of the E1 clock signal. To get the T overlap with E1, the E clock signal that is T delayed from the E(N+1) clock signal is selected. Since T is two half input clock cycles, such an E clock signal is the second E clock signal subsequent to the E(N+1) clock signal. Thus, the E(N+3) clock signal will provide the desired T overlap with the E1 clock signal, regardless of whether N is odd or even. A 3-input NOR gate that controls the resetting of the first latch and that processes the E1 clock signal will then also process the E(N+3) clock signal. Analogous reasoning shows that the resetting 3-input NOR for each successive latch is indexed by 1 from this resetting of the first latch. For example, the 3-input NOR gate that controls the resetting of the second latch will process E2 and the E(N+4) clock signal, and so on. Should this indexing lead to a value that is greater than 2N, a modulo-2N value is taken. For example, the indexing without any modulus being taken leads to the 3-input NOR gate that controls the resetting of the Nth latch to process the EN clock signal and an E(2N+2) clock signal. Since (2N+2) is greater than 2N, the modulo-2N value is taken, which is 2. Thus, the resetting of the Nth latch is controlled by a NOR of the EN clock signal, the E2 clock signal, and one of the input clock signals.
As indicated earlier, it is arbitrary which input clock signal is processed by the 3-input NOR gate that resets the first latch. But once a selection is made, each subsequent latch's resetting is controlled by the complement of the input clock signal that controlled the resetting of the previous latch. Similarly, the setting of the first latch is controlled by a complement of the input clock signal that controlled the setting of the Nth latch. This leads to two general patterns that depends upon whether the divisor N is even or odd. Should the divisor N be even, the resetting of the Nth latch is controlled by the complement of the input clock that controlled the resetting of the first latch. Conversely, if the divisor N is odd, the resetting of the Nth latch is controlled by the same input clock signal that controlled the resetting of the first latch. This can be seen for frequency divider 100 for which the divisor N is odd: both NOR gates 145 and 165 process the clkn input clock signal. But in frequency divider 200, NOR gate 225 processes the clkn input clock signal whereas NOR gate 255 processes the clkp input clock signal.
The resetting of the latches for an odd divisor N may thus be generalized as shown in FIG. 4 for a frequency divisor 400. There are N latches ranging from a first latch 405 to an Nth latch 420. A NOR gate 425 NORs the E1 clock signal and the E(N+3) clock signal with one of the input clock signals to generate the P1 clock signal to reset the first latch 405. In this implementation, the clkn input clock signal is selected although the clkp input clock signal may be selected for alternative implementations. The selection of the input clock signal for the gating of NOR gate 425 then determines the input clock selection for all the remaining latch resetting and latch setting NOR gates. In response to being reset, first latch 405 asserts the E(N+2) clock signal and resets the E2 clock signal. To control the resetting of the second latch 410, a NOR gate 435 NORs the E(N+4) and E2 clock signals with the clkp input clock signal to produce the P2 clock signal. The clkp input clock signal is selected because the P2 clock signal is delayed by T/2 with respect to the P1 clock signal. In response to being reset, the second latch 410 asserts the E(N+3) clock signal and resets the E3 clock signal. To control the resetting of the third latch 415, a NOR gate 445 NORs the E(N+5) and E3 clock signals with the clkn input clock signal to produce the P3 clock signal. In response to being reset, the third latch 415 asserts the E(N+4) clock signal and resets the E4 clock signal. More generally, it can be appreciated that an ith latch (i being between 1 and less than or equal to 2N) is reset by a NOR gate that NORs the E(i) clock signal with the E(i+N+2) clock signal along with the appropriate input clock signal to produce the Pi clock signal. In response to the assertion of the Pi clock signal, the ith latch asserts the E(i+N+1) clock signal and resets the E(i+1) clock signal. A modulo-2N value is taken of (i+N+1) if it exceeds 2N. This general pattern is true for the Nth latch 420 because it is reset by a NOR gate that NORs the EN clock signal. The E(i+N+2) clock signal is E2 when i is N. Thus, the Nth latch 420 is reset by a NOR gate 455 that NORs E2 with EN. In response to being reset, the Nth latch 420 asserts the E1 clock signal and resets the E(N+1) clock signal. The gating clock for NOR gate 455 is of the same polarity as selected for the gating of NOR gate 425 because there is an odd number of latches. Since the clkn input clock signal was processed by NOR gate 425, this same input clock signal is also processed by NOR gate 455.
A similar pattern exists for the setting of each latch in frequency divider 400. Each latch is set by a 3-input NOR gate that NORs the E signal with the same index plus N as the latch. For example, first latch 405 is reset by a NOR gate 430 that NORs the E(N+1) clock signal. As discussed earlier, the corresponding E signal that has an overlap of T with an ith E clock signal is E(i+N+2). Adding N+2 to the index of the E(N+1) clock signal leads to the E3 clock signal since 2N+3 is greater than 2N. Thus, NOR gate 430 NORs the E(N+1) and E3 clock signals to produce the P(N+1) clock signal. Since the PN clock is gated by the clkn input clock signal, NOR gate 430 is gated by the clkp input clock signal. In response to being set, first latch 405 asserts the E2 clock signal and resets the E(N+2) clock signal. The setting of each successive latch is controlled by a NOR of a pair of E clock signals whose indices are incremented by one with respect to the pair of E clock signal for the preceding latch. Thus, a NOR gate 440 that produces the P(N+2) clock signal to set the second latch 410 functions to NOR the E4 clock signal with the E(N+2) clock signal and the clkp input clock signal. In response to being set, second latch 410 asserts the E3 clock signal and resets the E(N+3) clock signal. Similarly, a NOR gate 450 that produces the P(N+3) clock signal to set the third latch 415 functions to NOR the E5 clock signal with the E(N+3) clock signal and the clkn input clock signal. In response to being set, the third latch 410 asserts the E4 clock signal and resets the E(N+4) clock signal. Finally, a NOR gate 460 asserts the P2N clock signal to control the setting of the Nth latch 420. To produce the P2N clock signal, NOR gate 460 NORs the E2N and E(N+2) clock signals with the clkn input clock signal.
With respect to the use of an even divisor N, an example frequency divider 500 is shown in FIG. 5 . It may be seen that the same selection of E clock signals occurs for the 3-input NOR gates in frequency divider 500 as was discussed for frequency divider 400. Like frequency divider 400, frequency divider 500 has N latches arranged from a first latch 505 to an Nth latch 520. A NOR gate 525 that resets the first latch with the P1 clock signal NORs the E1 and E(N+3) clock signals with the clkn input clock signal as discussed with regard to NOR gate 425. Similarly, a NOR gate 535 NORs the E2 and E(N+4) clock signals to reset a second latch 510 with the P2 clock signal. NOR gate 535 is thus the equivalent of NOR gate 435. In the same fashion, a NOR gate 545 NORs the E(N+5) and E3 clock signals to reset a third latch 515 with the P3 clock signal. But since there an even number of latches, the Nth latch 520 is reset by NOR gate 555 that is gated by the clkp input clock signal. In contrast, NOR gate 455 is gated by the clkn input clock signal.
The setting of the latches in frequency divider 500 is also analogous to the setting of the latches in frequency divider 400. For example, a NOR gate 530 NORs the E3 and E(N+1) clock signal to control the setting of the first latch 505 with the P(N+1) clock signal. But the gating of NOR gate 530 is controlled by the clkn input clock signal since the clkp input clock signal gates the setting of the Nth latch 520. The setting of the second latch 510 by a NOR gate 540 is thus gated by the clkp input clock signal. Similarly, the setting of the third latch 515 by a NOR gate 550 is gated by the clkn input clock signal. Finally, the setting of the Nth latch 520 by a NOR gate 560 is gated by the clkp input clock signal. Other than the input clock selection, it may be seen that the setting and resetting NOR gates of frequency divider 500 are NORing the same E clock signals as discussed analogously for frequency divider 400.
A method of frequency division in accordance with the disclosure will now be discussed with respect to the flowchart of FIG. 6 . The method includes an act 600 of dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%. The division of the input clock signals to form the plurality of E clock signals as discussed with respect to FIGS. 1A, 2A, 4, and 5 is an example of act 600. The method also includes an act 605 of processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %. The processing by the 3-input logic gates of FIGS. 1A, 2A, 4, and 5 to form the P clock signals is an example of act 605.
A frequency divider as disclosed herein may be incorporated in any suitable mobile device or electronic system. For example, as shown in FIG. 7 , a cellular telephone 700, a laptop computer 705, and a tablet PC 710 may all include a frequency divider in accordance with the disclosure. Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with a frequency divider constructed in accordance with the disclosure.
The disclosure will now be summarized in the following series of clauses:
    • Clause 1. A frequency divider, comprising:
      • a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises:
      • a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and
      • wherein an output terminal of the 2-input logic gate in each preceding stage in the series is coupled to a first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein an output terminal of the 2-input logic gate in the Nth stage is coupled to a first input terminal of the 3-input logic gate in the first stage.
    • Clause 2. The frequency divider of clause 1, wherein the 2-input logic gates are cross-coupled to form N latches.
    • Clause 3. The frequency divider of any of clauses 1-2, wherein each three-input logic gate has a second input terminal coupled to a clock source.
    • Clause 4. The frequency divider of clause 3, wherein each stage's three-input logic gate has a third input terminal coupled to the output terminal of the 2-input terminal in another one of the stages.
    • Clause 5. A frequency divider, comprising:
      • a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal;
      • a plurality of N latches, wherein N is a plural positive integer greater than two;
      • a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals; and
      • a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the second output terminal, a corresponding non-overlapping clock signal from a second plurality of N non-overlapping clock signals.
    • Clause 6. The frequency divider of clause 5, wherein each latch in the plurality of N latches comprises a cross-coupled pair of logic gates.
    • Clause 7. The frequency divider of clause 6, wherein the cross-coupled pair of logic gates in each latch in the plurality of N latches comprises a cross-coupled pair of NOR gates.
    • Clause 8. The frequency divider of any of clauses 5-7, wherein the plurality of N first logic gates comprises a first plurality of N 3-input NOR gates.
    • Clause 9. The frequency divider of any of clauses 5-8, wherein the plurality of N second logic gates comprises a second plurality of N 3-input NOR gates.
    • Clause 10. The frequency divider of clause 8, wherein the first plurality of N 3-input NOR gates is arranged from a first 3-input NOR gate to an Nth 3-input NOR gate and the first plurality of N non-overlapping clock signal is arranged from a first non-overlapping clock signal to an Nth non-overlapping clock signal, and wherein the first 3-input NOR gate is configured to output the first non-overlapping clock signal, a second 3-input NOR gate is configured to output a second non-overlapping clock signal, and so on such that the Nth 3-input NOR gate is configured to output the Nth non-overlapping clock signal.
    • Clause 11. The frequency divider of clause 9, wherein the second plurality of N 3-input NOR gates is arranged from an (N+1)th 3-input NOR gate to an 2Nth 3-input NOR gate and the second plurality of N non-overlapping clock signal is arranged from an (N+1)th non-overlapping clock signal to a 2Nth non-overlapping clock signal, and wherein the (N+1)th 3-input NOR gate is configured to output the (N+1)th non-overlapping clock signal, an (N+2)th 3-input NOR gate is configured to output an (N+2)th non-overlapping clock signal, and so on such that the 2Nth 3-input NOR gate is configured to output the 2Nth non-overlapping clock signal.
    • Clause 12. The frequency divider of any of clauses 5-11, wherein N is an even integer greater than two.
    • Clause 13. The frequency divider of any of clauses 5-11, wherein N is an odd integer greater than two.
    • Clause 14. The frequency divider of any of clauses 5-11, wherein the frequency divider is incorporated into a cellular telephone.
    • Clause 15. A divide-by-N frequency divider, comprising:
      • a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal;
      • a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater; and
      • a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.
    • Clause 16. The divide-by-N frequency divider of clause 15, wherein N equals three, and wherein the second frequency is ⅓ the first frequency.
    • Clause 17. The divide-by-N frequency divider of clause 16, wherein the plurality of N latches comprises a first latch, a second latch, and a third latch, and wherein the plurality of 2N logic gates comprises:
      • a first logic gate having its output terminal coupled to a reset terminal of the first latch;
      • a second logic gate having its output terminal coupled to a set terminal of the first latch;
      • a third logic gate having its output terminal coupled to a reset terminal of the second latch;
      • a fourth logic gate having its output terminal coupled to a set terminal of the second latch;
      • a fifth logic gate having its output terminal coupled to a reset terminal of the third latch; and
      • a sixth logic gate having its output terminal coupled to a set terminal of the third latch.
    • Clause 18. The divide-by-N frequency divider of clause 17, wherein each logic gate comprises a 3-input NOR gate.
    • Clause 19. The divide-by-N frequency divider of clause 18, wherein the corresponding pair of overlapping clock signals of the first latch comprises a second overlapping clock signal and a fifth overlapping clock signal, the corresponding pair of overlapping clock signals of the second latch comprises a second overlapping clock signal and a fifth overlapping clock signal, and the corresponding pair of overlapping clock signals of the third logic gate comprises a first overlapping clock signal and a fourth overlapping clock signal.
    • Clause 20. The divide-by-N frequency divider of clause 15, wherein N equals four, and wherein the second frequency is ¼ the first frequency.
    • Clause 21. The divide-by-N frequency divider of clause 20, wherein the plurality of N latches comprises a first latch, a second latch, a fourth latch and a third latch, and wherein the plurality of 2N logic gates comprises
      • a first logic gate having its output terminal coupled to a reset terminal of the first latch;
      • a second logic gate having its output terminal coupled to a set terminal of the first latch;
      • a third logic gate having its output terminal coupled to a reset terminal of the second latch;
      • a fourth logic gate having its output terminal coupled to a set terminal of the second latch;
      • a fifth logic gate having its output terminal coupled to a reset terminal of the third latch;
      • a sixth logic gate having its output terminal coupled to a set terminal of the third latch;
      • a seventh logic gate having its output terminal coupled to a reset terminal of the fourth latch; and
      • an eighth logic gate having its output terminal coupled to a set terminal of the fourth latch.
    • Clause 22. The frequency divider of clause 21, wherein each logic gate comprises a 3-input NOR gate.
    • Clause 23. A method of frequency division, comprising:
      • dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%; and
      • processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
    • Clause 24. The method of clause 23, wherein processing each pair of the overlapping clock signals comprises a NOR of the pair of the overlapping clock signals with the input clock signal to output a corresponding non-overlapping clock signal from the plurality of 2N non-overlapping clock signals.
    • Clause 25. The method of clause 23, wherein the input clock signal is a differential input clock signal including a positive input clock signal and a negative output clock signal, and wherein the processing of each pair of the overlapping clock signals comprises a NOR of the overlapping clock signal with one of the positive input clock signal and the negative output signal.
    • Clause 26. The method of clause 24, wherein the overlapping clock signals in each pair of overlapping clock signals have a delay with respect to each other of (N+2) times one-half of a period of the input clock signal.
It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.

Claims (26)

What is claimed is:
1. A frequency divider, comprising:
a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises:
a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and
wherein an output terminal of the 2-input logic gate in each preceding stage in the series is coupled to a first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein an output terminal of the 2-input logic gate in the Nth stage is coupled to a first input terminal of the 3-input logic gate in the first stage.
2. The frequency divider of claim 1, wherein the 2-input logic gates are cross-coupled to form N latches.
3. The frequency divider of claim 1, wherein each three-input logic gate has a second input terminal coupled to a clock source.
4. The frequency divider of claim 3, wherein each stage's three-input logic gate has a third input terminal coupled to the output terminal of the 2-input terminal in another one of the stages.
5. A frequency divider, comprising:
a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal;
a plurality of N latches, wherein N is a plural positive integer greater than two;
a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals; and
a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the second output terminal, a corresponding non-overlapping clock signal from a second plurality of N non-overlapping clock signals.
6. The frequency divider of claim 5, wherein each latch in the plurality of N latches comprises a cross-coupled pair of logic gates.
7. The frequency divider of claim 6, wherein the cross-coupled pair of logic gates in each latch in the plurality of N latches comprises a cross-coupled pair of NOR gates.
8. The frequency divider of claim 5, wherein the plurality of N first logic gates comprises a first plurality of N 3-input NOR gates.
9. The frequency divider of claim 5, wherein the plurality of N second logic gates comprises a second plurality of N 3-input NOR gates.
10. The frequency divider of claim 8, wherein the first plurality of N 3-input NOR gates is arranged from a first 3-input NOR gate to an Nth 3-input NOR gate and the first plurality of N non-overlapping clock signal is arranged from a first non-overlapping clock signal to an Nth non-overlapping clock signal, and wherein the first 3-input NOR gate is configured to output the first non-overlapping clock signal, a second 3-input NOR gate is configured to output a second non-overlapping clock signal, and so on such that the Nth 3-input NOR gate is configured to output the Nth non-overlapping clock signal.
11. The frequency divider of claim 9, wherein the second plurality of N 3-input NOR gates is arranged from an (N+1)th 3-input NOR gate to an 2Nth 3-input NOR gate and the second plurality of N non-overlapping clock signal is arranged from an (N+1)th non-overlapping clock signal to a 2Nth non-overlapping clock signal, and wherein the (N+1)th 3-input NOR gate is configured to output the (N+1)th non-overlapping clock signal, an (N+2)th 3-input NOR gate is configured to output an (N+2)th non-overlapping clock signal, and so on such that the 2Nth 3-input NOR gate is configured to output the 2Nth non-overlapping clock signal.
12. The frequency divider of claim 5, wherein N is an even integer greater than two.
13. The frequency divider of claim 5, wherein N is an odd integer greater than two.
14. The frequency divider of claim 5, wherein the frequency divider is incorporated into a cellular telephone.
15. A divide-by-N frequency divider, comprising:
a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal;
a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth of the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater; and
a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.
16. The divide-by-N frequency divider of claim 15, wherein N equals three, and wherein the second frequency is ⅓ the first frequency.
17. The divide-by-N frequency divider of claim 16, wherein the plurality of N latches comprises a first latch, a second latch, and a third latch, and wherein the plurality of 2N logic gates comprises:
a first logic gate having its output terminal coupled to a reset terminal of the first latch;
a second logic gate having its output terminal coupled to a set terminal of the first latch;
a third logic gate having its output terminal coupled to a reset terminal of the second latch;
a fourth logic gate having its output terminal coupled to a set terminal of the second latch;
a fifth logic gate having its output terminal coupled to a reset terminal of the third latch; and
a sixth logic gate having its output terminal coupled to a set terminal of the third latch.
18. The divide-by-N frequency divider of claim 17, wherein each logic gate comprises a 3-input NOR gate.
19. The divide-by-N frequency divider of claim 18, wherein the corresponding pair of overlapping clock signals of the first latch comprises a second overlapping clock signal and a fifth overlapping clock signal, the corresponding pair of overlapping clock signals of the second latch comprises a third overlapping clock signal and a sixth overlapping clock signal, and the corresponding pair of overlapping clock signals of the third logic gate comprises a first overlapping clock signal and a fourth overlapping clock signal.
20. The divide-by-N frequency divider of claim 15, wherein N equals four, and wherein the second frequency is ¼ the first frequency.
21. The divide-by-N frequency divider of claim 20, wherein the plurality of N latches comprises a first latch, a second latch, a fourth latch and a third latch, and wherein the plurality of 2N logic gates comprises
a first logic gate having its output terminal coupled to a reset terminal of the first latch;
a second logic gate having its output terminal coupled to a set terminal of the first latch;
a third logic gate having its output terminal coupled to a reset terminal of the second latch;
a fourth logic gate having its output terminal coupled to a set terminal of the second latch;
a fifth logic gate having its output terminal coupled to a reset terminal of the third latch;
a sixth logic gate having its output terminal coupled to a set terminal of the third latch;
a seventh logic gate having its output terminal coupled to a reset terminal of the fourth latch; and
an eighth logic gate having its output terminal coupled to a set terminal of the fourth latch.
22. The frequency divider of claim 21, wherein each logic gate comprises a 3-input NOR gate.
23. A method of frequency division, comprising:
dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%; and
processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
24. The method of claim 23, wherein processing each pair of the overlapping clock signals comprises a NOR of the pair of the overlapping clock signals with the input clock signal to output a corresponding non-overlapping clock signal from the plurality of 2N non-overlapping clock signals.
25. The method of claim 23, wherein the input clock signal is a differential input clock signal including a positive input clock signal and a negative output clock signal, and wherein the processing of each pair of the overlapping clock signals comprises a NOR of the overlapping clock signal with one of the positive input clock signal and the negative output signal.
26. The method of claim 24, wherein the overlapping clock signals in each pair of overlapping clock signals have a delay with respect to each other of (N+2) times one-half of a period of the input clock signal.
US17/899,564 2022-08-30 2022-08-30 Frequency divider for non-overlapping clock signals Active US11923849B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/899,564 US11923849B1 (en) 2022-08-30 2022-08-30 Frequency divider for non-overlapping clock signals
PCT/US2023/030977 WO2024049691A2 (en) 2022-08-30 2023-08-23 Frequency divider for non-overlapping clock signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17/899,564 US11923849B1 (en) 2022-08-30 2022-08-30 Frequency divider for non-overlapping clock signals

Publications (2)

Publication Number Publication Date
US20240072807A1 US20240072807A1 (en) 2024-02-29
US11923849B1 true US11923849B1 (en) 2024-03-05

Family

ID=88093702

Family Applications (1)

Application Number Title Priority Date Filing Date
US17/899,564 Active US11923849B1 (en) 2022-08-30 2022-08-30 Frequency divider for non-overlapping clock signals

Country Status (2)

Country Link
US (1) US11923849B1 (en)
WO (1) WO2024049691A2 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394769A (en) * 1981-06-15 1983-07-19 Hughes Aircraft Company Dual modulus counter having non-inverting feedback
US5528181A (en) 1994-11-02 1996-06-18 Advanced Micro Devices, Inc. Hazard-free divider circuit
US5633607A (en) * 1995-04-28 1997-05-27 Mosaid Technologies Incorporated Edge triggered set-reset flip-flop (SRFF)
US20020057117A1 (en) 2000-11-14 2002-05-16 Ka Lun Choi Frequency dividing circuit
US20020075989A1 (en) * 2000-12-19 2002-06-20 Samsung Electronics Co., Ltd. High-speed counter with sequential binary count order and method thereof
US20100201409A1 (en) 2009-02-12 2010-08-12 Sanyo Electric Co., Ltd. Frequency Divider Circuit
US20110025381A1 (en) * 2008-07-09 2011-02-03 Panasonic Corporation Multi-phase clock divider circuit
US10193539B1 (en) * 2017-08-21 2019-01-29 SK Hynix Inc. High speed data synchronization
US20190173476A1 (en) * 2017-12-05 2019-06-06 Integrated Device Technology, Inc. Modulus divider with deterministic phase alignment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4254793A4 (en) * 2020-12-25 2024-02-21 Huawei Technologies Co., Ltd. Multi-phase clock generation circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394769A (en) * 1981-06-15 1983-07-19 Hughes Aircraft Company Dual modulus counter having non-inverting feedback
US5528181A (en) 1994-11-02 1996-06-18 Advanced Micro Devices, Inc. Hazard-free divider circuit
US5633607A (en) * 1995-04-28 1997-05-27 Mosaid Technologies Incorporated Edge triggered set-reset flip-flop (SRFF)
US20020057117A1 (en) 2000-11-14 2002-05-16 Ka Lun Choi Frequency dividing circuit
US20020075989A1 (en) * 2000-12-19 2002-06-20 Samsung Electronics Co., Ltd. High-speed counter with sequential binary count order and method thereof
US20110025381A1 (en) * 2008-07-09 2011-02-03 Panasonic Corporation Multi-phase clock divider circuit
US20100201409A1 (en) 2009-02-12 2010-08-12 Sanyo Electric Co., Ltd. Frequency Divider Circuit
US10193539B1 (en) * 2017-08-21 2019-01-29 SK Hynix Inc. High speed data synchronization
US20190173476A1 (en) * 2017-12-05 2019-06-06 Integrated Device Technology, Inc. Modulus divider with deterministic phase alignment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Partial International Search Report—PCT/US2023/030977—ISA/EPO—dated Dec. 19, 2023.
Thijssen B J., et al., "2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter", IEEE Journal of Solid-State Circuits, vol. 56, Issue: 7, Jul. 2021, 11 Pages, doi: 10.1109/JSSC.2020.3031493.

Also Published As

Publication number Publication date
WO2024049691A3 (en) 2024-05-10
WO2024049691A2 (en) 2024-03-07
US20240072807A1 (en) 2024-02-29

Similar Documents

Publication Publication Date Title
US7005900B1 (en) Counter-based clock doubler circuits and methods with optional duty cycle correction and offset
US8519742B2 (en) Latch structure, frequency divider, and methods for operating same
US4935944A (en) Frequency divider circuit with integer and non-integer divisors
EP1776764B1 (en) Frequency divider
CN101908883B (en) Programmable fractional frequency divider
US4991187A (en) High speed prescaler
US8471607B1 (en) High-speed frequency divider architecture
US6906571B1 (en) Counter-based phased clock generator circuits and methods
CN107968646B (en) Programmable clock divider
US10530375B1 (en) High speed frequency divider
JP4977717B2 (en) Frequency divider circuit
US6404839B1 (en) Selectable clock divider circuit with a 50% duty cycle clock
US11923849B1 (en) Frequency divider for non-overlapping clock signals
US9590637B1 (en) High-speed programmable frequency divider with 50% output duty cycle
CN108777575B (en) Frequency divider
US6108393A (en) Enhanced prescaler phase interface
US7049864B2 (en) Apparatus and method for high frequency state machine divider with low power consumption
Geng et al. A Novel Design of a 47GHz Programmable Frequency Divider based on RLTSPC logic in 65nm CMOS
US4815114A (en) Elementary binary counter, synchronous binary counter and frequency divider in which said elementary counter is employed
US5987089A (en) Programmable divider with controlled duty cycle
CN117176139B (en) Frequency divider construction method and frequency divider with frequency division ratio of 2 plus or minus 1 to power N
CN118157659B (en) Odd-number frequency dividing circuit
CN110545100A (en) Low-power-consumption traveling wave frequency division circuit
JPH0683066B2 (en) Counter circuit
CN115632656A (en) Phase-locked loop capable of outputting multiple phases and multiple frequencies

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: QUALCOMM INCORPORATED, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NALLAM, NAGARJUNA;REEL/FRAME:061520/0770

Effective date: 20220911

STCF Information on status: patent grant

Free format text: PATENTED CASE