US11855212B2 - FDSOI device structure and preparation method thereof - Google Patents

FDSOI device structure and preparation method thereof Download PDF

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US11855212B2
US11855212B2 US18/086,326 US202218086326A US11855212B2 US 11855212 B2 US11855212 B2 US 11855212B2 US 202218086326 A US202218086326 A US 202218086326A US 11855212 B2 US11855212 B2 US 11855212B2
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sige
range
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amorphous silicon
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Zhonghua Li
Runling Li
Nan Li
Jianghua LENG
Tianpeng Guan
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Shanghai Huali Integrated Circuit Corp
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H01L29/7848—
    • H10P90/1906—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/402—Amorphous materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H10P90/1908—
    • H10W10/181—

Definitions

  • the present application relates to the field of semiconductor technologies, in particular to an FDSOI device structure and a fabrication method thereof.
  • a silicon channel-metal gate process is widely used in fabricating a 22 nm node Fully Depleted Silicon-on-Insulator (FDSOI) PMOS, where is the devices have silicon channels and high-k metal gates.
  • FDSOI Fully Depleted Silicon-on-Insulator
  • the stress in the channels needs to be further increased. Therefore, in order to in the channels, the silicon channels have been replaced with SiGe channels to increase the stress. Further metal gates have also been deployed.
  • the combined SiGe channel and metal gate process has significantly increased the compressive stress in the channels, thereby hole mobility has been improved significantly.
  • germanium (Ge) atoms in the SiGe channel of the existing technology may diffuse into the gate dielectric, thereby reducing reliability and performance of the devices.
  • the present application provides an FDSOI device structure and a preparation method thereof.
  • the present application provides an FDSOI device structure, comprising at least:
  • a silicon substrate a buried oxide layer disposed on the silicon substrate; a SiGe channel located on the buried oxide layer, wherein the thickness of the SiGe channel is in a range of 60-100 ⁇ ; a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer and a sidewall attached to sides of the metal gate; and a source-drain region disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source-drain region is a raised SiGe layer.
  • the thickness of the buried oxide layer is in a range of 100-300 ⁇ .
  • the thickness of the nitrogen passivation layer is in a range of 2-20 ⁇ .
  • the metal gate comprises a first stack structure and a second stack structure disposed on the first stack structure;
  • the first stack structure consists of a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially arranged from low to upper end;
  • the second stack structure comprises of a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer that are sequentially stacked from low to upper end.
  • the thickness of the gate oxide layer structure is in a range of 6-15 ⁇ .
  • the thickness of the high-k dielectric layer structure is in a range of 15-30 ⁇ .
  • the thickness of the TiN layer structure is in a range of 15-30 ⁇ .
  • the sidewalks are a SiCN structure or SiOCN structure.
  • the present application further provides a method for preparing FDSOI, the method comprising at least the following steps:
  • step 1 providing a silicon substrate, wherein a buried oxide layer is disposed on the silicon substrate, and an SOI layer is disposed on the buried oxide layer;
  • step 2 forming a SiGe layer on the SOI layer by means of epitaxial deposition
  • step 3 oxidizing the SiGe layer by means of high-temperature oxidation, so that Ge in the SiGe layer 04 diffuses into the SOI layer to form a SiGe channel with a thickness in a range of 60-100 ⁇ , wherein the SiGe layer is formed into a SiO 2 layer;
  • step 4 removing the SiO 2 layer
  • step 5 passivating an upper surface of the SiGe channel to form a nitrogen passivation layer
  • step 6 sequentially depositing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer;
  • step 7 forming an amorphous silicon layer on the TiN layer, depositing a hard mask layer on the amorphous silicon layer, then defining a gate morphology by means of photolithography, sequentially etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure consisting of a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially stacked from bottom to top and form an amorphous silicon layer structure disposed on the first stack structure and a hard mask layer structure disposed on the amorphous silicon layer structure, and then forming sidewalls of inner spacer and outer hard mask on sides of the first stack layer and the amorphous silicon layer structure;
  • step 8 epitaxially growing a source-drain region on the nitrogen passivation layer at both sides of the amorphous silicon layer structure, wherein the source-drain region is a raised SiGe;
  • step 9 removing the hard mask layer structure and the amorphous silicon layer structure, and forming a groove in the sidewall of spacer on the first stack layer;
  • step 10 sequentially depositing a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer in the groove such that the groove is filled, to form a second stack structure, wherein the first and second stack structures and the sidewall form a metal gate;
  • step 11 planarizing the aluminum layer, and then performing metal interconnection.
  • step 1 an native oxide is formed on the surface of the SOI layer; and forming the SiGe layer by means of epitaxial deposition in step 2 comprises steps of: first removing the native oxide on the surface of the SOI layer using at least one of HF, SiCoNi, HCL, and H 2 , and then growing the SiGe layer with a Ge concentration of 20%-60% in situ on the SOI layer, wherein the thickness of the SiGe layer is in a range of 50-400 ⁇ .
  • a reaction temperature of the high-temperature oxidation in step 3 is 1000-2000° C.
  • an oxidation mode of the high-temperature oxidation is alternately performing oxidation and annealing, wherein an annealing process is carried out in a nitrogen condition.
  • a method for removing the SiO 2 layer in step 4 comprises removing the SiO 2 layer by means of washing with HF or removing the SiO 2 layer by means of dry etching.
  • step 4 after the SiO 2 layer 05 is removed, the upper surface of the SiGe channel is exposed, and the upper surface of the SiGe channel is oxidized to form an oxide; and in step 5, before the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer, the oxide on the upper surface of the SiGe channel is first removed.
  • step 5 before the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer, the oxide on the upper surface of the SiGe channel is removed using at least one of HF, SiCoNi, HCl, and H 2 .
  • a method for passivating the upper surface of the SiGe channel to form the nitrogen passivation layer in step 5 comprises steps of: passivating the upper surface of the SiGe channel using nitrogen or NH 3 plasma, and then performing annealing, so as to form the nitrogen passivation layer.
  • the mode of depositing the gate oxide layer on the nitrogen passivation layer in step 6 is in-situ steam generation, and the thickness of the deposited gate oxide layer is 6-15 ⁇ ; the deposited high-k dielectric layer is HfO 2 or HfLaO 2 , and the thickness of the high-k dielectric layer is 15-30 ⁇ ; and the thickness of the deposited TiN layer is 15-30 ⁇ .
  • the concentration of Ge in the raised SiGe epitaxially grown in step 8 is 20%-50%, and the raised SiGe contains boron at a concentration in a range of 1*10 19 -1*10 21 cm ⁇ 3 ; and the thickness of the raised SiGe is in a range of 200-400 ⁇ .
  • the FDSOI device structure and preparation method thereof of the present application have the following beneficial effects: in a manufacturing process of an FDSOI device of the present application, a stack structure of a SiGe layer and a nitrogen passivation layer is used as a channel, avoiding the low stress of a silicon channel in the conventional process and the diffusion of Ge in a SiGe channel to a gate dielectric in the conventional process, and thereby improving the reliability and performance of the device.
  • FIG. 1 is a schematic diagram of a FDSOI device substrate, including a silicon substrate, a buried oxide layer, and an SOI layer disposed on the silicon substrate according to the present application.
  • FIG. 2 is a schematic diagram of the structure after a SiGe layer is disposed on the SOI layer, according to the present application.
  • FIG. 3 is a schematic diagram of the structure after disposing a SiGe channel and a SiO 2 layer, according to the present application.
  • FIG. 4 is a schematic diagram of the structure after removing the SiO 2 layer from the SiGe channel according to the present application.
  • FIG. 5 is a schematic structural diagram of forming a nitrogen passivation layer on the SiGe channel according to the present application.
  • FIG. 6 is a schematic diagram of the structure after disposing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer according to the present application.
  • FIG. 7 is a schematic structural diagram of forming a first stack structure, an amorphous silicon layer structure, and a hard mask layer structure one the nitrogen passivation layer according to the present application.
  • FIG. 8 is a schematic diagram of a structure after forming a source and a drain regions, sidewalls of inner spacer and an outer hard mask on sides of the amorphous silicon layer structure according to the present application.
  • FIG. 9 is a schematic diagram of the structure after removing the amorphous silicon layer structure to form a groove according to the present application.
  • FIG. 10 is a schematic diagram of an FDSOI device structure according to an embodiment of the present application.
  • FIGS. 1 - 10 Please refer to FIGS. 1 - 10 .
  • the figures provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, so the figures only show the components related to the present application, but are not drawn according to the number, shape and size of the components in actual implementations.
  • the pattern, number, and ratio of each component in actual implementations can be changed randomly, and the component layout pattern may be more complicated.
  • the present application provides an FDSOI device structure, which includes at least: a silicon substrate; a buried oxide layer disclosed on the surface of the silicon substrate; a SiGe channel disclosed on the buried oxide layer, wherein the thickness of the SiGe channel is in the range of 60-100 ⁇ ; a nitrogen passivation layer disclosed on the SiGe channel layer; a metal gate disclosed on the nitrogen passivation layer, and sidewalls attached to both sides of the metal gate; and a source region and a drain region disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source region and drain region are in a raised SiGe layer.
  • the FDSOI device structure in this embodiment includes: a silicon substrate 01 ; a buried oxide layer 02 disposed on the silicon substrate 01 , wherein in an example, the thickness of the buried oxide layer is in the range of 100-300 ⁇ ; a SiGe channel 06 disposed on the buried oxide layer 02 , wherein the thickness of the SiGe channel is in the range of 60-100 ⁇ ; a nitrogen passivation layer 07 disposed on the SiGe channel layer 06 ; a metal gate disposed on the nitrogen passivation layer 07 and sidewalls 13 attached to the walls of both sides of the metal gate, the metal gate includes a first stack structure of layers, and a second stack structure 15 disposed on the first stack structure.
  • the first stack structure which includes a gate oxide layer structure 08 ′, a high-k dielectric layer structure 09 ′, and a TiN layer structure 10 ′ that are sequentially stacked from low to upper end.
  • the second stack structure includes a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer that are sequentially stacked from low to upper end.
  • the thickness of the gate oxide layer structure is in the range of 6-15 ⁇ and the thickness of the high-k dielectric layer structure is in the range of 15-30 ⁇ .
  • the thickness of the TiN layer structure is in the range of 15-30 ⁇ ; and a source region and a drain region 14 disposed on the nitrogen passivation layer 07 at both sides of the metal gate, wherein the source and drain regions are built a raised SiGe layer.
  • the sidewalls of the first and second stacks include either a SiCN structure or a SiOCN structure.
  • the present application further provides a method for fabricating the FDSOI device, and the method includes at least the following steps:
  • step 1 providing a silicon substrate, disposing a buried oxide layer on the silicon substrate, and disposing an SOI layer on the buried oxide layer;
  • step 2 forming a SiGe layer on the SOI layer by means of epitaxial deposition, and the SOI is typically composed of a silicon layer on an SiO 2 layer;
  • step 3 oxidizing the SiGe layer by means of high-temperature diffusion, so that Ge elements in the SiGe layer are driven into the SOI layer to form a SiGe channel with a thickness in the range of 60-100 ⁇ , and the SiGe layer replaces the silicon layer remaining on the SiO 2 layer;
  • step 4 removing the SiO 2 layer
  • step 5 passivating an upper surface of the SiGe channel to form a nitrogen passivation layer
  • step 6 sequentially depositing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer;
  • step 7 forming an amorphous silicon layer on the TiN layer, depositing a hard mask layer on the amorphous silicon layer, then defining a gate morphology by means of photolithography, sequentially etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure which includes a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially stacked from low to upper end, and further forming an amorphous silicon layer structure disposed on the first stack structure and a hard mask layer structure disposed on the amorphous silicon layer structure.
  • step 7 includes, forming sidewalls which become inner spacers and outer hard masks on the sides of the first stack layer and the amorphous silicon layer structure;
  • step 8 epitaxially growing a source region and a drain region on the nitrogen passivation layer at both sides of the amorphous silicon layer structure, wherein the source and drain regions are built in a raised SiGe layer;
  • step 9 removing the hard mask layer structure and the amorphous silicon layer structure, and forming a groove in the sidewall of spacer on the first stack layer;
  • step 10 sequentially depositing a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer to fill in the groove, these four layers form a second stack structure 15 , wherein the first stack structure 08 ′, 09 ′, 10 ′, the second stack structure 15 and the sidewalls 13 form the metal gate; and
  • step 11 planarizing the aluminum layer, followed by interconnecting metal layers.
  • the method for fabricating a FDSOI device in this embodiment includes the following steps in more details.
  • Step 1 A silicon substrate 01 is provided, wherein a buried oxide layer 02 is disposed on the silicon substrate 01 , and a silicon-on-insulator (SOI) layer 03 is disposed on the buried oxide layer 02 .
  • SOI silicon-on-insulator
  • Step 2 A SiGe layer 04 is formed on the SOI layer 03 by means of epitaxial deposition, referring to FIG. 2 , which is a schematic diagram of the structure after the SiGe layer is disposed on the SOI layer according to the present application.
  • An native oxide layer is formed on the surface of the SOI layer in step 1, because an upper surface of the SOI layer is exposed to the air, therefore growing an native oxide layer.
  • step 2 forming the SiGe layer 04 includes steps of: first removing the native oxide on the surface of the SOI layer using at least one of hydrogen fluoride (HF), SiCoNiTM, HCL, and H 2 , and then growing the SiGe layer 04 in situ with a Ge concentration in a range of 20%-60% on the SOI layer, wherein the thickness of the SiGe layer 04 is in a range of 50-400 ⁇ .
  • HF hydrogen fluoride
  • Step 3 The SiGe layer 04 is oxidized by means of high-temperature diffusion, in which Ge atoms in the SiGe layer 04 are driven into the SOI layer to form a SiGe channel 06 with a thickness in the range of 60-100 ⁇ , in this process the Ge layer has turned into a SiGe layer 04 over a SiO 2 layer 05 , referring to FIG. 3 , a schematic diagram of a structure after forming the SiGe channel and the SiO 2 layer thereon according to the present application.
  • a reaction temperature of the high-temperature oxidation in step 3 is in a range of 1000-2000° C.
  • the mode of the high-temperature oxidation is alternately performing oxidation and annealing, wherein the annealing process is carried out in a nitrogen environment. That is to say, step 3 is performed in a high-temperature environment in a range of 1000-2000° C. to oxidize the SiGe layer 04 .
  • the Ge element in the SiGe layer 04 undergoes the alternating high temperature oxidation-annealing cycles for a number of times, as the result, Ge diffuses into the silicon-on-insulator (SOI) layer 03 beneath the SiGe layer 04 , thereby forming the SiGe channel 06 .
  • SOI silicon-on-insulator
  • Step 4 The SiO 2 layer 05 is removed, shown as in FIG. 4 , which is a schematic diagram of the structure after removing the SiO 2 layer from the SiGe channel according to the present application.
  • a method for removing the SiO 2 layer in step 4 includes removing the SiO 2 layer 05 by wet etching in HF or removing the SiO 2 layer by dry etching.
  • Step 5 Referring to FIG. 5 , passivating the upper surface of the SiGe channel with a nitrogen passivation layer
  • FIG. 5 shows the structure after the nitrogen passivation layer has disposed on the SiGe channel.
  • the oxide on the upper surface of the SiGe channel 06 is first removed using at least one of HF, SiCoNiTM, HCL, and H 2 , then the upper surface of the SiGe channel 06 is passivated to form the nitrogen passivation layer 07 .
  • step 4 after the SiO 2 layer 05 is removed, the upper surface of the SiGe channel 06 is exposed, and the upper surface of the SiGe channel 06 is oxidized to form an oxide; and in step 5, the oxide on the upper surface of the SiGe channel 06 is first removed, then the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer.
  • a method for passivating the upper surface of the SiGe channel to form the nitrogen passivation layer in step 5 includes steps of: passivating the upper surface of the SiGe channel using nitrogen or NH 3 plasma, and then performing annealing, so as to form the nitrogen passivation layer. So in this embodiment, after the oxide on the upper surface of the SiGe channel 06 is removed, then the upper surface of the SiGe channel is passivated using nitrogen or NH 3 plasma, to form the nitrogen passivation layer 07 .
  • Step 6 Agate oxide layer, a high-k dielectric layer, and a TiN layer are sequentially deposited on the nitrogen passivation layer, referring to FIG. 6 , which is a schematic diagram of the structure after the gate oxide layer, the high-k dielectric layer, and the TiN layer are disposed on the nitrogen passivation layer according to the present application.
  • the gate oxide layer 08 , the high-k dielectric layer 09 , and the TiN layer 10 are sequentially deposited on the nitrogen passivation layer 07 .
  • the technique of depositing the gate oxide layer 08 on the nitrogen passivation layer 07 in step 6 is in-situ steam growth, and the thickness of the deposited gate oxide layer 08 is in a range of 6-15 ⁇ ; the deposited high-k dielectric layer 09 is HfO 2 or HfLaO 2 , and the thickness of the high-k dielectric layer 09 is in a range of 15-30 ⁇ ; and the thickness of the deposited TiN layer 10 is in a range of 15-30 ⁇ .
  • Step 7 a schematic diagram of the structure after forming a first stack structure, an amorphous silicon layer structure, and a hard mask layer structure on the nitrogen passivation layer according to the present application.
  • An amorphous silicon layer is formed on the TiN layer, a hard mask layer is deposited on the amorphous silicon layer, a gate morphology is defined by a photolithography process, followed by sequential etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure.
  • the first stack structure includes a gate oxide layer structure 08 ′, a high-k dielectric layer structure 09 ′, and a TiN layer structure 10 ′ that are sequentially stacked from low to upper end.
  • An amorphous silicon layer structure 11 is disposed on the first stack structure, a hard mask layer structure 12 is disposed on the amorphous silicon layer structure 11 , and then sidewalls are formed on the walls of the sides of the first stack layer and the amorphous silicon layer structure 11 .
  • FIG. 8 which is a schematic diagram of the structure after forming a source and a drain regions and sidewalls on the sides of the amorphous silicon layer structure according to the present application.
  • the sidewalls 13 are attached to the sides of the first stack layer and the amorphous silicon layer structure 11 .
  • Step 8 A source and a drain regions are epitaxially grown on the nitrogen passivation layer at both sides of the first stack layer and the amorphous silicon layer structure, wherein the source and drain regions are built in a raised SiGe layer, referring to FIG. 8 , the source and drain regions 14 are built in a raised SiGe layer, the first stack layer and the amorphous silicon layer structure will be part of the metal gate, and the source and drain regions will be formed on both sides of the metal gate.
  • Step 9 The hard mask layer structure and the amorphous silicon layer structure are removed, and a groove is formed on the first stack layer and in between the sidewalls, referring to FIG. 9 , which is a schematic diagram of the structure after removing the amorphous silicon layer structure to form the groove according to the present application.
  • the amorphous silicon layer structure on the first stack layer is removed, and the groove M is formed.
  • the Ge concentration in the epitaxially grown raised SiGe layer in step 8 of this embodiment is in the range of 20%-50%, and the raised SiGe layer contains boron at a concentration in the range of 1*10 19 -1*10 21 cm ⁇ 3 ; and the thickness of the raised SiGe is in a range of 200-400 ⁇ .
  • Step 10 A TaN layer, a TiN layer, a TiAl layer, and an aluminum layer are sequentially deposited to fill the groove, and to form a second stack structure, wherein the first and second stack structures and the sidewalls form a metal gate, referring to FIG. 10 , which is schematic diagram of the structure after the second stack structure filled the groove.
  • the second stack structure includes a TaN layer disposed on the first stack layer, a TiN layer disposed on the TaN layer, a TiAl layer disposed on the TiN layer, and an aluminum layer disposed on the TiAl layer.
  • the metal gate in the present application includes the first stack layer, the second stack structure, and the sidewalls.
  • Step 11 The aluminum layer is planarized, followed by forming metal interconnection.
  • a FDSOI device what has a channel of a stack structure of a SiGe layer and a nitrogen passivation layer. This channel avoids the low stress of a silicon channel in the conventional process. In addition, this structure prevents the diffusion of Ge in the SiGe channel into the gate dielectric in the conventional process. Therefore, reliability and performance of the device are improved.
  • the present invention can effectively overcome these issues in the current technology, thus deserves a high value in industrial utilization.

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Abstract

FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is the divisional application of U.S. patent application Ser. No. 17/107,375 and claims the priority to U.S. Patent Application Ser. No. 17/107,375, filed Nov. 30, 2020, which claims the priority of Chinese patent application No. CN 202010992679.2, filed on Sep. 21, 2020 at CNIPA, and both entitled “FDSOI DEVICE STRUCTURE AND PREPARATION METHOD THEREOF”, the disclosure of which is incorporated herein by reference in entirety.
TECHNICAL FIELD
The present application relates to the field of semiconductor technologies, in particular to an FDSOI device structure and a fabrication method thereof.
BACKGROUND
At present, a silicon channel-metal gate process is widely used in fabricating a 22 nm node Fully Depleted Silicon-on-Insulator (FDSOI) PMOS, where is the devices have silicon channels and high-k metal gates. Being silicon channels, the stress in the channels needs to be further increased. Therefore, in order to in the channels, the silicon channels have been replaced with SiGe channels to increase the stress. Further metal gates have also been deployed. The combined SiGe channel and metal gate process has significantly increased the compressive stress in the channels, thereby hole mobility has been improved significantly.
However, germanium (Ge) atoms in the SiGe channel of the existing technology may diffuse into the gate dielectric, thereby reducing reliability and performance of the devices.
Therefore, it is necessary to provide a new device structure and fabrication method to solve the above problem.
BRIEF SUMMARY
In view of the above-described defects in the current devices, the present application provides an FDSOI device structure and a preparation method thereof.
The present application provides an FDSOI device structure, comprising at least:
a silicon substrate; a buried oxide layer disposed on the silicon substrate; a SiGe channel located on the buried oxide layer, wherein the thickness of the SiGe channel is in a range of 60-100 Å; a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer and a sidewall attached to sides of the metal gate; and a source-drain region disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source-drain region is a raised SiGe layer.
In some examples, the thickness of the buried oxide layer is in a range of 100-300 Å.
In some examples, the thickness of the nitrogen passivation layer is in a range of 2-20 Å.
In some examples, the metal gate comprises a first stack structure and a second stack structure disposed on the first stack structure; the first stack structure consists of a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially arranged from low to upper end; and the second stack structure comprises of a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer that are sequentially stacked from low to upper end.
In some examples, the thickness of the gate oxide layer structure is in a range of 6-15 Å.
In some examples, the thickness of the high-k dielectric layer structure is in a range of 15-30 Å.
In some examples, the thickness of the TiN layer structure is in a range of 15-30 Å.
In some examples, the sidewalks are a SiCN structure or SiOCN structure.
The present application further provides a method for preparing FDSOI, the method comprising at least the following steps:
step 1: providing a silicon substrate, wherein a buried oxide layer is disposed on the silicon substrate, and an SOI layer is disposed on the buried oxide layer;
step 2: forming a SiGe layer on the SOI layer by means of epitaxial deposition;
step 3: oxidizing the SiGe layer by means of high-temperature oxidation, so that Ge in the SiGe layer 04 diffuses into the SOI layer to form a SiGe channel with a thickness in a range of 60-100 Å, wherein the SiGe layer is formed into a SiO2 layer;
step 4: removing the SiO2 layer;
step 5: passivating an upper surface of the SiGe channel to form a nitrogen passivation layer;
step 6: sequentially depositing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer;
step 7: forming an amorphous silicon layer on the TiN layer, depositing a hard mask layer on the amorphous silicon layer, then defining a gate morphology by means of photolithography, sequentially etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure consisting of a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially stacked from bottom to top and form an amorphous silicon layer structure disposed on the first stack structure and a hard mask layer structure disposed on the amorphous silicon layer structure, and then forming sidewalls of inner spacer and outer hard mask on sides of the first stack layer and the amorphous silicon layer structure;
step 8: epitaxially growing a source-drain region on the nitrogen passivation layer at both sides of the amorphous silicon layer structure, wherein the source-drain region is a raised SiGe;
step 9: removing the hard mask layer structure and the amorphous silicon layer structure, and forming a groove in the sidewall of spacer on the first stack layer;
step 10: sequentially depositing a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer in the groove such that the groove is filled, to form a second stack structure, wherein the first and second stack structures and the sidewall form a metal gate; and
step 11: planarizing the aluminum layer, and then performing metal interconnection.
In some examples, in step 1, an native oxide is formed on the surface of the SOI layer; and forming the SiGe layer by means of epitaxial deposition in step 2 comprises steps of: first removing the native oxide on the surface of the SOI layer using at least one of HF, SiCoNi, HCL, and H2, and then growing the SiGe layer with a Ge concentration of 20%-60% in situ on the SOI layer, wherein the thickness of the SiGe layer is in a range of 50-400 Å.
In some examples, a reaction temperature of the high-temperature oxidation in step 3 is 1000-2000° C., and an oxidation mode of the high-temperature oxidation is alternately performing oxidation and annealing, wherein an annealing process is carried out in a nitrogen condition.
In some examples, a method for removing the SiO2 layer in step 4 comprises removing the SiO2 layer by means of washing with HF or removing the SiO2 layer by means of dry etching.
In some examples, in step 4, after the SiO2 layer 05 is removed, the upper surface of the SiGe channel is exposed, and the upper surface of the SiGe channel is oxidized to form an oxide; and in step 5, before the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer, the oxide on the upper surface of the SiGe channel is first removed.
In some examples, in step 5, before the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer, the oxide on the upper surface of the SiGe channel is removed using at least one of HF, SiCoNi, HCl, and H2.
In some examples, a method for passivating the upper surface of the SiGe channel to form the nitrogen passivation layer in step 5 comprises steps of: passivating the upper surface of the SiGe channel using nitrogen or NH3 plasma, and then performing annealing, so as to form the nitrogen passivation layer.
In some examples, the mode of depositing the gate oxide layer on the nitrogen passivation layer in step 6 is in-situ steam generation, and the thickness of the deposited gate oxide layer is 6-15 Å; the deposited high-k dielectric layer is HfO2 or HfLaO2, and the thickness of the high-k dielectric layer is 15-30 Å; and the thickness of the deposited TiN layer is 15-30 Å.
In some examples, the concentration of Ge in the raised SiGe epitaxially grown in step 8 is 20%-50%, and the raised SiGe contains boron at a concentration in a range of 1*1019-1*1021 cm−3; and the thickness of the raised SiGe is in a range of 200-400 Å.
As stated above, the FDSOI device structure and preparation method thereof of the present application have the following beneficial effects: in a manufacturing process of an FDSOI device of the present application, a stack structure of a SiGe layer and a nitrogen passivation layer is used as a channel, avoiding the low stress of a silicon channel in the conventional process and the diffusion of Ge in a SiGe channel to a gate dielectric in the conventional process, and thereby improving the reliability and performance of the device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a FDSOI device substrate, including a silicon substrate, a buried oxide layer, and an SOI layer disposed on the silicon substrate according to the present application.
FIG. 2 is a schematic diagram of the structure after a SiGe layer is disposed on the SOI layer, according to the present application.
FIG. 3 is a schematic diagram of the structure after disposing a SiGe channel and a SiO2 layer, according to the present application.
FIG. 4 is a schematic diagram of the structure after removing the SiO2 layer from the SiGe channel according to the present application.
FIG. 5 is a schematic structural diagram of forming a nitrogen passivation layer on the SiGe channel according to the present application.
FIG. 6 is a schematic diagram of the structure after disposing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer according to the present application.
FIG. 7 is a schematic structural diagram of forming a first stack structure, an amorphous silicon layer structure, and a hard mask layer structure one the nitrogen passivation layer according to the present application.
FIG. 8 is a schematic diagram of a structure after forming a source and a drain regions, sidewalls of inner spacer and an outer hard mask on sides of the amorphous silicon layer structure according to the present application.
FIG. 9 is a schematic diagram of the structure after removing the amorphous silicon layer structure to form a groove according to the present application.
FIG. 10 is a schematic diagram of an FDSOI device structure according to an embodiment of the present application.
 DETAILED DESCRIPTION OF THE DISCLOSURE
The implementations of the present application are described below using specific examples. Those skilled in the art could easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied in other different specific implementations, and various details in the specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.
Please refer to FIGS. 1-10 . It should be noted that the figures provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, so the figures only show the components related to the present application, but are not drawn according to the number, shape and size of the components in actual implementations. The pattern, number, and ratio of each component in actual implementations can be changed randomly, and the component layout pattern may be more complicated.
The present application provides an FDSOI device structure, which includes at least: a silicon substrate; a buried oxide layer disclosed on the surface of the silicon substrate; a SiGe channel disclosed on the buried oxide layer, wherein the thickness of the SiGe channel is in the range of 60-100 Å; a nitrogen passivation layer disclosed on the SiGe channel layer; a metal gate disclosed on the nitrogen passivation layer, and sidewalls attached to both sides of the metal gate; and a source region and a drain region disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source region and drain region are in a raised SiGe layer.
Referring to FIG. 10 , which is a schematic diagram of an FDSOI device structure according to an embodiment of the present application. The FDSOI device structure in this embodiment includes: a silicon substrate 01; a buried oxide layer 02 disposed on the silicon substrate 01, wherein in an example, the thickness of the buried oxide layer is in the range of 100-300 Å; a SiGe channel 06 disposed on the buried oxide layer 02, wherein the thickness of the SiGe channel is in the range of 60-100 Å; a nitrogen passivation layer 07 disposed on the SiGe channel layer 06; a metal gate disposed on the nitrogen passivation layer 07 and sidewalls 13 attached to the walls of both sides of the metal gate, the metal gate includes a first stack structure of layers, and a second stack structure 15 disposed on the first stack structure. The first stack structure which includes a gate oxide layer structure 08′, a high-k dielectric layer structure 09′, and a TiN layer structure 10′ that are sequentially stacked from low to upper end. The second stack structure includes a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer that are sequentially stacked from low to upper end. As another example, the thickness of the gate oxide layer structure is in the range of 6-15 Å and the thickness of the high-k dielectric layer structure is in the range of 15-30 Å. In still another example, the thickness of the TiN layer structure is in the range of 15-30 Å; and a source region and a drain region 14 disposed on the nitrogen passivation layer 07 at both sides of the metal gate, wherein the source and drain regions are built a raised SiGe layer. In this embodiment, the sidewalls of the first and second stacks include either a SiCN structure or a SiOCN structure.
The present application further provides a method for fabricating the FDSOI device, and the method includes at least the following steps:
step 1: providing a silicon substrate, disposing a buried oxide layer on the silicon substrate, and disposing an SOI layer on the buried oxide layer;
step 2: forming a SiGe layer on the SOI layer by means of epitaxial deposition, and the SOI is typically composed of a silicon layer on an SiO2 layer;
step 3: oxidizing the SiGe layer by means of high-temperature diffusion, so that Ge elements in the SiGe layer are driven into the SOI layer to form a SiGe channel with a thickness in the range of 60-100 Å, and the SiGe layer replaces the silicon layer remaining on the SiO2 layer;
step 4: removing the SiO2 layer;
step 5: passivating an upper surface of the SiGe channel to form a nitrogen passivation layer;
step 6: sequentially depositing a gate oxide layer, a high-k dielectric layer, and a TiN layer on the nitrogen passivation layer;
step 7: forming an amorphous silicon layer on the TiN layer, depositing a hard mask layer on the amorphous silicon layer, then defining a gate morphology by means of photolithography, sequentially etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure which includes a gate oxide layer structure, a high-k dielectric layer structure, and a TiN layer structure that are sequentially stacked from low to upper end, and further forming an amorphous silicon layer structure disposed on the first stack structure and a hard mask layer structure disposed on the amorphous silicon layer structure. In addition, step 7 includes, forming sidewalls which become inner spacers and outer hard masks on the sides of the first stack layer and the amorphous silicon layer structure;
step 8: epitaxially growing a source region and a drain region on the nitrogen passivation layer at both sides of the amorphous silicon layer structure, wherein the source and drain regions are built in a raised SiGe layer;
step 9: removing the hard mask layer structure and the amorphous silicon layer structure, and forming a groove in the sidewall of spacer on the first stack layer;
step 10: sequentially depositing a TaN layer, a TiN layer, a TiAl layer, and an aluminum layer to fill in the groove, these four layers form a second stack structure 15, wherein the first stack structure 08′, 09′, 10′, the second stack structure 15 and the sidewalls 13 form the metal gate; and
step 11: planarizing the aluminum layer, followed by interconnecting metal layers.
Referring to FIGS. 1-9 , the method for fabricating a FDSOI device in this embodiment includes the following steps in more details.
Step 1: A silicon substrate 01 is provided, wherein a buried oxide layer 02 is disposed on the silicon substrate 01, and a silicon-on-insulator (SOI) layer 03 is disposed on the buried oxide layer 02. Referring to FIG. 1 , a schematic diagram of the structure of the silicon substrate, the buried oxide layer, and SOI layer on the silicon substrate according to the present application.
Step 2: A SiGe layer 04 is formed on the SOI layer 03 by means of epitaxial deposition, referring to FIG. 2 , which is a schematic diagram of the structure after the SiGe layer is disposed on the SOI layer according to the present application. An native oxide layer is formed on the surface of the SOI layer in step 1, because an upper surface of the SOI layer is exposed to the air, therefore growing an native oxide layer. Therefore, in step 2 forming the SiGe layer 04 includes steps of: first removing the native oxide on the surface of the SOI layer using at least one of hydrogen fluoride (HF), SiCoNi™, HCL, and H2, and then growing the SiGe layer 04 in situ with a Ge concentration in a range of 20%-60% on the SOI layer, wherein the thickness of the SiGe layer 04 is in a range of 50-400 Å.
Step 3: The SiGe layer 04 is oxidized by means of high-temperature diffusion, in which Ge atoms in the SiGe layer 04 are driven into the SOI layer to form a SiGe channel 06 with a thickness in the range of 60-100 Å, in this process the Ge layer has turned into a SiGe layer 04 over a SiO2 layer 05, referring to FIG. 3 , a schematic diagram of a structure after forming the SiGe channel and the SiO2 layer thereon according to the present application.
In an example of the present application, a reaction temperature of the high-temperature oxidation in step 3 is in a range of 1000-2000° C., and the mode of the high-temperature oxidation is alternately performing oxidation and annealing, wherein the annealing process is carried out in a nitrogen environment. That is to say, step 3 is performed in a high-temperature environment in a range of 1000-2000° C. to oxidize the SiGe layer 04. In addition, the Ge element in the SiGe layer 04 undergoes the alternating high temperature oxidation-annealing cycles for a number of times, as the result, Ge diffuses into the silicon-on-insulator (SOI) layer 03 beneath the SiGe layer 04, thereby forming the SiGe channel 06. After the Ge element in the SiGe layer fully diffuses into the SOI layer, only oxidized silicon remains in this layer, as shown in FIG. 3 , thereby forming the SiO2 layer 05 located on the SiGe channel 06.
Step 4: The SiO2 layer 05 is removed, shown as in FIG. 4 , which is a schematic diagram of the structure after removing the SiO2 layer from the SiGe channel according to the present application. In an example, a method for removing the SiO2 layer in step 4 includes removing the SiO2 layer 05 by wet etching in HF or removing the SiO2 layer by dry etching.
Step 5: Referring to FIG. 5 , passivating the upper surface of the SiGe channel with a nitrogen passivation layer, FIG. 5 shows the structure after the nitrogen passivation layer has disposed on the SiGe channel. In an example, in step 5, the oxide on the upper surface of the SiGe channel 06 is first removed using at least one of HF, SiCoNi™, HCL, and H2, then the upper surface of the SiGe channel 06 is passivated to form the nitrogen passivation layer 07. In an example of the present application, in step 4, after the SiO2 layer 05 is removed, the upper surface of the SiGe channel 06 is exposed, and the upper surface of the SiGe channel 06 is oxidized to form an oxide; and in step 5, the oxide on the upper surface of the SiGe channel 06 is first removed, then the upper surface of the SiGe channel is passivated to form the nitrogen passivation layer.
In another example, a method for passivating the upper surface of the SiGe channel to form the nitrogen passivation layer in step 5 includes steps of: passivating the upper surface of the SiGe channel using nitrogen or NH3 plasma, and then performing annealing, so as to form the nitrogen passivation layer. So in this embodiment, after the oxide on the upper surface of the SiGe channel 06 is removed, then the upper surface of the SiGe channel is passivated using nitrogen or NH3 plasma, to form the nitrogen passivation layer 07.
Step 6: Agate oxide layer, a high-k dielectric layer, and a TiN layer are sequentially deposited on the nitrogen passivation layer, referring to FIG. 6 , which is a schematic diagram of the structure after the gate oxide layer, the high-k dielectric layer, and the TiN layer are disposed on the nitrogen passivation layer according to the present application. In step 6, the gate oxide layer 08, the high-k dielectric layer 09, and the TiN layer 10 are sequentially deposited on the nitrogen passivation layer 07. In an example of the present application, the technique of depositing the gate oxide layer 08 on the nitrogen passivation layer 07 in step 6 is in-situ steam growth, and the thickness of the deposited gate oxide layer 08 is in a range of 6-15 Å; the deposited high-k dielectric layer 09 is HfO2 or HfLaO2, and the thickness of the high-k dielectric layer 09 is in a range of 15-30 Å; and the thickness of the deposited TiN layer 10 is in a range of 15-30 Å.
For step 7, reference is made to FIG. 7 , a schematic diagram of the structure after forming a first stack structure, an amorphous silicon layer structure, and a hard mask layer structure on the nitrogen passivation layer according to the present application. Step 7: An amorphous silicon layer is formed on the TiN layer, a hard mask layer is deposited on the amorphous silicon layer, a gate morphology is defined by a photolithography process, followed by sequential etching the hard mask layer, the amorphous silicon layer, the TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure. The first stack structure includes a gate oxide layer structure 08′, a high-k dielectric layer structure 09′, and a TiN layer structure 10′ that are sequentially stacked from low to upper end. An amorphous silicon layer structure 11 is disposed on the first stack structure, a hard mask layer structure 12 is disposed on the amorphous silicon layer structure 11, and then sidewalls are formed on the walls of the sides of the first stack layer and the amorphous silicon layer structure 11. Referring to FIG. 8 , which is a schematic diagram of the structure after forming a source and a drain regions and sidewalls on the sides of the amorphous silicon layer structure according to the present application. The sidewalls 13 are attached to the sides of the first stack layer and the amorphous silicon layer structure 11.
Step 8: A source and a drain regions are epitaxially grown on the nitrogen passivation layer at both sides of the first stack layer and the amorphous silicon layer structure, wherein the source and drain regions are built in a raised SiGe layer, referring to FIG. 8 , the source and drain regions 14 are built in a raised SiGe layer, the first stack layer and the amorphous silicon layer structure will be part of the metal gate, and the source and drain regions will be formed on both sides of the metal gate.
Step 9: The hard mask layer structure and the amorphous silicon layer structure are removed, and a groove is formed on the first stack layer and in between the sidewalls, referring to FIG. 9 , which is a schematic diagram of the structure after removing the amorphous silicon layer structure to form the groove according to the present application. In step 9, the amorphous silicon layer structure on the first stack layer is removed, and the groove M is formed. In an example, the Ge concentration in the epitaxially grown raised SiGe layer in step 8 of this embodiment is in the range of 20%-50%, and the raised SiGe layer contains boron at a concentration in the range of 1*1019-1*1021 cm−3; and the thickness of the raised SiGe is in a range of 200-400 Å.
Step 10: A TaN layer, a TiN layer, a TiAl layer, and an aluminum layer are sequentially deposited to fill the groove, and to form a second stack structure, wherein the first and second stack structures and the sidewalls form a metal gate, referring to FIG. 10 , which is schematic diagram of the structure after the second stack structure filled the groove. The second stack structure includes a TaN layer disposed on the first stack layer, a TiN layer disposed on the TaN layer, a TiAl layer disposed on the TiN layer, and an aluminum layer disposed on the TiAl layer. The metal gate in the present application includes the first stack layer, the second stack structure, and the sidewalls.
Step 11: The aluminum layer is planarized, followed by forming metal interconnection.
In conclusion, the present application discloses that a FDSOI device what has a channel of a stack structure of a SiGe layer and a nitrogen passivation layer. This channel avoids the low stress of a silicon channel in the conventional process. In addition, this structure prevents the diffusion of Ge in the SiGe channel into the gate dielectric in the conventional process. Therefore, reliability and performance of the device are improved. The present invention can effectively overcome these issues in the current technology, thus deserves a high value in industrial utilization.
The above embodiments only exemplarily illustrate the principle and effect of the present application, but are not intended to limit the present application. Those skilled in the art could modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical concept disclosed in the present application shall still be covered by the claims of the present application.

Claims (9)

What is claimed is:
1. A method for fabricating a FDSOI device, comprising at least following steps:
step 1: providing a silicon substrate, disposing a buried oxide layer on the silicon substrate, and disposing a silicon-on-insulator (SOI) layer on the buried oxide layer;
step 2: forming a silicon-germanium (SiGe) layer on the SOI layer by means of epitaxial deposition;
step 3: oxidizing the SiGe layer by means of high-temperature oxidation, wherein germanium atoms in the SiGe layer diffuse into the SOI layer to form a SiGe channel layer, wherein a thickness of the SiGe channel layer is in a range of 60-100 A, wherein a SiO2 layer is formed on the SiGe channel layer;
step 4: removing the SiO2 layer;
step 5: passivating an upper surface of the SiGe channel layer to form a nitrogen passivation layer;
step 6: sequentially depositing a gate oxide layer, a high-k dielectric layer, and a first TiN layer on the nitrogen passivation layer;
step 7: forming an amorphous silicon layer on the first TiN layer, depositing a hard mask layer on the amorphous silicon layer, then defining a gate morphology by means of a photolithography process, followed by etching sequentially the hard mask layer, the amorphous silicon layer, the first TiN layer, the high-k dielectric layer, and the gate oxide layer, to form a first stack structure;
wherein the first stack structure comprises a gate oxide layer structure, a high-k dielectric layer structure, and a first TiN layer structure that are sequentially stacked from bottom to top;
wherein step 7 further comprises: forming an amorphous silicon layer structure located on the first stack structure and forming a hard mask layer structure located on the amorphous silicon layer structure, then forming sidewalls of inner spacers, and forming an outer hard mask on sides of the first stack layer and the amorphous silicon layer structure;
step 8: growing epitaxially a raised SiGe layer at both sides of the amorphous silicon layer structure, and forming a source region and a drain region in the raised SiGe layer;
step 9: removing the hard mask layer structure and the amorphous silicon layer structure, and forming a groove between the sidewalls of the inner spacers of the first stack layer;
step 10: sequentially depositing a TaN layer, a second TiN layer, a TiAl layer, and an aluminum layer in the groove, so to form a second stack structure in the groove, wherein the first stack structure, the second stack structure and the sidewalls of the inner spacers of the first stack layer form a metal gate, wherein the sidewalls cover sides of the first stack structure and extend up to a portion of the second stack structure; and
step 11: planarizing the aluminum layer, and then forming metal interconnection.
2. The method for fabricating the FDSOI device according to claim 1, wherein step 1 further comprises, forming an native oxide on a surface of the SOI layer; and in step 2, forming the SiGe layer by epitaxial deposition comprises steps of: first removing the native oxide from the surface of the SOI layer using at least one of HF, SiCoNi, HCL, and H2, and then growing the SiGe layer with a Ge concentration in a range of 0%-60% in-situ on the SOI layer, wherein a thickness of the SiGe layer is in a range of 50-400 Å.
3. The method for fabricating the FDSOI device according to claim 1, wherein a reaction temperature of the high-temperature oxidation in step 3 is in a range of 1000-2000° C., and an oxidation mode of the high-temperature oxidation is alternately applying an oxidation and an annealing process, wherein the annealing process is carried out in a nitrogen environment.
4. The method for fabricating the FDSOI device according to claim 1, wherein removing the Si0 2 layer in step 4 comprises removing the Si0 2 layer by wet etching with HF or removing the Si0 2 layer by dry etching.
5. The method for fabricating the FDSOI device according to claim 1, wherein in step 4, after the SiO2 layer is removed, an upper surface of the SiGe channel layer is exposed and oxidized to form an oxide; and wherein in step 5, the oxide on the upper surface of the SiGe channel layer is first removed, and then followed by nitrogen passivation to form the nitrogen passivation layer.
6. The method for fabricating the FDSOI device according to claim 5, wherein in step 5, wherein the oxide on the upper surface of the SiGe channel layer is removed using at least one of HF, SiCoNi, HCl, and H2.
7. The method for fabricating the FDSOI device according to claim 1, wherein in step 5, a method for passivating the upper surface of the SiGe channel layer to form the nitrogen passivation layer comprises steps of: passivating the upper surface of the SiGe channel layer using nitrogen or NH3 plasma, and then performing annealing, so as to form the nitrogen passivation layer.
8. The method for fabricating the FDSOI device according to claim 1, wherein in step 6, a technique of depositing the gate oxide layer on the nitrogen passivation layer comprises in-situ steam growth, wherein a thickness of the gate oxide layer is in a range of 6-15 Å; wherein the high-k dielectric layer is HfO2 or HfLaO2, a thickness of the high-k dielectric layer is in a range of 15-30 Å; and wherein a thickness of the deposited first TiN layer is in a range of 15-30 Å.
9. The method for fabricating the FDSOI device according to claim 1, wherein in step 8, a concentration of Ge in the epitaxially grown raised SiGe layer is in a range of 20%-50% and wherein the raised SiGe layer comprises boron at a concentration in a range of 1*1019-1*1021 cm−3; and wherein a thickness of the raised SiGe layer is in a range of 200-400 Å.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100151693A1 (en) * 2008-12-16 2010-06-17 Takashi Shimizu Method for manufacturing semiconductor device comprising mutioxide
US20130193514A1 (en) * 2012-02-01 2013-08-01 Stmicroelectronics, Inc. Method to enable the formation of silicon germanium channel of fdsoi devices for pfet threshold voltage engineering
US20200105895A1 (en) * 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Capping Layers in Metal Gates of Transistors

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1659623B1 (en) * 2004-11-19 2008-04-16 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for fabricating a germanium on insulator (GeOI) type wafer
FR2933534B1 (en) * 2008-07-03 2011-04-01 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE
US8124513B2 (en) * 2009-03-18 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Germanium field effect transistors and fabrication thereof
US9269804B2 (en) * 2012-07-28 2016-02-23 Semiwise Limited Gate recessed FDSOI transistor with sandwich of active and etch control layers
CN103730369B (en) * 2012-10-16 2017-12-12 中国科学院微电子研究所 Semiconductor device manufacturing method
US9287262B2 (en) * 2013-10-10 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivated and faceted for fin field effect transistor
KR101521555B1 (en) * 2014-01-28 2015-05-19 한양대학교 산학협력단 Method of manufacturing a substrate using a germanium condensation process and method of manufacturing a semicondictor device usnig the same
FR3025938B1 (en) * 2014-09-17 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives REALIZING SPACERS AT THE FLANK LEVEL OF A TRANSISTOR GRID
US11152214B2 (en) * 2016-04-20 2021-10-19 International Business Machines Corporation Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
CN113745147A (en) * 2020-05-14 2021-12-03 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure preparation method
CN113675218A (en) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure
CN211828771U (en) * 2020-05-14 2020-10-30 上海新微技术研发中心有限公司 FD-SOI substrate structure and device structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100151693A1 (en) * 2008-12-16 2010-06-17 Takashi Shimizu Method for manufacturing semiconductor device comprising mutioxide
US20130193514A1 (en) * 2012-02-01 2013-08-01 Stmicroelectronics, Inc. Method to enable the formation of silicon germanium channel of fdsoi devices for pfet threshold voltage engineering
US20200105895A1 (en) * 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Capping Layers in Metal Gates of Transistors

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