CN106558496B - Semiconductor device manufacturing method - Google Patents
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- CN106558496B CN106558496B CN201510634782.9A CN201510634782A CN106558496B CN 106558496 B CN106558496 B CN 106558496B CN 201510634782 A CN201510634782 A CN 201510634782A CN 106558496 B CN106558496 B CN 106558496B
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- 238000005121 nitriding Methods 0.000 claims description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
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- 239000001301 oxygen Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 229910020211 SiOxHy Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 125000000962 organic group Chemical group 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
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- -1 oxygen alkane Chemical class 0.000 description 1
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device manufacturing method, comprising: etching the substrate to form a plurality of fins; forming STI between the fins; forming a first high mobility layer on the fin portion exposing the STI; an oxidation and/or nitridation process is performed to convert the first high mobility layer into a dielectric layer and simultaneously convert the exposed STI fin portion into a second high mobility layer. According to the manufacturing method of the semiconductor device, the high mobility material serving as the sacrificial layer is oxidized, ions are driven to diffuse, so that the fins formed by the substrate material are converted into the high mobility material, the process is simplified, the cost is low, the performance of the device is improved, and the device is beneficial to device miniaturization.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing methods, have small size mobility channel more particularly to one kind
FinFET manufacturing method.
Background technique
It moves ahead to continue to press on Moore's Law, the driving current needs of device get a greater increase and need to control short
Channelling effect.Body silicon fin gate fin-fet (finfet) device for being integrated with mobility channel, which is considered most potential, to be pushed away
The device of the development of dynamic Moore's Law.
The production method of mobility channel finfet device usually grows mobility channel material on a silicon substrate.
The channel of high mobility is usually made of high mobility material, such as germanium, germanium silicon, III--V race material, II--VI race material etc..With
For SiGe, the fin of high mobility material composition is re-formed after the growth was completed.A kind of Integrated Solution is to be formed in conventional method
After silicon fin and STI, one layer of germanium silicon of extension is as high mobility material.
But conventional integrated technique faces following problems:
1) entire fin is made of silicon fin and germanium silicon epitaxial layer, due to being made of this two parts, so entire fin is difficult
Thin to do, this is unfavorable for the further size reduction of device.The fin mobility being in inside channel simultaneously is not high, is unfavorable for
Promote the performance of device.
2) when the concentration of germanium is higher, carrier mobility is higher.But with the raising of germanium concentration, germanium silicon or germanium
The crucial thickness (critical thickness is more than that this thickness will generate more defect) of extension becomes smaller.When scarce
When falling into more, the carrier mobility of the material will degenerate, to hinder the performance of raising device.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose one kind can simplify technique reduce at
The FinFET manufacturing method of this small size mobility channel.
For this purpose, the present invention provides a kind of method, semi-conductor device manufacturing methods, comprising: etched substrate forms multiple fins；?
STI is formed between fin；The first high mobility layer is formed on the fin portion for exposing STI；Execute oxidation and/or nitridation work
First high mobility layer is changed into dielectric layer and the fin portion for exposing STI is changed into the second high mobility layer simultaneously by skill.
Wherein, it executes oxidation and/or nitriding process makes the non-Si elements diffusion in the first high mobility layer to exposing STI
Fin portion and reconfigure to form the second high mobility layer with fin material.
Wherein, it before or after forming the first high mobility layer, individually or is formed together and prevents high mobility layer
In non-the element silicon barrier layer and anti-break-through barrier layer spread to substrate.
Wherein, the atomic number for injecting ion in the barrier layer that non-element silicon is spread to substrate in high migrating layer is prevented to be less than
Non- Si element in first high mobility layer, to prevent non-Si elements diffusion to substrate.Wherein, the ion of injection be selected from C, N, O,
F, S's is any and combinations thereof.
Wherein, the doped chemical on anti-break-through barrier layer according to device different type select three races or group-v element and itself or
The simple substance or compound of person and other race's elements composition.
Wherein, the material of the first high mobility layer be selected from III--V race, II--VI race, V compound semiconductor any
Kind and combinations thereof.
Wherein, the size of the second high mobility layer is less than the size for the fin that etched substrate is formed.
Wherein, non-Si element will be lower than with the concentration of fin portion interface in outer surface in the first high mobility layer
Concentration.
Wherein, forming the second high mobility layer further comprises later the grid being developed across on the second high mobility layer
Pole stacks, and forms source-drain area in the second high mobility layer of gate stack two sides.
Wherein, doped region also serves as break-through barrier layer.
It is driven according to method, semi-conductor device manufacturing method of the invention by aoxidizing the high mobility material as sacrificial layer
Ion spread so that substrate material constitute fin be converted to high mobility material, improve device to simplify technique and low cost
Performance is simultaneously miniature conducive to device.
Detailed description of the invention
Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:
Fig. 1 to Fig. 3 is the cross-sectional view according to each step of FinFET manufacturing method of the invention；And
Fig. 4 is the schematic flow chart according to FinFET manufacturing method of the invention.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the FinFET manufacturing method that can simplify the small size mobility channel that technique reduces cost.It needs to refer to
Out, similar appended drawing reference indicates similar structure, term " first " use herein, " second ", "upper", "lower"
Etc. can be used for modifying various device architectures or manufacturing process.These modifications do not imply that modified device junction unless stated otherwise
The space of structure or manufacturing process, order or hierarchical relationship.
As shown in Fig. 4 and Fig. 1, etched substrate forms multiple fins.
Substrate 1 is provided, material can be monocrystalline silicon, SOI, monocrystalline germanium, GeOI, strained silicon (Strained Si), germanium silicon
, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (SiGe) or compound semiconductor materials
(InSb) and carbon-based semiconductors such as graphene, SiC, carbon nanotube etc..In a preferred embodiment of the invention, substrate 1
For monocrystalline silicon, in order to compatible with CMOS technology and reduce manufacturing cost.
Etched substrate 1 (is not shown, can be the soft mask of photoresist or the hard mask of dielectric material) using mask graph,
Form the groove (not shown) between the multiple fin structure 1F extended in a first direction and adjacent fin structure.Etching
The preferably anisotropic dry etching of technique, such as dry plasma etch or RIE, etching gas such as carbon fluorine base gas is (extremely
Contain carbon, fluorine atom less, can also there are also other atoms such as hydrogen, nitrogen, oxygen), chlorine, bromine vapor, HCl, HBr etc., can also add
The oxidants such as oxygen, CO, ozone are to adjust etch rate.
Fill insulant forms shallow trench isolation (STI) 2 in groove between fin structure 1F.Such as pass through hot oxygen
The techniques such as change, LPCVD, PECVD form the STI 2 of insulating materials in the groove between fin structure 1F.In the present invention one
In a preferred embodiment, STI2 material is silicon oxide or silicon nitride substrate matter, such as SiOx、SiNx、SiOxNy、SiOxCy、
SiOxFy、SiOxHy、SiNxCy、SiNxFy(each xy is not necessarily integer).Expose the part 1C of the fin 1F on 2 top STI
It will act as the source-drain area and channel region of FinFET.In another preferred embodiment of the present invention, the material of STI 2 is low-k materials
To reduce the parasitic capacitance of device, formation process is spin coating, spraying, silk-screen printing, and wherein low-k materials are including but not limited to organic
Low-k materials (such as organic polymer containing aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline
Boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials,
Porous silica, porous SiOCH, it mixes C silica, mix the porous amorphous carbon of F, porous diamond, porous organo polysilica conjunction
Object).In another preferred embodiment of the present invention, the material of STI2 further includes negative expansion dielectric material or positive thermal expansion medium material
Material (preferably, 100K at a temperature of the linear coefficient of cubical expansion absolute value be greater than 10-- 4/ K) sublayer, further to increase
Strong channel region stress, negative expansion dielectric material are to include selected from Bi0..95La0..05NiO3、BiNiO3、ZrW2O8It is any and
The perofskite type oxide of a combination thereof, just thermally expanding dielectric material to be includes Ag3[Co(CN)6] frame material.
Optionally or preferably, ion implanting is executed, below the channel region 1C of fin 1F (such as 2 near top of STI)
Doped region 3 is formed, the barrier layer of the ion diffusion as subsequent high mobility material.Implantation Energy such as 500eV~500KeV
And preferably 20KeV~80KeV, implantation dosage such as 1012~1016And preferably 5 × 1012~1014Atom/cm3, the element of injection
Atomic number is less than the subsequent element (element to be spread in a preferred embodiment of the invention is Ge) that will be spread, such as
The element of injection is preferably chosen from any and combinations thereof of C, N, O, F, S, and (C and Si, Ge are all IV race member to most preferably C
Element, atomic structure is similar, and barrier layer can be regarded as the reticular structure that Si and C form, if to prevent the high mobilities material such as Ge
Material diffusion or migration, selecting the lesser purpose of atomic number is exactly in order to enable mesh size reduction, so can effectively prevent
The material of larger atomic number migrates).Ion implanting can be vertical injection, be also possible to inclination injection (towards channel region
1C), the angle for tilting injection is, for example, 5~15 degree.Annealing can be executed after injection, the impurity activation of the injection made and again
Distribution, accurate control so that doped region 3 peak concentration at or near 2 top STI (namely in fin 1F top channel area
The lower section of 1C, for example, with flushed at the top of STI 2 or slightly lower 1~3nm).Such as 550~1050 DEG C of annealing temperature, preferably 650~
900 DEG C, 700~800 DEG C best, annealing time 1s~10min, 10s~5min, 1~3min.Further, these adulterate from
Son can also make 3 conduction type of doped region opposite with channel region or directly as dielectric simultaneously so as to form anti-
Break-through barrier layer is dielectrically separated from effect between substrate and channel to improve, eliminate or reduces substrate leakage currents.
Furthermore before or after forming the first high mobility layer, extraly individually or be formed together prevent it is non-in high mobility layer
The barrier layer and anti-break-through barrier layer namely barrier layer 3 and anti-break-through barrier layer (not shown) that element silicon is spread to substrate can
It can also be formed step by step with being formed together.The doped chemical on anti-break-through barrier layer selects three races or five races according to device different type
Simple substance or compound of the element with itself or with other race's elements composition.
As shown in fig. 4 and fig. 2, the shape on the part (namely following channel region 1C) for expose the fin 1F at 2 top STI
It is greater than 1/ fin of substrate at the carrier mobility of the first high mobility layer 4 namely layer 4 different from fin 1F/ 1 material of substrate
1F.By the techniques epitaxial growth such as MOCVD, MBE, ALD be selected from III--V race, II--VI race, V compound semiconductor Gao Qian
Shifting rate material, for example, SiGe, SiC, SiGeC, SiGeSn, SiGaN, SiGaP, SiGaAs, InSiN, InSiP, InSiAs,
InSiSb any and combinations thereof high mobility material or their component proportion material, such as SiGeSn, SiInGaAs.At this
It invents in a preferred embodiment, deposition process parameters, particularly unstripped gas proportion is adjusted, so that close to fin 1F table in layer 4
The content of the non-Si element (such as Ge) in face is lower, and preferably shorter than 30%, lower than 20% even below 10%, so that from layer
4 exposed surface has biggish concentration gradient to layer 4 and fin 1F/ top 1C interface descending concentrations, is convenient for subsequent member
Plain thermal diffusion.
As shown in Fig. 4 and Fig. 3, oxidation and/or nitriding process are executed, the first high mobility layer 4 is partly or completely oxidized
At dielectric layer 5, while 1C at the top of fin 1F being made to be changed into the second high mobility layer 6.Oxidation and/or nitridation (are including oxygen
Or nitrogen atmosphere high temperature heat treatment) such as 800~1300 DEG C, preferably 900~1100 DEG C of technological temperature, best 1000
DEG C, time such as 10min~2h, preferably 20min~1h, best 30min.Oxidation and/or nitridation so that Si element in layer 4 with
O/N is combined and is formed silicon oxide or silicon nitride based dielectric material, rather than Si element due to concentration gradient presence and to fin 1F
Top 1C diffusion, and redistribute and combine in the 1C of top, form the second high mobility layer 6.Second high mobility layer, 6 material
Material can be same or similar with the first high mobility layer material 4.In the process, due to being optionally present doped region 3 and mixing
The atomic number of doped chemical is less than non-Si element (namely the element in doped region 3 in the first high mobility floor 4 in miscellaneous area 3
Bigger with the bond strength of Si, the mesh size of the reticular structure of formation is smaller, conducive to entirely preventing atomic number big (correspondingly
Size is larger) elements diffusion migration), therefore the diffusion of non-Si element will stop on doped region 3, it is therefore prevented that bottom break-through,
Reduce substrate leakage.Furthermore it is noted that when layer 4 is fully oxidized and/or nitrogenizes, layer 4 and the top fin 1F 1C
Between interface also can be partially oxidized and/or nitrogenize simultaneously, to further reduce the line width of channel region 1C, be conducive into
One step improves device integration.
Hereafter, it can etch 6 at the top of the fin of the removal exposure high mobility material of dielectric layer 5, deposition is developed across channel
The gate stack in area forms source-drain area in the fin of gate stack two sides, forms the interlayer dielectric layer for covering entire chip
(ILD), etching ILD, which forms contact hole and fills metal, realizes source and drain interconnection, is finally completed FinFET manufacture.
It is driven according to method, semi-conductor device manufacturing method of the invention by aoxidizing the high mobility material as sacrificial layer
Ion spread so that substrate material constitute fin be converted to high mobility material, improve device to simplify technique and low cost
Performance is simultaneously miniature conducive to device.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and disclosed device architecture
And its manufacturing method will include all embodiments fallen within the scope of the present invention.
Claims (8)
1. a kind of method, semi-conductor device manufacturing method, comprising:
Etched substrate forms multiple fins；
STI is formed between fin；
The first high mobility layer is formed on the fin portion for exposing STI, surface to the first height of the first high mobility layer migrates
Rate layer successively decreases with the non-Si concentration of element in fin interface；
Oxidation and/or nitriding process are executed, the first high mobility layer is changed into dielectric layer and the fin portion of STI will be exposed simultaneously
Divide and is changed into the second high mobility layer.
2. method as claimed in claim 1, wherein execute oxidation and/or nitriding process makes the non-Si in the first high mobility layer
Elements diffusion reconfigures to form the second high mobility layer with fin material to the fin portion for exposing STI.
3. method as claimed in claim 1, wherein before or after forming the first high mobility layer, an independent or similar shape
At preventing the barrier layer and anti-break-through barrier layer that non-element silicon is spread to substrate in high mobility layer.
4. method as claimed in claim 3, wherein prevent from injecting in the barrier layer that non-element silicon is spread to substrate in high migrating layer from
The atomic number of son is less than the non-Si element in the first high mobility layer, to prevent non-Si elements diffusion to substrate.
5. method as claimed in claim 4, wherein the ion of injection is selected from any and combinations thereof of C, N, O, F, S.
6. method as claimed in claim 3, wherein the doped chemical on anti-break-through barrier layer according to device different type select three races or
Simple substance or compound of the group-v element with itself or with other race's elements composition.
7. method as claimed in claim 1, wherein the material of the first high mobility layer is selected from iii-v, II-VI group, V race chemical combination
Object semiconductor it is any and combinations thereof.
8. method as claimed in claim 1, wherein forming the second high mobility layer further comprises later being developed across second
Gate stack on high mobility layer forms source-drain area in the second high mobility layer of gate stack two sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510634782.9A CN106558496B (en) | 2015-09-29 | 2015-09-29 | Semiconductor device manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510634782.9A CN106558496B (en) | 2015-09-29 | 2015-09-29 | Semiconductor device manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN106558496A CN106558496A (en) | 2017-04-05 |
| CN106558496B true CN106558496B (en) | 2019-09-24 |
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