US11761920B2 - Concentration estimation method - Google Patents
Concentration estimation method Download PDFInfo
- Publication number
- US11761920B2 US11761920B2 US17/094,621 US202017094621A US11761920B2 US 11761920 B2 US11761920 B2 US 11761920B2 US 202017094621 A US202017094621 A US 202017094621A US 11761920 B2 US11761920 B2 US 11761920B2
- Authority
- US
- United States
- Prior art keywords
- layer
- transistor
- electrode
- gate
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 72
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 31
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 25
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 238000005259 measurement Methods 0.000 claims description 19
- 125000004432 carbon atom Chemical group C* 0.000 claims description 17
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910001845 yogo sapphire Inorganic materials 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 230000005533 two-dimensional electron gas Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000013507 mapping Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 2
- 239000013626 chemical specie Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001955 cumulated effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/22—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
- G01N27/221—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance by investigating the dielectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/002—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating the work function voltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2648—Characterising semiconductor materials
Definitions
- the present disclosure generally concerns electronic devices and, more particularly, electronic power components based on gallium nitride (GaN).
- GaN gallium nitride
- Gallium nitride currently is a component of many electronic components, for example, high electron mobility transistors (HEMT).
- HEMT transistors comprising at least one gallium nitride crystal layer particularly enable to switch high electric currents, for example, in the order of several tens of amperes, under high bias voltages, for example, in the order of several hundreds of volts.
- Such transistors are further compatible with high operating frequencies, typically in the order of one megahertz.
- Impurities are frequently intentionally introduced into the gallium nitride layer of gallium nitride transistors. Such impurities, for example, carbon atoms, particularly contribute to obtaining transistors having an improved voltage behavior. However, too strong a carbon concentration in the gallium nitride layer may decrease the lifetime of transistors.
- gallium nitride components it is attempted, on manufacturing of gallium nitride components, to obtain a given carbon concentration, for example enabling to reach an optimal tradeoff between the voltage behavior and the lifetime of the components. It would be desirable to be able to estimate, after manufacturing, the carbon concentration in the gallium nitride layer of such components. This would in particular enable to better control the manufacturing of gallium nitride components.
- An embodiment overcomes all or part of the disadvantages of known methods for estimating the carbon concentration in the gallium nitride layer of an electronic component.
- An embodiment provides a method of estimating a nitrogen site carbon concentration, in a first epitaxial carbon-doped gallium nitride layer of an electronic component, comprising steps of:
- said method further comprises a step comprising calculating, based on the surface concentration and on a partial thickness of the first layer, a nitrogen site carbon volume concentration in the first layer.
- the heating of the component is performed at a temperature in the range from one hundred to two hundred and fifty degrees Celsius, preferably from one hundred and fifty to two hundred and fifty degrees Celsius.
- the stack forms, with the first electrode, a MOS-type structure comprising:
- the capacitance is estimated according to respective thicknesses and dielectric permittivities of the second layer and of the third layer.
- the first layer is located on a substrate, preferably a silicon wafer with a ⁇ 111 ⁇ orientation.
- the offset of the threshold voltage of the component is determined at the end of a step of application, between the first electrode and a second electrode of the component, of a negative bias voltage.
- the bias voltage is smaller than ⁇ 1 V, preferably approximately equal to ⁇ 5 V.
- the step of application of the bias voltage lasts for from one to ten thousand seconds, preferably from one hundred to ten thousand seconds.
- the step of application of the bias voltage is interrupted, for from ten to one hundred microseconds, several times to estimate the threshold voltage of the component.
- the threshold voltage of the component is estimated based on a measurement of the variation of the capacitance, between the first electrode and the second electrode, according to a variation of the potential applied to the first electrode.
- the threshold voltage of the component is estimated based on a measurement of the variation of an electric current crossing the component, according to a variation of the potential applied to the first electrode.
- the component is a transistor, preferably a high electron mobility transistor, the first electrode being a gate electrode and the second electrode being an electrode connected to the substrate.
- the component is a MOS capacitor.
- epitaxy parameters of the first layer are adapted according to the estimation of the nitrogen site carbon concentration.
- FIG. 1 is a partial simplified perspective cross-section view of an embodiment of a field-effect transistor
- FIG. 2 is a partial simplified cross-section view of a portion of the transistor of FIG. 1 illustrating an operating mode
- FIG. 3 is a partial simplified cross-section view of the portion of FIG. 2 of the transistor of FIG. 1 illustrating another operating mode
- FIG. 4 is a logical diagram of the sequence of steps of an implementation mode of a method of estimation of a nitrogen site carbon concentration in a gallium nitride layer
- FIG. 5 is a circuit equivalent to the portion of FIG. 2 of the transistor of FIG. 1 ;
- FIG. 6 is a partial simplified cross-section view of the transistor of FIG. 1 ;
- FIG. 7 is a timing diagram of the variation of a gate potential
- FIG. 8 is a graph of the variation of a drain current according to a gate potential
- FIG. 9 is a graph of the variation of a capacitance according to a gate potential
- FIG. 10 is a graph of the time variation for different temperatures of an offset of a threshold voltage of an electronic component
- FIG. 11 is a graph of the time variation for different temperatures of an offset of a threshold voltage of another electronic component
- FIG. 12 is a partial simplified cross-section view of an example of a capacitor
- FIG. 13 is a partial simplified cross-section view of the portion of FIG. 2 of the transistor of FIG. 1 in still another operating mode;
- FIG. 14 is a partial simplified cross-section view of the portion of FIG. 2 of the transistor of FIG. 1 in still another operating mode
- FIG. 15 is a partial simplified view of a transistor in an operating mode
- FIG. 16 is a partial simplified view of another transistor in another operating mode
- FIG. 17 is a graph of the time variation of an offset of a threshold voltage of electronic components
- FIG. 18 is an Arrhenius graph associated with a first time constant
- FIG. 19 is an Arrhenius graph associated with a second time constant
- FIG. 20 is a graph of the variation according to a depth of a chemical species concentration
- FIG. 21 is a partial simplified cross-section view of a normally-off transistor
- FIG. 22 is a partial simplified cross-section view of a normally-on transistor
- FIG. 23 is a graph of the time variation of an offset of a threshold voltage of the transistors of FIGS. 21 and 22 ;
- FIG. 24 is a mapping of ionized traps inside of the portion of FIG. 2 of the transistor of FIG. 1 in an operating mode
- FIG. 25 is a mapping of ionized traps inside of the portion of FIG. 2 of the transistor of FIG. 1 in another operating mode
- FIG. 26 is a graph of the variation, according to a depth, of a conduction band energy.
- FIG. 27 is a graph of the time variation of a conduction band energy.
- FIG. 1 is a partial simplified perspective cross-section view of an embodiment of a field-effect transistor 100 .
- transistor 100 comprises a substrate 102 .
- Substrate 102 is for example a wafer having a diameter of two hundred millimeters (eight inches), mainly made of crystal silicon (Si), and having a surface (the upper surface of substrate 102 , in the orientation of FIG. 1 ) with a ⁇ 111 ⁇ orientation.
- a layer 104 is located on top of and in contact with the upper surface of substrate 102 .
- Layer 104 is preferably a “full plate” layer, in other words a layer entirely covering the upper surface of substrate 102 .
- layer 104 is preferably a so-called transition layer having a composition different from that of substrate 102 .
- Layer 106 of transistor 100 is located on top of and in contact with layer 104 .
- Layer 106 is for example formed by epitaxial growth from a surface of transition layer 104 (the upper surface of layer 104 , in the orientation of FIG. 1 ).
- Layer 104 particularly allows a progressive lattice parameter adaptation, for example causing a relaxation of the lattice stress, between substrate 102 and layer 106 .
- layer 106 is made of doped gallium nitride (GaN). More particularly, layer 106 has a crystal structure comprising gallium nitride cells having doping impurities, preferably carbon atoms (C), intentionally introduced therein. This means, in other words, that layer 106 forms a gallium nitride crystal lattice and that, in certain cells of the lattice, one or a plurality of atoms are each substituted with a carbon atom.
- doping impurities preferably carbon atoms (C)
- the carbon atoms introduced during the epitaxy of layer 106 mainly substitute to nitrogen atoms of the gallium nitride crystal lattice. It is then said that the carbon atoms occupy nitrogen sites of the gallium nitride crystal structure of the layer 106 of transistor 100 or, more simply, that the carbon atoms are “nitrogen site” carbon atoms.
- the nitrogen site carbon atoms in gallium nitride layer 106 behave as acceptors. In other words, the presence of nitrogen site carbon atoms in gallium nitride layer 106 results in a p-type doping of layer 106 . This provides, in particular, a transistor 100 having a better voltage behavior than an equivalent transistor having a layer 106 comprising no nitrogen site carbon atoms.
- GaN:C designates the composition of a layer mainly made of gallium nitride and comprising nitrogen site carbon atoms, for example, the layer 106 of transistor 100 .
- transistor 100 comprises still another layer 108 .
- Layer 108 is located on top of and in contact with layer 106 .
- Layer 108 preferably acts as a barrier layer.
- layer 108 enables to adjust a threshold voltage value, noted V TH , of transistor 100 .
- Transistor 100 comprises still another layer 110 .
- Layer 110 is located on top of and in contact with layer 108 .
- Layer 110 of transistor 100 is mainly made of gallium nitride.
- layer 110 comprises doping impurities. The impurities present in layer 110 may be unintentionally introduced during and/or after one or a plurality of steps of forming of layer 110 . In this case, layer 110 is said to be unintentionally doped.
- GaN:UID designates the composition of a layer mainly made of unintentionally doped gallium nitride, for example, layer 110 of transistor 100 .
- Layer 110 is partially covered with still another layer 112 .
- layer 112 has a multilayer structure.
- layer 112 has a multilayer structure.
- layer 112 is located on top of and in contact with a portion of the upper surface of layer 110 .
- layer 112 is located on top of and in contact with a portion of the upper surface of layer 110 .
- a portion 110 L of layer 110 located on the left-hand side of transistor 100 , is not covered with layer 112 ;
- a source electrode 114 S of transistor 100 is located on top of and in contact with the portion 110 L of layer 110 which is not covered with layer 112 .
- a drain electrode 114 D of transistor 100 is located on top of and in contact with the portion 110 R of layer 110 which is not covered with layer 112 .
- Source electrode 114 S and drain electrode 114 D are for example formed from a same layer.
- a gate electrode 114 G of transistor 100 is located between source electrode 114 S and drain electrode 114 D.
- Gate electrode 114 G extends vertically from the upper surface of layer 112 to the lower surface of transistor 100 . More particularly, gate electrode 114 G crosses layer 112 across its entire thickness and penetrates into layer 110 without crossing layer 110 . Further, the gate electrode 114 G of transistor 100 extends laterally on layer 112 .
- Gate electrode 114 G has, in cross-section view in FIG. 1 , a “T”-shaped cross-section.
- gate electrode 114 G is made of at least one metal and/or of at least one metal alloy.
- Layer 116 of transistor 100 is a gate oxide layer, intended to electrically insulate gate electrode 114 G from layers 110 and 112 .
- Layer 116 is preferably mainly made of alumina (Al 2 O 3 ).
- Layer 116 has a thickness in the range from 20 nm to 40 nm, preferably equal to 30 nm.
- layer 118 of transistor 100 integrally covers the upper portion of the “T” formed by gate electrode 114 G, and lateral surfaces of the gate oxide layer 116 .
- Layer 118 is located on top of and in contact with the upper surface of layer 112 . In the orientation of FIG. 1 , layer 118 extends laterally, leftwards, all the way to source electrode 1145 , and, rightwards, all the way to drain electrode 114 D.
- Source electrode 114 S is on top of and in contact with a portion of layer 112 and a portion of layer 118 , these portions being both located on the left-hand side of the “T” formed by gate electrode 114 G.
- drain electrode 114 D is on top of and in contact with a portion of layer 112 and a portion of layer 118 , these portions being both located on the right-hand side of transistor 100 .
- another source electrode 114 S′ is located on top of and in contact with a portion of layer 118 located on the right-hand side of the “T” formed by gate electrode 114 G.
- layer 120 is located on top of and in contact with a portion of layer 118 located between source electrode 114 S′ and drain electrode 114 D. As illustrated in FIG. 1 , layer 120 laterally extends:
- drain electrode 114 D drain electrode
- Layers 118 and 120 are preferably based on dielectric materials.
- layer 120 may be made of tetraethyl orthosilicate (TEOS).
- Transistor 100 further comprises:
- a source pad or terminal 122 S extending on top of and in contact with the left-hand portion of source electrode 114 S and a left-hand portion of layer 120 ;
- drain pad or terminal 122 D located on top of and in contact with a right-hand portion of layer 120 and a right-hand portion of drain electrode 114 D.
- source pad 122 S and drain pad 122 D are respectively connected to source electrode 1145 and to drain electrode 114 D.
- source pad 122 S is taken to a potential node V S , this amounts to taking source electrode 1145 to potential V S .
- drain pad 122 D is taken to a potential node V D , this amounts to taking source electrode 114 D to potential V D .
- gate electrode 114 G may be coupled, preferably connected, to a gate pad or terminal. When the gate pad is taken to a potential noted V G , this amounts to taking gate electrode 114 G to potential V G .
- source electrode 1145 is connected to substrate 102 .
- the potential V S to which source electrode 114 S is taken is then equivalent to a potential applied to the substrate 102 of transistor 100 , generally the ground.
- distance L GS corresponds to a lateral dimension of a portion of layer 112 located on the left-hand side of gate electrode 114 G.
- Distance L GD corresponds to a lateral dimension of a portion of layer 112 located on the right-hand side of gate electrode 114 G.
- distances L GS , L GD , and L G respectively correspond to the gate-source distance, to the gate-drain distance, and to the gate length of transistor 100 .
- transistor 100 is a field-effect transistor, more particularly a field-effect transistor with a metal-oxide-semiconductor (MOS) or metal-insulator-semiconductor (MIS) structure.
- Transistor 100 is preferably a high electron mobility transistor (HEMT).
- HEMT high electron mobility transistor
- Transistor 100 is said to be “normally off”. In other words, transistor 100 conducts no current, or a negligible electric current, between its source electrode 114 S and its drain electrode 114 D when its gate electrode 114 G is taken to a substantially zero electric potential.
- the transistor 100 of FIG. 1 is capable of switching electric currents having an intensity in the order of 30 A under a bias voltage in the order of 600 V between its source electrode 114 S and its drain electrode 114 D (and thus between its source pad 122 S and its drain pad 122 D).
- Transistor 100 may in particular be used for power signal switching applications at frequencies in the order of one megahertz (MHz).
- Portion 124 is approximately centered on gate electrode 114 G and includes areas of transistor 100 located in the vicinity of gate electrode 114 G.
- FIG. 2 is a partial simplified cross-section view of the portion 124 of the transistor 100 of FIG. 1 illustrating an operating mode where transistor 100 is off.
- transistor 100 conducts no electric current, or a current of negligible intensity, between its source electrode 114 S (SOURCE) and its drain electrode 114 D (DRAIN).
- the operating mode illustrating in FIG. 2 for example corresponds to a situation where a voltage, noted V GS , smaller than the threshold voltage V TH of transistor 100 is applied between the gate electrode 114 G (GATE) and the source electrode 114 S of transistor 100 .
- Transistor 100 being normally off, threshold voltage V TH corresponds to a limiting voltage value above which transistor 100 turns on.
- the source electrode 114 S of transistor 100 is for example grounded, that is, taken to a substantially null potential. Voltage V GS is then approximately equal to the potential V G applied to the gate electrode 114 G of transistor 100 .
- layer 112 has a multilayer structure comprising a sub-layer 112 - 1 located on top of and in contact with GaN:UID layer 110 , and another sub-layer 112 - 2 , located on top of and in contact with sub-layer 112 - 1 .
- gate electrode 114 G has a multilayer structure comprising a sub-layer 114 G- 1 , located on top of and in contact with gate oxide 116 , and another sub-layer 114 G- 2 , located on top of and in contact with sub-layer 114 G- 1 .
- the sub-layer 112 - 1 of layer 112 is made of aluminum-gallium nitride (AlGaN);
- the sub-layer 112 - 2 of layer 112 is a passivation layer capable of having a multilayer structure
- the sub-layer 114 G- 1 of gate electrode 114 G is made of at least one metal and/or of at least one metal alloy
- the sub-layer 114 G- 2 of gate electrode 114 G is made of at least one metal and/or of at least one metal alloy.
- Gate oxide layer 116 has, in cross-section view in FIG. 2 , a “V” shape into which the “T”-shaped gate electrode 114 G is inserted. Two horizontal portions of layer 116 laterally extend on top of and in contact with the sub-layer 112 - 2 of layer 112 . Two oblique portions of layer 116 cross layer 112 and join another horizontal portion of the layer 116 formed inside of GaN:UID layer 110 .
- the gate of transistor 100 comprising gate oxide layer 116 and gate electrode 114 G, is said to be “recessed” in GaN:UID layer 110 .
- the gate of transistor 100 is obtained, for example, by forming a cavity inside of layer 110 and then by successively depositing, in this cavity, layer 116 and the sub-layers 114 G- 1 and 114 G- 2 of gate electrode 114 G. A MOS-type gate is thus formed.
- the gate of transistor 100 recessed in layer 110 , separates two portions of a two-dimensional electron gas (2DEG).
- the two-dimensional electron gas 2DEG is symbolized in FIG. 2 by two dotted lines on either side of gate electrode 114 G.
- the two-dimensional electron gas 2DEG is located in GaN:UID layer 110 , close to the interface between layer 110 and AlGaN sub-layer 112 - 1 .
- Source and drain electrodes 114 S and 114 D are preferably connected to the two-dimensional electron gas 2DEG.
- FIG. 3 is a partial simplified cross-section view of the portion 124 of FIG. 2 of the transistor 100 of FIG. 1 illustrating another operating mode where transistor 100 is on.
- transistor 100 conducts, between its source electrode 114 S (SOURCE) and its drain electrode 114 D (DRAIN), an electric current of non-null intensity, for example, in the order of several tens of amperes.
- the operating mode illustrated in FIG. 3 for example corresponds to a situation where the potential V G applied to gate electrode 114 G (GATE) of transistor 100 exceeds the threshold voltage V TH of transistor 100 .
- the two portions of the two-dimensional electron gas 2DEG are coupled, at the level of the gate of transistor 100 , by an electron channel 302 .
- this operating mode there thus exists a conduction path, formed of the two portions of the two-dimensional electron gas 2DEG and of electron channel 302 , between the source electrode 114 S and the drain electrode 114 D of transistor 100 .
- Transistor 100 is thus in an on state.
- FIG. 4 is a logic diagram of the sequence of steps of an implementation mode of a method of estimation of a nitrogen site carbon concentration in a gallium nitride layer of a device.
- the implementation mode of the method described in relation with FIG. 4 enables, for example, to estimate a nitrogen site carbon atom concentration in the GaN:C layer 106 of transistor 100 ( FIG. 1 ).
- the method illustrated in FIG. 4 comprises a step (block 402 , Estimate stack capacitance) comprising estimating a value of an electric capacitance, noted C eq , of a stack of layers.
- a step comprising estimating a value of an electric capacitance, noted C eq , of a stack of layers.
- equivalent capacitance C eq is estimated, for example, based on the capacitances of the layers between gate electrode 114 G and the GaN:C layer 106 having its nitrogen site atom concentration desired to be estimated.
- the estimation of equivalent capacitance C eq in the case of transistor 100 is discussed in further detail hereafter in relation with FIG. 5 .
- Step 404 comprises estimating an offset, noted ⁇ V TH , of the threshold voltage V TH of transistor 100 under the effect of the potential V G applied to the gate of transistor 100 .
- step 404 comprises a sub-step (bloc 404 - 1 , Heat device) comprising heating the device, in the present case, transistor 100 .
- Transistor 100 is heated to a temperature in the range from one hundred degrees Celsius (100° C.) to two hundred and fifty degrees Celsius (250° C.), preferably from one hundred and fifty degrees Celsius (150° C.) to two hundred and fifty degrees Celsius (250° C.).
- the temperature to which transistor 100 is heated is then maintained as stable as possible until the end of step 404 .
- Step 404 comprises another sub-step (bloc 404 - 2 , Apply gate stress bias), subsequent to sub-step 404 - 1 .
- Sub-step 404 - 2 comprises applying to the gate of transistor 100 a non-null, preferably negative, gate potential V G .
- the gate potential V G applied to the gate of transistor 100 during sub-step 404 - 2 is smaller than ⁇ 1 V, preferably approximately equal to ⁇ 5 V.
- the potential V G applied to the gate of transistor 100 is equivalent to gate-source bias voltage V GS .
- transistor 100 is submitted to potential V G , or to bias voltage V GS , for a time period in the order of one tenth of a second (0.1 s).
- step 404 - 2 is preceded by an operation (not shown in FIG. 4 ) comprising measuring an initial value of the threshold voltage V TH of transistor 100 .
- the initial value of threshold voltage V TH is subsequently used as a reference to determine the offset ⁇ V TH of the threshold voltage V TH of transistor 100 .
- Step 404 comprises still another sub-step (bloc 404 - 3 , Remove gate stress bias), subsequent to sub-step 404 - 2 .
- Sub-step 404 - 3 comprises temporarily stopping applying a negative potential V G to the gate of transistor 100 .
- Step 404 further comprises another sub-step (bloc 404 - 4 , Measure V TH ), subsequent to sub-step 404 - 3 .
- Sub-step 404 - 4 comprises measuring the threshold voltage V TH of transistor 100 . Operations enabling to obtain a measurement of threshold voltage V TH are discussed in further detail hereafter in relation with FIGS. 8 and 9 .
- threshold voltage V TH is measured during a time period in the range from ten microseconds (10 ⁇ 5 s) to one hundred microseconds (10 ⁇ 4 s), preferably equal to ten microseconds (10 ⁇ 5 s).
- Successive sub-steps 404 - 2 , 404 - 3 , and 404 - 4 are preferably repeated several times during a total duration, noted TD.
- Duration TD is between one second (1 s) and ten thousand seconds (10 4 s), preferably between one hundred seconds (100 s) and ten thousand seconds (10 4 s).
- Duration TD corresponds, to within the interruptions enabling to measure threshold voltage V TH , to a total duration of application of potential V G during step 404 .
- Step 404 comprises still another sub-step (block 404 - 5 , Timing over?), subsequent to sub-step 404 - 4 .
- Sub-step 404 - 5 comprises testing whether duration TD has elapsed or not. If duration TD has not elapsed yet (output “no” of block 404 - 5 ), it is returned to sub-step 404 - 2 of application of potential V G and the operations of successive sub-steps 404 - 2 , 404 - 3 , and 404 - 4 are repeated.
- Step 404 is then continued by proceeding to still another sub-step (block 404 - 6 , pad V TH (t)), subsequent to sub-step 404 - 5 in the case where duration TD has elapsed.
- sub-step 404 - 6 comprises plotting a curve of the variation, over time t, of threshold voltage V TH based on the different values measured during sub-step 404 - 4 .
- Step 404 comprises still another sub-step (block 404 - 7 , Infer ⁇ V TH ), subsequent to sub-step 404 - 6 .
- sub-step 404 - 7 comprises deducing, from the curve obtained during sub-step 404 - 6 , the offset ⁇ V TH of the threshold voltage V TH of transistor 100 under the effect of the application of potential V G during time period TD during step 404 .
- it is based, in order to deduce offset ⁇ V TH , on the initial value of the threshold voltage V TH of transistor 100 such as previously measured at step 404 - 2 of application of gate potential V G .
- Step 406 comprises calculating a surface concentration, noted N S , of nitrogen site carbon in the GaN:C layer of the studied device.
- Surface concentration N S is calculated from:
- surface concentration N S is calculated by applying the following formula:
- a volume concentration, noted N V is then calculated from surface concentration N S and from a partial thickness, noted t eff , of layer 106 .
- Volume concentration N V is for example calculated during a step (not shown in FIG. 4 ) subsequent to step 406 .
- partial thickness t eff is also called effective thickness. Effective thickness t eff is preferably in the order of one hundred nanometers.
- volume concentration N V is calculated by applying the following formula:
- the implementation of the method discussed hereabove in relation with FIG. 4 particularly enables to estimate the nitrogen site surface concentration N S in carbon-doped gallium nitride epitaxial layer 106 ( FIG. 1 ).
- the estimation of surface concentration N S is in particular valid for an area of layer 106 located in the vicinity of the interface between layer 106 and layer 108 ( FIG. 1 ).
- An advantage of the implementation mode discussed in relation with FIG. 4 lies in the fact that the estimation of the nitrogen site carbon surface concentration N S in layer 106 enables to adapt epitaxy parameters of layer 106 .
- epitaxy parameters of layer 106 may be varied to obtain a transistor 100 having satisfactory electric performances (for example, the voltage behavior, the switching frequency, the voltage drop, etc.).
- the nitrogen site carbon surface concentration N S in the layer 106 of this transistor 100 is then estimated.
- other measurements of surface concentration N S in the layers 106 of these other transistors may be performed. A repeatability of a manufacturing process of transistors 100 is thus for example controlled.
- FIG. 5 is a circuit equivalent to portion 124 of the transistor 100 of FIG. 1 .
- FIG. 5 in particular illustrates an implementation mode, in the case of transistor 100 , of the step 402 of the method discussed in relation with FIG. 4 .
- FIG. 5 only shows carbon-doped gallium nitride layer 106 (GaN:C), unintentionally-doped gallium nitride layer 110 (GaN:UID), and alumina layer 116 (Al 2 O 3 ).
- layer 108 is here omitted from stack 124 . It is assumed that:
- Equivalent capacitance C eq corresponds, in this example, to the capacitance of the layers forming a stack separating gate electrode 114 G ( FIG. 1 ) from GaN:C layer 106 having its nitrogen site carbon surface concentration N S desired to be estimated, as discussed in relation with the implementation mode of FIG. 4 .
- capacitances C GaNUID and C Al2O3 are estimated according to respective thicknesses and dielectric permittivities of layers 110 and 116 .
- the respective thicknesses and dielectric permittivities of layers 110 and 116 are preferably theoretically estimated.
- the respective thicknesses and/or dielectric permittivities of layers 110 and 116 are obtained by at least one measurement performed on transistor 100 .
- FIG. 6 is a partial simplified cross-section view of the transistor 100 of FIG. 1 .
- FIG. 6 particularly illustrates an implementation mode, in the case of transistor 100 , of an electric configuration of transistor 100 during sub-step 404 - 2 of the method discussed in relation with FIG. 4 .
- the source electrode 114 S and the drain electrode 114 D of transistor 100 are both set to ground.
- the non-null gate potential V G is imposed, on a gate pad 122 , by a voltage source external to transistor 100 , for example, by a measurement device (not shown).
- FIG. 7 is a timing diagram of the variation, over time t, of the absolute value of the gate potential V G to which the gate electrode 114 G of transistor 100 is taken.
- FIG. 7 partially illustrates an implementation mode of step 404 of the method discussed in relation with FIG. 4 .
- a gate potential V G equal, in absolute value, to a value noted V Gstress , is applied to the gate electrode 114 G of transistor 100 .
- Source electrode 114 S being grounded, this amounts to applying, between gate electrode 114 G and source electrode 114 S, a bias voltage V GS equal to V Gstress .
- Gate potential V G is maintained substantially equal to value V GStress until a time t 1 , subsequent to time t 0 .
- a substantially null potential V G is applied to the gate electrode 114 G of transistor 100 . Then, from time t 1 and until a time t 2 subsequent to time t 1 , a measurement of the threshold voltage V TH of transistor 100 is measured.
- the measurement of threshold voltage V TH is performed, as illustrated in FIG. 7 , by applying in stages, to the gate electrode 114 G of transistor 100 , increasing values of gate potential V G . Although this is not shown in FIG. 7 , a measurement of the drain current, noted I D , is performed at each stage, and thus for each new value of potential V G .
- a new cycle of application of potential V GStress and of measurement of threshold voltage V TH then starts at time t 2 .
- a plurality of cycles of this type may thus follow one another between time t 2 and a time t 3 , subsequent to time t 2 , at which an ultimate measurement 404 - 4 of the threshold voltage V TH of transistor 100 starts.
- Such an ultimate measurement 404 - 4 of the threshold voltage V TH of transistor 100 ends at a time t 4 , subsequent to time t 3 . Assuming that duration TD has elapsed between times t 3 and t 4 , the gate electrode 114 G of transistor 100 is taken to a null potential V G from time t 4 . At time t 4 , it can then be proceeded to the sub-step 404 - 6 of the method discussed in relation with FIG. 4 .
- FIG. 8 is a graph of the variation of a drain current according to a gate potential.
- FIG. 8 illustrates an example of a curve 800 of the variation, during sub-step 404 - 4 of measurement of threshold voltage V TH , of the drain current ID of transistor 100 according to gate potential V G .
- curve 800 of the variation of gate current ID according to the gate potential V G of transistor 100 has:
- the value of potential V G for which drain current ID starts notably increasing in other words the value of potential V G for which it is passed from portion 800 - 1 of curve 800 to the portion 800 - 2 of curve 800 is approximately equal to the threshold voltage V TH of transistor 100 .
- the measurement of the drain current ID of transistor 100 according to gate potential V G thus is a way to access the threshold voltage V TH of transistor 100 .
- FIG. 9 is a graph of the variation of a capacitance according to a gate potential.
- FIG. 9 illustrates an example of a curve 900 of the variation, during sub-step 404 - 4 ( FIG. 4 ) of measurement of threshold voltage V TH , of a gate capacitance C of transistor 100 according to gate potential V G .
- curve 900 of the variation of gate capacitance C according to the gate potential V G of transistor 100 has:
- curve 900 has an inflexion point 900 - 3 marking a separation between portion 900 - 1 and portion 900 - 2 .
- the value of potential V G corresponding to the inflexion point 900 - 3 of curve 900 in other words the value of potential V G for which it is passed from portion 900 - 1 of curve 900 to portion 900 - 2 of curve 900 , is approximately equal to the threshold voltage V TH of transistor 100 .
- the measurement of capacitance C of transistor 100 according to gate potential V G thus is another way to access the threshold voltage V TH of transistor 100 .
- FIG. 10 is a graph of the time variation for different temperatures of an offset of a threshold voltage of an electronic component.
- FIG. 10 illustrates examples of curves 1000 - 1 , 1000 - 2 , 1000 - 3 , 1000 - 4 , 1000 - 5 , 1000 - 6 , 1000 - 7 , and 1000 - 8 of the variation, over time t (in seconds), of the offset ⁇ V TH (in volts) of the threshold voltage V TH of transistor 100 .
- transistor 100 has a 0.25- ⁇ m gate length L G ( FIG. 1 ) and a 200- ⁇ m gate width.
- Curves 1000 - 1 to 1000 - 8 are obtained by applying a potential V Gstress ( FIG. 7 ) of approximately ⁇ 5 V.
- curves 1000 - 1 to 1000 - 8 of FIG. 10 for example result from the implementation of step 404 of the method discussed in relation with FIG. 4 for different heating temperatures of transistor 100 . More particularly, in the example of FIG. 10 , curves 1000 - 1 to 1000 - 8 correspond to a heating of transistor 100 , during step 404 , at temperatures respectively equal to twenty-five degrees Celsius (25° C.), seventy five degrees Celsius (75° C.), one hundred degrees Celsius (100° C.), one hundred and twenty five degrees Celsius (125° C.), one hundred and fifty degrees Celsius (150° C.), one hundred and seventy five degrees Celsius (175° C.), two hundred degrees Celsius (200° C.), and two hundred and twenty five degrees Celsius (225° C.).
- the curves 1000 - 1 to 1000 - 8 of FIG. 10 each have two time constants, noted ⁇ 1 and ⁇ 2 , respectively associated with two plateaus.
- Curve 1000 - 8 particularly exhibits a plateau between approximately one hundred microseconds (10 ⁇ 4 s) and ten milliseconds (10 ⁇ 2 s), having time constant ⁇ 1 associated therewith, and another plateau starting around one hundred seconds (10 2 s), having time constant ⁇ 2 associated therewith.
- the difference between the two plateaus enables, as illustrated in FIG. 10 , to estimate the value of offset ⁇ V TH .
- FIG. 11 is a graph of the time variation for different temperatures of an offset of a threshold voltage of another electronic component.
- FIG. 11 illustrates examples of curves 1100 - 1 , 1100 - 2 , 1100 - 3 , 1100 - 4 , 1100 - 5 , 1100 - 6 , 1100 - 7 , and 1100 - 8 of the variation over time t (in seconds) of the offset ⁇ V TH (in volts) of the threshold voltage V TH of transistor 100 .
- the curves 1100 - 1 to 1100 - 8 of FIG. 11 are obtained in conditions similar to those of curves 1000 - 1 to 1000 - 8 of FIG. 10 , respectively, except for the fact that, in FIG. 11 , transistor 100 has a gate length equal to 20 ⁇ m.
- FIG. 12 is a partial simplified cross-section view of an example of a capacitor 1200 .
- capacitor 1200 is a metal-oxide-semiconductor (MOS) capacitor.
- Capacitor 1200 comprises:
- Layer 1204 and layer 1206 of capacitor 1200 are respectively similar to the layers 106 and 116 of the transistor 100 of FIG. 1 .
- the implementation mode of the method discussed hereabove in relation with FIG. 4 may be adapted to the estimation of a nitrogen site carbon concentration in the GaN:C layer 1204 of MOS capacitor 1200 .
- Potential V 1 may possibly be for example substantially null while potential V 2 is for example similar to the potential V G discussed hereabove in relation with FIG. 7 .
- Threshold voltage V TH corresponds, in the case of MOS capacitor 1200 , to a limiting voltage between an inversion mode and a depletion mode of MOS capacitor 1200 .
- FIG. 13 is a partial simplified cross-section view of the portion 124 of FIG. 2 of the transistor 100 of FIG. 1 in still another operating mode.
- FIG. 13 particularly illustrates a situation where a gate potential V G greater than threshold voltage V TH starts being applied to transistor 100 .
- charges 1300 forming part of the electron channel 302 formed between the two portions of the two-dimensional electron gas 2DEG are submitted to an electric field (symbolized by arrows 1302 ) directed towards gate electrode 114 G.
- This causes the trapping, in gate oxide layer 116 , of charges 1304 originating from electron channel 302 .
- the operating mode illustrated in FIG. 13 is called “accumulation state” due to the fact that charges, here electrons, are accumulated in gate oxide layer 116 .
- FIG. 14 is a partial simplified cross-section view of the portion 124 of FIG. 2 of the transistor 100 of FIG. 1 in still another operating mode.
- FIG. 14 particularly illustrates a situation where a gate potential V G greater than threshold voltage V TH has been applied for several seconds to transistor 100 .
- the charges 1304 trapped in gate oxide layer 116 each generate an electric field (symbolized by arrows 1306 ).
- the electric field 1306 generated by each charge 1304 tends to opposite the electric field 1302 of the charges 1300 of electron channel 302 .
- bias temperature instability This phenomenon particularly causes a progressive degradation of the electric performance of transistor 100 .
- Such a phenomenon particularly seems to be responsible for the offset ⁇ V TH of the threshold voltage V TH of transistor 100 .
- FIG. 15 is a partial simplified view of a transistor 1500 in an operating mode.
- Transistor 1500 is an n-channel MOS transistor (nMOS) comprising:
- regions 1508 - 1 and 1508 - 2 are respectively connected to the source and to the drain of transistor 1500 . It is further assumed that:
- Charges 1510 originate from an electron channel 1512 (Electron channel) formed in layer 1502 between regions 1508 - 1 and 1508 - 2 , and at the interface between layer 1502 and layer 1504 .
- the trapping of electrons 1510 in layer 1504 causes a positive offset ⁇ V TH of threshold voltage V TH , called positive bias temperature instability (pBTI).
- pBTI positive bias temperature instability
- FIG. 16 is a partial simplified view of another transistor 1600 in another operating mode.
- Transistor 1600 is a p-channel MOS transistor (pMOS) comprising:
- regions 1608 - 1 and 1608 - 2 are respectively connected to the source and to the drain of transistor 1600 . It is further assumed that:
- Charges 1610 originate from a hole channel 1612 (Hole channel) formed in layer 1602 between regions 1608 - 1 and 1608 - 2 , at the interface between layer 1602 and layer 1604 .
- Hole channel hole channel
- the trapping of holes 1510 in layer 1604 causes a negative offset ⁇ V TH of threshold voltage V TH , called negative bias temperature instability (nBTI).
- nBTI negative bias temperature instability
- the transistor 100 discussed in relation with FIG. 1 being a transistor of nMOS type, that is, exhibiting no holes, it is not expected to observe a negative offset ⁇ V TH of the threshold voltage V TH of transistor 100 when a negative potential V G is applied to its gate.
- the inventors have observed that the fact of taking the gate of transistor 100 to a negative potential V G progressively causing, over time, a negative offset ⁇ V TH .
- FIG. 17 is a graph of the variation, over time tin seconds (s), of an offset ⁇ V TH in volts (V) of a threshold voltage V TH of electronic components, for example, transistors similar to transistor 100 but having different gate lengths L G .
- the graph of FIG. 17 particularly comprises:
- the curves 1700 , 1702 , 1704 , and 1706 of FIG. 17 are obtained, for example, for a potential V Gstress of ⁇ 5 V, a gate width of 200 ⁇ m, and a temperature of twenty-five degrees Celsius (25° C.). As illustrated in FIG. 17 , a decrease in the gate length L G of transistor 100 tends to increase the offset ⁇ V TH of threshold voltage V TH .
- FIG. 17 further illustrates the presence, for each curve 1700 , 1702 , 1704 , and 1706 , of the time constants ⁇ 1 and ⁇ 2 previously described in relation with FIG. 10 .
- FIG. 18 is an Arrhenius plot associated with time constant ⁇ 1 .
- FIG. 18 particularly illustrates, for different gate lengths L G , the variation of the natural logarithm of time constant ⁇ 1 (ln( ⁇ 1 )) according to a quotient noted q/K B T (in eV ⁇ 1 ), where:
- the graph of FIG. 18 particularly comprises:
- the curves 1800 , 1802 , 1804 , and 1806 of FIG. 18 are obtained, for example, for a potential V Gstress of ⁇ 5 V and a gate length of 200 ⁇ m.
- Curves 1800 , 1802 , 1804 , and 1806 are lines substantially having a same slope, corresponding to an activation energy equal to approximately 0.8 eV.
- FIG. 19 is an Arrhenius plot associated with time constant ⁇ 2 .
- FIG. 19 particularly illustrates, for different gate lengths L G , the variation of the natural logarithm of time constant ⁇ 2 (ln( ⁇ 2 )) according to quotient q/K B T (in eV ⁇ 1 ) described hereabove in relation in FIG. 18 .
- the graph of FIG. 19 particularly comprises:
- curves 1900 , 1902 , 1904 , and 1906 of FIG. 19 are obtained, for example, for a potential V Gstress of ⁇ 5 V and a gate length of 200 ⁇ m.
- Curves 1900 , 1902 , 1904 , and 1906 are lines substantially having a same slope, corresponding to an activation energy equal to approximately 0.8 eV.
- the inventors have observed that the activation energies associated with time constants ⁇ 1 and ⁇ 2 were both substantially equal to 0.8 eV. It is considered that this corresponds to an ionization energy of the nitrogen site carbon atoms in a gallium nitride layer.
- FIG. 20 is a graph of the variation, according to a depth, in arbitrary units, of a chemical species concentration (Intensity), in arbitrary units.
- the depth is, in FIG. 20 , referenced to gate electrode 114 G ( FIG. 1 ).
- the graph of FIG. 20 is, for example, obtained by secondary ion mass spectrometry (SIMS) at the upper surface of portion 124 of transistor 100 ( FIG. 1 ).
- SIMS spectroscopy is for example performed after a wet etching of TEOS layer 120 by a 30 min exposure to a 10% hydrofluoric acid (HF) solution. This enables to improve the resolution of the measurement.
- HF hydrofluoric acid
- the graph of FIG. 20 comprises four depth areas:
- curve 2006 reveals a high carbon nitride concentration in carbon-doped gallium nitride layer 106 .
- Curve 2006 further reveals a large carbon population in the vicinity of the interface between layer 116 and layer 110 .
- FIG. 21 is a partial simplified cross-section view of a normally-off transistor 2100 .
- Transistor 2100 has, for example, a structure similar to that of transistor 100 as discussed hereabove in relation with FIG. 1 .
- Transistor 2100 particularly comprises:
- layer 116 is “U”-shaped. Layer 116 totally crosses layer 112 and penetrates into layer 110 . Gate electrode 114 G is located on top of and in contact with layer 116 . In other words, transistor 2100 has a recessed gate in GaN:UID layer 110 .
- gate length L G corresponds to the length of the lower portion of the “U” formed by layer 116 .
- FIG. 22 is a partial simplified cross-section view of a normally-on transistor 2200 .
- the transistor 2200 of FIG. 22 comprises elements common with the transistor 2100 of FIG. 21 . The common elements will not be detailed again hereafter.
- the transistor 2200 of FIG. 22 differs from the transistor 2100 of FIG. 21 mainly in that transistor 2200 has a “non-recessed” gate.
- gate oxide layer 116 Al 2 O 3
- the two-dimensional electron gas 2DEG is formed in layer 110 (GaN:UID), in the vicinity of the interface between layer 110 and sub-layer 112 - 1 (AlGaN).
- FIG. 23 is a graph of the variation, over time (Stress time), in seconds (s), of an offset ⁇ V TH of a threshold voltage, in volts (V), of the transistors 2100 and 2200 of FIGS. 21 and 22 , respectively.
- Graph 23 particularly comprises:
- Transistors 2100 and 2200 have a gate length L G equal to 1 ⁇ m and a gate width equal to 100 ⁇ m.
- Curves 2302 and 2304 are obtained by applying bias voltages, respectively, of ⁇ 5 V and of ⁇ 10 V, and by heating transistors 2100 and 2200 to a temperature of one hundred and fifty degrees Celsius (150° C.).
- the curve 2302 corresponding to normally-off transistor 2100 has two stages having time constants ⁇ 1 and ⁇ 2 associated therewith, as discussed hereabove in relation with FIG. 10 .
- the curve 2304 corresponding to normally-on transistor 2200 has a single stage having another time constant associated therewith.
- the graph of FIG. 23 seems to indicate that time constant ⁇ 2 corresponds to GaN:C layer 106 .
- FIG. 24 is a mapping of ionized traps inside of portion 124 of FIG. 2 of the transistor 100 of FIG. 1 in an operating mode.
- the traps here correspond to nitrogen site carbon atoms in GaN:C layer 106 . It is here considered, for simplification, that layer 108 is omitted from stack 124 .
- Transistor 100 has a gate length L G equal to 1 ⁇ m.
- FIG. 24 more particularly illustrates a situation prior to the application of potential V GStress ( FIG. 7 ) to the gate of transistor 100 .
- V GStress FIG. 7
- most of the ionized traps of layer 106 are located under gate oxide layer 116 , in an area 2402 located close to the interface between layer 106 and layer 110 .
- Areas 2404 distant from the interface between layer 106 and layer 110 that is, more distant from this interface than area 2402 , however have a lower ionized trap concentration.
- FIG. 25 is a mapping of ionized traps inside of the portion 124 of FIG. 2 of the transistor 100 of FIG. 1 in another operating mode.
- the traps here again correspond to nitrogen site carbon atoms in GaN:C layer 106 . It is here again considered, for simplification, that layer 108 is omitted from stack 124 .
- Transistor 100 has a gate length L G equal to 1 ⁇ m.
- FIG. 25 more particularly illustrates a situation 1 ⁇ s after the application, for 10 3 s, of potential V GStress ( FIG. 7 ) to the gate of transistor 100 .
- Potential V GStress is here equal to ⁇ 5 V.
- most of the ionized traps of layer 106 are located on either side of gate oxide layer 116 , in areas 2502 located close to the interface between layer 106 and layer 110 .
- An area 2504 located under layer 116 and close to the interface between layer 106 and layer 110 has, as illustrated in FIG. 25 , a lower ionized trap concentration.
- Such a lower ionized trap concentration under the gate oxide layer 116 of transistor 100 seems to be responsible for the offset ⁇ V TH of the threshold voltage of transistor 100 .
- FIG. 26 is a graph of the variation, according to a depth (Depth), of a conduction band energy (E C ), in electron-volts (eV), as compared with the Fermi level.
- FIG. 26 illustrates, in particular, the variation of conduction band energy E C :
- the graph of FIG. 26 comprises three depth areas:
- FIG. 27 is a graph of the variation, over time, in seconds (s), of the conduction band energy (E C ), in electron-volts (eV), referenced to the Fermi level.
- Energy E C is for example measured at a depth of approximately 1 nm under the middle of the gate of transistor 100 .
- Curves 2702 and 2704 are comparable with a dynamic variation of the threshold voltage V TH of transistor 100 .
- the offset ⁇ V TH of the threshold voltage V TH of transistor 100 becomes null after a time period approximately equal to 10 s after the application of gate potential V G .
Abstract
Description
-
- a second gallium nitride layer located on the first layer; and
- a third alumina layer, penetrating into the second layer,
- the first electrode being located on top of and in contact with the third layer.
-
- LGS for a distance separating a lower portion of the
source electrode 114S from the vertical portion of the “T” formed bygate electrode 114G; - LGD for a distance separating the vertical portion of the “T” formed by
gate electrode 114G from a lower portion ofdrain electrode 114D; and - LG the length of the vertical portion of the “T” formed by
gate electrode 114G.
- LGS for a distance separating a lower portion of the
-
- the equivalent capacitance Ceq, obtained at the end of
step 402; - the offset ΔVTH of threshold voltage VTH, obtained at the end of
step 404; and - the elementary charge, noted q, approximately equal to 1.6·10−19 C.
- the equivalent capacitance Ceq, obtained at the end of
-
-
layer 110 has a capacitance noted CGaNUID; and -
layer 116 has a capacitance noted CAl2O3.
-
-
- the source potential VS to which the
source electrode 114S oftransistor 100 is taken is substantially null (VS=0 V); - the drain potential VD to which the
drain electrode 114D oftransistor 100 is taken is substantially null (VD=0 V); and - the gate potential VG to which the
gate electrode 114G oftransistor 100 is taken is non null (VG≠0 V), preferably negative.
- the source potential VS to which the
-
- a portion 800-1 (on the left-hand side, in
FIG. 8 ) where the drain current ID is substantially null; and - another portion 800-2 (on the right-hand side, in
FIG. 8 ) when drain current ID progressively increases from a value approximately equal to zero up to a maximum value, noted ID max.
- a portion 800-1 (on the left-hand side, in
-
- a portion 900-1 (on the left-hand side, in
FIG. 9 ) where capacitance C increases from a minimum value, noted CMIN, until an intermediate value, noted CINT; and - another portion 900-2 (on the right-hand side in
FIG. 9 ) where capacitance C increases from value CINT to a maximum value, noted CMAX.
- a portion 900-1 (on the left-hand side, in
-
- an electrode 1202 taken to a potential V1;
- a carbon-doped gallium nitride layer 1204 (GaN:C) located on top of and in contact with electrode 1202;
- an alumina layer 1206 (Al2O3), located on top of and in contact with layer 1204; and
- another
electrode 1208, located on top of and in contact withlayer 1206, and taken to a potential V2.
-
- a layer 1502 (p-type semiconductor) made of a p-type doped semiconductor;
- a gate oxide layer 1504 (Gate oxide), located on top of and in contact with a portion of
layer 1502; - a gate metal layer 1506 (Gate metal), located on top of and in contact with
gate oxide layer 1504; and - two regions 1508-1 (n-type) and 1508-2 (n-type) made of n-type doped semiconductor material, formed in
layer 1502 on either side ofgate oxide layer 1504.
-
- the source of
transistor 1500 is taken to a null potential, for example, the ground; - the drain of
transistor 1500 is taken to a positive potential; and - the gate of
transistor 1500 is taken to a positive potential greater than the threshold voltage oftransistor 1500.
- the source of
-
- a layer 1602 (n-type semiconductor) made of an n-type doped semiconductor material;
- a gate oxide layer 1604 (Gate oxide), located on top of and in contact with a portion of
layer 1602; - a gate metal layer 1606 (Gate metal), located on top of and in contact with
gate oxide layer 1604; and - two regions 1608-1 (p-type) and 1608-2 (p-type) made of a p-type doped semiconductor material, formed in
layer 1602 on either side ofgate oxide layer 1604.
-
- the source of
transistor 1600 is taken to a null potential, for example, the ground; - the drain of
transistor 1600 is taken to a negative potential; and - the gate of
transistor 1600 is taken to a negative potential smaller than the threshold voltage oftransistor 1600.
- the source of
-
- a
curve 1700 of the variation of the offset ΔVTH of the threshold voltage VTH of atransistor 100 having a gate length LG equal to 2 μm (LG=2 μm); - a
curve 1702 of the variation of the offset ΔVTH of the threshold voltage VTH of atransistor 100 having a gate length LG equal to 1 μm (LG=1 μm); - a
curve 1704 of the variation of the offset ΔVTH of the threshold voltage VTH of atransistor 100 having a gate length LG equal to 0.5 μm (LG=0.5 μm); and - a
curve 1706 of the variation of the offset ΔVTH of the threshold voltage VTH of atransistor 100 having a gate length LG equal to 0.25 μm (LG=0.25 μm).
- a
-
- q stands for the elementary charge, approximately equal to 1.6·10−19 C;
- KB stands for Boltzmann's constant, approximately equal to 8.6·10−5 eV·K−1; and
- T stands for the absolute temperature, expressed in degrees Kelvin.
-
- a
curve 1800 corresponding to atransistor 100 having a gate length LG equal to 2 μm (LG=2 μm); - a
curve 1802 corresponding to atransistor 100 having a gate length LG equal to 1 μm (LG=1 μm); - a
curve 1804 corresponding to atransistor 100 having a gate length LG equal to 0.5 μm (LG=0.5 μm); and - a
curve 1806 corresponding to atransistor 100 having a gate length LG equal to 0.25 μm (LG=0.25 μm).
- a
-
- a
curve 1900 corresponding to atransistor 100 having a gate length LG equal to 2 μm (LG=2 μm); - a
curve 1902 corresponding to atransistor 100 having a gate length LG equal to 1 μm (LG=1 μm); - a
curve 1904 corresponding to atransistor 100 having a gate length LG equal to 0.5 μm (LG=0.5 μm); and - a
curve 1906 corresponding to atransistor 100 having a gate length LG equal to 0.25 μm (LG=0.25 μm).
- a
-
- an area (Gate metallization) corresponding to the thickness of
gate electrode 114G; - another area (Al2O3) corresponding to
gate oxide layer 116; - still another area (GaN:UID+BB) corresponding to the cumulated thicknesses of
layers - still another area (GaN:C) corresponding to layer 106.
- an area (Gate metallization) corresponding to the thickness of
-
- a curve 202 shows a variation of the aluminum oxide concentration;
- another
curve 2004 shows a gallium nitride concentration variation; - still another
curve 2006 shows a carbon nitride concentration variation; and - still another
curve 2008 shows a carbon concentration variation.
-
- silicon substrate 102 (Si-8″ substrate);
- transition layer 104 (Transition layer);
- carbon-doped gallium nitride layer 106 (GaN:C);
- barrier layer 108 (Back-barrier);
- unintentionally doped gallium nitride layer 110 (GaN:UID);
-
layer 112, comprising aluminum gallium sub-layer 112-1 (AlGaN) and passivation sub-layer 112-2 (Passivation layers); - gate oxide layer 116 (Al2O3);
-
gate metal electrode 114G (Gate metal); and - layer 118 (Dielectric) based on dielectric materials.
-
- gate oxide layer 116 (Al2O3) penetrates into passivation sub-layer 112-2; and
-
gate electrode 114G (Gate metal), located on top of and in contact withlayer 116, is covered with layer 118 (Dielectric).
-
- a
curve 2302 corresponding to the variation of the offset ΔVTH of the threshold voltage of the normally-off transistor 2100 ofFIG. 21 ; and - another
curve 2304 corresponding to the variation of the offset ΔVTH of the threshold voltage of the normally-ontransistor 2200 ofFIG. 22 .
- a
-
- along a cross-section AA in the operating mode of
FIG. 24 (curve 2602); and - along cross-section AA in the operating mode of
FIG. 25 (curve 2604).
- along a cross-section AA in the operating mode of
-
- an area (Al2O3) corresponding to
gate oxide layer 116; - another area (GaN:UID) corresponding to layer 110; and
- still another area (GaN:C) corresponding to layer 106.
- an area (Al2O3) corresponding to
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1913213 | 2019-11-26 | ||
FR1913213A FR3103558B1 (en) | 2019-11-26 | 2019-11-26 | Method for evaluating a concentration |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210156812A1 US20210156812A1 (en) | 2021-05-27 |
US11761920B2 true US11761920B2 (en) | 2023-09-19 |
Family
ID=69743415
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/094,621 Active 2041-09-06 US11761920B2 (en) | 2019-11-26 | 2020-11-10 | Concentration estimation method |
Country Status (3)
Country | Link |
---|---|
US (1) | US11761920B2 (en) |
EP (1) | EP3828920A1 (en) |
FR (1) | FR3103558B1 (en) |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3062975B2 (en) | 1991-12-10 | 2000-07-12 | 株式会社ジャパンエナジー | Method for manufacturing semiconductor device |
US6151559A (en) * | 1997-06-21 | 2000-11-21 | Williams; Thomas H. | System and method for characterizing undesirable noise of a signal path within a selected frequency band |
US20100264511A1 (en) * | 2001-08-13 | 2010-10-21 | Michael J Haji-Sheikh | Providing current control over wafer borne semiconductor devices using trenches |
US20160056085A1 (en) * | 2014-08-21 | 2016-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device testing apparatus, semiconductor device testing method, and semiconductor device manufacturing method |
US20160313260A1 (en) * | 2015-04-27 | 2016-10-27 | The Trustees Of Dartmouth College | Systems, probes, and methods for dielectric testing of wine in bottle |
WO2018123285A1 (en) | 2016-12-27 | 2018-07-05 | 住友化学株式会社 | Method for manufacturing group-iii nitride laminate, inspection method, and group-iii nitride laminate |
JP2019137566A (en) | 2018-02-07 | 2019-08-22 | 信越半導体株式会社 | Method for measuring carbon concentration in silicon crystal |
US20200262526A1 (en) * | 2015-12-23 | 2020-08-20 | Koninklijke Philips N.V. | Marine structure |
US20210392723A1 (en) * | 2017-11-28 | 2021-12-16 | National Institute Of Advanced Industrial Science And Technology | Microwave processing apparatus, microwave processing method, and chemical reaction method |
US20220057338A1 (en) * | 2018-09-14 | 2022-02-24 | Tokyo Institute Of Technology | Integrated circuit and sensor system |
-
2019
- 2019-11-26 FR FR1913213A patent/FR3103558B1/en active Active
-
2020
- 2020-10-27 EP EP20204097.8A patent/EP3828920A1/en active Pending
- 2020-11-10 US US17/094,621 patent/US11761920B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3062975B2 (en) | 1991-12-10 | 2000-07-12 | 株式会社ジャパンエナジー | Method for manufacturing semiconductor device |
US6151559A (en) * | 1997-06-21 | 2000-11-21 | Williams; Thomas H. | System and method for characterizing undesirable noise of a signal path within a selected frequency band |
US20100264511A1 (en) * | 2001-08-13 | 2010-10-21 | Michael J Haji-Sheikh | Providing current control over wafer borne semiconductor devices using trenches |
US20160056085A1 (en) * | 2014-08-21 | 2016-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device testing apparatus, semiconductor device testing method, and semiconductor device manufacturing method |
US20160313260A1 (en) * | 2015-04-27 | 2016-10-27 | The Trustees Of Dartmouth College | Systems, probes, and methods for dielectric testing of wine in bottle |
US20200262526A1 (en) * | 2015-12-23 | 2020-08-20 | Koninklijke Philips N.V. | Marine structure |
WO2018123285A1 (en) | 2016-12-27 | 2018-07-05 | 住友化学株式会社 | Method for manufacturing group-iii nitride laminate, inspection method, and group-iii nitride laminate |
US20210392723A1 (en) * | 2017-11-28 | 2021-12-16 | National Institute Of Advanced Industrial Science And Technology | Microwave processing apparatus, microwave processing method, and chemical reaction method |
JP2019137566A (en) | 2018-02-07 | 2019-08-22 | 信越半導体株式会社 | Method for measuring carbon concentration in silicon crystal |
US20220057338A1 (en) * | 2018-09-14 | 2022-02-24 | Tokyo Institute Of Technology | Integrated circuit and sensor system |
Non-Patent Citations (3)
Title |
---|
Fang et al., Deep traps in AlGaN/GaN heterostructures studied by deep level transient spectroscopy: Effect of carbon concentration in GaN buffer layers. Journal of Applied Physics. Sep. 15, 2010;108(6):063706. |
FR1913213, Jul. 31, 2020, Preliminary Search Report. |
Preliminary Search Report for French Application No. 1913213, dated Jul. 31, 2020. |
Also Published As
Publication number | Publication date |
---|---|
US20210156812A1 (en) | 2021-05-27 |
EP3828920A1 (en) | 2021-06-02 |
FR3103558A1 (en) | 2021-05-28 |
FR3103558B1 (en) | 2021-11-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8044432B2 (en) | Low density drain HEMTs | |
US20210013314A1 (en) | Vertical gallium oxide (ga2o3) power fets | |
TWI406413B (en) | Low density drain hemts | |
US7972915B2 (en) | Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs | |
US7932539B2 (en) | Enhancement-mode III-N devices, circuits, and methods | |
CN101336482B (en) | Low density drain hemts | |
Chindalore et al. | Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers | |
US20210358749A1 (en) | Semiconductor wafer, electronic device, method of performing inspection on semiconductor wafer, and method of manufacturing electronic device | |
US8592951B2 (en) | Semiconductor wafer having W-shaped dummy metal filling section within monitor region | |
Le Royer et al. | Normally-OFF 650V GaN-on-Si MOSc-HEMT transistor: benefits of the fully recessed gate architecture | |
Zhu et al. | Threshold voltage shift and interface/border trapping mechanism in Al 2 O 3/AlGaN/GaN MOS-HEMTs | |
US11761920B2 (en) | Concentration estimation method | |
Kilchytska et al. | Accurate effective mobility extraction by split CV technique in SOI MOSFETs: Suppression of the influence of floating-body effects | |
Kammeugne et al. | Parasitic Capacitance Analysis in Short Channel GaN MIS-HEMTs | |
Chanana | Issues in current-voltage/capacitance-voltage traces-based MIS characterisation that improves understanding for a better design of n-channel MOSFETs on Si and SiC | |
Kumar et al. | Dielectric thickness and fin width dependent OFF-state degradation in AlGaN/GaN SLCFETs | |
Yang et al. | Substrate bias enhanced trap effects on time-dependent dielectric breakdown of GaN MIS-HEMTs | |
Heuken et al. | Localization and analysis of surface charges trapped in AlGaN/GaN HEMTs using multiple secondary MIS gates | |
KOM KAMMEUGNE et al. | In Depth Parasitic Capacitance Analysis on Gan-Hemts with Recessed Mis Gate | |
Putcha et al. | Interpretation and modelling of dynamic-R ON kinetics in GaN-on-Si HEMTs for mm-wave applications | |
Rai et al. | Improved lumped element model for GaN-based MIS-HEMT gate stack in the spill-over regime | |
Rathaur et al. | Time-dependent multiple gate voltage reliability of hybrid ferroelectric charge trap gate stack (FEG) GaN HEMT for power device applications | |
Thakur et al. | Analysis of interface trap charges and densities using capacitance-voltage (CV) and conductance voltage (GV) methods in steep retrograded Al2O3, ZrO2 and HfO2 based gate all around FinFETs | |
Kammeugne et al. | In Depth Parasitic Capacitance Analysis on GaN-HEMTs with Recessed MIS Gate | |
Roll et al. | Effect of Gate Voltage Stress on InGaAs MOSFET With HfO 2 or Al 2 O 3 Dielectric |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
AS | Assignment |
Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, FRANCE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIEY, ABYGAEL;JAUD, MARIE-ANNE;VANDENDAELE, WILLIAM;REEL/FRAME:054693/0569 Effective date: 20201201 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction |