TWI406413B - Low density drain hemts - Google Patents

Abstract

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Description

Low density absorber HEMTs Cross-reference to related applications

The present application claims priority to U.S. Provisional Patent Application No. 60/740, filed on Nov. 29, 2005, and to U.S. Provisional Application Serial No

The present application relates to a method for suppressing breakdown voltage and current collapse suppression in a normally-off high electron mobility transistor ("HEMT"), and more particularly to fabricating aluminum gallium nitride using an electrodeless absorber side surface field engineering design. Gallium nitride ("AlGaN/GaN") HEMT, resulting in a "low density absorber" HEMT.

Excessive electric fields can cause problems in semiconductor devices. (One type of problem is hot carriers, where high-energy electrons or holes are fully capable of passing through the medium; another type of problem is avalanche, where conduction becomes uncontrolled.) Even designed to have a minimum logic voltage In working devices, it is important to ensure that the voltage does not change too sharply at the sinker boundary; and in devices used to switch higher voltages, there is an increasing need to minimize the peak electric field.

Absorbent engineering design has been one of the longest-standing sub-areas of integrated device development, dating back to the original LDD recommendations of 1974. See Blanchard's "High Voltage Simultaneous Diffusion Grid CMOS", 9 IEEE J.S.S.C. 103 (1974). Many techniques have been used to control the peak electric field in high voltage devices, typically including various configurations of field plates and non-carrier diffusion.

This long-standing developmental challenge is particularly relevant to the newer areas of enhanced mode ("E-type") III-N HEMT. The normally-off AlGaN/GaN HEMTs are required for microwave power amplifiers and power electronics applications because they provide simplified circuit configuration and operating conditions that are beneficial to device safety. However, normally-off AlGaN/GaN HEMTs typically exhibit lower maximum sink currents than their normally-on counterparts, especially at threshold voltages that increase to approximately +1V to ensure 2DEG channels at zero gate bias. When it is completely cut off and provides additional work safety. In order to compensate for the reduction in maximum current and to achieve the same power handling capability, the breakdown voltage (V _{B K} ) needs to be further improved, but preferably at the expense of increased gate-sink distance (which inevitably increases device size). . The use of a field plate connected to a gate or source electrode can effectively increase V _{B K} by modifying the surface field distribution. However, the gate plates of the gate terminals may introduce additional gate capacitances (C _{G S} and C _{G D} ) that reduce the gain and cutoff frequency of the device. Source-extreme field plates have been used to achieve increased V _{B K} and mitigate gain reduction, but this requires a thick dielectric layer between the gate and the field plates.

One problem in GaN devices is current collapse: when the source-sink voltage reaches a level at which impact ionization may occur, the maximum current carried by the device may actually decrease. It has been shown that this undesirable effect is caused by a trapping phenomenon in which the intermediate band gap state is occupied by hot electrons.

Low density absorber HEMT

The present application discloses a new method of controlling the electric field in a field effect transistor. The disclosed method and apparatus are used to fabricate a HEMT that modifies the surface field distribution between the gate and the sink of a normally-off HEMT. Part or all of the area between the gate and the sink can be converted to a region of low density 2DEG using CF ₄ plasma processing to form a low density absorber ("LDD") HEMT. The off-state breakdown voltage can be increased, and the current collapse can be completely suppressed in the LDD-HEMT without significant degradation in gain and cutoff frequency.

In various embodiments, the disclosed innovations provide at least one or more of the following advantages: It is allowed to modify the surface field distribution in a normally-off HEMT without using a field plate electrode.

. It is easy to achieve an asymmetrical modification of only the suction side.

. No change in topology is required: the addition of additional fixed charge in the wide band gap barrier does not affect the physical topology.

. Provides increased breakdown voltage and suppressed current collapse without degradation of gain or cutoff frequency.

. No additional process steps are added to those process steps that are already required for enhanced + depleted III-N production.

. Surface state compensation and solution compensation are reduced or prevented.

. Current collapse is reduced or prevented.

A number of innovative theories of the present application are described with particular reference to the presently preferred embodiments, by way of example and not limitation.

The present application provides a simple way to modify the surface field distribution between the gate and the absorber without the use of field plate electrodes. Field modification is achieved by effectively forming a low density absorber ("LDD") by changing part or all of the area between the gate and the absorber to a region of low DEDE 2DEG. With the same device size, the off-state breakdown voltage V _{B K is increased} from 60V in the HEMT without LDD to more than 90V in devices with LDD. No degradation of f _t was observed in the LDD-HEMT, and _a slight improvement in power gain and f _{m a x was} observed. In addition, current collapse can be completely suppressed in the LDD-HEMT.

Instance

The AlGaN/GaNLDD-HEMT was fabricated in accordance with the processes shown in Figs. 47A to 47F. The epitaxial structure and device fabrication flow of the LDD-HEMT on a sapphire substrate is similar to that used in Figure 3 except that in addition to the additional step shown in Figure 47D, it defines the LDD region at the end of device processing. After the window of the low density absorber region is defined, the CF ₄ plasma treatment at 150 W RF source power is applied for 45 seconds. The samples were annealed at 400 ° C for 10 minutes. Figure 47E illustrates a cross section of the finished LDD-HEMT. The gate length (L _G ) was 1 μm, and the gate-source spacing (L _{G S} ) was 1 μm. The gate-sink spacing (L _{G D} ) was chosen to be 1 μm or 3 μm. The length of the low-density absorber region (L _{L D D} ) is 0.5 μm and 1 μm for devices having 1 μm L _{G D} , and 0.5 μm, 1 μm, 1.5 μm, 2 μm, and 3 μm for devices having 3 μm L _{G D} . A schematic diagram of the 2DEG density distribution in different regions of the LDD-HEMT is shown in Figure 47F. For comparison testing, a conventional HEMT device with L _{L D D} =0 was also fabricated on the same wafer.

The fluoride ions in the AlGaN layer added to the LDD region provide a negative fixed charge that modulates the surface electric field and the 2DEG density, allowing for redistribution of the electric field and reduction of the peak field. The function of the LDD region is similar to the metal field plate in increasing the breakdown voltage, but does not introduce any additional capacitance. Secondly, the fluoride ions added to the AlGaN layer can effectively enhance the energy band and effectively block the process of replenishment and replenishment. The addition of fluoride ions in the AlGaN layer is considered to be a substitution, and the fluorine atoms can fill the nitrogen vacancies in the AlGaN layer. Therefore, current collapse associated with surface states and wells can also be suppressed by achieving low density absorbers.

Figure 48 illustrates the breakdown voltage increase in the LDD-HEMT. A 50% increase in V _{B K} is achieved by converting half of the gate-sucker region to a low density region. As shown in Fig. 48, a device having L _{G D} = 1 μm and L _{L D D} = 0.5 μm exhibits similarity to that achieved in a more bulky device (without LDD) having L _{G D} = 3 μm and L _{L D D} = 0 μm. The breakdown voltage. The correlation between V _{B K} and L _{L D D} is shown in Fig. 49. For devices with the same L _{G D} = 3 μm and different L _{L D D} (0 or 3 μm), the same V _{t h} = 0.75 V, I _{M A X} = 300 mA/mm and G _M = 150 mS/mm are obtained. . As shown in Figures 50, 51 and 52, the LDD-HEMT shows the results of the current gain and f _t not degraded, the power gain (MSG/MAG) and f _{m a x} slightly increased - the increased output resistance (RDS). The only unfavorable result imposed on the LDD-HEMT is the increased on-resistance that causes the knee voltage increase of up to 2V, as shown in Figures 53 and 54, which is much less than the increase in V _{B K} (>30V). Figure 55 shows that the reverse gate-sucker leakage current at 20V bias can be reduced from 25μA/mm to 15μA/mm in LDD-HEMT compared to conventional devices. Figure 56 illustrates DC and pulsed I-V characteristics, as well as illustrating the passivation effect of fluoride ions having different L _{L D D} . As L _{L D D} increases, current collapse is reduced, resulting in complete suppression (L _{L D D} = 3 μm) when the gate-sucker region is completely treated with fluoride ions. A comparison of large signal measurements is shown in Figures 57 and 58. Due to current collapse, the maximum power of a conventional HEMT is saturated at approximately 0.69 W/mm. The LDD-HEMT with suppressed current collapse exhibited a maximum power of 1.58 W/mm.

The LDD-HEMT structure and process described above can be integrated into the patterned fluorine-enhanced enhancement + depletion process using a wide bandgap layer, as will now be described.

3A through 3F illustrate a process of fabricating a reinforced mode III nitride HFET in accordance with a first embodiment of the present invention. Figure 3A illustrates a preferred epitaxial structure of the present innovation in which reference numerals 110, 120, 130 and 140 denote substrates (e.g., sapphire, ruthenium or SiC), nucleation layers (low temperature grown GaN nucleation layers, AlGaN or AlN). a high temperature growth GaN buffer layer and an Al _x Ga _{1 - x} N barrier layer including a modulation doping carrier supply layer. A method of fabricating a reinforced mode III nitride HFET of one embodiment will be described below. The mesa isolation was formed using a Cl ₂ /He plasma dry etch followed by a source/sucker ohmic contact formation 160 of Ti, Al, Ni, and Au annealed at 850 ° C for 45 seconds, as shown in FIG. 3B. Subsequently, the photoresist 170 forms a pattern to expose the gate window. Then, fluoride ions are added to the Al _x Ga _{1 - x} N barrier layer by, for example, fluorine plasma treatment or fluorine ion implantation, as shown in Fig. 3C. The gate 180 is formed on the barrier layer 140 by deposition and lift-off of Ni and Au as shown in FIG. 3D. Thereafter, the rear gate RTA was carried out at 400-450 ° C for 10 minutes. Passivation layer 190 is grown on top of the wafer as shown in Figure 3E. Finally, the contact pads are opened by eliminating portions of the passivation layer on the contact pads, as shown in Figure 3F.

Instance

The AlGaN/GaN HEMT structure was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT Metal Organic Compound Chemical Vapor Deposition (MOCVD) system. The HEMT structure consists of a low temperature GaN nucleation layer, a 2.5-m thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. Energy barrier layer is made of 3-nm undoped spacer, to 2.5 x 10 ^{1 8} cm ^{- 3} 15-nm doped carrier supply layer, and a 2-nm undoped cover layer. Hall measurement structure at room temperature to obtain 1.3x10 ^{1 3} cm ^- sheet electron ^density and electron mobility of 1000 cm ² / Vs is. The device mesas were formed using a Cl ₂ /He plasma dry etch in an STS ICP-RIE system followed by a source/sucker ohmic contact formation with Ti/Al/Ni/Au anneal at 850 ° C for 45 seconds. The ohmic contact resistance is typically measured as 0.8 ohm-mm.

After opening the gate window with a length of 1 nm by contact photolithography, the samples were processed in a RIE system with CF ₄ plasma at 150 W RF plasma power for 150 seconds. The treatment pressure is usually 50 mTorr. The typical depth profile of the fluoride ion thus added via this treatment is Gaussian, and the typical depth when the fluorine concentration drops by an order of magnitude from the peak is 20 nm. Note that ion implantation is another method of adding fluoride ions and it is estimated that about 10 KeV of energy will be required.

Ni/Au electron beam evaporation and stripping are then performed to form a gate. The gate region and gate of the plasma treatment are self-aligned. The back gate RTA was carried out at 400 ° C for 10 minutes. This RTA temperature is chosen because RTA at temperatures above 500 °C may degrade both the gate Schottky contact and the source/sink ohmic contact. The device has a source-gate spacing of L _{s g} =1 μm and a gate-sink spacing of L _{g d} =2 μm. The D-type HEMT was also fabricated on the same sample without plasma treatment of the gate region.

Figure 2 illustrates the transfer characteristics of Al-GaN/GaN HEMTs of Type D and Type E (before and after post-gate annealing). Define V _{t h} as the linear extrapolation of the sink current at the gate bias intercept of the peak transconductance ( g _m ) point. The V _{t h of the} E-type device is determined to be 0.9V, while the V _{t h of the} D-type device It is -4.0V. V _{t h} shift above 4V is achieved by plasma processing. At V _{g s} =0, the transconductance reaches zero, indicating a true E-type operation. The sink current is completely pinched off and shows a 28 μA/mm leakage at V _{d s} =6V, the most recently reported minimum for the E-type AlGaN/GaN HEMT. For each peak g _m D-HEMT is 151 mS / mm for the E-HEMT and is 148 mS / mm. The maximum sink current (I _{m a x} ) reaches 313 mA/mm for the E-type HEMT at a gate bias (V _{g s} ) of 3 V. Comparison of current-voltage (I-V) characteristics of E-type devices before and after RTA shows that RTA at 400 °C for 10 minutes causes damage during recovery of plasma processing and achieves high current density and transconductance Important role. Figure 4A illustrates the output curve of an E-type device before and after the RTA process. No change in the threshold voltage was observed after RTA. At 2.5 V V _{g s} , the saturation absorber current (247 mA/mm) of the E-type device after RTA at 400 °C is 85% higher than that before RTA (133 mA/mm), and the E-type with RTA The knee voltage of the device is 2.2V, and the sink current is 95% saturated sink current. In the off state of V _{g s} =0 V, the sinker breakdown voltage is greater than 80 V, indicating no degradation compared to that observed in the D-type HEMT. 4B illustrates these three devices I _g / V _{g s} curve. A lower gate leakage current is achieved for the E-type HEMT, especially after the RTA.

To investigate the mechanism of V _{t h} shift by CF ₄ plasma treatment, secondary samples were subjected to secondary ion mass spectrometry (SIMS) measurements to monitor changes in the atomic composition of the CF ₄ plasma treated AlGaN/GaN material. In addition to Al, Ga, and N, a large amount of fluorine atoms were detected in the plasma-treated sample. Figure 5 illustrates the fluorine atom concentration profile of a sample treated with 150 W of CF ₄ plasma power for 2.5 minutes. The concentration of fluorine atoms is highest near the surface of AlGaN and drops by an order of magnitude in the channel. It can be inferred that the fluoride ions produced by the CF ₄ plasma are added to the surface of the sample, similar to the effect of plasma immersion ion implantation ("PIII") as a technique for developing ultra-shallow junctions in advanced germanium technology. Due to the strong electronegativity of the fluoride ions, the added fluoride ions can provide a fixed negative charge in the AlGaN energy barrier and effectively deplete electrons in the channel. The D-type HEMT can be converted to an E-type HEMT as enough fluoride ions are added to the AlGaN energy barrier. The CF ₄ plasma treatment produces a threshold voltage shifting element as large as 4.9 V. After the RTA at 400 ° C for 10 minutes, the peak fluorine atom concentration near the AlGaN surface did not change, and a more significant decrease was observed around the AlGaN/GaN interface. It should be noted, however, that SIMS measurements from different trips do not provide an accurate quantitative comparison due to the lack of reference standards. However, small changes in V _{t h} before and after RTA indicate that the total number of fluoride ions added to the AlGaN barrier is nearly constant before and after RTA, while plasma damage is greatly restored by RTA. The lower gate reverse leakage current of the E-type HEMT can be attributed to the upward band bending of the AlGaN layer due to the addition of fluoride ions. After the RTA process, defects in the metal and AlGaN interface caused by CF ₄ are recovered, resulting in further suppression of gate leakage current. It was observed from the atomic force microscopy ("AFM") measurements performed on the patterned samples that the plasma treatment produced only a 0.8 nm reduction of the entire AlGaN barrier layer (20 nm thick).

Small signal RF characteristics on wafers of D-type and E-type AlGaN/GaN HEMTs were measured from 0.1 to 39.1 GHz. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of the two types of devices with a 1 μm long gate are derived as a function of frequency from the measured S-parameters, as shown in Figure 5. At V _{d s} =12 and V _{g s} =1.9 V, a current gain cutoff frequency ( f _T ) of 10.1 GHz and a power gain cutoff frequency ( f _MAX ) of 34.3 GHz are obtained for the E-type AlGaN/GaN HEMT, slightly less than it. The D-type counterpart, which measures 13.1 and 37.1 GHz, respectively, at a 12 V sink bias and a -3 V gate bias.

One advantage of this innovation is that an E-type HFET having fluoride ions added to the barrier layer can withstand a larger gate bias (>3V) corresponding to a larger input voltage swing.

Thermal reliability testing has also shown that the addition of fluoride ions in AlGaN barriers is stable up to 700 °C. However, Schottky contacts made of nickel are only stable below 500 °C. Therefore, the application temperature range is as high as 500 ° C unless another Schottky contact technique is used. The tungsten gate is a possible candidate.

In Figure 7, the effect of different post-gate RTAs measured by SIMS on the distribution of fluorine atoms in AlGaN/GaN heterojunctions is illustrated. Unprocessed devices are used as a reference.

It can be found that the fluoride ion added to the AlGaN barrier layer by the CF ₄ plasma treatment can effectively shift the threshold voltage forward. The addition of fluoride ions in the AlGaN layer was confirmed by secondary ion mass spectrometry (SIMS) measurement as shown in FIG. In CF ₄ plasma processing, fluoride ions are implanted into the AlGaN/GaN heterojunction in a self-built electric field analogous to RF power.

It is also found from the results shown in Fig. that the injected fluoride ions have good thermal stability in the AlGaN layer up to 700 °C. It should be noted that although the presence of fluoride ions is determined to be the cause of the threshold voltage shifting element, it is not clear where the fluoride ions occupy, whether it is interstitial or substitutable. It has deep energy level transient spectroscopy ( "DLTS") to the CF ₄ plasma sample HEMT processed. The fluoride ion added to the AlGaN barrier appears to introduce a deep energy state below the conduction band minimum of at least 1.8 eV. Therefore, fluoride ions are considered to introduce deep energy levels like negatively charged acceptors in AlGaN.

Note that in a SIMS chart such as that of FIG. 7, it is difficult to perform an accurate calculation of the concentration from the SIMS measurement because the beam size is not known. However, the belt structure and calculated according to the threshold voltage, the peak of F concentration may be up to about 1 x 20 cm ^{- 3.}

In FIG. 7A, the effect of different plasma power levels without RTA measured by SIMS on the distribution of fluorine atoms in the AlGaN/GaN heterojunction is illustrated.

Note that the 200W and 400W lines indicate "bumps" on the interface between the AlGaN/GaN interfaces. During the addition process, fluoride ions may fill the surface or interface state (or "well"), resulting in an "abnormal stop." Therefore, this indicates that there are more wells at the interface. In addition, the 600W and 800W lines do not indicate bulges, most likely due to greater penetration depth and overall concentration.

Unprocessed devices are used as a reference. In FIG. 7B, the effect of different post gate processing temperatures of 600 W fixed power on the distribution of fluorine atoms in the AlGaN/GaN heterojunction for RTA measured by SIMS is illustrated. Unprocessed devices are used as a reference. Note that the distribution in AlGaN at 700 ° C and below shows the conventional effect of root Dt, but the distribution in the AlGaN layer seems to reflect very different diffusivity (or possibly some other starting energy effect). Therefore, the data show that fluoride ions are more stable in AlGaN than in GaN. In addition, the binding energy may be higher, and the fluorine-related energy state is greater in AlGaN than in the GaN than in the conduction band.

Sensitivity to plasma processing parameters was also investigated. The device was fabricated with different V _{t h} values by applying different CF ₄ plasma powers and processing times. Five different combinations are used: 100 W, 60 seconds, 150 W, 20 seconds, 150 W, 60 seconds, 150 W, 150 seconds, and 200 W, 60 seconds. For comparison, untreated CF ₄ HEMT treated and also on the same sample prepared in the same processing. All devices are not passivated in order to avoid any confusion caused by the passivation layer, which may alter the stress of the AlGaN layer and change the piezoelectric polarization. All HEMT devices have a gate length of 1 μm, a source-gate spacing of L _{s g} =1 μm, and a gate-sink spacing of L _{g d} = 2 μm. The DC current-voltage (I-V) characteristics of the fabricated device were measured using an HP4156A parametric analyzer. The transfer characteristics and transconductance (g _m ) characteristics are shown in Figures 8A and 8B, respectively. Conventional HEMT (ie, without CF ₄ plasma treatment) was used as the baseline device, and the threshold voltage of all other CF ₄ plasma treated HEMTs moved in the positive direction. V _{t h is} defined as the linear extrapolated gate bias intercept of the sink current at the peak transconductance (g _m ) point, and V _{t h of} all devices is extracted and listed in FIG. For a conventional HEMT, V _{t h} is -4 V. For a HEMT treated with CF ₄ plasma at 150 W for 150 seconds, V _{t h} is 0.9 V, which corresponds to the E-type HEMT. A maximum V _{t h} shift of 4.9V is achieved. In order to reveal the effects of CF ₄ plasma treatment, the plotted curve 10 in FIG V _{t h} correlation with the CF ₄ plasma processing time and RF power. A larger shift in V _{t h} is achieved as the plasma power increases and longer processing times are employed. As the plasma processing time increases, more fluoride ions are implanted into the AlGaN layer. The increased fluoride ion concentration results in a reduced electron density in the channel and causes a positive shift in V _{t h} . When the plasma power is increased, a higher energy of fluorine ions, fluorine ions, and the ionization rate of flow enhancement due to CF ₄ increases. With higher energy, fluoride ions can reach deeper depths closer to the channel. The closer the fluoride ions are to the channel, they are more efficient at depleting 2DEG and achieve a larger shift in V _{t h} . The increased fluoride ion flow rate has the same effect as V _{t h} as the increase in plasma treatment time by increasing the fluorine atom concentration in the AlGaN layer. It should be noted that the quasi-linear V _{t h} versus time and V _{t h} versus power relationship indicates the possibility of accurate control of the V _{t h} of the AlGaN/GaN HEMT. Although V _{t h} was shifted by CF ₄ plasma treatment, g _{m was} not degraded. 8B, the maximum g _m for all devices in the 149-166 mS / mm in a range of 150 W in addition to the devices for 60 seconds, it has higher peak 186 mS / mm of g _m. It is suspected that this singularity is caused by the inconsistency in epitaxial growth. It was determined by AFM measurements of CF ₄ treated patterned samples (where a portion of the sample was processed and other parts were treated with plasma) that CF ₄ plasma treatment produced only a decrease in AlGaN thickness of less than 1 nm. , as shown in Figure 11. Thus, a near constant transconductance indicates that according to this innovation, the 2DEG mobility in the channel is maintained during device fabrication. A key step in maintaining transconductance is the post-gate annealing process.

Recovering damage caused by plasma by post-gate annealing

As mentioned previously, the plasma typically causes damage and creates defects in the semiconductor material, thereby degrading the mobility of the carriers. RTA is an effective way to fix these damages and restore mobility. In the CF ₄ plasma treated AlGaN/GaN HEMT, the sink current and transconductance degradation occur after the plasma treatment. In Figures 12A and 12B, plots of absorber current and transconductance measured on untreated and processed devices (200 W, 60 seconds) before and after RTA (400 ° C, 10 minutes) are plotted. Figure 13 compares the output characteristics of processed devices before and after RTA. After the RTA in the processed device, the sink current is 76% higher and the transconductance is 51% higher. The RTA process restores most of the mobility degradation of the plasma treated device, while exhibiting no significant effect on conventional unprocessed devices. Therefore, the recovery of I _d and g _m in the CF ₄ plasma treated device is the result of an effective recovery of 2DEG mobility on this RTA condition. This lower RTA temperature indicates a CF ₄ plasma treatment yield ratio compared to the higher annealing temperature of 700 ° C required to recover the damage caused by chlorine-based ICP-RIE in the case of a groove gate. Chlorine ICP-RIE is less damaged. It also enables the RTA process to be performed after gate deposition, thereby achieving the goal of a self-aligned process. If V _{t h} previously defined, the CF ₄ plasma processing device of the V _{t h} appears after RTA displaced from 0.03V to -0.29V. When the starting point of g _m shown in FIG. 12B or the starting point of I _d on the logarithmic scale shown in the inset of FIG. 12A is used as a criterion for evaluating V _{t h} , the device after CF ₄ plasma treatment V _{t h} did not change after RTA. The good thermal stability of V _{t h} is consistent with the good thermal stability of the fluorine atoms in the previously described AlGaN layer.

Schottky gate leakage current suppression

AlGaN/GaN HEMTs always exhibit a reverse gate leakage current that is much higher than the theoretical prediction of the thermionic emission ("TE") model. Higher gate currents degrade the noise performance of the device and increase standby power. Specifically, the forward gate current limits the gate input voltage swing, thus limiting the maximum sink current. Other ways have been tried to suppress the gate current of the AlGaN/GaN HEMT. These efforts include the use of gate metals with higher work functions, the use of copper, modified HEMT structures (such as the addition of GaN cap layers), or the turning of metal insulator semiconductor heterojunction field effect transistors (MISHFETs). In the inventive CF ₄ plasma treated AlGaN/GaN HEMT, suppression of gate current in the reverse and forward bias regions is achieved. Gate current suppression indicates a correlation with CF ₄ plasma processing conditions.

14A and 14B illustrate different gate currents of AlGaN CF ₄ plasma processing / GaN HEMT's. Fig. 14B is an enlarged graph of the forward gate bias region. In the reverse bias region, compared to the conventional HEMT without a CF ₄ plasma treatment, AlGaN all CF ₄ plasma processing / GaN HEMT of the gate leakage current is reduced. AlGaN ² A / mm to 60 seconds at 200W plasma / GaN HEMT of 7 × 10 ^{- -} at V _g = -20V, gate leakage from the conventional HEMT of 1.2 × 10 ⁷ A / mm decreased more than four orders of magnitude . In the forward region, the gate current of all CF ₄ plasma treated AlGaN/GaN HEMTs is also reduced. Therefore, the turn-on voltage of the gate Schottky diode is expanded to increase the swing of the input voltage of the anti-gate. With a 1 mA/mm standard, the turn-on voltage of the gate Schottky diode increases from 1 V in a conventional HEMT to 1.75 V in an AlGaN/GaN HEMT treated with 200 W of 60 sec CF ₄ plasma.

The suppression of the gate leakage current in the CF ₄ plasma-treated AlGaN/GaN HEMT can be explained as follows. In the CF ₄ plasma treatment, fluoride ions are added to the AlGaN layer. These ions having strong electronegativity serve as fixed negative charges which cause the upward conduction band bending in the AlGaN barrier layer due to the electrostatic induction effect. Therefore, an additional energy barrier height Φ _F as shown in FIG. 23 is formed, and the effective metal semiconductor energy barrier height is increased from Φ _B to Φ _B + Φ _F . This increased barrier height effectively suppresses the gate Schottky diode current in the reverse and forward bias regions. With higher plasma power and longer processing time, the concentration of fluoride ions in the AlGaN layer increases, and the effective barrier height is further increased, resulting in more significant gate current suppression. In Fig. 9, the effective barrier height and ideal factor extracted from the forward region of the measured gate current by using the TE model are explained in detail. The effective barrier height of the conventional HEMT is 0.4 eV, and for a HEMT treated with 60 seconds of CF ₄ plasma at 200 W, the effective barrier height is increased to 0.9 eV. The effective barrier height of the CF ₄ plasma treated HEMT also shows a trend with increasing plasma power and processing time, which has a higher effective barrier height than the HET treated at 150 W for 20 seconds. This exception is considered to be due to processing changes. The fact that the extracted effective energy barrier height is much lower than the theoretical prediction value and a large ideal factor (>2.4) indicates that the gate current of the fabricated AlGaN/GaN HEMT is not by the TE mechanism but by other mechanisms such as vertical tunneling. Wear, surface energy barrier refinement, and well assisted tunneling to control. Therefore, the energy barrier height and ideal factor extracted by using the TE model are not accurate. However, they provide information about well-characterized mechanism for explaining the gate current AlGaN CF ₄ plasma processing / GaN HEMT of the inhibition.

The dynamic I-V characteristics were investigated by studying the effect of CF ₄ plasma treatment on the absorption of the sink current by using the Accent DIVA D265 system. The pulse width is 0.2 μs and the pulse interval is 1 ms. The static point is slightly (~0.5V) lower than the pinch-off V _{G S} and V _{D S} =15V. Compared to the static I-V characteristics, the maximum sink current of the conventional D-type HEMT is reduced by 63%, while the maximum sink current of the E-type HEMT treated with CF ₄ plasma of 150 seconds at 150 W is reduced by 6%.

The decrease in the sink current drop of the E-type HEMT may be caused by the increased gate bias of the dead point (V _{G S} = 0 V for the E-type HEMT and V _{G S} = -4.5 V for the D-type HEMT).

RF small signal characteristics

The on-wafer small-signal RF characterization of the fabricated AlGaN/GaN HEMTs was performed using a Cascade microwave probe and an Agilent 8722ES network analyzer over a frequency range of 0.1-39.1 GHz. The open pad de-embedding is performed using the S-parameter of the dummy pad to eliminate the parasitic capacitance of the detection pad. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of all devices with a gate length of 1 μm are derived from the de-embedded S-parameter as a function of frequency. The current cutoff frequency ( f _t ) and the maximum oscillation frequency ( f _{m a x} ) are extracted from the current gain and MSG/MAG in unity gain. It has been observed that the natures f _t and f _{m a x} are generally 10-15% higher than non-essential in the absence of a de-embedding process. For the E-type HEMT, the correlation between f _t and f _{m a x} and the gate bias is shown in FIG. Both f _t and f _{m a x} are relatively constant at both the low and high gate biases, indicating good linearity. Figure 16 lists f _t and f _{m a x for} all samples. For conventional HEMTs, f _t and f _{m a x} are 13.1 and 37.1 GHz, while for CF ₄ plasma treated HEMT, f _t and f _{m a x are} approximately 10 and 34 GHz, slightly lower than the conventional HEMT, but except It is processed at 150W for 60 seconds outside the HEMT. This higher f _t and f _{m a x} in a 150 W/60 second device is consistent with the previously provided higher g _m and is attributed to material inconsistencies and processing variations. The slightly lower f _t and f _{m a x in the} CF ₄ plasma treated HEMT indicate that the post-gate RTA at 400 ° C effectively recovers the 2DEG mobility that is degraded by plasma treatment, but recovers less than 100%. We recommend that RTA temperature and time optimization be required to further improve 2DEG mobility without degrading the gate Schottky contact.

MISHFET

In another embodiment, the E-type Si ₃ N ₄ /AlGaN/GaN MISHFET is constructed using a two-stage Si ₃ N ₄ process with a thin layer of Si ₃ N ₄ (15 nm) under the gate and in the entry and exit regions. A thick layer of Si ₃ N ₄ (about 125 nm) is featured. Fluorine-based plasma processing is used to convert the device from D to E. E-type MISHFET with a 1-μm long gate coverage area exhibits a 2V threshold voltage, 6.8V (compared to approximately 3V implemented in an E-type AlGaN/GaN HEMT), and a forward-going gate bias and 420mA/mm Maximum current density.

The AlGaN/GaN HFET structure used in this example was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT MOCVD system. The HFET structure consists of a 50-nm thick low temperature GaN nucleation layer, a 2.5-μm thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. Energy barrier layer is made of 3-nm undoped spacer, to 2 × 10 ^{1 8} cm ^{- 3} 16-nm doped carrier supply layer, and a 2-nm undoped cover layer. The capacitance-voltage ("C-V") measurement performed by the mercury probe produces an initial threshold voltage of -4V for this sample. The processing flow is as shown in Figs. 17A to 17F. The device mesa was dried by Cl ₂ /He plasma in an STS ICP-RIE system followed by Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) annealed at 850 °C for 30 seconds. A source/sucker ohmic contact is formed to form as shown in FIG. 17A. Then, a first Si ₃ N ₄ layer (about 125 nm) was deposited onto the sample by plasma enhanced chemical vapor deposition (PECVD) as shown in FIG. 17B. After opening the gate window with a length of 1-μm by photolithography, the sample was placed in a RIE system and subjected to CF ₄ plasma treatment, which eliminated Si ₃ N ₄ and added fluoride ions in AlGaN. The RF power of the plasma was 150 W as shown in Fig. 17C. The gas flow was controlled to 150 sccm and the total etching and processing time was 190 seconds. After the photoresist is removed, a second Si ₃ N ₄ film (about 15 nm) is deposited by PECVD to form an insulating layer between the gate metal and AlGaN, as shown in FIG. 17D. Subsequently, the Si ₃ N ₄ layer is patterned and etched to open the window in the source and absorber ohmic contact regions, as shown in Figure 17E. Then, a 2-μm long gate is defined by photolithography, followed by electron beam evaporation and lift-off of Ni/Au (~50 nm/300 nm), as shown in Fig. 17F. To ensure that the gate covers the entire plasma processing area, the metal gate length (2 μm) is selected to be larger than the processed gate region (1 μm), resulting in a T gate configuration. The gate suspended in the source/sink-in and out regions is insulated from the AlGaN layer by a thick Si ₃ N ₄ layer, keeping the gate capacitance at a low level. Finally, the entire sample was annealed at 400 ° C for 10 minutes to repair the damage caused by the plasma in the AlGaN barrier and the channel. Measured from the bottom of the gate, the gate-source and gate-sink spacing are both 1.5 μm. An E-type MISHFET was designed for a dc test using a gate width of 10 μm and a gate width of 100 μm for RF characterization.

The device being constructed is characterized. The DC output characteristics of the E-type MISHFET are plotted in FIG. At V _{G S} =7V, the device exhibits a peak current density of approximately 420 mA/mm, approximately 5.67 Ω. The on resistance of mm and the knee voltage of approximately 3.3V. Figure 19A illustrates the transfer characteristics of the same device having a gate size of 1 x 10-μm. It can be seen that V _{t h is} approximately 2 V, indicating a 6-V shift of V _{t h} achieved by insertion of a Si ₃ N ₄ insulator and plasma treatment (compared to a conventional D-type HFET). The peak transconductance gm is approximately 125 mS/mm. Fig. 19B illustrates the gate leakage current at the negative bias and forward bias. The forward biased turn-on voltage of the gate is approximately 6.8V, providing much greater gate bias swing than the E-type HFET. Pulse measurements were made on an E-type MISHFET having a gate size of 1 x 100-μm using a pulse length of 0.2 μs and a pulse interval of 1 ms. The static bias point is chosen at V _{G S} =0V (below V _{t h} ) and V _{D S} =20V. Figure 20 shows that the pulse peak current is higher than static, indicating no current collapse in the device. Large devices with a gate width of 100-μm have a static maximum current density of approximately 330 mA/mm, which is less than devices with a gate width of 10-μm (approximately 420 mA/mm). The lower peak current density in larger devices is due to the automatic heating effect that reduces current density. Due to the minimal auto-heating during pulse measurement, the maximum current of a 100-μm wide device can reach the same level as a 10-μm wide device. The small signal RF characteristics on the wafer were performed from 0.1 to 39.1 GHz at V _{D S} = 10 V to a 100-μm wide E-type MISHFET. As shown in FIG. 21, the maximum current gain cutoff frequency (f _T ) and the power gain cutoff frequency (f _{m a x} ) are 13.3 and 23.3 GHz, respectively. When the gate bias is 7V, the small-signal RF performance is not significantly degraded, with f _{T of} 13.1 GHz and f _{m a x of} 20.7 GHz, indicating that the Si ₃ N ₄ insulator provides good insulation between the gate metal and the semiconductor. .

model

A theoretical representation model was developed for this part of the innovation. For a conventional AlGaN/GaN HEMT with a erbium modulation doped layer, as shown in Figure 7, the polarization charge needs to be considered when calculating the HEMT threshold voltage. By considering the effects of charge polarization, surface and buffer well modifications from the commonly used formula, the threshold voltage of an AlGaN/GaN HEMT can be expressed as:

The parameters are defined as follows: φ _B is the metal semiconductor Schottky barrier height.

σ is the total net (spontaneous and piezoelectric) polarized charge on the barrier-AlGaN/GaN interface.

d is the thickness of the AlGaN barrier layer.

N _{s i} ( x ) is the erbium doping concentration.

Δ E _C is the conduction band offset on the AlGaN/GaN heterojunction.

E _f0 is the difference between the essential Fermi level of the GaN channel and the edge of the conduction band.

ε is the dielectric constant of AlGaN.

N _{s t} is the net charge surface well per unit area.

N _b is an effective net charge buffer well per unit area.

C _b is the effective buffer-channel capacitance per unit area.

The last two terms in equation (1) describe the effects of the surface well and the buffer well, respectively. The AlGaN surface is at x=0, and the direction pointing to the channel is the positive direction of the body. To represent the device described above, a fixed negative charge is introduced into the AlGaN barrier layer under the gate. Due to electrostatic induction, these fixed negative charges can deplete 2DEG in the channel, increase the energy band, and thus modulate V _{t h} . Including the effect of the negative charge defined in the AlGaN energy barrier, the threshold voltage modified from equation (1) is expressed as:

The positive charge distribution curve N _si ( x ) is replaced by a net charge distribution N _si ( x ) - N _F ( x ), where N _F ( x ) is the concentration of the negatively charged fluoride ion. The surface well density ( N _st ) can be modified by plasma processing.

By applying the Poisson equation and Fermi-Dillac statistics, the analogy consists of a conduction band profile and an electron distribution of an AlGaN/GaN HEMT structure with and without fluoride ions added to the AlGaN layer. Both structures have the same epitaxial structure, as shown in Figure 7. For the HEMT structure with fluoride ion added, the distribution curve of the negatively charged fluoride ion was extracted from the SIMS measurement of the fluorine atom distribution of the AlGaN/GaN HEMT structure processed by CF ₄ plasma at 150 W for 150 seconds and converted to E-type HEMT. . An analog conduction band diagram for zero gate bias is plotted in Figures 22 and 23. E analogy to the conduction band of the HEMT type, as shown, the fluorine concentration in the AlGaN surface 22 through 3x10 ¹⁹ cm using fluorine concentration peak ^{- 3} linear distribution to approximate calculation, and the fluorine concentration is assumed to be in the AlGaN / GaN interface ignorable. A total fluoride ion concentration of about 3x10 ^{1 3} cm ^{- 2} is sufficient to compensate not only for erbium doping (about 3.7x10 ^{1 3} cm ^{- 2} ) in AlGaN barriers, but also for piezoelectric and spontaneous polarization induced charges (about 1x10 ^{1 3} cm ^{- 2} ). Two salient features can be observed. First, the conduction band minimum of the 2DEG channel of the plasma-treated structure is higher than the Fermi level compared to the untreated AlGaN/GaN HEMT structure, indicating a fully depleted channel and an E-type HEMT. As shown in the electron distribution curve in Figure 24, in the plasma treated configuration, there is no electron in the channel under zero gate bias, indicating E-type HEMT operation. Second, the fixed negatively charged fluoride ion causes an upward bending of the conduction band, particularly in the AlGaN energy barrier, resulting in an additional energy barrier height Φ F , as shown in FIG. This enhanced energy barrier significantly suppresses the gate Schottky diode current of the AlGaN/GaN HEMT in the reverse and forward bias regions.

The epitaxial structure of the single-rock integrated E/D type HFET is composed of: (a) a semiconductor substrate (sapphire, SiC, germanium, AlN or GaN, etc.); (b) a buffer layer grown on the substrate; c) a channel layer; (d) an energy barrier layer comprising an undoped spacer layer, a modulated doped carrier supply layer, and an undoped cap layer. The fabrication process includes: (f) active area isolation; (g) ohmic contact formation on the source and sink terminals; (h) photolithography of the gate region of the E-type HFET; (i) for the E-type HFET Fluoride-based plasma treatment of the exposure barrier; (j) gate metal deposition of the E-type HFET; (k) photolithography of the gate region of the D-type HFET; (1) gate metal of the D-type HFET Deposition; ml) surface passivation of D-type and E-type HFETs; (n) gate annealing at elevated temperatures. The schematic processing flow of such a single stone body is shown in FIG.

The active device isolation in the monolithic process described above employs a mesa etch that features an active region elimination in the region without the HFET by etching techniques. This method imposes restrictions on the density of the integrated body and the resolution of the light lithography. For high frequency circuits, the edge of the mesa also introduces additional discontinuities in the propagation of the wave, which in turn complicates circuit design and analysis. Fluoride-based plasma processing can be used for device isolation because it can deplete electrons in the channel (providing electrical cutoff of the channel). With increased plasma power and processing time, regions that do not require active components can be electrically fully turned off, providing electrical isolation between the devices. This method does not involve any material removal, thus achieving a flat wafer surface in a planar process.

Instance

26A through 26F illustrate the process of an E/D type HFET of a single-magnet volume circuit in accordance with one embodiment of the present invention. Figure 26A illustrates a preferred epitaxial structure of the present invention, wherein reference numerals 110, 120, 130 and 140 denote a substrate, a low temperature grown GaN nucleation layer, a high temperature grown GaN buffer layer, and an Al comprising a modulated dopant carrier supply layer. _x Ga _{1 - x} N barrier layer. The manufacturing method of the single-rock integrated body of the E/D type HFET of the integrated circuit is as follows. For D-type and E-type HFETs, mesa isolation is formed using both Cl ₂ /He plasma dry etching followed by source/sink ohmic contact formation 160 with Ti, Al, Ni, and Au annealed at 850 ° C for 45 seconds. As shown in Fig. 26B. The gate and source interconnections of the gate and D-type HFET are patterned by photoresist 170 as shown in Figure 26C, followed by deposition and stripping of Ni and Au 178. Thereafter, the gate, pad and second interconnect of the E-type HFET are patterned using a photoresist 175 as shown in FIG. 26D. Fluoride ions are then added to the Al _x Ga _{1 - x} N barrier layer under the gate of the E-type HFET, for example by fluoride plasma treatment or fluoride ion implantation, as shown in Figure 26D. The gate 180 is formed on the barrier layer 140 by depositing and stripping Ni and Au. Thereafter, the post gate rapid thermal annealing (RTA) was carried out at 400-450 ° C for 10 minutes. A passivation layer 190 is grown on top of the wafer as shown in Figure 26E. Then, they are opened by eliminating portions of the contact pads and the passivation layer on the via holes, as shown in Fig. 26F. Finally, a third interconnect is formed.

20 nm Al _{0 . 2 5} Ga _{0 . 7} on a 2 μm GaN buffer layer for a typical CF ₄ plasma treatment condition of 150 Hz for E-type HFETs and a typical post-gate RTA condition of 10 minutes at 450 ° C. _An E/D HFET inverter and a 17-stage direct-coupled ring oscillator are built up on the N N barrier. The inverter has a NM _{L of} 0.21 V and a NM _{H of} 0.51 V at a supply voltage of 1.5V. When a supply voltage of 3.5V is applied, the 17-stage ring oscillator exhibits a maximum oscillation frequency of 225 MHz corresponding to a minimum propagation delay of 130 ps.

Instance

This embodiment describes a method of planar monolithic integration of E-type and D-type AlGaN/GaN HFETs. As described in the first embodiment, isolation between active elements can be achieved by establishing an active element mesa via etching that establishes a non-planar wafer surface. In the production of integrated circuits, the planar process is always in line with the needs. Depletion of the expected passive (isolated) regions by fluoride-based plasma processing can be achieved following the same principle of depletion of channels with negatively charged fluoride ions in AlGaN. Both plasma power and processing time can be increased to enhance carrier depletion. The processing flow is shown in Figure 27, where: (a) source/sink ohmic contact formation; (b) D-type HFET gate definition by photolithography; (c) D-type HFET gate metallization and mutual The portion formed; (d) the definition of the E-type HFET gate followed by photolithography followed by the plasma treatment; (e) the portion formed by the gate metallization and interconnection of the E-type HFET; (f) the lithography through the light The isolation region definition followed by the second fluoride-based plasma treatment is followed; (g) followed by the passivated final wafer.

Instance

The AlGaN/GaN HEMT structure in this example was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT MOCVD system. The HEMT structure consists of a low temperature GaN nucleation layer, a 2.5-μm thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. The barrier layer consists of a 3-nm undoped spacer, a 21-nm carrier supply layer doped with 2 x 1018 cm ^{- 3} , and a 2-nm undoped overlay. Hall measurements at room temperature to produce a configuration of 1.3x1013 cm ^- sheet electron ^density and electron mobility of 950 cm ² / Vs is.

The process of the product system is shown in Figure 28. First, the source/sink ohmic contact of the E/D device is simultaneously deposited by electron beam evaporation of Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) and at 850 ° C for 30 seconds. Rapid thermal annealing is formed as shown in Figure 28(a). Second, the active regions of the E/D type devices are patterned by photolithography, followed by CF ₄ plasma processing in a reactive ion etching system. The plasma power is 300W and the processing time is 100 seconds. The gas flow was controlled to 150 sccm and the plasma bias was set to 0V. The isolation region is a position in which a large amount of fluorine ions are added to the AlGaN and GaN layers in the vicinity of the surface, and then the two-dimensional electron gas in the channel is depleted, as shown in Fig. 28(b). Then, the gate of the D-type HEMT is patterned by contact photolithography followed by electron beam evaporation and lift-off of Ni/Au (50 nm/300 nm) as shown in Fig. 28(c). Subsequently, the gates and interconnections of the E-type HEMT are defined. Prior to electron beam evaporation of Ni/Au, the gate region of the E-type HEMT was treated with CF ₄ plasma at 170 W for 150 seconds (which has negligible etching of AlGaN) as shown in Figure 28(d). This plasma processing performs the function of converting the processed device from a D-type to an E-type HEMT. A 200 nm thick tantalum nitride passivation layer was deposited by PECVD and the probe pads were opened. Then, the sample was annealed at 400 ° C for 10 minutes in order to repair the AlGaN barrier of the E-type HEMT and the plasma-induced damage in the channel, as shown in Fig. 28(e). In comparison, a D-type device was fabricated on a standard sample from another sample from the same substrate. In a standard process, inductively coupled plasma reactive ion etching was used to define the mesa as the active region. For the direct coupled FET logic inverter shown in Figure 1A, the E-type HEMT driver is designed for gate length, gate-source spacing, gate-sink spacing, and gate widths of 1.5, 1.5, 1.5, and 50, respectively. Μm; D-type HEMT load is designed as gate length, gate-source spacing, gate-sink spacing and gate width of 4, 3, 3 and 8 μm, yielding a ratio of 16.7 = (W _E / L _E ) / (W _D / L _D ). For the characterization of discrete E-type and D-type HEMTs having a gate size of 1.5 x 100 μm.

Device and circuit characteristics

For the E/D type HEMT fabricated by the planar process, the output characteristics are plotted in FIG. The peak current densities of the D and E HEMTs are approximately 730 and 190 mA/mm. Figure 30 illustrates a comparison of DC transfer characteristics between a plane and a standard process. It can be seen that the inductive leakage current of the planar process is approximately 0.3 mA/mm, which is the same level as that fabricated by standard mesa etching. The D-type HEMT through the planar process has the same attractor current and transconductance characteristics as the standard process, as shown in Fig. 30(b). In addition, the leakage current between the two pads (400 × 100 μm ² ) was measured at intervals of 150 μm. At a DC bias of 10 V, the same level (about 30 μA) of the sample was etched on a standard mesa, and the leakage current through the planar process was approximately 38 μA. Compared to standard countertop processes, fluoride-based plasma treatment achieves the same level of active component isolation for a fully flat area process. Compared with the device type D, E mode HEMT exhibits a smaller transconductance ( "g _m"), which is introduced by a plasma damage due to incomplete recovery. The fact that the sample has passed the thermal annealing at 400 ° C also indicates that good thermal stability is expected at temperatures up to at least 400 ° C. It should be noted that ion implantation techniques have also been developed for inter-device isolation achieved by multiple energy N+ implants to create severe lattice damage over the entire thickness of the GaN buffer layer. Compared to ion implantation technology, CF ₄ plasma processing technology has the advantages of low cost and low damage.

An E/D type HEMT DCFL inverter fabricated by a flat area process was characterized. Figure 31 illustrates the measured static voltage transfer curve of an inverter at a supply voltage V _{D D} = 3.3V. The high and low output logic levels (V _{O H} and V _{O L} ) are 3.3 and 0.45 V, respectively, with an output swing of 2.85V (V _{O H} -V _{O L} ). The DC voltage gain in the linear region is 2.9. The low and high noise margins are 0.34 and 1.47 V by defining the values of V _{I L} and V _{I H} at the unity gain point. The inverter DC current is also shown in FIG. The leakage current with the E-type device pinch-off is approximately 3 μA, which is consistent with discrete device results.

Instance

Figure 32 illustrates an AlGaN/GaN epitaxial heterojunction during fabrication of a HEMT in accordance with the present innovation. These include the following: 2.5 μm GaN buffer layer and a channel, 2 nm undoped _{Al 0 2 5 Ga 0 7 5} N spacer, having a 1 × 1018 cm ^{- 3} Si-doped 15nm Al _{0... 2 5} Ga _{0 . 7 5} N carrier supply layer, and 3 nm undoped Al _{0 . 2 5} Ga _{0 . 7 5} N cover layer. The structure was grown on a sapphire substrate in an Aixtron 2000 HT MOCVD system. The process flow is shown in Figures 33(a) through 33(f).

The mesa and source/sucker ohmic contacts are formed simultaneously for the E-type and D-type HEMTs, as shown in Figures 33(a) and (b). Then, the gate of the D-type HEMT is formed by photolithography, metal deposition, and lift-off as shown in FIGS. 33(c) and (d). After defining the gate and interconnect pattern of the E-type HEMT, the sample is processed in the STS RIE system with CF ₄ plasma at 150 W source power for 150 seconds, as shown in Figure 33(e), then for the E-type. Gate metallization and stripping of HEMT. It was examined by atomic force microscopy ("AFM") measurements that the thickness of the AlGaN barrier was reduced by 0.8 nm after plasma treatment. Subsequently, the post gate was thermally annealed at 450 ° C for 10 minutes as shown in Fig. 33 (f). The CF ₄ plasma treatment converts the treated GaN HEMT from D to E. The threshold voltage shift amount depends on processing conditions, such as plasma power and processing time, as previously described. The post gate anneal is used to recover the damage introduced by the plasma in the AlGaN barrier and the channel. In principle, the higher the annealing temperature, the more effective the damage repair. However, in practice, the post gate anneal temperature should not exceed the maximum temperature that the gate Schottky contact can withstand (in our case, ~500 ° C), as previously described. We found that the characteristics of the D-type HEMT remained unchanged after annealing, while the absorber current density of the E-type HEMT increased significantly. It was found that the post gate annealing had no effect on the threshold voltage shifting elements generated by the plasma treatment.

For E/D inverters and ring oscillators, the most important physical design parameter is the drive/load ratio β = (W _g / L _g ) E type / (W _g / L _g ) D type. Several E/D inverters and ring oscillators with beta varying from 6.7 to 50 were designed and fabricated on the same sample. The geometric parameters of each design are listed in Figure 34. Discrete E-type and D-type GaN HEMTs with a gate size of 1 x 100 μm were fabricated simultaneously on the same sample for dc and RF testing.

Characteristics of E/D HEMT

The DC current-voltage (I-V) characteristics of discrete devices were measured using the HP4156A parametric analyzer. The transfer characteristics of the E/D type HEMT are plotted in Fig. 35(a). On-wafer small-signal RF characterization of discrete devices was performed using a Cascade microwave probe and an Agilent 8722ES network analyzer in the frequency range of 0.1-39.1 GHz. The measurement parameters of the E/D type HEMT are listed in FIG. The threshold voltage and peak transconductance (g _{m , m a x} ) were 0.75 V and 132 mS/mm for the E-type HEMT and -2.6 V and 142 mS/mm for the D-type HEMT. 480mA / mm lower peak current density of the HEMT due to the D-type AlGaN barrier layer can be 25% lower Al composition and 1 × 1018 cm ^{- 3} lower doping density caused. Unlike AlGaN/GaN HEMTs for RF/microwave power amplifiers, digital ICs require less current density. As shown in Fig. 35(b), a low knee voltage of 2.5 V was obtained for the E-type HEMT. On the gate bias of 2.5V, 7.1 Ω is achieved for the E-type HEMT. The on-resistance of mm, which is the same as the on-resistance of a D-type HEMT at the same saturation current level. One observation is that the gate current in the reverse and forward bias conditions is significantly reduced in the E-type HEMT compared to the D-type HEMT, as shown in Figure 37 (a). This mechanism of gate current suppression is to modulate the potential in the AlGaN energy barrier by negatively charged fluoride ions introduced by plasma processing. By classifying the Poisson equation and the Fermi-Dillac statistics, the D and E HEMT analog lead bands are plotted. For the E-HEMT analogy conduction band profile fluoro distribution be approximated by a linear function, the characteristics of the function is on the AlGaN surface 3 × 1019 cm ^- Maximum fluoride ion concentration ³ and reaches the AlGaN / GaN interface Zero (can be ignored). About 3 × 1013 cm ^- total fluorine ion sheet concentration of about ² is sufficient to compensate for only 3.7 × 1012 cm ^- Si + ² concentration of the donor, but also compensated piezoelectric and spontaneous polarization-induced charges (about 1 × 1013 cm ^{- 2).} It should be noted that the Schottky barrier height on the gate/AlGaN junction is assumed to remain constant in this example. From the analog conduction band shown in Figures 37(b) and (c), the potential of the AlGaN barrier can be significantly increased by the addition of fluoride ions, resulting in an enhanced Schottky barrier and subsequent gate current suppression. Gate current suppression in forward bias is particularly beneficial for digital IC applications. The suppressed gate current allows the gate bias of the E-type device to increase to 2.5V. This increase results in a larger gate voltage swing, a larger dynamic range of input, and a higher fan-out. The increased input voltage swing allows for higher supply voltages, which is an important factor in achieving higher operating speeds and higher noise margins for digital ICs. Without an increased gate input swing, a larger supply voltage will produce an output voltage (in logic "high") that exceeds the turn-on voltage of the input gate of the next stage. The wider dynamic range of the input enables direct logic level matching between the input and output, eliminating the need for level adjustment between adjacent stages.

It should be noted that tantalum nitride passivation, which is an important technique generally used for stable operation of GaN-based HEMTs, can also affect the threshold voltage to a lesser extent. In general, the deposition of a tantalum nitride passivation layer over the active region can alter the stress in the AlGaN and GaN layers. Subsequently, the device's piezoelectric polarization charge density and threshold voltage can be modified slightly. In general, the widely used tantalum nitride layer deposited by high frequency PECVD introduces an additional tensile stress in the AlGaN layer, resulting in a negative shifting element of the threshold voltage in the range of a few tenths of a volt. In fact, this effect should be considered in the process design. The plasma treatment dose can be increased accordingly to compensate for the negative shifting elements in the threshold voltage generated by the SiN passivation layer. The stress of the SiN passivation layer can also be reduced by modifying the process parameters of the PECVD deposition such that the negative shift elements in the threshold voltage are minimized.

Example: DCFL inverter

A schematic circuit diagram of an E/D HEMT inverter is shown in FIG. 1A, in which a D-type HEMT is used as a load, its gate is connected to its source, and an E-type HEMT is used as a driver. Figure 1B illustrates a fabrication photomicrograph of an inverter in accordance with the present innovation. The fabricated inverter was characterized using the HP4156A parametric analyzer. Figure 38 illustrates the quiescent voltage transfer characteristics (solid curve) of a typical E/D HEMT inverter. The rise in the output voltage at a large input voltage (>2.1V) is the result of the conduction of the gate Schottky diode. The dash curve is the same transfer curve with the swap axis and represents the input-output characteristics of the next inverter stage. The parameter definitions are as described for GaAs and InP based HEMTs. The static output levels (V _{O H} and V _{O L} ) are given by the two intersections of the curves of the stable equilibrium point, and the difference between the two levels is defined as the output logic voltage swing. The inverter threshold voltage (V _{T H} ) is defined as V _{i n} , where V _{i n} is equal to V _{o u t} . The static noise margin is measured using the logic low noise margin (NM _L ) and the maximum width of the logic high noise margin (NM _H ). A measured static voltage transfer curve for an E/D inverter having a supply voltage V _{D D} = 1.5 V having a variation of 6.7 to 50 is plotted in FIG. The high output logic level (V _{O H} ) remains at 1.5V, indicating that the E-type HEMT is completely off, while the low output logic level (V _{O L} ) is improved from 0.34 to 0.09V due to the increase in β from 6.7 to 50. Therefore, the output logic swing defined as V _{O H} -V _{O L} increases from 1.16 to 1.41V. When β is increased from 6.7 to 50, V _{T H is} reduced from 0.88 to 0.61V, and the DC voltage gain (G) in the linear region is increased from 2 to 4.1. Figure 40 shows the static noise margins and the measured values of V _{O H} , V _{O L} , output logic swing, V _{T H} and G. Both NM _L and NM _H are improved as β increases.

The quiescent voltage transfer curve with an inverter of β = 10 is measured at different supply voltages and plotted in Figure 41. Circuit performance parameters are listed in Figure 42. As the supply voltage increases, all parameters of the E/D inverter increase accordingly. This means that the increase in supply voltage improves the static performance of the E/D inverter. As you know, for HEMT and MESFET E/D inverters, the input voltage is always limited by the turn-on voltage of the gate Schottky diode. At large input voltages, the gate conductance causes an increased voltage drop across the parasitic source resistance of the E-type device used as a driver, thereby increasing the voltage at the logic low level. As the supply voltage and the required input voltage increase, an increase in the output voltage can be observed in the static transfer curve, as shown in Figure 41. The gate current can significantly degrade the ability of the inverter to drive multiple stages as it increases through a large input voltage, thereby reducing fan-out. Typically, the turn-on voltage of the gate Schottky diode is approximately 1 V for a conventional AlGaN/GaN HEMT. For the gate recess E-type GaN HEMT, the thinned AlGaN energy barrier further reduces the turn-on voltage due to the increased tunneling current. Therefore, for an inverter based on a gate recess E-type GaN HEMT, the output voltage rises when the input voltage exceeds 0.8V. As described earlier, the E-type GaN HEMT fabricated by CF ₄ plasma treatment has a suppressed gate current due to the enhanced Schottky barrier in the AlGaN layer, which is caused by negatively charged fluoride ions. Such a gate current suppression achieves a large input voltage swing of the E/D inverter. As can be seen in Figure 41, the rise in output voltage did not occur until the input voltage exceeded 2V, indicating an approximately 1V spread of the input voltage swing. Figure 43 illustrates the dependence of load current and input current on the input voltage. A lower input current (gate current of the E-type HEMT) indicates a larger fan-out. In the "on" state, when the input voltage is greater than 2V, the input current exceeds 10% of the load current.

Example: DCFL Ring Oscillator

Figure 1B illustrates a schematic circuit diagram of a DCFL ring oscillator formed using an odd number of E/D inverter chains. The seventeen-stage ring oscillator is fabricated using β = 6.7, 10, and 25 of the inverter. For each ring oscillator, 36 transistors are used, including an output buffer. Figure 1D illustrates a photomicrograph of a ring oscillator made in accordance with the innovations. The ring oscillator was characterized on the wafer using an Agilent E4404B spectrum analyzer and an HP 54522A oscilloscope. DC power consumption is also measured during operation of the ring oscillator. 44 and 45 illustrate the frequency domain and time domain characteristics of a 17-stage ring oscillator having β = 10 at a V _{D D} = 3.5 V bias. The basic oscillation frequency is 225 MHz. According to the formula of the propagation delay of each stage τpd = (2 nf ) ^{- 1} , where the number of stages is 17, and τ _{p d is} calculated as 130 ps / level. The correlation of τ _{p d} and the power delay product to V _{D D} is plotted in Figure 46. As the supply voltage increases, the propagation delay is reduced and the power delay product is increased. Compared to τ _{p d} measured at 1V (234 ps/stage), τ _{p d} measured at 3.5 V is reduced by 45%. The fact that the ring oscillator can operate at this high V _{D D} is due to the greater input voltage swing achieved by the CF ₄ plasma processing technique used in the integrated process. A minimum power delay product of 0.113 pJ/stage was found at V _{D D} of 1V. Figure 46 also illustrates the τ _{p d} and power delay product characteristics of a ring oscillator with β = 6.7 and 25. For a ring oscillator with β = 6.7, the larger τ _{p d} and power delay product is due to the larger input capacitance determined by the larger gate length (1.5 μm) of the E-type HEMT. For a ring oscillator with β = 25, the larger τ _{p d} is due to the lower charge current determined by the larger gate length (4 μm) of the D-type HEMT, while the power delay product is at and with β = The ring oscillator of 10 has the same rating. When this integrated technique is implemented in a sub-micron system, the gate delay time is expected to be further reduced.

Recently, discrete E-type HEMT and DCFL ring oscillators have been tested at elevated temperatures up to 375 C. No significant shift was observed in the threshold voltage of the E-type HEMT, and the ring oscillator exhibited an oscillation frequency of 70 MHz at 375 C.

According to an inventive embodiment of the disclosed class, there is provided: a field effect transistor comprising: a source contact and a sink contact; a channel in a vertical dissimilar semiconductor material covered by a gate, the source being contacted with the source Absorbing contact electrical separation; the vertically different material having a higher aluminum fraction and a wider band gap near the surface; and a region of the semiconductor material that replenishes charge, which is located at the gate and Between the channels, and also extending laterally toward the absorber.

According to an inventive embodiment of the disclosed class, there is provided: a method for fabricating a semiconductor active device comprising the steps of: i) introducing a dopant into a first semiconductor material, wherein the at least one deep is formed by exposing the patterned layer Energy level, thereby introducing a charge of charge; and ii) forming a heterojunction transistor comprising a channel region in a narrower band gap semiconductor immediately below a respective portion of the first semiconductor; wherein the transistor Some of the methods further include connecting the channel region to the trapped charge over portions of the first semiconductor material of the respective absorber region.

Modifications and changes

Those skilled in the art will appreciate that the inventive concept described herein can be modified and changed in a wide range of applications, and the scope of the patent subject matter is accordingly not limited by any of the specific exemplary embodiments provided.

In the above embodiment, two levels of fixed charge are provided between the gate and the sink. However, in the alternative, additional intermediate steps may be employed as necessary, or continuous increments may be employed.

For high voltage applications, it is also possible to utilize the same technique described above for the use on the absorber side, also including a fixed charge component on the source side. This will slightly degrade the on-resistance, but may be advantageous in situations where it is necessary to withstand the maximum voltage in the HEMT.

The methods and structures described above provide new tools in electric field control. These concepts apply not only to HEMT or MISHFET devices, but also to III-N MESFET (Metal Semiconductor FET) and MOSFET devices. (The MESFET device does not use a gate insulator, but provides a Schottky barrier between the gate and the channel.)

For another example, small changes in semiconductor composition, such as the use of phosphorus-containing nitrides instead of pure nitrides, or the use of Al _x Ga _{1 - x} N on Al _y Ga _{1 - y} N heterojunctions for basic HEMT structures are Think of it as an alternative.

For another example, in the various device configurations shown, various materials may be optionally used for the gate (considering any resulting differences in work function).

Similarly, various changes or substitutions can be made in the epitaxial layer doping.

Similarly, as described above, various materials can be optionally used for the substrate.

Various disclosed embodiments provide field effect transistors having a new class of absorber engineering designs, i.e., new methods of electric field control on the absorber side. However, it is also contemplated that the disclosed transistor embodiments may be part of a combined device structure, such as where a lateral transistor is used to control the implantation of another device structure.

In another alternative embodiment, it is also contemplated that the proposed field shaped fixed charge can be used for electric field shaping in high voltage diodes, particularly on the anode side.

It is also contemplated that the present invention can be combined with conventional absorber field modification techniques, such as differential diffusion, field plates, and/or sidewall spacers.

Additional general backgrounds that help to illustrate changes and implementations can be found in the following publications, which are hereby incorporated by reference in their entirety: Y. Cai et al., IEEE EDL, Vol. 26, pp. 435-437, July 2005; W. Saito et al., IEEE T-ED, Vol. 53, pp. 356-362, February 2006; Y. Ando et al., IEEE EDL, Vol. 24, pp. 289-291, 2003; Y.F. Wu et al., IEDM 2004, pp. 1078-1079; Y. Ando et al., IEDM 2005, pp. 576-579.

No description in the present application should be construed as implying that any specific element, step, or function is required to be included in the scope of the application. The scope of the patent subject matter is defined only by the scope of the patent application that is permitted. Moreover, none of the scope of these patent applications is intended to invoke the sixth paragraph of Section 31 of 35 USC, unless the exact word "components for" follows the participle.

The scope of the patent application filed is intended to be as comprehensive as possible, and no subject matter is intentionally abandoned, dedicated or discarded.

The innovations of the present disclosure are described with reference to the drawings, which show an important exemplary embodiment of the present invention and are incorporated by reference to the accompanying drawings in which: FIG. 1 illustrates a prior art E-type HFET.

Figure 1A illustrates a schematic diagram of a DCFL circuit for an E/D inverter.

Figure 1B illustrates a DCFL circuit for a ring oscillator.

Figure 1C illustrates a photomicrograph of an inverter as an embodiment of the innovation.

Figure 1D illustrates a photomicrograph of a ring oscillator as an embodiment of the innovation.

2 illustrates the transfer characteristics of a conventional D-type HEMT, E-type HEMT, and an embodiment of the present innovation that does not utilize the innovation.

3A to 3F illustrate one embodiment of a process of fabricating an E-type AlGaN/GaN HFET.

4A illustrates the I-V output characteristics of one embodiment of an E-type AlGaN/GaN HFET.

4B illustrates I _g -V _{g s} characteristics of one embodiment of an E-type AlGaN/GaN HFET.

Figure 5 illustrates a fluoride ion concentration profile measured by "SIMS" for one embodiment of an E-type AlGaN/GaN HFET.

Figure 6 illustrates a cross section of one embodiment of the innovation prior to injection of fluoride ions.

Figure 7 illustrates a fluoride ion concentration profile measured by "SIMS" for various embodiments.

7A and 7B illustrate fluoride ion concentration profiles measured by "SIMS" of various embodiments.

Figure 8A illustrates the transfer characteristics of I _d versus V _{g s} of an E-type AlGaN/GaN HFET after different CF ₄ plasma processing conditions.

8B illustrates the transfer characteristics of the E-type AlGaN after CF ₄ plasma treatment of different conditions / GaN HFET's on V _{g s} g _m of.

Figure 9 illustrates the extracted barrier height and ideality factor for a gate Schottky diode treated with different CF ₄ plasmas.

Figure 10 illustrates the V _{t h of} various E-type AlGaN/GaN HFETs correlated with plasma power and processing time.

Figure 11 illustrates an AFM image illustrating the microetching effect of CF ₄ plasma treatment on an AlGaN layer.

Figure 12A illustrates DC I _d versus V _{g s} transfer characteristics for various E-type AlGaN/GaN HFET embodiments.

12B illustrates various DC g _m E type AlGaN / GaN HFET embodiments _s transfer characteristic of V _g.

Figure 13 illustrates the DC output characteristics of an E-type AlGaN/GaN HFET embodiment.

14A illustrates a forward and reverse gate current having ₄ plasma processing CF various different E-type AlGaN / GaN HFET embodiments.

FIG 14B illustrates an enlarged and forward gate currents with different CF ₄ plasma processing various E-type AlGaN / GaN HFET embodiments.

Figure 15 illustrates the dependence of f _t and f _{m a x} on the gate bias, where V _{d s is} fixed at 12V.

Figure 16 illustrates the measured f _t and f _{m a x} on wafers treated with different CF ₄ plasmas.

17A to 17F illustrate an exemplary process of fabricating an E-type Si ₃ N ₄ AlGaN/GaN MISHFET.

Figure 18 illustrates an exemplary DC output characteristic.

Fig. 19A illustrates the transfer characteristics.

Fig. 19B illustrates the gate leakage current.

Figure 20 illustrates the pulse measurement results.

Figure 21 illustrates the small signal RF characteristics.

Figure 22 illustrates an analog conduction band diagram of a conventional D-type AlGaN/GaN HEMT without CF ₄ plasma treatment.

Figure 23 illustrates an E-type AlGaN having a CF ₄ plasma processing / GaN HEMT of the conduction band of the analog FIG.

FIG 24 illustrates CF ₄ plasma processing is not a conventional D-type AlGaN / GaN HEMT and an E-type AlGaN having a CF ₄ plasma processing electron concentration / GaN HEMT's.

Figure 25 illustrates an embodiment of a process flow for a single-ply integrated body of E-type and D-type HEMTs of an inverter according to the present innovation.

Figures 26A through 26F illustrate an exemplary process flow for a single-rock composite of E-type and D-type HFETs.

Figure 27 illustrates the planar process flow of a single stone body.

Figure 28 illustrates another exemplary process flow for an E/D type HEMT.

Figure 29 illustrates the DC output characteristics of D-HEMT and E-HEMT fabricated by a planar process.

Figure 30 compares the transfer characteristics of a planar process with the transfer characteristics of a conventional process.

Figure 31 illustrates the static voltage transfer characteristics of an E/DHEMT inverter fabricated by a planar fabrication process.

Figure 32 illustrates the epitaxial structure of a HEMT used in an exemplary embodiment.

Figure 33 illustrates the process flow of a single-rock product of E-type and D-type HEMTs for a single-rock inverter.

Figure 34 illustrates exemplary geometric parameters of an inverter and a ring oscillator.

Figure 35 illustrates the DCI-V transfer characteristics and output characteristics of the disclosed exemplary D-type and E-type AlGaN/GaN HEMTs.

Figure 36 illustrates the performance of the fabricated E-type and D-type AlGaN/GaN HEMTs.

Figure 37 D and E illustrate the HEMT I _g -V _g characteristics and the analog sidebands turned under the gate HEMT type D and E of the HEMT.

Figure 38 illustrates the static voltage transfer characteristics of a conventional E/D HEMT inverter.

Figure 39 illustrates static voltage transfer characteristics of E/D HEMT inverters with β = 6.7, 10, 25, and 50, in accordance with various disclosed embodiments.

Figure 40 illustrates the noise margin of an inverter with different beta values.

Figure 41 illustrates the quiescent voltage transfer characteristics of an E/D HEMT inverter with β = 10 measured at different supply voltages.

Figure 42 illustrates the noise margins measured at different V _{D D for} an inverter with β = 10.

Figure 43 illustrates the load and input current of an inverter having β = 10 at V _{D D} = 2.5 V, according to an exemplary embodiment.

Figure 44 illustrates the spectrum of a 17-stage ring oscillator having β = 10 at a V _{D D} = 3.5 V bias, and Figure 45 illustrates its time domain characteristics.

Figure 46 illustrates the dependence of the propagation delay and power delay products of a circuit embodiment on the supply voltage.

Figure 47 illustrates a process flow for the fabrication of an LDD-HEMT in accordance with one embodiment of the present innovation.

Figure 47A illustrates a 2DEG of an LDD-HEMT in accordance with one embodiment of the innovation.

Figure 48 illustrates an off-state breakdown voltage for one embodiment of the innovation.

Figure 49 illustrates the correlation of the breakdown voltage to the length of the LDD region of the fixed gate-sucker spacing L _{G D} = 3 μm for various embodiments of the present innovation.

Figure 50 illustrates the DC transfer characteristics of one embodiment of the innovation.

Figure 51 illustrates the cutoff frequency of one embodiment of the innovation.

FIG 52 illustrates H _{2 1} and MSG / MAG to one embodiment of the present innovations.

Figure 53 illustrates a DC output curve for one embodiment of the innovation.

Figure 54 illustrates the on-resistance and knee voltage of various embodiments of the innovation.

Figure 55 illustrates the gate-sucker diode I-V characteristics of one embodiment of the innovation.

Figure 56 illustrates DC and pulsed I-V characteristics of various embodiments of the innovation.

Figure 57 illustrates the large signal power characteristics without the help of this innovation.

Figure 58 illustrates the large signal power characteristics of one embodiment of the innovation.

Claims (15)

A field effect transistor comprising: a source contact and a sink contact; a channel in a vertically different semiconductor material covered by a gate, the source contact being electrically separated from the absorber contact; the vertical difference The material has a higher aluminum fraction and a wider band gap near the surface; and a charge-retaining region within the semiconductor material between the gate and the channel and also laterally toward the absorber extension, wherein, after the passage of a fluorine-based plasma treatment, which employed selected from the group consisting of CF _4, SF _6, BF _3, and mixtures thereof in the feed gas. The transistor of claim 1, wherein the semiconductor material is an AlGaN/GaN layered structure. The transistor according to claim 1, wherein the semiconductor material is an epitaxial layer supported by a substrate of sapphire, yttrium, SiC, AlN or GaN. The transistor according to claim 1, wherein the semiconductor material is a nucleation layer comprising GaN or AlN, a buffer layer of GaN or AlGaN, a GaN channel, and an epitaxial structure of an AlGaN barrier. The transistor of claim 1, wherein the source contact and the absorber contact are deposited by depositing a plurality of metal layers and rapidly retreating A fire is formed in which the metal is selected from the group consisting of Ti, Al, Ni, and Au. The transistor according to claim 1, wherein the passivation selected from the group consisting of tantalum nitride, cerium oxide, polyimine, and benzocyclobutene is deposited on the transistor. Subsequent steps of the material. The transistor of claim 1 is further subjected to thermal annealing substantially at the highest temperature that does not change the Schottky barrier under the gate. A method for fabricating a semiconductor active device, comprising: i) introducing a dopant into a first semiconductor material, wherein a pattern layer is exposed thereto to form at least one deep energy level thereof, thereby introducing a trapped charge; Ii) forming a heterojunction transistor comprising a channel region in a narrower bandgap semiconductor immediately below a respective portion of the first semiconductor; wherein some of the transistors further comprise connecting the channel region The charge is added to portions of the first semiconductor material of the respective absorber regions. The method of claim 8, wherein the portion of the corresponding channel region covered by the trapped charge and also with the string Another portion of the semiconductor material that is not covered by the trapped charge is coupled to the respective absorber region. The method of claim 8, wherein some of the transistors comprise a portion of the first semiconductor material that connects the channel region to a respective absorber region, but not The channel region is coupled to the trapped charge over a portion of the first semiconductor material of the respective source region. The method of claim 8, wherein the semiconductor material is an AlGaN/GaN layered structure. The method of claim 8, wherein the semiconductor material is an epitaxial layer supported by a substrate of sapphire, yttrium, SiC, AlN or GaN. The method of claim 8, wherein the semiconductor material is a nucleation layer comprising GaN or AlN, a buffer layer of GaN or AlGaN, a GaN channel, and an epitaxial structure of an AlGaN barrier. The method of claim 8, further comprising depositing on the transistor a passivation material selected from the group consisting of tantalum nitride, hafnium oxide, polyimine, and benzocyclobutene. Next steps. The method of claim 8, further comprising thermally annealing substantially at a maximum temperature that does not change the Schottky barrier under the gate.