TWI406413B - Low density drain hemts - Google Patents
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 10
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/2003—Nitride compounds
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Abstract
Description
本申請要求2005年11月29日提交的美國臨時專利申請60/740256以及2005年12月8日提交的美國臨時專利申請60/748339的優先權,通過引用將這兩者結合於此。The present application claims priority to U.S. Provisional Patent Application No. 60/740, filed on Nov. 29, 2005, and to U.S. Provisional Application Serial No
本申請涉及常斷高電子遷移率電晶體(“HEMT”)中的崩潰電壓提高和電流崩塌抑制的方法,具體來說,涉及採用無電極吸極側表面場工程設計來製作氮化鋁鎵/氮化鎵(“AlGaN/GaN”)HEMT,從而産生“低密度吸極”HEMT。The present application relates to a method for suppressing breakdown voltage and current collapse suppression in a normally-off high electron mobility transistor ("HEMT"), and more particularly to fabricating aluminum gallium nitride using an electrodeless absorber side surface field engineering design. Gallium nitride ("AlGaN/GaN") HEMT, resulting in a "low density absorber" HEMT.
過度的電場可能在半導體器件中引起問題。(一種類型的問題是熱載流子,其中高能電子或電洞充分變為能夠穿過介質;另一種類型的問題是雪崩,其中傳導變為不受控制。)甚至在設計成以最小邏輯電壓工作的器件中,重要的是確保電壓在吸極邊界上不會過於銳利地改變;以及在用於開關較高電壓的器件中,越來越需要使峰值電場為最小。Excessive electric fields can cause problems in semiconductor devices. (One type of problem is hot carriers, where high-energy electrons or holes are fully capable of passing through the medium; another type of problem is avalanche, where conduction becomes uncontrolled.) Even designed to have a minimum logic voltage In working devices, it is important to ensure that the voltage does not change too sharply at the sinker boundary; and in devices used to switch higher voltages, there is an increasing need to minimize the peak electric field.
吸極工程設計一直是積體器件發展的最長期的子區域之一,追溯到1974年的原始LDD建議。參見Blanchard的“高電壓同時擴散矽柵CMOS”,9IEEE J.S.S.C.103(1974)。許多技術已經用來控制高壓器件中的峰值電場,通常包括場極板和非載流擴散的各種配置。Absorbent engineering design has been one of the longest-standing sub-areas of integrated device development, dating back to the original LDD recommendations of 1974. See Blanchard's "High Voltage Simultaneous Diffusion Grid CMOS", 9 IEEE J.S.S.C. 103 (1974). Many techniques have been used to control the peak electric field in high voltage devices, typically including various configurations of field plates and non-carrier diffusion.
這種長期存在的發展難題與加強模態(“E型”)III-N HEMT的較新領域特別相關。常斷AlGaN/GaN HEMT是微波功率放大器和功率電子應用所需的,因為它們提供簡化的電路配置以及對器件安全有利的工作條件。但是,常斷AlGaN/GaN HEMT與它們的常通對應物相比,通常呈現更低的最大吸極電流,特別是在臨限電壓增加到大約+1V以確保在零閘極偏壓上2DEG通道的完全截止以及提供附加工作安全性時。為了補償最大電流的減小以及取得相同的功率處理能力,崩潰電壓(VB K )需要進一步提高,但是最好不以增加的閘極-吸極距離(這不可避免地增加器件尺寸)為代價。連接到閘極或源電極的場極板的使用可通過修改表面場分佈有效地提高VB K 。但是,閘極端接的場極板可能引入附加閘極電容(CG S 和CG D ),它們減小器件的增益和截止頻率。源極端接的場極板已用於實現提高的VB K 以及減輕增益降低,但是這需要閘極和場極板之間的厚介質層。This long-standing developmental challenge is particularly relevant to the newer areas of enhanced mode ("E-type") III-N HEMT. The normally-off AlGaN/GaN HEMTs are required for microwave power amplifiers and power electronics applications because they provide simplified circuit configuration and operating conditions that are beneficial to device safety. However, normally-off AlGaN/GaN HEMTs typically exhibit lower maximum sink currents than their normally-on counterparts, especially at threshold voltages that increase to approximately +1V to ensure 2DEG channels at zero gate bias. When it is completely cut off and provides additional work safety. In order to compensate for the reduction in maximum current and to achieve the same power handling capability, the breakdown voltage (V B K ) needs to be further improved, but preferably at the expense of increased gate-sink distance (which inevitably increases device size). . The use of a field plate connected to a gate or source electrode can effectively increase V B K by modifying the surface field distribution. However, the gate plates of the gate terminals may introduce additional gate capacitances (C G S and C G D ) that reduce the gain and cutoff frequency of the device. Source-extreme field plates have been used to achieve increased V B K and mitigate gain reduction, but this requires a thick dielectric layer between the gate and the field plates.
GaN器件中的一個問題是電流崩塌現象:當源極-吸極電壓達到可能發生碰撞電離的電平時,器件承載的最大電流實際上可能減小。已經表明,這種不合需要的影響是由其中中間帶隙狀態由熱電子佔據的補獲現象引起的。One problem in GaN devices is current collapse: when the source-sink voltage reaches a level at which impact ionization may occur, the maximum current carried by the device may actually decrease. It has been shown that this undesirable effect is caused by a trapping phenomenon in which the intermediate band gap state is occupied by hot electrons.
本申請公開控制場效電晶體中的電場的新方法。公開的方法及裝置用於製作修改常斷HEMT的閘極與吸極之間的表面場分佈的HEMT。閘極與吸極之間的區域的部分或全部可採用CF4 電漿處理變換為具有低密度的2DEG的區域,從而形成低密度吸極(“LDD”)HEMT。截止狀態崩潰電壓可得到提高,以及電流崩塌可在LDD-HEMT中完全被抑制,而沒有出現增益和截止頻率的明顯降級。The present application discloses a new method of controlling the electric field in a field effect transistor. The disclosed method and apparatus are used to fabricate a HEMT that modifies the surface field distribution between the gate and the sink of a normally-off HEMT. Part or all of the area between the gate and the sink can be converted to a region of low density 2DEG using CF 4 plasma processing to form a low density absorber ("LDD") HEMT. The off-state breakdown voltage can be increased, and the current collapse can be completely suppressed in the LDD-HEMT without significant degradation in gain and cutoff frequency.
在各種實施例中,所公開的創新提供至少以下優點中的一個或多個:.允許修改常斷HEMT中的表面場分佈而不使用場極板電極。In various embodiments, the disclosed innovations provide at least one or more of the following advantages: It is allowed to modify the surface field distribution in a normally-off HEMT without using a field plate electrode.
.易於實現僅對吸極側的不對稱修改。. It is easy to achieve an asymmetrical modification of only the suction side.
.不需要拓撲的改變:加入寬帶隙能障層中的附加固定電荷不影響物理拓撲。. No change in topology is required: the addition of additional fixed charge in the wide band gap barrier does not affect the physical topology.
.提供提高的崩潰電壓和抑制的電流崩塌,而沒有出現增益或截止頻率的降級。. Provides increased breakdown voltage and suppressed current collapse without degradation of gain or cutoff frequency.
.不對增強+耗盡III-N製作已經需要的那些過程步驟添加任何附加過程步驟。. No additional process steps are added to those process steps that are already required for enhanced + depleted III-N production.
.表面狀態補獲和解補獲被減小或阻止。. Surface state compensation and solution compensation are reduced or prevented.
.電流崩塌被減小或阻止。. Current collapse is reduced or prevented.
具體參照當前優選實施例(作為實例而不是限制)來描述本申請的大量創新理論。A number of innovative theories of the present application are described with particular reference to the presently preferred embodiments, by way of example and not limitation.
本申請提供無需利用場極板電極而修改閘極與吸極之間的表面場分佈的簡單方式。通過把閘極與吸極之間的區域的部分或全部變為具有低密度的2DEG的區域,有效地形成低密度吸極(“LDD”),來實現場修改。採用相同的器件尺寸,截止狀態崩潰電壓VB K 從沒有LDD的HEMT中的60V提高到具有LDD的器件中的90V以上。在LDD-HEMT中沒有觀察到ft 的降級,以及觀察到功率增益和fm a x 的輕微改進。另外,電流崩塌在LDD-HEMT中可被完全抑制。The present application provides a simple way to modify the surface field distribution between the gate and the absorber without the use of field plate electrodes. Field modification is achieved by effectively forming a low density absorber ("LDD") by changing part or all of the area between the gate and the absorber to a region of low DEDE 2DEG. With the same device size, the off-state breakdown voltage V B K is increased from 60V in the HEMT without LDD to more than 90V in devices with LDD. No degradation of f t was observed in the LDD-HEMT, and a slight improvement in power gain and f m a x was observed. In addition, current collapse can be completely suppressed in the LDD-HEMT.
AlGaN/GaNLDD-HEMT按照圖47A至47F所示的過程來製作。在藍寶石基材上的LDD-HEMT的磊晶結構和器件製作流程與用於圖3的過程相似,除了圖47D所示的一個附加步驟,它在器件加工結束時定義LDD區域。在低密度吸極區的視窗被定義之後,在150W的RF源功率下的CF4 電漿處理應用45秒。樣本則以400℃退火10分鐘。圖47E說明成品LDD-HEMT的截面。閘極長度(LG )為1μm,以及閘極-源極間隔(LG S )為1μm。閘極-吸極間隔(LG D )被選擇為1μm或3μm。低密度吸極區的長度(LL D D )對於具有1μm LG D 的器件為0.5μm和1μm,以及對於具有3μm LG D 的器件為0.5μm、1μm、1.5μm、2μm和3μm。LDD-HEMT的不同區域中的2DEG密度分佈的示意圖如圖47F所示。為了比較測試,具有LL D D =0的傳統HEMT器件也在相同晶片上製作。The AlGaN/GaNLDD-HEMT was fabricated in accordance with the processes shown in Figs. 47A to 47F. The epitaxial structure and device fabrication flow of the LDD-HEMT on a sapphire substrate is similar to that used in Figure 3 except that in addition to the additional step shown in Figure 47D, it defines the LDD region at the end of device processing. After the window of the low density absorber region is defined, the CF 4 plasma treatment at 150 W RF source power is applied for 45 seconds. The samples were annealed at 400 ° C for 10 minutes. Figure 47E illustrates a cross section of the finished LDD-HEMT. The gate length (L G ) was 1 μm, and the gate-source spacing (L G S ) was 1 μm. The gate-sink spacing (L G D ) was chosen to be 1 μm or 3 μm. The length of the low-density absorber region (L L D D ) is 0.5 μm and 1 μm for devices having 1 μm L G D , and 0.5 μm, 1 μm, 1.5 μm, 2 μm, and 3 μm for devices having 3 μm L G D . A schematic diagram of the 2DEG density distribution in different regions of the LDD-HEMT is shown in Figure 47F. For comparison testing, a conventional HEMT device with L L D D =0 was also fabricated on the same wafer.
被加入LDD區域的AlGaN層中的氟離子提供負的固定電荷,它可調製表面電場及2DEG密度,從而允許電場的重新分佈以及峰值場的減小。LDD區域的功能在提高崩潰電壓方面與金屬場極板相似,但是沒有引入任何附加電容。其次,被加入AlGaN層的氟離子可有效地提升能帶,有效地阻擋補獲和解補獲過程。AlGaN層中氟離子的加入被認為是替位的,並且氟原子可填充AlGaN層中的氮空位。因此,與表面狀態和阱關聯的電流崩塌也可通過實現低密度吸極來抑制。The fluoride ions in the AlGaN layer added to the LDD region provide a negative fixed charge that modulates the surface electric field and the 2DEG density, allowing for redistribution of the electric field and reduction of the peak field. The function of the LDD region is similar to the metal field plate in increasing the breakdown voltage, but does not introduce any additional capacitance. Secondly, the fluoride ions added to the AlGaN layer can effectively enhance the energy band and effectively block the process of replenishment and replenishment. The addition of fluoride ions in the AlGaN layer is considered to be a substitution, and the fluorine atoms can fill the nitrogen vacancies in the AlGaN layer. Therefore, current collapse associated with surface states and wells can also be suppressed by achieving low density absorbers.
圖48說明LDD-HEMT中的崩潰電壓提高。通過把閘極-吸極區域的一半轉換為低密度區域,在VB K 方面實現50%增加。如圖48所示,具有LG D =1μm和LL D D =0.5μm的器件呈現與具有LG D =3μm和LL D D =0μm的更笨重器件(沒有LDD)中所實現的相似的崩潰電壓。VB K 與LL D D 的相關性如圖49所示。對於具有相同的LG D =3μm和不同的LL D D (0或3 μm)的器件,獲得相同的Vt h =0.75V、IM A X =300mA/mm和GM =150mS/mm。如圖50、51和52所示,LDD-HEMT顯示電流增益和ft 沒有降級、功率增益(MSG/MAG)和fm a x 輕微提高---增加的輸出電阻(RDS)的結果。施加到LDD-HEMT上的唯一不利結果是引起最多2V的膝節電壓增加的增加的導通電阻,如圖53和圖54所示,它遠遠小於VB K 的提高(>30V)。圖55表明,與傳統器件相比,在20V的偏壓上的反向閘極-吸極的漏電流在LDD-HEMT中可從25μA/mm減小到15μA/mm。圖56說明DC和脈衝I-V特性,以及說明具有不同LL D D 的氟離子的鈍化效應。隨著LL D D 增加,電流崩塌被減小,從而在閘極-吸極區域由氟離子完全處理時達到完全抑制(LL D D =3μm)。大信號測量的比較如圖57和圖58所示。由於電流崩塌,傳統HEMT的最大功率在大約0.69W/mm飽和。具有抑制的電流崩塌的LDD-HEMT呈現1.58 W/mm的最大功率。Figure 48 illustrates the breakdown voltage increase in the LDD-HEMT. A 50% increase in V B K is achieved by converting half of the gate-sucker region to a low density region. As shown in Fig. 48, a device having L G D = 1 μm and L L D D = 0.5 μm exhibits similarity to that achieved in a more bulky device (without LDD) having L G D = 3 μm and L L D D = 0 μm. The breakdown voltage. The correlation between V B K and L L D D is shown in Fig. 49. For devices with the same L G D = 3 μm and different L L D D (0 or 3 μm), the same V t h = 0.75 V, I M A X = 300 mA/mm and G M = 150 mS/mm are obtained. . As shown in Figures 50, 51 and 52, the LDD-HEMT shows the results of the current gain and f t not degraded, the power gain (MSG/MAG) and f m a x slightly increased - the increased output resistance (RDS). The only unfavorable result imposed on the LDD-HEMT is the increased on-resistance that causes the knee voltage increase of up to 2V, as shown in Figures 53 and 54, which is much less than the increase in V B K (>30V). Figure 55 shows that the reverse gate-sucker leakage current at 20V bias can be reduced from 25μA/mm to 15μA/mm in LDD-HEMT compared to conventional devices. Figure 56 illustrates DC and pulsed I-V characteristics, as well as illustrating the passivation effect of fluoride ions having different L L D D . As L L D D increases, current collapse is reduced, resulting in complete suppression (L L D D = 3 μm) when the gate-sucker region is completely treated with fluoride ions. A comparison of large signal measurements is shown in Figures 57 and 58. Due to current collapse, the maximum power of a conventional HEMT is saturated at approximately 0.69 W/mm. The LDD-HEMT with suppressed current collapse exhibited a maximum power of 1.58 W/mm.
以上所述的LDD-HEMT結構和製程可積體到採用寬帶隙層的形成圖案的氟處理的增強+耗盡製程中,現在將進行描述。The LDD-HEMT structure and process described above can be integrated into the patterned fluorine-enhanced enhancement + depletion process using a wide bandgap layer, as will now be described.
圖3A至3F說明根據本發明的第一實施例製作加強模態III氮化物HFET的過程。圖3A說明本創新的一個優選磊晶結構,在其中,參考標號110、120、130和140表示基材(例如藍寶石、矽或SiC)、核化層(低溫生長GaN核化層、AlGaN或AlN)、高溫生長GaN緩衝層以及包括調製摻雜載流子供應層的Alx Ga1 - x N能障層。下面描述一個實施例的加強模態III氮化物HFET的製造方法。臺面隔離利用Cl2 /He電漿乾式蝕刻、然後是具有以850℃退火45秒的Ti、Al、Ni和Au的源極/吸極歐姆接觸形成160來形成,如圖3B所示。隨後,光阻劑170形成圖案而曝光閘極視窗。然後,通過例如氟電漿處理或者氟離子注入,把氟離子加入Alx Ga1 - x N能障層,如圖3C所示。閘極180通過沉積和剝離Ni及Au在能障層140上形成,如圖3D所示。此後,後閘極RTA在400-450℃進行10分鐘。鈍化層190在晶片頂部生長,如圖3E所示。最後,通過消除接觸焊盤上的鈍化層的部分打開接觸焊盤,如圖3F所示。3A through 3F illustrate a process of fabricating a reinforced mode III nitride HFET in accordance with a first embodiment of the present invention. Figure 3A illustrates a preferred epitaxial structure of the present innovation in which reference numerals 110, 120, 130 and 140 denote substrates (e.g., sapphire, ruthenium or SiC), nucleation layers (low temperature grown GaN nucleation layers, AlGaN or AlN). a high temperature growth GaN buffer layer and an Al x Ga 1 - x N barrier layer including a modulation doping carrier supply layer. A method of fabricating a reinforced mode III nitride HFET of one embodiment will be described below. The mesa isolation was formed using a Cl 2 /He plasma dry etch followed by a source/sucker ohmic contact formation 160 of Ti, Al, Ni, and Au annealed at 850 ° C for 45 seconds, as shown in FIG. 3B. Subsequently, the photoresist 170 forms a pattern to expose the gate window. Then, fluoride ions are added to the Al x Ga 1 - x N barrier layer by, for example, fluorine plasma treatment or fluorine ion implantation, as shown in Fig. 3C. The gate 180 is formed on the barrier layer 140 by deposition and lift-off of Ni and Au as shown in FIG. 3D. Thereafter, the rear gate RTA was carried out at 400-450 ° C for 10 minutes. Passivation layer 190 is grown on top of the wafer as shown in Figure 3E. Finally, the contact pads are opened by eliminating portions of the passivation layer on the contact pads, as shown in Figure 3F.
在Aixtron AIX 2000 HT金屬有機化合物化學汽相沉積(MOCVD)系統中在(0001)藍寶石基材上生長AlGaN/GaN HEMT結構。HEMT結構由低溫GaN核化層、2.5-m厚的無意識摻雜GaN緩衝層以及具有標稱30% Al成分的AlGaN能障層組成。能障層由3-nm未摻雜隔離片、以2.5 x 101 8 cm- 3 摻雜的15-nm載流子供應層以及2-nm未摻雜覆蓋層組成。結構的室溫霍爾測量得到1.3x101 3 cm- 2 的電子片密度以及1000 cm2 /Vs的電子遷移率。器件臺面利用STS ICP-RIE系統中的Cl2 /He電漿乾式蝕刻、然後是具有以850℃退火45秒的Ti/Al/Ni/Au的源極/吸極歐姆接觸形成來形成。歐姆接觸電阻通常被測量為0.8 ohm-mm。The AlGaN/GaN HEMT structure was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT Metal Organic Compound Chemical Vapor Deposition (MOCVD) system. The HEMT structure consists of a low temperature GaN nucleation layer, a 2.5-m thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. Energy barrier layer is made of 3-nm undoped spacer, to 2.5 x 10 1 8 cm - 3 15-nm doped carrier supply layer, and a 2-nm undoped cover layer. Hall measurement structure at room temperature to obtain 1.3x10 1 3 cm - sheet electron density and electron mobility of 1000 cm 2 / Vs is. The device mesas were formed using a Cl 2 /He plasma dry etch in an STS ICP-RIE system followed by a source/sucker ohmic contact formation with Ti/Al/Ni/Au anneal at 850 ° C for 45 seconds. The ohmic contact resistance is typically measured as 0.8 ohm-mm.
在通過接觸光微影打開具有1 nm長度的閘極視窗之後,樣本在RIE系統中通過CF4 電漿以150 W的RF電漿功率處理150秒。處理的壓力通常為50 mTorr。經由該處理這樣加入的氟離子的典型深度分佈曲線為高斯的,以及氟濃度從峰值下降一個數量級時的典型深度是20 nm。注意,離子注入是加入氟離子的另一種方法,並且估計將需要大約10 KeV的能量。After opening the gate window with a length of 1 nm by contact photolithography, the samples were processed in a RIE system with CF 4 plasma at 150 W RF plasma power for 150 seconds. The treatment pressure is usually 50 mTorr. The typical depth profile of the fluoride ion thus added via this treatment is Gaussian, and the typical depth when the fluorine concentration drops by an order of magnitude from the peak is 20 nm. Note that ion implantation is another method of adding fluoride ions and it is estimated that about 10 KeV of energy will be required.
隨後執行Ni/Au電子束蒸發和剝離以形成閘極。電漿處理的閘極區和閘極自對準。後閘極RTA在400℃進行10分鐘。這個RTA溫度經過選擇,因為在高於500℃的溫度的RTA可能使閘極肖特基接觸和源極/吸極歐姆接觸都降級。器件具有Ls g =1 μm的源-閘極間隔以及Lg d =2μm的柵-吸極間隔。D型HEMT也在相同的樣本上製作,而沒有對閘極區進行電漿處理。Ni/Au electron beam evaporation and stripping are then performed to form a gate. The gate region and gate of the plasma treatment are self-aligned. The back gate RTA was carried out at 400 ° C for 10 minutes. This RTA temperature is chosen because RTA at temperatures above 500 °C may degrade both the gate Schottky contact and the source/sink ohmic contact. The device has a source-gate spacing of L s g =1 μm and a gate-sink spacing of L g d =2 μm. The D-type HEMT was also fabricated on the same sample without plasma treatment of the gate region.
圖2說明D型以及E型(後閘極退火之前及之後)AlGaN/GaN HEMT的轉移特性。把Vt h 定義為吸極電流的線性外插在峰值跨導( g m )點的閘極偏壓截距,E型器件的Vt h 確定為0.9V,而D型器件的Vt h 為-4.0V。高於4V的Vt h 移位通過電漿處理來實現。在Vg s =0處,跨導達到零,表明真實的E型操作。吸極電流被完全夾斷,並且在Vd s =6V時顯示28 μA/mm的泄漏,即對於E型AlGaN/GaN HEMT最近報告的最小值。峰值gm 分別對於D型HEMT為151 mS/mm以及對於E型HEMT為148 mS/mm。最大吸極電流(Im a x )對於E型HEMT在3 V的閘極偏壓(Vg s )時達到313 mA/mm。在RTA之前及之後的E型器件的電流-電壓(I-V)特性的比較表明,以400℃進行10分鐘的RTA在恢復電漿處理期間引起的損壞以及實現高電流密度和跨導方面起重要作用。圖4A說明RTA過程之前和之後的E型器件的輸出曲線。在RTA之後沒有觀察到臨限電壓的變化。在2.5V的Vg s ,以400℃進行的RTA之後的E型器件的飽和吸極電流(247 mA/mm)比RTA之前的(133 mA/mm)高85%,以及具有RTA的E型器件的膝節電壓為2.2V,其中吸極電流為95%的飽和吸極電流。在Vg s =0V的截止狀態吸極崩潰電壓大於80V,表明與D型HEMT中所觀察的相比沒有降級。圖4B說明這三個器件的Ig /Vg s 曲線。對於E型HEMT實現更低的閘極漏電流,特別是在RTA之後。Figure 2 illustrates the transfer characteristics of Al-GaN/GaN HEMTs of Type D and Type E (before and after post-gate annealing). Define V t h as the linear extrapolation of the sink current at the gate bias intercept of the peak transconductance ( g m ) point. The V t h of the E-type device is determined to be 0.9V, while the V t h of the D-type device It is -4.0V. V t h shift above 4V is achieved by plasma processing. At V g s =0, the transconductance reaches zero, indicating a true E-type operation. The sink current is completely pinched off and shows a 28 μA/mm leakage at V d s =6V, the most recently reported minimum for the E-type AlGaN/GaN HEMT. For each peak g m D-HEMT is 151 mS / mm for the E-HEMT and is 148 mS / mm. The maximum sink current (I m a x ) reaches 313 mA/mm for the E-type HEMT at a gate bias (V g s ) of 3 V. Comparison of current-voltage (I-V) characteristics of E-type devices before and after RTA shows that RTA at 400 °C for 10 minutes causes damage during recovery of plasma processing and achieves high current density and transconductance Important role. Figure 4A illustrates the output curve of an E-type device before and after the RTA process. No change in the threshold voltage was observed after RTA. At 2.5 V V g s , the saturation absorber current (247 mA/mm) of the E-type device after RTA at 400 °C is 85% higher than that before RTA (133 mA/mm), and the E-type with RTA The knee voltage of the device is 2.2V, and the sink current is 95% saturated sink current. In the off state of V g s =0 V, the sinker breakdown voltage is greater than 80 V, indicating no degradation compared to that observed in the D-type HEMT. 4B illustrates these three devices I g / V g s curve. A lower gate leakage current is achieved for the E-type HEMT, especially after the RTA.
為了研究通過CF4 電漿處理的Vt h 移位的機制,對伴隨的樣本進行二次離子質譜(SIMS)測量,以便監測CF4 電漿處理的AlGaN/GaN材料的原子組成變化。除了Al、Ga和N之外,在電漿處理後的樣本中檢測到大量氟原子。圖5說明以150W的CF4 電漿功率處理2.5分鐘的樣本的氟原子濃度分佈曲線。氟原子的濃度在AlGaN表面附近最高,並在通道中下降一個數量級。可以推斷,通過CF4 電漿所産生的氟離子被加入樣本表面,與作為開發用於實現先進矽技術中的超淺接面的技術的電漿浸入離子注入(“PIII”)的效果相似。由於氟離子的強負電性,加入的氟離子可在AlGaN能障中提供固定的負電荷並且有效地耗盡通道中的電子。隨著足夠的氟離子被加入AlGaN能障,D型HEMT可轉換為E型HEMT。CF4 電漿處理可産生大至4.9 V的臨限電壓移位元。在以400℃進行10分鐘的RTA之後,AlGaN表面附近的峰值氟原子濃度沒有改變,而AlGaN/GaN介面周圍則遇到更明顯的降低。但是應當注意,來自不同行程的SIMS測量結果由於缺乏參考標準而沒有提供精確的定量比較。然而,在RTA之前和之後的Vt h 的小變化表明,被加入AlGaN能障的氟離子的總數在RTA之前和之後接近常數,而電漿損壞則通過RTA得到較大的恢復。E型HEMT的較低閘極反向漏電流可歸因於由於氟離子加入而引起的AlGaN層的向上能帶彎曲。在RTA過程之後,CF4 所引起的金屬和AlGaN的介面上的缺陷被恢復,從而産生對閘極漏電流的進一步抑制。從對於形成圖案的樣本進行的原子力顯微術(“AFM”)測量中觀察到,電漿處理僅産生整個AlGaN能障層(20 nm厚)的0.8 nm的減小。To investigate the mechanism of V t h shift by CF 4 plasma treatment, secondary samples were subjected to secondary ion mass spectrometry (SIMS) measurements to monitor changes in the atomic composition of the CF 4 plasma treated AlGaN/GaN material. In addition to Al, Ga, and N, a large amount of fluorine atoms were detected in the plasma-treated sample. Figure 5 illustrates the fluorine atom concentration profile of a sample treated with 150 W of CF 4 plasma power for 2.5 minutes. The concentration of fluorine atoms is highest near the surface of AlGaN and drops by an order of magnitude in the channel. It can be inferred that the fluoride ions produced by the CF 4 plasma are added to the surface of the sample, similar to the effect of plasma immersion ion implantation ("PIII") as a technique for developing ultra-shallow junctions in advanced germanium technology. Due to the strong electronegativity of the fluoride ions, the added fluoride ions can provide a fixed negative charge in the AlGaN energy barrier and effectively deplete electrons in the channel. The D-type HEMT can be converted to an E-type HEMT as enough fluoride ions are added to the AlGaN energy barrier. The CF 4 plasma treatment produces a threshold voltage shifting element as large as 4.9 V. After the RTA at 400 ° C for 10 minutes, the peak fluorine atom concentration near the AlGaN surface did not change, and a more significant decrease was observed around the AlGaN/GaN interface. It should be noted, however, that SIMS measurements from different trips do not provide an accurate quantitative comparison due to the lack of reference standards. However, small changes in V t h before and after RTA indicate that the total number of fluoride ions added to the AlGaN barrier is nearly constant before and after RTA, while plasma damage is greatly restored by RTA. The lower gate reverse leakage current of the E-type HEMT can be attributed to the upward band bending of the AlGaN layer due to the addition of fluoride ions. After the RTA process, defects in the metal and AlGaN interface caused by CF 4 are recovered, resulting in further suppression of gate leakage current. It was observed from the atomic force microscopy ("AFM") measurements performed on the patterned samples that the plasma treatment produced only a 0.8 nm reduction of the entire AlGaN barrier layer (20 nm thick).
從0.1至39.1 GHz測量D型和E型AlGaN/GaN HEMT的晶片上小信號RF特性。具有1 μm長閘極的兩種類型的器件的電流增益和最大穩定增益/最大可用增益(MSG/MAG)作為頻率的函數從所測量S參數中得出,如圖5所示。在Vd s =12和Vg s =1.9 V處,對於E型AlGaN/GaN HEMT獲得10.1 GHz的電流增益截止頻率( f T )以及34.3 GHz的功率增益截止頻率( f MAX ),略小於它的D型對應物,後者的在12 V的吸極偏壓和-3V的閘極偏壓上分別測量為13.1和37.1 GHz。Small signal RF characteristics on wafers of D-type and E-type AlGaN/GaN HEMTs were measured from 0.1 to 39.1 GHz. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of the two types of devices with a 1 μm long gate are derived as a function of frequency from the measured S-parameters, as shown in Figure 5. At V d s =12 and V g s =1.9 V, a current gain cutoff frequency ( f T ) of 10.1 GHz and a power gain cutoff frequency ( f MAX ) of 34.3 GHz are obtained for the E-type AlGaN/GaN HEMT, slightly less than it. The D-type counterpart, which measures 13.1 and 37.1 GHz, respectively, at a 12 V sink bias and a -3 V gate bias.
本創新的一個優點在於,具有被加入能障層的氟離子的E型HFET可經受與更大輸入電壓擺動對應的更大閘極偏壓(>3V)。One advantage of this innovation is that an E-type HFET having fluoride ions added to the barrier layer can withstand a larger gate bias (>3V) corresponding to a larger input voltage swing.
熱可靠性測試也已經表明,AlGaN能障中的氟離子加入一直到700℃都是穩定的。但是,由鎳製作的肖特基接觸僅在500℃以下才是穩定的。因此,應用溫度範圍高達500℃,除非採用另一種肖特基接觸技術。鎢閘極是一種可能的候選者。Thermal reliability testing has also shown that the addition of fluoride ions in AlGaN barriers is stable up to 700 °C. However, Schottky contacts made of nickel are only stable below 500 °C. Therefore, the application temperature range is as high as 500 ° C unless another Schottky contact technique is used. The tungsten gate is a possible candidate.
在圖7中,說明通過SIMS測量的不同後閘極RTA對AlGaN/GaN異質接面中的氟原子分佈的影響。未處理器件用作參考。In Figure 7, the effect of different post-gate RTAs measured by SIMS on the distribution of fluorine atoms in AlGaN/GaN heterojunctions is illustrated. Unprocessed devices are used as a reference.
可以發現,通過CF4 電漿處理被加入AlGaN能障層的氟離子可有效地使臨限電壓正向移位元。AlGaN層中的氟離子的加入通過二次離子質譜(SIMS)測量來確認,如圖7所示。在CF4 電漿處理中,氟離子在RF功率所類比的自建電場中被注入AlGaN/GaN異質接面。It can be found that the fluoride ion added to the AlGaN barrier layer by the CF 4 plasma treatment can effectively shift the threshold voltage forward. The addition of fluoride ions in the AlGaN layer was confirmed by secondary ion mass spectrometry (SIMS) measurement as shown in FIG. In CF 4 plasma processing, fluoride ions are implanted into the AlGaN/GaN heterojunction in a self-built electric field analogous to RF power.
從圖7所示的結果中還得出,注入的氟離子一直到700℃都在AlGaN層中具有良好的熱穩定性。應當注意,雖然氟離子的存在被確定為臨限電壓移位元的原因,但是不清楚氟離子佔據什麽位置,是填隙還是替位。已經對於CF4 電漿所處理的HEMT樣本進行深能階瞬態光譜學(“DLTS”)。被加入AlGaN能障的氟離子看來引入低於導帶最小值至少1.8eV的深能階狀態。因此,氟離子被認為在AlGaN中引入類似帶負電荷受主的深能階。It is also found from the results shown in Fig. that the injected fluoride ions have good thermal stability in the AlGaN layer up to 700 °C. It should be noted that although the presence of fluoride ions is determined to be the cause of the threshold voltage shifting element, it is not clear where the fluoride ions occupy, whether it is interstitial or substitutable. It has deep energy level transient spectroscopy ( "DLTS") to the CF 4 plasma sample HEMT processed. The fluoride ion added to the AlGaN barrier appears to introduce a deep energy state below the conduction band minimum of at least 1.8 eV. Therefore, fluoride ions are considered to introduce deep energy levels like negatively charged acceptors in AlGaN.
注意,在例如圖7的SIMS圖表中,難以從SIMS測量中進行濃度的精確計算,因為不知道射束大小。但是,根據帶結構和臨限電壓計算,F濃度的峰值可能高到大約1 x 20 cm- 3 。Note that in a SIMS chart such as that of FIG. 7, it is difficult to perform an accurate calculation of the concentration from the SIMS measurement because the beam size is not known. However, the belt structure and calculated according to the threshold voltage, the peak of F concentration may be up to about 1 x 20 cm - 3.
在圖7A中,說明通過SIMS測量的未經RTA的不同電漿功率級對於AlGaN/GaN異質接面中的氟原子分佈的影響。In FIG. 7A, the effect of different plasma power levels without RTA measured by SIMS on the distribution of fluorine atoms in the AlGaN/GaN heterojunction is illustrated.
注意,200W和400W線條表明AlGaN/GaN介面之間的介面上的“凸起(bump)”。在加入過程中,氟離子可能填充表面或介面狀態(或“阱”),産生“反常停止”。因此,這表明在介面上存在更多阱。此外,600W和800W線條沒有表明凸起,很可能是因為更大的穿透深度和整體濃度。Note that the 200W and 400W lines indicate "bumps" on the interface between the AlGaN/GaN interfaces. During the addition process, fluoride ions may fill the surface or interface state (or "well"), resulting in an "abnormal stop." Therefore, this indicates that there are more wells at the interface. In addition, the 600W and 800W lines do not indicate bulges, most likely due to greater penetration depth and overall concentration.
未處理的器件用作參考。在圖7B中,說明通過SIMS測量的對於RTA採用600W的固定功率的不同後閘極處理溫度對AlGaN/GaN異質接面中的氟原子分佈的影響。未處理的器件用作參考。注意,700℃及以下的AlGaN中的分佈顯示根Dt的常規效果,但是AlGaN層中的分佈似乎反映極為不同的擴散率(或者可能的其他某種啟動能量效果)。因此,資料表明,氟離子在AlGaN中比在GaN中更穩定。此外,結合能可能更高,以及氟相關的能態在AlGaN中比在GaN中低於導帶的程度更大。Unprocessed devices are used as a reference. In FIG. 7B, the effect of different post gate processing temperatures of 600 W fixed power on the distribution of fluorine atoms in the AlGaN/GaN heterojunction for RTA measured by SIMS is illustrated. Unprocessed devices are used as a reference. Note that the distribution in AlGaN at 700 ° C and below shows the conventional effect of root Dt, but the distribution in the AlGaN layer seems to reflect very different diffusivity (or possibly some other starting energy effect). Therefore, the data show that fluoride ions are more stable in AlGaN than in GaN. In addition, the binding energy may be higher, and the fluorine-related energy state is greater in AlGaN than in the GaN than in the conduction band.
還研究了對於電漿處理參數的敏感度。通過應用不同的CF4 電漿功率和處理時間以不同的Vt h 值來製作器件。採用五種不同的組合:100 W、60秒,150 W、20秒,150 W、60秒,150 W、150秒以及200 W、60秒。為了進行比較,未經CF4 處理的HEMT也在相同的樣本上並且在相同的加工過程中製作。所有器件未經鈍化,以便避免鈍化層引起的任何混亂,它可能改變AlGaN層的應力並且改變壓電極化。所有HEMT器件具有1 μm的閘極長度、Ls g =1μm的源-閘極間隔以及Lg d =2μm的柵-吸極間隔。製作的器件的DC電流-電壓(I-V)特性採用HP4156A參數分析儀來測量。轉移特性和跨導(gm )特性分別如圖8A和圖8B所示。採取傳統的HEMT(即未經CF4 電漿處理)作為基線器件,所有其他CF4 電漿處理的HEMT的臨限電壓移向正方向。把Vt h 定義為在峰值跨導(gm )點的吸極電流的線性外插的閘極偏壓截距,所有器件的Vt h 在圖9中提取並列出。對於傳統的HEMT,Vt h 為-4 V。對於通過CF4 電漿以150 W處理150秒的HEMT,Vt h 為0.9V,它對應於E型HEMT。實現4.9V的最大Vt h 移位。為了進一步揭示CF4 電漿處理的效果,Vt h 與CF4 電漿處理時間以及RF功率的相關性在圖10中繪出曲線。隨著電漿功率增大以及採用更長的處理時間,實現Vt h 的更大移位。隨著電漿處理時間的增加,更多氟離子被注入AlGaN層。增大的氟離子濃度導致通道中減小的電子密度,並且引起Vt h 的正移位。當電漿功率增大時,氟離子獲得更高能量,以及氟離子流量因CF4 的增強電離速率而增大。採用更高的能量,氟離子可達到更接近通道的更深的深度。氟離子越接近通道,則它們在耗盡2DEG時更有效,並且實現Vt h 的更大移位。增大的氟離子流量對Vt h 具有與通過提高AlGaN層中的氟原子濃度的電漿處理時間的增加相同的效果。應當注意,准線性Vt h 對時間以及Vt h 對功率關係表明AlGaN/GaN HEMT的Vt h 的準確控制的可能性。雖然Vt h 通過CF4 電漿處理被移位,但是gm 沒有降級。如圖8B所示,所有器件的最大gm 處於149-166 mS/mm的範圍內,除了以150 W處理60秒的器件之外,它具有186 mS/mm的更高峰值gm 。猜想這個奇異點由磊晶生長中的非一致性引起。通過對CF4 處理的形成圖案的樣本(其中,樣本的一部分被處理,並防止其他部分經過電漿處理)進行的AFM測量來確定,CF4 電漿處理僅産生小於1 nm的AlGaN厚度減小,如圖11所示。因此,接近恒定的跨導表明,根據本創新,在器件製作中保持通道中的2DEG遷移率。保持跨導的一個關鍵步驟是後閘極退火過程。Sensitivity to plasma processing parameters was also investigated. The device was fabricated with different V t h values by applying different CF 4 plasma powers and processing times. Five different combinations are used: 100 W, 60 seconds, 150 W, 20 seconds, 150 W, 60 seconds, 150 W, 150 seconds, and 200 W, 60 seconds. For comparison, untreated CF 4 HEMT treated and also on the same sample prepared in the same processing. All devices are not passivated in order to avoid any confusion caused by the passivation layer, which may alter the stress of the AlGaN layer and change the piezoelectric polarization. All HEMT devices have a gate length of 1 μm, a source-gate spacing of L s g =1 μm, and a gate-sink spacing of L g d = 2 μm. The DC current-voltage (I-V) characteristics of the fabricated device were measured using an HP4156A parametric analyzer. The transfer characteristics and transconductance (g m ) characteristics are shown in Figures 8A and 8B, respectively. Conventional HEMT (ie, without CF 4 plasma treatment) was used as the baseline device, and the threshold voltage of all other CF 4 plasma treated HEMTs moved in the positive direction. V t h is defined as the linear extrapolated gate bias intercept of the sink current at the peak transconductance (g m ) point, and V t h of all devices is extracted and listed in FIG. For a conventional HEMT, V t h is -4 V. For a HEMT treated with CF 4 plasma at 150 W for 150 seconds, V t h is 0.9 V, which corresponds to the E-type HEMT. A maximum V t h shift of 4.9V is achieved. In order to reveal the effects of CF 4 plasma treatment, the plotted curve 10 in FIG V t h correlation with the CF 4 plasma processing time and RF power. A larger shift in V t h is achieved as the plasma power increases and longer processing times are employed. As the plasma processing time increases, more fluoride ions are implanted into the AlGaN layer. The increased fluoride ion concentration results in a reduced electron density in the channel and causes a positive shift in V t h . When the plasma power is increased, a higher energy of fluorine ions, fluorine ions, and the ionization rate of flow enhancement due to CF 4 increases. With higher energy, fluoride ions can reach deeper depths closer to the channel. The closer the fluoride ions are to the channel, they are more efficient at depleting 2DEG and achieve a larger shift in V t h . The increased fluoride ion flow rate has the same effect as V t h as the increase in plasma treatment time by increasing the fluorine atom concentration in the AlGaN layer. It should be noted that the quasi-linear V t h versus time and V t h versus power relationship indicates the possibility of accurate control of the V t h of the AlGaN/GaN HEMT. Although V t h was shifted by CF 4 plasma treatment, g m was not degraded. 8B, the maximum g m for all devices in the 149-166 mS / mm in a range of 150 W in addition to the devices for 60 seconds, it has higher peak 186 mS / mm of g m. It is suspected that this singularity is caused by the inconsistency in epitaxial growth. It was determined by AFM measurements of CF 4 treated patterned samples (where a portion of the sample was processed and other parts were treated with plasma) that CF 4 plasma treatment produced only a decrease in AlGaN thickness of less than 1 nm. , as shown in Figure 11. Thus, a near constant transconductance indicates that according to this innovation, the 2DEG mobility in the channel is maintained during device fabrication. A key step in maintaining transconductance is the post-gate annealing process.
如前面所述,電漿通常引起損壞,並産生半導體材料中的缺陷,因而使載流子的遷移率降級。RTA是一種修復這些損壞並恢復遷移率的有效方法。在CF4 電漿處理的AlGaN/GaN HEMT中,吸極電流和跨導降級就在電漿處理之後發生。在圖12A和圖12B中,繪製了在RTA(400℃,10分鐘)之前和之後在未處理器件和已處理器件(200 W,60秒)上測量的吸極電流和跨導的曲線。圖13比較RTA之前和之後的已處理器件的輸出特性。在已處理器件中RTA之後,吸極電流高76%,以及跨導高51%。RTA過程可恢復電漿處理後的器件的遷移率降級的大部分,而對傳統的未處理器件表現出不明顯影響。因此,CF4 電漿處理的器件中的Id 和gm 的恢復是在這個RTA條件上的2DEG遷移率的有效恢復的結果。與在凹槽閘極的情況中恢復由基於氯的ICP-RIE所産生的損壞所需的700℃的較高退火溫度相比,這個較低的RTA溫度錶明CF4 電漿處理産生比基於氯的ICP-RIE更低的損壞。它還使RTA過程能夠在閘極沉積之後進行,從而實現自對準製程的目標。如果採用Vt h 的先前定義,則CF4 電漿處理的器件的Vt h 在RTA之後似乎從0.03V移位到-0.29V。當圖12B所示的gm 的起始點或者圖12A的插入圖所示的對數標度上的Id 的起始點用作評估Vt h 的標準時,CF4 電漿處理後的器件的Vt h 在RTA之後沒有改變。Vt h 的良好熱穩定性與先前所述的AlGaN層中的氟原子的良好熱穩定性一致。As mentioned previously, the plasma typically causes damage and creates defects in the semiconductor material, thereby degrading the mobility of the carriers. RTA is an effective way to fix these damages and restore mobility. In the CF 4 plasma treated AlGaN/GaN HEMT, the sink current and transconductance degradation occur after the plasma treatment. In Figures 12A and 12B, plots of absorber current and transconductance measured on untreated and processed devices (200 W, 60 seconds) before and after RTA (400 ° C, 10 minutes) are plotted. Figure 13 compares the output characteristics of processed devices before and after RTA. After the RTA in the processed device, the sink current is 76% higher and the transconductance is 51% higher. The RTA process restores most of the mobility degradation of the plasma treated device, while exhibiting no significant effect on conventional unprocessed devices. Therefore, the recovery of I d and g m in the CF 4 plasma treated device is the result of an effective recovery of 2DEG mobility on this RTA condition. This lower RTA temperature indicates a CF 4 plasma treatment yield ratio compared to the higher annealing temperature of 700 ° C required to recover the damage caused by chlorine-based ICP-RIE in the case of a groove gate. Chlorine ICP-RIE is less damaged. It also enables the RTA process to be performed after gate deposition, thereby achieving the goal of a self-aligned process. If V t h previously defined, the CF 4 plasma processing device of the V t h appears after RTA displaced from 0.03V to -0.29V. When the starting point of g m shown in FIG. 12B or the starting point of I d on the logarithmic scale shown in the inset of FIG. 12A is used as a criterion for evaluating V t h , the device after CF 4 plasma treatment V t h did not change after RTA. The good thermal stability of V t h is consistent with the good thermal stability of the fluorine atoms in the previously described AlGaN layer.
AlGaN/GaN HEMT始終呈現遠遠高於熱離子發射(“TE”)模型的理論預測值的反向閘極漏電流。較高的閘極電流使器件的雜訊性能降級,並且提高待機功耗。具體來說,正向閘極電流限制閘極輸入電壓擺動,因而限制最大吸極電流。已經嘗試其他方式來抑制AlGaN/GaN HEMT的閘極電流。這些努力包括採用具有較高功函數的閘極金屬、採用銅、修改HEMT結構(例如添加GaN覆蓋層)或者轉向金屬絕緣體半導體異質接面場效電晶體(MISHFET)。在本創新的CF4 電漿處理的AlGaN/GaN HEMT中,可實現反向以及正向偏壓區中的閘極電流的抑制。閘極電流抑制表明與CF4 電漿處理條件的相關性。AlGaN/GaN HEMTs always exhibit a reverse gate leakage current that is much higher than the theoretical prediction of the thermionic emission ("TE") model. Higher gate currents degrade the noise performance of the device and increase standby power. Specifically, the forward gate current limits the gate input voltage swing, thus limiting the maximum sink current. Other ways have been tried to suppress the gate current of the AlGaN/GaN HEMT. These efforts include the use of gate metals with higher work functions, the use of copper, modified HEMT structures (such as the addition of GaN cap layers), or the turning of metal insulator semiconductor heterojunction field effect transistors (MISHFETs). In the inventive CF 4 plasma treated AlGaN/GaN HEMT, suppression of gate current in the reverse and forward bias regions is achieved. Gate current suppression indicates a correlation with CF 4 plasma processing conditions.
圖14A和圖14B說明採用不同的CF4 電漿處理的AlGaN/GaN HEMT的閘極電流。圖14B是正向閘極偏壓區的放大曲線。在反向偏壓區中,與未經CF4 電漿處理的傳統HEMT相比,所有CF4 電漿處理的AlGaN/GaN HEMT的閘極漏電流減小。在Vg =-20V,閘極漏電流從傳統HEMT的1.2×10- 2 A/mm到以200W電漿處理60秒的AlGaN/GaN HEMT的7×10- 7 A/mm下降超過四個數量級。在正向區中,所有CF4 電漿處理的AlGaN/GaN HEMT的閘極電流也減小。因此,閘極肖特基二極體的導通電壓擴展,以反閘極輸入電壓擺動增加。採用1 mA/mm作為標準,閘極肖特基二極體的導通電壓從傳統HEMT的1 V增加到以200 W經60秒的CF4 電漿處理的AlGaN/GaN HEMT的1.75 V。14A and 14B illustrate different gate currents of AlGaN CF 4 plasma processing / GaN HEMT's. Fig. 14B is an enlarged graph of the forward gate bias region. In the reverse bias region, compared to the conventional HEMT without a CF 4 plasma treatment, AlGaN all CF 4 plasma processing / GaN HEMT of the gate leakage current is reduced. AlGaN 2 A / mm to 60 seconds at 200W plasma / GaN HEMT of 7 × 10 - - at V g = -20V, gate leakage from the conventional HEMT of 1.2 × 10 7 A / mm decreased more than four orders of magnitude . In the forward region, the gate current of all CF 4 plasma treated AlGaN/GaN HEMTs is also reduced. Therefore, the turn-on voltage of the gate Schottky diode is expanded to increase the swing of the input voltage of the anti-gate. With a 1 mA/mm standard, the turn-on voltage of the gate Schottky diode increases from 1 V in a conventional HEMT to 1.75 V in an AlGaN/GaN HEMT treated with 200 W of 60 sec CF 4 plasma.
CF4 電漿處理的AlGaN/GaN HEMT中的閘極漏電流的抑制可說明如下。在CF4 電漿處理中,氟離子被加入AlGaN層。具有強負電性的這些離子用作固定負電荷,它們因靜電感應效應而引起AlGaN能障層中的向上導帶彎曲。因此,形成如圖23所示的附加能障高度ΦF ,以及有效金屬半導體能障高度從ΦB 增加到ΦB +ΦF 。這種增加的能障高度可有效地抑制反向以及正向偏壓區中的閘極肖特基二極體電流。採用更高的電漿功率和更長的處理時間,AlGaN層中的氟離子濃度增加,以及有效能障高度進一步提高,從而産生更顯著的閘極電流抑制。在圖9中,詳細說明通過利用TE模型從測量的閘極電流的正向區提取的有效能障高度和理想因數。傳統HEMT的有效能障高度為0.4eV,而對於以200 W進行60秒的CF4 電漿處理的HEMT,有效能障高度增加到0.9eV。CF4 電漿處理的HEMT的有效能障高度還顯示隨電漿功率和處理時間增加的趨勢,除了以150 W處理20秒的HEMT之外,它具有較高的有效能障高度。這個例外被認為是由於加工變化引起的。所提取有效能障高度遠遠低於理論預測值和很大的理想因數(>2.4)的事實表明,製作的AlGaN/GaN HEMT的閘極電流不是由TE機制而是由其他機制、如垂直隧穿、表面能障細化以及阱輔助隧穿來控制的。因此,通過利用TE模型提取的能障高度和理想因數不準確。然而,它們提供用於說明CF4 電漿處理的AlGaN/GaN HEMT中的閘極電流抑制的機制的充分定性資訊。The suppression of the gate leakage current in the CF 4 plasma-treated AlGaN/GaN HEMT can be explained as follows. In the CF 4 plasma treatment, fluoride ions are added to the AlGaN layer. These ions having strong electronegativity serve as fixed negative charges which cause the upward conduction band bending in the AlGaN barrier layer due to the electrostatic induction effect. Therefore, an additional energy barrier height Φ F as shown in FIG. 23 is formed, and the effective metal semiconductor energy barrier height is increased from Φ B to Φ B + Φ F . This increased barrier height effectively suppresses the gate Schottky diode current in the reverse and forward bias regions. With higher plasma power and longer processing time, the concentration of fluoride ions in the AlGaN layer increases, and the effective barrier height is further increased, resulting in more significant gate current suppression. In Fig. 9, the effective barrier height and ideal factor extracted from the forward region of the measured gate current by using the TE model are explained in detail. The effective barrier height of the conventional HEMT is 0.4 eV, and for a HEMT treated with 60 seconds of CF 4 plasma at 200 W, the effective barrier height is increased to 0.9 eV. The effective barrier height of the CF 4 plasma treated HEMT also shows a trend with increasing plasma power and processing time, which has a higher effective barrier height than the HET treated at 150 W for 20 seconds. This exception is considered to be due to processing changes. The fact that the extracted effective energy barrier height is much lower than the theoretical prediction value and a large ideal factor (>2.4) indicates that the gate current of the fabricated AlGaN/GaN HEMT is not by the TE mechanism but by other mechanisms such as vertical tunneling. Wear, surface energy barrier refinement, and well assisted tunneling to control. Therefore, the energy barrier height and ideal factor extracted by using the TE model are not accurate. However, they provide information about well-characterized mechanism for explaining the gate current AlGaN CF 4 plasma processing / GaN HEMT of the inhibition.
動態I-V特性通過利用Accent DIVA D265系統研究CF4 電漿處理對吸極電流擴散的影響來進行。脈衝寬度為0.2μs,並且脈衝間隔為1 ms。靜點處於略(~0.5V)低於夾斷斷的VG S ,且VD S =15V。與靜態I-V特性相比,傳統D型HEMT的最大吸極電流降低63%,而採用以150 W進行150秒的CF4 電漿處理的E型HEMT的最大吸極電流降低6%。The dynamic I-V characteristics were investigated by studying the effect of CF 4 plasma treatment on the absorption of the sink current by using the Accent DIVA D265 system. The pulse width is 0.2 μs and the pulse interval is 1 ms. The static point is slightly (~0.5V) lower than the pinch-off V G S and V D S =15V. Compared to the static I-V characteristics, the maximum sink current of the conventional D-type HEMT is reduced by 63%, while the maximum sink current of the E-type HEMT treated with CF 4 plasma of 150 seconds at 150 W is reduced by 6%.
E型HEMT的吸極電流下降的減輕可能是由靜點的提高的閘極偏壓引起的(對於E型HEMT,VG S =0V,對於D型HEMT,VG S =-4.5V)。The decrease in the sink current drop of the E-type HEMT may be caused by the increased gate bias of the dead point (V G S = 0 V for the E-type HEMT and V G S = -4.5 V for the D-type HEMT).
製作的AlGaN/GaN HEMT的晶片上小信號RF特性描述利用Cascade微波探針和Agilent 8722ES網路分析儀在0.1-39.1GHz的頻率範圍上進行。採用假焊盤的S參數來執行開放焊盤解嵌,以便消除探測焊盤的寄生電容。具有1 μm長的閘極的所有器件的電流增益和最大穩定增益/最大可用增益(MSG/MAG)作為頻率的函數從解嵌S參數中得出。電流截止頻率( f t )和最大振盪頻率( f m a x )以單位增益從電流增益和MSG/MAG中提取。已經觀察到,本質ft 和fm a x 在沒有解嵌過程時一般比非本質的高10-15%。對於E型HEMT, f t 和 f m a x 與閘極偏壓的相關性如圖15所示。 f t 以及 f m a x 在低和高閘極偏壓上都比較恒定,表明良好線性度。圖16列出所有樣本的 f t 和 f m a x 。對於傳統的HEMT, f t 和 f m a x 為13.1和37.1GHz,而對於CF4 電漿處理的HEMT, f t 和 f m a x 近似為10和34GHz,略低於傳統的HEMT,但是除以150W處理60秒的HEMT之外。150W/60秒的器件中的這個較高的 f t 和 f m a x 與之前提供的較高的 g m 一致,並且歸因於材料不一致性和加工變化。CF4 電漿處理的HEMT中略低的 f t 和 f m a x 表明,以400℃進行的後閘極RTA可有效地恢復通過電漿處理而降級的2DEG遷移率,但恢復小於100%。我們建議,需要RTA溫度和時間的優化來進一步改進2DEG遷移率,同時沒有使閘極肖特基接觸降級。The on-wafer small-signal RF characterization of the fabricated AlGaN/GaN HEMTs was performed using a Cascade microwave probe and an Agilent 8722ES network analyzer over a frequency range of 0.1-39.1 GHz. The open pad de-embedding is performed using the S-parameter of the dummy pad to eliminate the parasitic capacitance of the detection pad. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of all devices with a gate length of 1 μm are derived from the de-embedded S-parameter as a function of frequency. The current cutoff frequency ( f t ) and the maximum oscillation frequency ( f m a x ) are extracted from the current gain and MSG/MAG in unity gain. It has been observed that the natures f t and f m a x are generally 10-15% higher than non-essential in the absence of a de-embedding process. For the E-type HEMT, the correlation between f t and f m a x and the gate bias is shown in FIG. Both f t and f m a x are relatively constant at both the low and high gate biases, indicating good linearity. Figure 16 lists f t and f m a x for all samples. For conventional HEMTs, f t and f m a x are 13.1 and 37.1 GHz, while for CF 4 plasma treated HEMT, f t and f m a x are approximately 10 and 34 GHz, slightly lower than the conventional HEMT, but except It is processed at 150W for 60 seconds outside the HEMT. This higher f t and f m a x in a 150 W/60 second device is consistent with the previously provided higher g m and is attributed to material inconsistencies and processing variations. The slightly lower f t and f m a x in the CF 4 plasma treated HEMT indicate that the post-gate RTA at 400 ° C effectively recovers the 2DEG mobility that is degraded by plasma treatment, but recovers less than 100%. We recommend that RTA temperature and time optimization be required to further improve 2DEG mobility without degrading the gate Schottky contact.
在另一個實施例中,E型Si3 N4 /AlGaN/GaN MISHFET採用兩級Si3 N4 過程來構建,它以閘極之下的Si3 N4 薄層(15nm)以及出入區中的Si3 N4 厚層(大約125nm)為特色。基於氟的電漿處理用於把器件從D型轉換到E型。具有1-μm長閘極覆蓋面積的E型MISHFET呈現2V的臨限電壓、6.8V(與E型AlGaN/GaN HEMT中實現的大約3V進行比較)的正向導通閘極偏壓以及420mA/mm的最大電流密度。In another embodiment, the E-type Si 3 N 4 /AlGaN/GaN MISHFET is constructed using a two-stage Si 3 N 4 process with a thin layer of Si 3 N 4 (15 nm) under the gate and in the entry and exit regions. A thick layer of Si 3 N 4 (about 125 nm) is featured. Fluorine-based plasma processing is used to convert the device from D to E. E-type MISHFET with a 1-μm long gate coverage area exhibits a 2V threshold voltage, 6.8V (compared to approximately 3V implemented in an E-type AlGaN/GaN HEMT), and a forward-going gate bias and 420mA/mm Maximum current density.
這個實例中使用的AlGaN/GaN HFET結構在Aixtron AIX 2000 HT MOCVD系統中的(0001)藍寶石基材上生長。HFET結構由50-nm厚的低溫GaN核化層、2.5-μm厚的無意識摻雜GaN緩衝層以及具有標稱30% Al成分的AlGaN能障層組成。能障層由3-nm未摻雜隔離片、以2×101 8 cm- 3 摻雜的16-nm載流子供應層以及2-nm未摻雜覆蓋層組成。水銀探針進行的電容-電壓(“C-V”)測量對於這個樣本産生-4V的初始臨限電壓。加工流程如圖17A至17F所示。器件臺面利用STS ICP-RIE系統中的Cl2 /He電漿乾式蝕刻、然後是具有以850℃退火30秒的Ti/Al/Ni/Au(20 nm/150 nm/50 nm/80 nm)的源極/吸極歐姆接觸形成來形成,如圖17A所示。然後,第一Si3 N4 層(大約125 nm)通過電漿增強化學汽相沉積(PECVD)沉積到樣本上,如圖17B所示。在通過光微影打開具有1-μm長度的閘極視窗之後,樣本放在RIE系統中經過CF4 電漿處理,它在AlGaN中消除Si3 N4 和加入氟離子。電漿的RF功率為150W,如圖17C所示。氣流被控制為150 sccm,以及總蝕刻和處理時間是190秒。在消除光阻劑之後,第二Si3 N4 薄膜(大約15 nm)通過PECVD被沉積以便形成閘極金屬與AlGaN之間的絕緣層,如圖17D所示。隨後,Si3 N4 層被形成圖案和蝕刻,以便在源極和吸極歐姆接觸區域中打開視窗,如圖17E所示。然後,2-μm長的閘極通過光微影、然後是Ni/Au(~50 nm/300 nm)的電子束蒸發和剝離來定義,如圖17F所示。為了確保閘極覆蓋整個電漿處理區域,金屬閘極長度(2 μm)被選擇為大於已處理閘極區(1 μm),從而産生T閘極配置。懸於源/吸極出入區域中的閘極通過厚Si3 N4 層與AlGaN層絕緣,使閘極電容保持在低水平。最後,整個樣本以400℃退火10分鐘,以便修復AlGaN能障和通道中的電漿引起的損壞。從閘極的底部進行測量,閘極-源極和閘極-吸極間隔均為1.5 μm。對於dc測試採用10 μm的閘極寬度以及對於RF特徵描述採用100 μm的閘極寬度來設計E型MISHFET。The AlGaN/GaN HFET structure used in this example was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT MOCVD system. The HFET structure consists of a 50-nm thick low temperature GaN nucleation layer, a 2.5-μm thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. Energy barrier layer is made of 3-nm undoped spacer, to 2 × 10 1 8 cm - 3 16-nm doped carrier supply layer, and a 2-nm undoped cover layer. The capacitance-voltage ("C-V") measurement performed by the mercury probe produces an initial threshold voltage of -4V for this sample. The processing flow is as shown in Figs. 17A to 17F. The device mesa was dried by Cl 2 /He plasma in an STS ICP-RIE system followed by Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) annealed at 850 °C for 30 seconds. A source/sucker ohmic contact is formed to form as shown in FIG. 17A. Then, a first Si 3 N 4 layer (about 125 nm) was deposited onto the sample by plasma enhanced chemical vapor deposition (PECVD) as shown in FIG. 17B. After opening the gate window with a length of 1-μm by photolithography, the sample was placed in a RIE system and subjected to CF 4 plasma treatment, which eliminated Si 3 N 4 and added fluoride ions in AlGaN. The RF power of the plasma was 150 W as shown in Fig. 17C. The gas flow was controlled to 150 sccm and the total etching and processing time was 190 seconds. After the photoresist is removed, a second Si 3 N 4 film (about 15 nm) is deposited by PECVD to form an insulating layer between the gate metal and AlGaN, as shown in FIG. 17D. Subsequently, the Si 3 N 4 layer is patterned and etched to open the window in the source and absorber ohmic contact regions, as shown in Figure 17E. Then, a 2-μm long gate is defined by photolithography, followed by electron beam evaporation and lift-off of Ni/Au (~50 nm/300 nm), as shown in Fig. 17F. To ensure that the gate covers the entire plasma processing area, the metal gate length (2 μm) is selected to be larger than the processed gate region (1 μm), resulting in a T gate configuration. The gate suspended in the source/sink-in and out regions is insulated from the AlGaN layer by a thick Si 3 N 4 layer, keeping the gate capacitance at a low level. Finally, the entire sample was annealed at 400 ° C for 10 minutes to repair the damage caused by the plasma in the AlGaN barrier and the channel. Measured from the bottom of the gate, the gate-source and gate-sink spacing are both 1.5 μm. An E-type MISHFET was designed for a dc test using a gate width of 10 μm and a gate width of 100 μm for RF characterization.
所構建的器件則被表徵。在圖18中繪製了E型MISHFET的DC輸出特性。在VG S =7V,器件呈現大約420 mA/mm的峰值電流密度、大約5.67Ω.mm的導通電阻以及大約3.3V的膝節電壓。圖19A說明具有1×10-μm閘極尺寸的相同器件的轉移特性。可以看到,Vt h 大約為2V,表明通過插入Si3 N4 絕緣體和電漿處理實現的Vt h 的6-V移位(與傳統的D型HFET進行比較)。峰值跨導gm大約為125 mS/mm。圖19B說明負偏壓以及正向偏壓時的閘極漏電流。閘極的正向偏壓導通電壓大約為6.8V,提供比E型HFET大得多的閘極偏壓擺動。採用0.2 μs的脈衝長度和1 ms的脈衝間隔對具有1×100-μm閘極尺寸的E型MISHFET進行脈衝測量。靜態偏壓點選擇在VG S =0V(低於Vt h )和VD S =20V。圖20表明,脈衝峰值電流高於靜態的,表明器件中沒有電流崩塌。具有100-μm閘極寬度的大器件的靜態最大電流密度大約為330 mA/mm,小於具有10-μm閘極寬度的器件(大約420 mA/mm)。較大器件中的較低峰值電流密度是由於降低電流密度的自動加熱效應引起的。由於在脈衝測量期間出現極小自動加熱,因此,100-μm寬的器件的最大電流可達到與10-μm寬的器件相同的電平。晶片上小信號RF特性從0.1至39.1GHz在VD S =10V對100-μm寬的E型MISHFET執行。如圖21所示,最大電流增益截止頻率(fT )和功率增益截止頻率(fm a x )分別為13.3和23.3GHz。當閘極偏壓為7V時,小信號RF性能沒有明顯降級,其中具有13.1GHz的fT 和20.7GHz的fm a x ,表明Si3 N4 絕緣體提供閘極金屬與半導體之間的良好絕緣。The device being constructed is characterized. The DC output characteristics of the E-type MISHFET are plotted in FIG. At V G S =7V, the device exhibits a peak current density of approximately 420 mA/mm, approximately 5.67 Ω. The on resistance of mm and the knee voltage of approximately 3.3V. Figure 19A illustrates the transfer characteristics of the same device having a gate size of 1 x 10-μm. It can be seen that V t h is approximately 2 V, indicating a 6-V shift of V t h achieved by insertion of a Si 3 N 4 insulator and plasma treatment (compared to a conventional D-type HFET). The peak transconductance gm is approximately 125 mS/mm. Fig. 19B illustrates the gate leakage current at the negative bias and forward bias. The forward biased turn-on voltage of the gate is approximately 6.8V, providing much greater gate bias swing than the E-type HFET. Pulse measurements were made on an E-type MISHFET having a gate size of 1 x 100-μm using a pulse length of 0.2 μs and a pulse interval of 1 ms. The static bias point is chosen at V G S =0V (below V t h ) and V D S =20V. Figure 20 shows that the pulse peak current is higher than static, indicating no current collapse in the device. Large devices with a gate width of 100-μm have a static maximum current density of approximately 330 mA/mm, which is less than devices with a gate width of 10-μm (approximately 420 mA/mm). The lower peak current density in larger devices is due to the automatic heating effect that reduces current density. Due to the minimal auto-heating during pulse measurement, the maximum current of a 100-μm wide device can reach the same level as a 10-μm wide device. The small signal RF characteristics on the wafer were performed from 0.1 to 39.1 GHz at V D S = 10 V to a 100-μm wide E-type MISHFET. As shown in FIG. 21, the maximum current gain cutoff frequency (f T ) and the power gain cutoff frequency (f m a x ) are 13.3 and 23.3 GHz, respectively. When the gate bias is 7V, the small-signal RF performance is not significantly degraded, with f T of 13.1 GHz and f m a x of 20.7 GHz, indicating that the Si 3 N 4 insulator provides good insulation between the gate metal and the semiconductor. .
為本創新的一部分開發了理論表徵模型。對於具有矽調製摻雜層的傳統AlGaN/GaN HEMT,如圖7所示,在計算HEMT臨限電壓時需要考慮極化電荷。通過考慮電荷極化、表面和緩衝阱的效應從一般使用的公式進行修改,AlGaN/GaN HEMT的臨限電壓可表示為:
其中參數定義如下:φ B 是金屬半導體肖特基能障高度。The parameters are defined as follows: φ B is the metal semiconductor Schottky barrier height.
σ是在能障-AlGaN/GaN介面上的總淨(自發的以及壓電的)極化電荷。σ is the total net (spontaneous and piezoelectric) polarized charge on the barrier-AlGaN/GaN interface.
d是AlGaN能障層厚度。d is the thickness of the AlGaN barrier layer.
N s i (x )是矽摻雜濃度。 N s i ( x ) is the erbium doping concentration.
△E C 是在AlGaN/GaN異質接面上的導帶偏移。Δ E C is the conduction band offset on the AlGaN/GaN heterojunction.
E f0 是GaN通道的本質費米能階與導帶邊緣之間的差。 E f0 is the difference between the essential Fermi level of the GaN channel and the edge of the conduction band.
ε是AlGaN的介電常數。ε is the dielectric constant of AlGaN.
N s t 是每個單位面積的淨電荷表面阱。 N s t is the net charge surface well per unit area.
N b 是每個單位面積的有效淨電荷緩衝阱。 N b is an effective net charge buffer well per unit area.
C b 是每個單位面積的有效緩衝-通道電容。 C b is the effective buffer-channel capacitance per unit area.
等式(1)中的最後兩項分別描述表面阱和緩衝阱的效應。AlGaN表面處於x=0,以及指向通道的方向為積體的正方向。為了表示以上所述的器件,固定負電荷被引入閘極之下的AlGaN能障層。由於靜電感應,這些固定負電荷可耗盡通道中的2DEG,提高能帶,因而調製Vt h
。包括AlGaN能障中限定的負電荷的效應,從等式(1)修改的臨限電壓表示為:
正電荷分佈曲線N si (x )由淨電荷分佈N si (x )-N F (x )代替,其中N F (x )為帶負電荷氟離子的濃度。表面阱密度(N st )可通過電漿處理來修改。The positive charge distribution curve N si ( x ) is replaced by a net charge distribution N si ( x ) - N F ( x ), where N F ( x ) is the concentration of the negatively charged fluoride ion. The surface well density ( N st ) can be modified by plasma processing.
通過應用泊松方程和費米-迪拉克統計,類比由帶有和沒有被加入AlGaN層的氟離子的AlGaN/GaN HEMT結構的導帶分佈曲線和電子分佈來組成。兩種結構都具有相同的磊晶結構,如圖7所示。對於加入氟離子的HEMT結構,帶負電荷氟離子的分佈曲線從通過CF4 電漿以150 W處理150秒並轉換為E型HEMT的AlGaN/GaN HEMT結構的氟原子分佈的SIMS測量結果中提取。在圖22和圖23中繪製了零閘極偏壓時的類比導帶圖。對於E型HEMT的類比導帶,如圖22所示,氟濃度通過利用峰值氟濃度在AlGaN表面為3x10 19 cm- 3 的線性分佈來近似計算,以及氟濃度假定為在AlGaN/GaN介面上是可忽略的。大約3x101 3 cm- 2 的總氟離子片濃度足以不僅補償AlGaN能障中的矽摻雜(大約3.7x101 3 cm- 2 ),而且還補償壓電和自發極化感應電荷(大約1x101 3 cm- 2 )。可觀察到兩個顯著特徵。首先,與未處理AlGaN/GaN HEMT結構相比,電漿處理的結構的2DEG通道的導帶最小值高於費米能階,表明完全耗盡的通道和E型HEMT。如圖24中的電子分佈曲線所示,在電漿處理的結構中,在零閘極偏壓下的通道中沒有電子,表明E型HEMT操作。其次,固定帶負電荷氟離子特別在AlGaN能障中導致導帶的向上彎曲,從而産生附加能障高度ΦF ,如圖23所示。這種增強的能障可明顯抑制反向以及正向偏壓區中的AlGaN/GaN HEMT的閘極肖特基二極體電流。By applying the Poisson equation and Fermi-Dillac statistics, the analogy consists of a conduction band profile and an electron distribution of an AlGaN/GaN HEMT structure with and without fluoride ions added to the AlGaN layer. Both structures have the same epitaxial structure, as shown in Figure 7. For the HEMT structure with fluoride ion added, the distribution curve of the negatively charged fluoride ion was extracted from the SIMS measurement of the fluorine atom distribution of the AlGaN/GaN HEMT structure processed by CF 4 plasma at 150 W for 150 seconds and converted to E-type HEMT. . An analog conduction band diagram for zero gate bias is plotted in Figures 22 and 23. E analogy to the conduction band of the HEMT type, as shown, the fluorine concentration in the AlGaN surface 22 through 3x10 19 cm using fluorine concentration peak - 3 linear distribution to approximate calculation, and the fluorine concentration is assumed to be in the AlGaN / GaN interface ignorable. A total fluoride ion concentration of about 3x10 1 3 cm - 2 is sufficient to compensate not only for erbium doping (about 3.7x10 1 3 cm - 2 ) in AlGaN barriers, but also for piezoelectric and spontaneous polarization induced charges (about 1x10 1 3 cm - 2 ). Two salient features can be observed. First, the conduction band minimum of the 2DEG channel of the plasma-treated structure is higher than the Fermi level compared to the untreated AlGaN/GaN HEMT structure, indicating a fully depleted channel and an E-type HEMT. As shown in the electron distribution curve in Figure 24, in the plasma treated configuration, there is no electron in the channel under zero gate bias, indicating E-type HEMT operation. Second, the fixed negatively charged fluoride ion causes an upward bending of the conduction band, particularly in the AlGaN energy barrier, resulting in an additional energy barrier height Φ F , as shown in FIG. This enhanced energy barrier significantly suppresses the gate Schottky diode current of the AlGaN/GaN HEMT in the reverse and forward bias regions.
單石積體E/D型HFET的磊晶結構由以下各項組成:(a)半導體基材(藍寶石,SiC,矽,AlN或GaN等);(b)在基材上生長的緩衝層;(c)通道層;(d)能障層,包括未摻雜間隔層、調製摻雜載流子供應層和未摻雜覆蓋層。製作過程包括:(f)有源區隔離;(g)源極和吸極端子上的歐姆接觸形成;(h)E型HFET的閘極區域的光微影;(i)對E型HFET的曝光能障層的基於氟化物的電漿處理;(j)E型HFET的閘極金屬沉積;(k)D型HFET的閘極區的光微影;(l)D型HFET的閘極金屬沉積;ml)D型和E型HFET的表面鈍化;(n)以升高的溫度進行的閘極退火。這種單石積體的示意加工流程如圖25所示。The epitaxial structure of the single-rock integrated E/D type HFET is composed of: (a) a semiconductor substrate (sapphire, SiC, germanium, AlN or GaN, etc.); (b) a buffer layer grown on the substrate; c) a channel layer; (d) an energy barrier layer comprising an undoped spacer layer, a modulated doped carrier supply layer, and an undoped cap layer. The fabrication process includes: (f) active area isolation; (g) ohmic contact formation on the source and sink terminals; (h) photolithography of the gate region of the E-type HFET; (i) for the E-type HFET Fluoride-based plasma treatment of the exposure barrier; (j) gate metal deposition of the E-type HFET; (k) photolithography of the gate region of the D-type HFET; (1) gate metal of the D-type HFET Deposition; ml) surface passivation of D-type and E-type HFETs; (n) gate annealing at elevated temperatures. The schematic processing flow of such a single stone body is shown in FIG.
上述單石積體過程中的主動元件隔離採用臺面蝕刻,它以通過蝕刻技術在沒有HFET的區域中的有源區域消除為特色。這種方法對積體密度、光微影解析度施加限制。對於高頻電路,臺面的邊緣還對波的傳播引入附加間斷,這又使電路設計和分析複雜化。由於基於氟化物的電漿處理能夠耗盡通道中的電子(提供通道的電氣截止),因此可用於器件隔離。採用增加的電漿功率和處理時間,不需要主動元件的區域可在電氣上完全截止,從而提供器件之間的電氣隔離。這種方法不涉及任何材料消除,因而實現平面製程的平坦晶片表面。The active device isolation in the monolithic process described above employs a mesa etch that features an active region elimination in the region without the HFET by etching techniques. This method imposes restrictions on the density of the integrated body and the resolution of the light lithography. For high frequency circuits, the edge of the mesa also introduces additional discontinuities in the propagation of the wave, which in turn complicates circuit design and analysis. Fluoride-based plasma processing can be used for device isolation because it can deplete electrons in the channel (providing electrical cutoff of the channel). With increased plasma power and processing time, regions that do not require active components can be electrically fully turned off, providing electrical isolation between the devices. This method does not involve any material removal, thus achieving a flat wafer surface in a planar process.
圖26A至26F說明根據本發明的一個實施例單石積體積體電路的E/D型HFET的過程。圖26A說明本發明的一個優選磊晶結構,其中參考標號110、120、130和140表示基材、低溫生長GaN核化層、高溫生長GaN緩衝層以及包括調製摻雜載流子供應層的Alx Ga1 - x N能障層。積體電路的E/D型HFET的單石積體的製造方法如下所述。對於D型以及E型HFET,臺面隔離同時利用Cl2 /He電漿乾式蝕刻、然後是具有以850℃退火45秒的Ti、Al、Ni和Au的源極/吸極歐姆接觸形成160來形成,如圖26B所示。閘極以及D型HFET的閘極-源極互連如圖26C所示通過光阻劑170來形成圖案,之後跟隨沉積和剝離Ni和Au 178。此後,E型HFET的閘極、焊盤和第二互連採用光阻劑175來形成圖案,如圖26D所示。然後,例如通過氟化物電漿處理或者氟化物離子注入,把氟化物離子加入E型HFET的閘極之下的Alx Ga1 - x N能障層,如圖26D所示。閘極180通過沉積和剝離Ni及Au在能障層140上形成。此後,後閘極快速熱退火(RTA)在400-450℃進行10分鐘。鈍化層190在晶片頂部生長,如圖26E所示。然後,通過消除接觸焊盤和通孔上的鈍化層的部分將它們打開,如圖26F所示。最後,形成第三互連。26A through 26F illustrate the process of an E/D type HFET of a single-magnet volume circuit in accordance with one embodiment of the present invention. Figure 26A illustrates a preferred epitaxial structure of the present invention, wherein reference numerals 110, 120, 130 and 140 denote a substrate, a low temperature grown GaN nucleation layer, a high temperature grown GaN buffer layer, and an Al comprising a modulated dopant carrier supply layer. x Ga 1 - x N barrier layer. The manufacturing method of the single-rock integrated body of the E/D type HFET of the integrated circuit is as follows. For D-type and E-type HFETs, mesa isolation is formed using both Cl 2 /He plasma dry etching followed by source/sink ohmic contact formation 160 with Ti, Al, Ni, and Au annealed at 850 ° C for 45 seconds. As shown in Fig. 26B. The gate and source interconnections of the gate and D-type HFET are patterned by photoresist 170 as shown in Figure 26C, followed by deposition and stripping of Ni and Au 178. Thereafter, the gate, pad and second interconnect of the E-type HFET are patterned using a photoresist 175 as shown in FIG. 26D. Fluoride ions are then added to the Al x Ga 1 - x N barrier layer under the gate of the E-type HFET, for example by fluoride plasma treatment or fluoride ion implantation, as shown in Figure 26D. The gate 180 is formed on the barrier layer 140 by depositing and stripping Ni and Au. Thereafter, the post gate rapid thermal annealing (RTA) was carried out at 400-450 ° C for 10 minutes. A passivation layer 190 is grown on top of the wafer as shown in Figure 26E. Then, they are opened by eliminating portions of the contact pads and the passivation layer on the via holes, as shown in Fig. 26F. Finally, a third interconnect is formed.
在對於E型HFET以150 W進行150秒的典型CF4 電漿處理條件和以450℃進行10分鐘的典型後閘極RTA條件的2μm GaN緩衝層上的20nm Al0 . 2 5 Ga0 . 7 5 N能障層上建立E/D HFET反相器和17級直接耦合環形振盪器。反相器在1.5V的電源電壓上具有0.21V的NML 和0.51V的NMH 。當施加3.5V的電源電壓時,17級環形振盪器呈現與130 ps的最小傳播延遲對應的225 MHz的最大振盪頻率。20 nm Al 0 . 2 5 Ga 0 . 7 on a 2 μm GaN buffer layer for a typical CF 4 plasma treatment condition of 150 Hz for E-type HFETs and a typical post-gate RTA condition of 10 minutes at 450 ° C. An E/D HFET inverter and a 17-stage direct-coupled ring oscillator are built up on the N N barrier. The inverter has a NM L of 0.21 V and a NM H of 0.51 V at a supply voltage of 1.5V. When a supply voltage of 3.5V is applied, the 17-stage ring oscillator exhibits a maximum oscillation frequency of 225 MHz corresponding to a minimum propagation delay of 130 ps.
這個實施例描述E型和D型AlGaN/GaN HFET的平面單石積體的方法。如第一實施例所述,主動元件之間的隔離可通過經由建立非平坦晶片表面的蝕刻建立主動元件臺面來獲得。在積體電路製作中,平面製程始終是符合需要的。遵照通過AlGaN中的帶負電荷氟離子的通道耗盡的相同原理,可實現通過基於氟化物的電漿處理的預期無源(被隔離)區域的耗盡。電漿功率和處理時間均可增加,以便增強載流子耗盡。加工流程如圖27所示,其中:(a)源極/吸極歐姆接觸形成;(b)通過光微影進行的D型HFET閘極定義;(c)D型HFET閘極金屬化以及互連形成的部分;(d)通過光微影之後跟隨電漿處理進行的E型HFET閘極定義;(e)E型HFET閘極金屬化和互連形成的部分;(f)通過光微影之後跟隨第二基於氟化物的電漿處理進行的隔離區域定義;(g)之後跟隨鈍化的最終晶片。This embodiment describes a method of planar monolithic integration of E-type and D-type AlGaN/GaN HFETs. As described in the first embodiment, isolation between active elements can be achieved by establishing an active element mesa via etching that establishes a non-planar wafer surface. In the production of integrated circuits, the planar process is always in line with the needs. Depletion of the expected passive (isolated) regions by fluoride-based plasma processing can be achieved following the same principle of depletion of channels with negatively charged fluoride ions in AlGaN. Both plasma power and processing time can be increased to enhance carrier depletion. The processing flow is shown in Figure 27, where: (a) source/sink ohmic contact formation; (b) D-type HFET gate definition by photolithography; (c) D-type HFET gate metallization and mutual The portion formed; (d) the definition of the E-type HFET gate followed by photolithography followed by the plasma treatment; (e) the portion formed by the gate metallization and interconnection of the E-type HFET; (f) the lithography through the light The isolation region definition followed by the second fluoride-based plasma treatment is followed; (g) followed by the passivated final wafer.
這個實例中的AlGaN/GaN HEMT結構在Aixtron AIX 2000 HT MOCVD系統中的(0001)藍寶石基材上生長。HEMT結構由低溫GaN核化層、2.5-μm厚的無意識摻雜GaN緩衝層以及具有標稱30% Al成分的AlGaN能障層組成。能障層由3-nm未摻雜隔離片、以2 x 1018 cm- 3 摻雜的21-nm載流子供應層以及2-nm未摻雜覆蓋層組成。結構的室溫霍爾測量産生1.3x1013 cm- 2 的電子片密度以及950 cm2 /Vs的電子遷移率。The AlGaN/GaN HEMT structure in this example was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT MOCVD system. The HEMT structure consists of a low temperature GaN nucleation layer, a 2.5-μm thick unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal 30% Al composition. The barrier layer consists of a 3-nm undoped spacer, a 21-nm carrier supply layer doped with 2 x 1018 cm - 3 , and a 2-nm undoped overlay. Hall measurements at room temperature to produce a configuration of 1.3x1013 cm - sheet electron density and electron mobility of 950 cm 2 / Vs is.
積體製程流程如圖28所示。首先,E/D型器件的源極/吸極歐姆接觸同時通過電子束蒸發的Ti/Al/Ni/Au(20 nm/150 nm/50 nm/80 nm)的沉積和以850℃進行30秒的快速熱退火來形成,如圖28(a)所示。其次,E/D型兩種器件的有源區域通過光微影來形成圖案,其後跟隨反應離子蝕刻系統中的CF4 電漿處理。電漿功率為300W,以及處理時間為100秒。氣流被控制為150sccm,以及電漿偏壓設置為0V。隔離區域是其中大量氟離子被加入表面附近的AlGaN和GaN層、然後耗盡通道中的二維電子氣的位置,如圖28(b)所示。然後,D型HEMT的閘極通過接觸光微影、之後跟隨Ni/Au(50 nm/300 nm)的電子束蒸發和剝離來形成圖案,如圖28(c)所示。隨後,定義E型HEMT的閘極和互連。在Ni/Au的電子束蒸發之前,E型HEMT的閘極區域通過CF4 電漿以170 W處理150秒(它具有對AlGaN的可忽略的蝕刻),如圖28(d)所示。這個電漿處理執行把處理的器件從D型轉換為E型HEMT的功能。200nm厚的氮化矽鈍化層通過PECVD沉積,以及打開探測焊盤。然後,樣本以400℃退火10分鐘,以便修復E型HEMT的AlGaN能障和通道中的電漿引起的損壞,如圖28(e)所示。作為比較,D型器件在來自相同基材的另一個樣本上通過標準製程來製作,在標準製程中,感應耦合電漿反應離子蝕刻用於把臺面定義為有源區域。對於圖1A所示的直接耦合FET邏輯反相器,E型HEMT驅動器設計成閘極長度、閘極-源極間隔、閘極-吸極間隔和閘極寬度分別為1.5、1.5、1.5和50 μm;D型HEMT負載設計成閘極長度、閘極-源極間隔、閘極-吸極間隔和閘極寬度為4、3、3和8 μm,産生16.7的比率β=(WE /LE )/(WD /LD )。對於表徵製作具有1.5×100μm的閘極尺寸的分立E型和D型HEMT。The process of the product system is shown in Figure 28. First, the source/sink ohmic contact of the E/D device is simultaneously deposited by electron beam evaporation of Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) and at 850 ° C for 30 seconds. Rapid thermal annealing is formed as shown in Figure 28(a). Second, the active regions of the E/D type devices are patterned by photolithography, followed by CF 4 plasma processing in a reactive ion etching system. The plasma power is 300W and the processing time is 100 seconds. The gas flow was controlled to 150 sccm and the plasma bias was set to 0V. The isolation region is a position in which a large amount of fluorine ions are added to the AlGaN and GaN layers in the vicinity of the surface, and then the two-dimensional electron gas in the channel is depleted, as shown in Fig. 28(b). Then, the gate of the D-type HEMT is patterned by contact photolithography followed by electron beam evaporation and lift-off of Ni/Au (50 nm/300 nm) as shown in Fig. 28(c). Subsequently, the gates and interconnections of the E-type HEMT are defined. Prior to electron beam evaporation of Ni/Au, the gate region of the E-type HEMT was treated with CF 4 plasma at 170 W for 150 seconds (which has negligible etching of AlGaN) as shown in Figure 28(d). This plasma processing performs the function of converting the processed device from a D-type to an E-type HEMT. A 200 nm thick tantalum nitride passivation layer was deposited by PECVD and the probe pads were opened. Then, the sample was annealed at 400 ° C for 10 minutes in order to repair the AlGaN barrier of the E-type HEMT and the plasma-induced damage in the channel, as shown in Fig. 28(e). In comparison, a D-type device was fabricated on a standard sample from another sample from the same substrate. In a standard process, inductively coupled plasma reactive ion etching was used to define the mesa as the active region. For the direct coupled FET logic inverter shown in Figure 1A, the E-type HEMT driver is designed for gate length, gate-source spacing, gate-sink spacing, and gate widths of 1.5, 1.5, 1.5, and 50, respectively. Μm; D-type HEMT load is designed as gate length, gate-source spacing, gate-sink spacing and gate width of 4, 3, 3 and 8 μm, yielding a ratio of 16.7 = (W E / L E ) / (W D / L D ). For the characterization of discrete E-type and D-type HEMTs having a gate size of 1.5 x 100 μm.
對於通過平面製程製作的E/D型HEMT,在圖29中繪製了輸出特性。D型和E型HEMT的峰值電流密度大約為730和190 mA/mm。圖30說明平面與標準製程之間的DC轉移特性比較。可以看到,平面製程的吸極漏電流大約為0.3mA/mm,達到與通過標準臺面蝕刻製作的器件相同的水平。通過平面製程的D型HEMT具有與通過標準製程的相當的吸極電流和跨導特性,如圖30(b)所示。另外,兩個焊盤之間(400×100 μm2 )的漏電流採用150 μm的間隔來測量。在10V的DC偏壓上,在標準臺面蝕刻樣本的相同電平(大約30μA),通過平面製程的漏電流大約為38μA。與標準臺面製程相比,基於氟化物的電漿處理可實現主動元件隔離的相同等級,從而實現完全平面積體製程。與D型器件相比,E型HEMT呈現更小的跨導(“ g m ”),這是由電漿引入的損壞的不完全恢復引起的。樣本已經通過以400℃進行的熱退火的事實還表明,在至少一直到400℃的溫度上預計有良好的熱穩定性。應當注意,還開發離子注入技術用於通過多個能量N+注入以便在GaN緩衝層的整個厚度上産生嚴重晶格損壞所實現的器件間隔離。與離子注入技術相比,CF4 電漿處理技術具有低成本和低損壞的優點。For the E/D type HEMT fabricated by the planar process, the output characteristics are plotted in FIG. The peak current densities of the D and E HEMTs are approximately 730 and 190 mA/mm. Figure 30 illustrates a comparison of DC transfer characteristics between a plane and a standard process. It can be seen that the inductive leakage current of the planar process is approximately 0.3 mA/mm, which is the same level as that fabricated by standard mesa etching. The D-type HEMT through the planar process has the same attractor current and transconductance characteristics as the standard process, as shown in Fig. 30(b). In addition, the leakage current between the two pads (400 × 100 μm 2 ) was measured at intervals of 150 μm. At a DC bias of 10 V, the same level (about 30 μA) of the sample was etched on a standard mesa, and the leakage current through the planar process was approximately 38 μA. Compared to standard countertop processes, fluoride-based plasma treatment achieves the same level of active component isolation for a fully flat area process. Compared with the device type D, E mode HEMT exhibits a smaller transconductance ( "g m"), which is introduced by a plasma damage due to incomplete recovery. The fact that the sample has passed the thermal annealing at 400 ° C also indicates that good thermal stability is expected at temperatures up to at least 400 ° C. It should be noted that ion implantation techniques have also been developed for inter-device isolation achieved by multiple energy N+ implants to create severe lattice damage over the entire thickness of the GaN buffer layer. Compared to ion implantation technology, CF 4 plasma processing technology has the advantages of low cost and low damage.
通過平面積體製程製作的E/D型HEMT DCFL反相器被表徵。圖31說明在電源電壓VD D =3.3V的反相器的測量靜態電壓轉移曲線。高和低輸出邏輯電平(VO H 和VO L )分別為3.3和0.45 V,其中具有2.85V的輸出擺動(VO H -VO L )。線性區域中的DC電壓增益為2.9。通過定義單位增益點上的VI L 和VI H 的值,低和高雜訊邊限為0.34和1.47 V。在圖31中還示出反相器DC電流。具有E型器件夾斷的漏電流大約為3 μA,它與分立器件結果一致。An E/D type HEMT DCFL inverter fabricated by a flat area process was characterized. Figure 31 illustrates the measured static voltage transfer curve of an inverter at a supply voltage V D D = 3.3V. The high and low output logic levels (V O H and V O L ) are 3.3 and 0.45 V, respectively, with an output swing of 2.85V (V O H -V O L ). The DC voltage gain in the linear region is 2.9. The low and high noise margins are 0.34 and 1.47 V by defining the values of V I L and V I H at the unity gain point. The inverter DC current is also shown in FIG. The leakage current with the E-type device pinch-off is approximately 3 μA, which is consistent with discrete device results.
圖32說明根據本創新的HEMT的製作期間的AlGaN/GaN磊晶異質接面。它們包括以下各項:2.5 μm GaN緩衝層和通道,2 nm未摻雜Al0 . 2 5 Ga0 . 7 5 N間隔片,具有以1×1018 cm- 3 摻雜的Si的15nm Al0 . 2 5 Ga0 . 7 5 N載流子供應層,以及3 nm未摻雜Al0 . 2 5 Ga0 . 7 5 N覆蓋層。結構在Aixtron 2000 HT MOCVD系統中在藍寶石基材上生長。製程流程如圖33(a)至33(f)所示。Figure 32 illustrates an AlGaN/GaN epitaxial heterojunction during fabrication of a HEMT in accordance with the present innovation. These include the following: 2.5 μm GaN buffer layer and a channel, 2 nm undoped Al 0 2 5 Ga 0 7 5 N spacer, having a 1 × 1018 cm - 3 Si-doped 15nm Al 0... 2 5 Ga 0 . 7 5 N carrier supply layer, and 3 nm undoped Al 0 . 2 5 Ga 0 . 7 5 N cover layer. The structure was grown on a sapphire substrate in an Aixtron 2000 HT MOCVD system. The process flow is shown in Figures 33(a) through 33(f).
臺面和源極/吸極歐姆接觸同時為E型以及D型HEMT形成,如圖33(a)和(b)所示。然後,D型HEMT的閘極通過光微影、金屬沉積和剝離來形成,如圖33(c)和(d)所示。在定義E型HEMT的閘極和互連的圖案之後,樣本在STS RIE系統中通過CF4 電漿以150 W的源功率處理150秒,如圖33(e)所示,然後是對於E型HEMT的閘極金屬化和剝離。通過原子力顯微學(“AFM”)測量來檢查,AlGaN能障厚度在電漿處理之後減小0.8 nm。隨後,後閘極熱退火以450℃進行10分鐘,如圖33(f)所示。CF4 電漿處理把處理的GaN HEMT從D型轉換為E型。臨限電壓移位元量取決於處理條件,例如電漿功率和處理時間,如前面所述。後閘極退火用於恢復AlGaN能障和通道中的電漿引入的損壞。原則上,退火溫度越高,損壞修復越有效。但是,實際上,後閘極退火溫度不應當超過閘極肖特基接觸可經受的最高溫度(在我們的情況中,~500℃),如前面所述。我們發現,D型HEMT的特性在退火之後保持不變,而E型HEMT的吸極電流密度則顯著增加。發現後閘極退火對於電漿處理所産生的臨限電壓移位元沒有影響。The mesa and source/sucker ohmic contacts are formed simultaneously for the E-type and D-type HEMTs, as shown in Figures 33(a) and (b). Then, the gate of the D-type HEMT is formed by photolithography, metal deposition, and lift-off as shown in FIGS. 33(c) and (d). After defining the gate and interconnect pattern of the E-type HEMT, the sample is processed in the STS RIE system with CF 4 plasma at 150 W source power for 150 seconds, as shown in Figure 33(e), then for the E-type. Gate metallization and stripping of HEMT. It was examined by atomic force microscopy ("AFM") measurements that the thickness of the AlGaN barrier was reduced by 0.8 nm after plasma treatment. Subsequently, the post gate was thermally annealed at 450 ° C for 10 minutes as shown in Fig. 33 (f). The CF 4 plasma treatment converts the treated GaN HEMT from D to E. The threshold voltage shift amount depends on processing conditions, such as plasma power and processing time, as previously described. The post gate anneal is used to recover the damage introduced by the plasma in the AlGaN barrier and the channel. In principle, the higher the annealing temperature, the more effective the damage repair. However, in practice, the post gate anneal temperature should not exceed the maximum temperature that the gate Schottky contact can withstand (in our case, ~500 ° C), as previously described. We found that the characteristics of the D-type HEMT remained unchanged after annealing, while the absorber current density of the E-type HEMT increased significantly. It was found that the post gate annealing had no effect on the threshold voltage shifting elements generated by the plasma treatment.
對於E/D反相器和環形振盪器,最重要的物理設計參數是驅動/負載比β=(Wg /Lg )E型/(Wg /Lg )D型。具有從6.7至50變化的β的若干E/D反相器和環形振盪器在相同樣本上設計和製作。在圖34中列出各設計的幾何參數。具有1×100μm的閘極尺寸的分立E型和D型GaN HEMT對於dc和RF測試在相同樣本上同時製作。For E/D inverters and ring oscillators, the most important physical design parameter is the drive/load ratio β = (W g / L g ) E type / (W g / L g ) D type. Several E/D inverters and ring oscillators with beta varying from 6.7 to 50 were designed and fabricated on the same sample. The geometric parameters of each design are listed in Figure 34. Discrete E-type and D-type GaN HEMTs with a gate size of 1 x 100 μm were fabricated simultaneously on the same sample for dc and RF testing.
分立器件的DC電流-電壓(I-V)特性採用HP4156A參數分析儀來測量。在圖35(a)中繪製了E/D型HEMT的轉移特性。分立器件的晶片上小信號RF表徵利用Cascade微波探針和Agilent 8722ES網路分析儀在0.1-39.1 GHz的頻率範圍中進行。在圖36中列出E/D型HEMT的測量參數。臨限電壓和峰值跨導(gm , m a x )對於E型HEMT為0.75V和132mS/mm,以及對於D型HEMT為-2.6V和142mS/mm。D型HEMT的480mA/mm的較低峰值電流密度是由於AlGaN能障層中25%的較低Al成分和1×1018 cm- 3 的較低摻雜密度引起的。與用於RF/微波功率放大器的AlGaN/GaN HEMT不同,數位IC對電流密度的要求較小。如圖35(b)所示,對於E型HEMT獲得2.5V的低膝節電壓。在2.5V的閘極偏壓上,對於E型HEMT實現7.1 Ω.mm的導通電阻,它與相同飽和電流電平上的D型HEMT的導通電阻相同。一種觀察結果是,與D型HEMT相比,反向以及正向偏壓條件中的閘極電流在E型HEMT中顯著減小,如圖37(a)所示。這種閘極電流抑制的機制是通過由電漿處理所引入的帶負電荷氟離子調製AlGaN能障中的電勢。通過求解泊松方程和費米-迪拉克統計,對於D以及E型HEMT類比導邊帶圖。對於E型HEMT的類比導帶,氟分佈的分佈曲線通過線性函數來近似計算,該函數的特點是在AlGaN表面上的3×1019 cm- 3 的最大氟離子濃度並在AlGaN/GaN介面上達到零(可忽略)。大約3×1013 cm- 2 的總氟離子片濃度足以不僅補償大約3.7×1012 cm- 2 的Si+施主的濃度,而且還補償壓電和自發極化感應電荷(大約1×1013 cm- 2 )。應當注意,閘極/AlGaN結上的肖特基能障高度在本例中假定為保持不變。從圖37(b)和(c)所示的類比導帶看到,AlGaN能障的電勢可通過氟離子的加入顯著提高,從而産生增強的肖特基能障以及後續的閘極電流抑制。正向偏壓中的閘極電流抑制對於數位IC應用特別有益。抑制的閘極電流允許E型器件的閘極偏壓增加到2.5V。這種增加産生更大的閘極電壓擺動、輸入的更大動態範圍以及更高的扇出。增加的輸入電壓擺動允許更高的電源電壓,它在實現數位IC的更高操作速度和更高雜訊邊限時是一個重要因素。沒有增加的閘極輸入擺動,較大的電源電壓將産生超過下一級的輸入閘極的導通電壓的輸出電壓(在邏輯“高”)。輸入的更寬動態範圍實現輸入與輸出之間的直接邏輯電平匹配,從而消除對相鄰級之間的電平調節的需要。The DC current-voltage (I-V) characteristics of discrete devices were measured using the HP4156A parametric analyzer. The transfer characteristics of the E/D type HEMT are plotted in Fig. 35(a). On-wafer small-signal RF characterization of discrete devices was performed using a Cascade microwave probe and an Agilent 8722ES network analyzer in the frequency range of 0.1-39.1 GHz. The measurement parameters of the E/D type HEMT are listed in FIG. The threshold voltage and peak transconductance (g m , m a x ) were 0.75 V and 132 mS/mm for the E-type HEMT and -2.6 V and 142 mS/mm for the D-type HEMT. 480mA / mm lower peak current density of the HEMT due to the D-type AlGaN barrier layer can be 25% lower Al composition and 1 × 1018 cm - 3 lower doping density caused. Unlike AlGaN/GaN HEMTs for RF/microwave power amplifiers, digital ICs require less current density. As shown in Fig. 35(b), a low knee voltage of 2.5 V was obtained for the E-type HEMT. On the gate bias of 2.5V, 7.1 Ω is achieved for the E-type HEMT. The on-resistance of mm, which is the same as the on-resistance of a D-type HEMT at the same saturation current level. One observation is that the gate current in the reverse and forward bias conditions is significantly reduced in the E-type HEMT compared to the D-type HEMT, as shown in Figure 37 (a). This mechanism of gate current suppression is to modulate the potential in the AlGaN energy barrier by negatively charged fluoride ions introduced by plasma processing. By classifying the Poisson equation and the Fermi-Dillac statistics, the D and E HEMT analog lead bands are plotted. For the E-HEMT analogy conduction band profile fluoro distribution be approximated by a linear function, the characteristics of the function is on the AlGaN surface 3 × 1019 cm - Maximum fluoride ion concentration 3 and reaches the AlGaN / GaN interface Zero (can be ignored). About 3 × 1013 cm - total fluorine ion sheet concentration of about 2 is sufficient to compensate for only 3.7 × 1012 cm - Si + 2 concentration of the donor, but also compensated piezoelectric and spontaneous polarization-induced charges (about 1 × 1013 cm - 2). It should be noted that the Schottky barrier height on the gate/AlGaN junction is assumed to remain constant in this example. From the analog conduction band shown in Figures 37(b) and (c), the potential of the AlGaN barrier can be significantly increased by the addition of fluoride ions, resulting in an enhanced Schottky barrier and subsequent gate current suppression. Gate current suppression in forward bias is particularly beneficial for digital IC applications. The suppressed gate current allows the gate bias of the E-type device to increase to 2.5V. This increase results in a larger gate voltage swing, a larger dynamic range of input, and a higher fan-out. The increased input voltage swing allows for higher supply voltages, which is an important factor in achieving higher operating speeds and higher noise margins for digital ICs. Without an increased gate input swing, a larger supply voltage will produce an output voltage (in logic "high") that exceeds the turn-on voltage of the input gate of the next stage. The wider dynamic range of the input enables direct logic level matching between the input and output, eliminating the need for level adjustment between adjacent stages.
應當注意,作為一般用於基於GaN的HEMT的穩定操作的重要技術的氮化矽鈍化還可在較低程度上影響臨限電壓。一般來說,氮化矽鈍化層在有源區域上的沉積可改變AlGaN和GaN層中的應力。隨後,器件的壓電極化電荷密度和臨限電壓可經過少量修改。一般來說,通過高頻PECVD沉積的廣泛使用的氮化矽層在AlGaN層中引入附加張應力,從而産生十分之幾伏特的範圍中的臨限電壓的負移位元。實際上,這種影響應當在製程設計中加以考慮。電漿處理劑量可相應增加,從而補償通過SiN鈍化層産生的臨限電壓中的負移位元。SiN鈍化層的應力還可通過修改PECVD沉積的製程參數來減小,使得臨限電壓中的負移位元為最小。It should be noted that tantalum nitride passivation, which is an important technique generally used for stable operation of GaN-based HEMTs, can also affect the threshold voltage to a lesser extent. In general, the deposition of a tantalum nitride passivation layer over the active region can alter the stress in the AlGaN and GaN layers. Subsequently, the device's piezoelectric polarization charge density and threshold voltage can be modified slightly. In general, the widely used tantalum nitride layer deposited by high frequency PECVD introduces an additional tensile stress in the AlGaN layer, resulting in a negative shifting element of the threshold voltage in the range of a few tenths of a volt. In fact, this effect should be considered in the process design. The plasma treatment dose can be increased accordingly to compensate for the negative shifting elements in the threshold voltage generated by the SiN passivation layer. The stress of the SiN passivation layer can also be reduced by modifying the process parameters of the PECVD deposition such that the negative shift elements in the threshold voltage are minimized.
E/D HEMT反相器的電路示意圖如圖1A所示,在其中,D型HEMT用作負載,其閘極連接到其源極,以及E型HEMT用作驅動器。圖1B說明根據本創新的反相器的製作顯微照片。製作的反相器採用HP4156A參數分析儀進行表徵。圖38說明典型的E/D HEMT反相器的靜態電壓轉移特性(實線曲線)。在大輸入電壓(>2.1V)的輸出電壓的升高是閘極肖特基二極體導通的結果。短劃線曲線是具有交換軸的相同轉移曲線,並且表示下一個反相器級的輸入-輸出特性。參數定義遵照對於基於GaAs和InP的HEMT所述。靜態輸出電平(VO H 和VO L )由穩定平衡點的曲線的兩個相交點給定,以及兩個電平之間的差被定義為輸出邏輯電壓擺動。反相器臨限電壓(VT H )被定義為Vi n ,其中Vi n 等於Vo u t 。靜態雜訊邊限採用邏輯低雜訊邊限(NML )以及邏輯高雜訊邊限(NMH )的最大寬度的方法來測量。在圖39中繪製了在電源電壓VD D =1.5V具有從6.7到50變化的β的E/D反相器的測量靜態電壓轉移曲線。高輸出邏輯電平(VO H )保持為1.5V,表明E型HEMT完全斷開,而低輸出邏輯電平(VO L )由於β從6.7增加到50而從0.34改進到0.09V。因此,定義為VO H -VO L 的輸出邏輯擺動從1.16增加到1.41V。當β從6.7增加到50時,VT H 從0.88減小到0.61V,線性區域中的DC電壓增益(G)從2增加到4.1。圖40列出靜態雜訊邊限以及VO H 、VO L 、輸出邏輯擺動、VT H 和G的測量值。NML 以及NMH 均隨β增加而改進。A schematic circuit diagram of an E/D HEMT inverter is shown in FIG. 1A, in which a D-type HEMT is used as a load, its gate is connected to its source, and an E-type HEMT is used as a driver. Figure 1B illustrates a fabrication photomicrograph of an inverter in accordance with the present innovation. The fabricated inverter was characterized using the HP4156A parametric analyzer. Figure 38 illustrates the quiescent voltage transfer characteristics (solid curve) of a typical E/D HEMT inverter. The rise in the output voltage at a large input voltage (>2.1V) is the result of the conduction of the gate Schottky diode. The dash curve is the same transfer curve with the swap axis and represents the input-output characteristics of the next inverter stage. The parameter definitions are as described for GaAs and InP based HEMTs. The static output levels (V O H and V O L ) are given by the two intersections of the curves of the stable equilibrium point, and the difference between the two levels is defined as the output logic voltage swing. The inverter threshold voltage (V T H ) is defined as V i n , where V i n is equal to V o u t . The static noise margin is measured using the logic low noise margin (NM L ) and the maximum width of the logic high noise margin (NM H ). A measured static voltage transfer curve for an E/D inverter having a supply voltage V D D = 1.5 V having a variation of 6.7 to 50 is plotted in FIG. The high output logic level (V O H ) remains at 1.5V, indicating that the E-type HEMT is completely off, while the low output logic level (V O L ) is improved from 0.34 to 0.09V due to the increase in β from 6.7 to 50. Therefore, the output logic swing defined as V O H -V O L increases from 1.16 to 1.41V. When β is increased from 6.7 to 50, V T H is reduced from 0.88 to 0.61V, and the DC voltage gain (G) in the linear region is increased from 2 to 4.1. Figure 40 shows the static noise margins and the measured values of V O H , V O L , output logic swing, V T H and G. Both NM L and NM H are improved as β increases.
具有β=10的反相器的靜態電壓轉移曲線在不同的電源電壓上被測量,並在圖41中繪製曲線。電路性能參數在圖42中列出。當電源電壓增加時,E/D反相器的所有參數相應增加。這意味著,電源電壓的增加改進E/D反相器的靜態性能。大家知道,對於HEMT和MESFET E/D反相器,輸入電壓始終受到閘極肖特基二極體的導通電壓限制。在大輸入電壓時,閘極導電引起用作驅動器的E型器件的寄生源極電阻上增加的電壓降,從而提高邏輯低電平的電壓。當電源電壓和所需輸入電壓增加時,可在靜態轉移曲線中觀察到輸出電壓的升高,如圖41所示。閘極電流在通過大輸入電壓增加時可能使反相器驅動多個級的能力明顯降級,從而減小扇出。通常,閘極肖特基二極體的導通電壓對於常規AlGaN/GaN HEMT大約為1 V。對於閘極凹槽E型GaN HEMT,變薄的AlGaN能障因提高的隧穿電流而進一步減小導通電壓。因此,對於基於閘極凹槽E型GaN HEMT的反相器,輸出電壓在輸入電壓超過0.8V時升高。如前面所述,通過CF4 電漿處理製作的E型GaN HEMT因AlGaN層中增強的肖特基能障而具有被抑制的閘極電流,它由負電氟離子引起。這樣一種閘極電流抑制實現E/D反相器的較大輸入電壓擺動。在圖41中可以看到,輸出電壓的升高在輸入電壓超過2V之前沒有發生,表明輸入電壓擺動的大約1V擴展。圖43說明負載電流和輸入電流與輸入電壓的相關性。較低的輸入電流(E型HEMT的閘極電流)表明更大扇出量。在“導通”狀態,當輸入電壓大於2V時,輸入電流超過10%的負載電流。The quiescent voltage transfer curve with an inverter of β = 10 is measured at different supply voltages and plotted in Figure 41. Circuit performance parameters are listed in Figure 42. As the supply voltage increases, all parameters of the E/D inverter increase accordingly. This means that the increase in supply voltage improves the static performance of the E/D inverter. As you know, for HEMT and MESFET E/D inverters, the input voltage is always limited by the turn-on voltage of the gate Schottky diode. At large input voltages, the gate conductance causes an increased voltage drop across the parasitic source resistance of the E-type device used as a driver, thereby increasing the voltage at the logic low level. As the supply voltage and the required input voltage increase, an increase in the output voltage can be observed in the static transfer curve, as shown in Figure 41. The gate current can significantly degrade the ability of the inverter to drive multiple stages as it increases through a large input voltage, thereby reducing fan-out. Typically, the turn-on voltage of the gate Schottky diode is approximately 1 V for a conventional AlGaN/GaN HEMT. For the gate recess E-type GaN HEMT, the thinned AlGaN energy barrier further reduces the turn-on voltage due to the increased tunneling current. Therefore, for an inverter based on a gate recess E-type GaN HEMT, the output voltage rises when the input voltage exceeds 0.8V. As described earlier, the E-type GaN HEMT fabricated by CF 4 plasma treatment has a suppressed gate current due to the enhanced Schottky barrier in the AlGaN layer, which is caused by negatively charged fluoride ions. Such a gate current suppression achieves a large input voltage swing of the E/D inverter. As can be seen in Figure 41, the rise in output voltage did not occur until the input voltage exceeded 2V, indicating an approximately 1V spread of the input voltage swing. Figure 43 illustrates the dependence of load current and input current on the input voltage. A lower input current (gate current of the E-type HEMT) indicates a larger fan-out. In the "on" state, when the input voltage is greater than 2V, the input current exceeds 10% of the load current.
圖1B說明DCFL環形振盪器的示意電路圖,它採用奇數E/D反相器鏈來形成。十七級環形振盪器採用反相器的β=6.7、10和25來製作。對於各環形振盪器,採用36個電晶體,包括輸出緩衝器。圖1D說明根據本創新的所製作環形振盪器的顯微照片。環形振盪器利用Agilent E4404B頻譜分析儀和HP 54522A示波器在晶片上表徵。在環形振盪器的操作期間還測量DC功耗。圖44和45說明在VD D =3.5V偏壓的具有β=10的17級環形振盪器的頻域和時域特性。基本振盪頻率為225MHz。根據每級的傳播延遲的公式τpd=(2 nf )- 1 ,其中級數為17,以及τp d 計算為130ps/級。在圖46中繪製了τp d 和功率延遲乘積對VD D 的相關性。隨著電源電壓的增加,傳播延遲被減小,而功率延遲乘積則增加。與在1V所測量的τp d 相比(234ps/級),在3.5 V所測量的τp d 減小45%。環形振盪器可在這種高VD D 上工作的事實歸因於積體過程中所使用的CF4 電漿處理技術所實現的更大輸入電壓擺動。在1V的VD D 上發現0.113 pJ/級的最小功率延遲乘積。圖46還說明具有β=6.7和25的環形振盪器的τp d 及功率延遲乘積特性。對於具有β=6.7的環形振盪器,較大的τp d 和功率延遲乘積是由於E型HEMT的更大閘極長度(1.5μm)所確定的更大輸入電容引起的。對於具有β=25的環形振盪器,較大的τp d 是由於D型HEMT的更大閘極長度(4μm)所確定的更低充電電流引起的,而功率延遲乘積則處於與具有β=10的環形振盪器相同的等級。當這種積體技術在次微米體系中實現時,預計閘極延遲時間會進一步減小。Figure 1B illustrates a schematic circuit diagram of a DCFL ring oscillator formed using an odd number of E/D inverter chains. The seventeen-stage ring oscillator is fabricated using β = 6.7, 10, and 25 of the inverter. For each ring oscillator, 36 transistors are used, including an output buffer. Figure 1D illustrates a photomicrograph of a ring oscillator made in accordance with the innovations. The ring oscillator was characterized on the wafer using an Agilent E4404B spectrum analyzer and an HP 54522A oscilloscope. DC power consumption is also measured during operation of the ring oscillator. 44 and 45 illustrate the frequency domain and time domain characteristics of a 17-stage ring oscillator having β = 10 at a V D D = 3.5 V bias. The basic oscillation frequency is 225 MHz. According to the formula of the propagation delay of each stage τpd = (2 nf ) - 1 , where the number of stages is 17, and τ p d is calculated as 130 ps / level. The correlation of τ p d and the power delay product to V D D is plotted in Figure 46. As the supply voltage increases, the propagation delay is reduced and the power delay product is increased. Compared to τ p d measured at 1V (234 ps/stage), τ p d measured at 3.5 V is reduced by 45%. The fact that the ring oscillator can operate at this high V D D is due to the greater input voltage swing achieved by the CF 4 plasma processing technique used in the integrated process. A minimum power delay product of 0.113 pJ/stage was found at V D D of 1V. Figure 46 also illustrates the τ p d and power delay product characteristics of a ring oscillator with β = 6.7 and 25. For a ring oscillator with β = 6.7, the larger τ p d and power delay product is due to the larger input capacitance determined by the larger gate length (1.5 μm) of the E-type HEMT. For a ring oscillator with β = 25, the larger τ p d is due to the lower charge current determined by the larger gate length (4 μm) of the D-type HEMT, while the power delay product is at and with β = The ring oscillator of 10 has the same rating. When this integrated technique is implemented in a sub-micron system, the gate delay time is expected to be further reduced.
近來,分立E型HEMT和DCFL環形振盪器已經以高達375 C的升高溫度進行了測試。在E型HEMT的臨限電壓中沒有觀察到明顯移位,並且環形振盪器在375 C呈現70 MHz的振盪頻率。Recently, discrete E-type HEMT and DCFL ring oscillators have been tested at elevated temperatures up to 375 C. No significant shift was observed in the threshold voltage of the E-type HEMT, and the ring oscillator exhibited an oscillation frequency of 70 MHz at 375 C.
根據所公開類別的創造性實施例,提供:場效電晶體,包括:源極接觸和吸極接觸;由閘極覆蓋的垂直不同質半導體材料中的通道,它使所述源極接觸與所述吸極接觸電氣分離;所述垂直不同質材料在表面附近具有更高的鋁份額和更寬的帶隙;以及所述半導體材料內的補獲電荷的區域,它位於所述閘極與所述通道之間,並且還朝所述吸極橫向延伸。According to an inventive embodiment of the disclosed class, there is provided: a field effect transistor comprising: a source contact and a sink contact; a channel in a vertical dissimilar semiconductor material covered by a gate, the source being contacted with the source Absorbing contact electrical separation; the vertically different material having a higher aluminum fraction and a wider band gap near the surface; and a region of the semiconductor material that replenishes charge, which is located at the gate and Between the channels, and also extending laterally toward the absorber.
根據所公開類別的創造性實施例,提供:一種用於製作半導體主動元件的方法,包括以下動作:i)把摻雜劑引入第一半導體材料,在其中通過形成圖案層曝光,形成其至少一個深能階,由此引入補獲電荷;以及ii)形成異質接面電晶體,它包括緊接在所述第一半導體的相應部分下方的更窄帶隙半導體中的通道區;其中,所述電晶體中的一些還包括把所述通道區連接到相應吸極區的所述第一半導體材料的若干部分之上的所述補獲電荷。According to an inventive embodiment of the disclosed class, there is provided: a method for fabricating a semiconductor active device comprising the steps of: i) introducing a dopant into a first semiconductor material, wherein the at least one deep is formed by exposing the patterned layer Energy level, thereby introducing a charge of charge; and ii) forming a heterojunction transistor comprising a channel region in a narrower band gap semiconductor immediately below a respective portion of the first semiconductor; wherein the transistor Some of the methods further include connecting the channel region to the trapped charge over portions of the first semiconductor material of the respective absorber region.
本領域的技術人員會理解,本申請所描述的創造性概念可在極大範圍的應用中進行修改和變更,以及專利主題的範圍相應地不受所提供的具體示範理論的任一個限制。Those skilled in the art will appreciate that the inventive concept described herein can be modified and changed in a wide range of applications, and the scope of the patent subject matter is accordingly not limited by any of the specific exemplary embodiments provided.
在上述實施例中,在閘極與吸極之間提供兩級固定電荷。但是,在備選方案中,必要時可採用附加中間步長,或者可採用連續增量。In the above embodiment, two levels of fixed charge are provided between the gate and the sink. However, in the alternative, additional intermediate steps may be employed as necessary, or continuous increments may be employed.
對於高電壓應用,還能夠利用以上對於在吸極側上使用所述的相同技術,在源極側也包括固定電荷成分。這將使導通電阻輕微降級,但是在HEMT中需要經受最大電壓的情況中可能是有利的。For high voltage applications, it is also possible to utilize the same technique described above for the use on the absorber side, also including a fixed charge component on the source side. This will slightly degrade the on-resistance, but may be advantageous in situations where it is necessary to withstand the maximum voltage in the HEMT.
以上所述的方法及結構在電場控制中提供新工具。這些概念不僅適用於HEMT或MISHFET器件,而且適用於III-N MESFET(金屬半導體FET)和MOSFET器件。(MESFET器件不採用閘極絕緣體,而是提供閘極與通道之間的肖特基能障。)The methods and structures described above provide new tools in electric field control. These concepts apply not only to HEMT or MISHFET devices, but also to III-N MESFET (Metal Semiconductor FET) and MOSFET devices. (The MESFET device does not use a gate insulator, but provides a Schottky barrier between the gate and the channel.)
對於另一個實例,半導體成分的小變更、例如含磷氮化物代替純氮化物的使用或者對於基本HEMT結構在Aly Ga1 - y N異質接面上的Alx Ga1 - x N的使用被認為是備選方案。For another example, small changes in semiconductor composition, such as the use of phosphorus-containing nitrides instead of pure nitrides, or the use of Al x Ga 1 - x N on Al y Ga 1 - y N heterojunctions for basic HEMT structures are Think of it as an alternative.
對於另一個實例,在所示的各種器件結構中,各種材料可以可選地用於閘極(考慮功函數的任何所産生的差異)。For another example, in the various device configurations shown, various materials may be optionally used for the gate (considering any resulting differences in work function).
類似地,可在磊晶層摻雜中進行各種變化或替代。Similarly, various changes or substitutions can be made in the epitaxial layer doping.
類似地,如上所述,各種材料可以可選地用於基材。Similarly, as described above, various materials can be optionally used for the substrate.
各種公開的實施例提供具有新種類的吸極工程設計、即吸極側的電場控制的新方法的場效電晶體。但是,也考慮到,公開的電晶體實施例可能是合併器件結構的一部分,例如其中的橫向晶體管用來控制對另一個器件結構的注入。Various disclosed embodiments provide field effect transistors having a new class of absorber engineering designs, i.e., new methods of electric field control on the absorber side. However, it is also contemplated that the disclosed transistor embodiments may be part of a combined device structure, such as where a lateral transistor is used to control the implantation of another device structure.
在另一類備選實施例中,還考慮到,所建議的場成形固定電荷可用於高壓二極體中的電場成形、特別是在陽極側。In another alternative embodiment, it is also contemplated that the proposed field shaped fixed charge can be used for electric field shaping in high voltage diodes, particularly on the anode side.
還考慮到,本發明可與傳統吸極場修改技術結合,例如採用差分擴散、場極板和/或側壁隔離片。It is also contemplated that the present invention can be combined with conventional absorber field modification techniques, such as differential diffusion, field plates, and/or sidewall spacers.
幫助說明變更和實現的附加的一般背景可見於以下出版物,通過引用將其全部結合於此:.Y.Cai等人,IEEE EDL,Vol.26,第435-437頁,2005年7月;.W.Saito等人,IEEE T-ED,Vol.53,第356-362頁,2006年2月;.Y.Ando等人,IEEE EDL,Vol.24,第289-291頁,2003年;.Y.F.Wu等人,IEDM 2004,第1078-1079頁;.Y.Ando等人,IEDM 2005,第576-579頁。Additional general backgrounds that help to illustrate changes and implementations can be found in the following publications, which are hereby incorporated by reference in their entirety: Y. Cai et al., IEEE EDL, Vol. 26, pp. 435-437, July 2005; W. Saito et al., IEEE T-ED, Vol. 53, pp. 356-362, February 2006; Y. Ando et al., IEEE EDL, Vol. 24, pp. 289-291, 2003; Y.F. Wu et al., IEDM 2004, pp. 1078-1079; Y. Ando et al., IEDM 2005, pp. 576-579.
本申請中任何描述不應當理解為暗示任何具體元件、步驟或功能是必須包含在申請專利範圍中的必要元素。專利主題的範圍僅由允許的申請專利範圍來定義。此外,這些申請專利範圍中沒有一個意在援引35 USC第112節的第六段,除非確切的詞語“用於...的部件”之後跟隨分詞。No description in the present application should be construed as implying that any specific element, step, or function is required to be included in the scope of the application. The scope of the patent subject matter is defined only by the scope of the patent application that is permitted. Moreover, none of the scope of these patent applications is intended to invoke the sixth paragraph of Section 31 of 35 USC, unless the exact word "components for" follows the participle.
所提交的申請專利範圍意在盡可能全面,以及沒有主題被有意放棄、專用或丟棄。The scope of the patent application filed is intended to be as comprehensive as possible, and no subject matter is intentionally abandoned, dedicated or discarded.
參照附圖來描述本公開創新,附圖示出本創新的重要示範實施例,並通過引用結合到其說明中,附圖中:圖1說明先有技術的E型HFET。The innovations of the present disclosure are described with reference to the drawings, which show an important exemplary embodiment of the present invention and are incorporated by reference to the accompanying drawings in which: FIG. 1 illustrates a prior art E-type HFET.
圖1A說明用於E/D反相器的DCFL電路示意圖。Figure 1A illustrates a schematic diagram of a DCFL circuit for an E/D inverter.
圖1B說明用於環形振盪器的DCFL電路。Figure 1B illustrates a DCFL circuit for a ring oscillator.
圖1C說明反相器的顯微照片作為本創新的一個實施例。Figure 1C illustrates a photomicrograph of an inverter as an embodiment of the innovation.
圖1D說明環形振盪器的顯微照片作為本創新的一個實施例。Figure 1D illustrates a photomicrograph of a ring oscillator as an embodiment of the innovation.
圖2說明沒有利用本創新的傳統D型HEMT、E型HEMT以及本創新的一個實施例的轉移特性。2 illustrates the transfer characteristics of a conventional D-type HEMT, E-type HEMT, and an embodiment of the present innovation that does not utilize the innovation.
圖3A至3F說明製作E型AlGaN/GaN HFET的過程的一個實施例。3A to 3F illustrate one embodiment of a process of fabricating an E-type AlGaN/GaN HFET.
圖4A說明E型AlGaN/GaN HFET的一個實施例的I-V輸出特性。4A illustrates the I-V output characteristics of one embodiment of an E-type AlGaN/GaN HFET.
圖4B說明E型AlGaN/GaN HFET的一個實施例的Ig -Vg s 特性。4B illustrates I g -V g s characteristics of one embodiment of an E-type AlGaN/GaN HFET.
圖5說明E型AlGaN/GaN HFET的一個實施例的通過“SIMS”所測量的氟離子濃度分佈曲線。Figure 5 illustrates a fluoride ion concentration profile measured by "SIMS" for one embodiment of an E-type AlGaN/GaN HFET.
圖6說明注入氟離子之前本創新的一個實施例的截面。Figure 6 illustrates a cross section of one embodiment of the innovation prior to injection of fluoride ions.
圖7說明各種實施例的通過“SIMS”所測量的氟離子濃度分佈曲線。Figure 7 illustrates a fluoride ion concentration profile measured by "SIMS" for various embodiments.
圖7A和圖7B說明各種實施例的通過“SIMS”所測量的氟離子濃度分佈曲線。7A and 7B illustrate fluoride ion concentration profiles measured by "SIMS" of various embodiments.
圖8A說明在不同的CF4 電漿處理條件之後的E型AlGaN/GaN HFET的Id 對Vg s 的轉移特性。Figure 8A illustrates the transfer characteristics of I d versus V g s of an E-type AlGaN/GaN HFET after different CF 4 plasma processing conditions.
圖8B說明在不同的CF4 電漿處理條件之後的E型AlGaN/GaN HFET的gm 對Vg s 的轉移特性。8B illustrates the transfer characteristics of the E-type AlGaN after CF 4 plasma treatment of different conditions / GaN HFET's on V g s g m of.
圖9說明採用不同CF4 電漿處理的閘極肖特基二極體的所提取能障高度和理想因數。Figure 9 illustrates the extracted barrier height and ideality factor for a gate Schottky diode treated with different CF 4 plasmas.
圖10說明各種E型AlGaN/GaN HFET的Vt h 與電漿功率和處理時間的相關性。Figure 10 illustrates the V t h of various E-type AlGaN/GaN HFETs correlated with plasma power and processing time.
圖11說明AFM圖像,說明在AlGaN層上的CF4 電漿處理的微小蝕刻效果。Figure 11 illustrates an AFM image illustrating the microetching effect of CF 4 plasma treatment on an AlGaN layer.
圖12A說明各種E型AlGaN/GaN HFET實施例的DC Id 對Vg s 轉移特性。Figure 12A illustrates DC I d versus V g s transfer characteristics for various E-type AlGaN/GaN HFET embodiments.
圖12B說明各種E型AlGaN/GaN HFET實施例的DC gm 對Vg s 轉移特性。12B illustrates various DC g m E type AlGaN / GaN HFET embodiments s transfer characteristic of V g.
圖13說明一個E型AlGaN/GaN HFET實施例的DC輸出特性。Figure 13 illustrates the DC output characteristics of an E-type AlGaN/GaN HFET embodiment.
圖14A說明E型AlGaN/GaN HFET的各種實施例的具有不同CF4 電漿處理的反向以及正向閘極電流。14A illustrates a forward and reverse gate current having 4 plasma processing CF various different E-type AlGaN / GaN HFET embodiments.
圖14B說明E型AlGaN/GaN HFET的各種實施例的具有不同CF4 電漿處理的放大和正向閘極電流。FIG 14B illustrates an enlarged and forward gate currents with different CF 4 plasma processing various E-type AlGaN / GaN HFET embodiments.
圖15說明ft 和fm a x 與閘極偏壓的相關性,其中Vd s 固定在12V。Figure 15 illustrates the dependence of f t and f m a x on the gate bias, where V d s is fixed at 12V.
圖16說明採用不同CF4 電漿處理的晶片上所測量ft 和fm a x 。Figure 16 illustrates the measured f t and f m a x on wafers treated with different CF 4 plasmas.
圖17A至17F說明製作E型Si3 N4 AlGaN/GaN MISHFET的一個示範過程。17A to 17F illustrate an exemplary process of fabricating an E-type Si 3 N 4 AlGaN/GaN MISHFET.
圖18說明示範DC輸出特性。Figure 18 illustrates an exemplary DC output characteristic.
圖19A說明轉移特性。Fig. 19A illustrates the transfer characteristics.
圖19B說明閘極漏電流。Fig. 19B illustrates the gate leakage current.
圖20說明脈衝測量結果。Figure 20 illustrates the pulse measurement results.
圖21說明小信號RF特性。Figure 21 illustrates the small signal RF characteristics.
圖22說明沒有CF4 電漿處理的傳統D型AlGaN/GaN HEMT的類比導帶圖。Figure 22 illustrates an analog conduction band diagram of a conventional D-type AlGaN/GaN HEMT without CF 4 plasma treatment.
圖23說明具有CF4 電漿處理的E型AlGaN/GaN HEMT的類比導帶圖。Figure 23 illustrates an E-type AlGaN having a CF 4 plasma processing / GaN HEMT of the conduction band of the analog FIG.
圖24說明沒有CF4 電漿處理的傳統D型AlGaN/GaN HEMT以及具有CF4 電漿處理的E型AlGaN/GaN HEMT的電子濃度。FIG 24 illustrates CF 4 plasma processing is not a conventional D-type AlGaN / GaN HEMT and an E-type AlGaN having a CF 4 plasma processing electron concentration / GaN HEMT's.
圖25說明根據本創新的反相器的E型和D型HEMT的單石積體的製程流程的一個實施例。Figure 25 illustrates an embodiment of a process flow for a single-ply integrated body of E-type and D-type HEMTs of an inverter according to the present innovation.
圖26A至26F說明E型和D型HFET的單石積體的一個示範製程流程。Figures 26A through 26F illustrate an exemplary process flow for a single-rock composite of E-type and D-type HFETs.
圖27說明單石積體的平面製程流程。Figure 27 illustrates the planar process flow of a single stone body.
圖28說明E/D型HEMT的另一個示範製程流程。Figure 28 illustrates another exemplary process flow for an E/D type HEMT.
圖29說明通過平面製程製作的D-HEMT和E-HEMT的DC輸出特性。Figure 29 illustrates the DC output characteristics of D-HEMT and E-HEMT fabricated by a planar process.
圖30把平面製程的轉移特性與傳統製程的轉移特性進行比較。Figure 30 compares the transfer characteristics of a planar process with the transfer characteristics of a conventional process.
圖31說明通過平面製作製程所製作的E/DHEMT反相器的靜態電壓轉移特性。Figure 31 illustrates the static voltage transfer characteristics of an E/DHEMT inverter fabricated by a planar fabrication process.
圖32說明一個示範實施例中使用的HEMT的磊晶結構。Figure 32 illustrates the epitaxial structure of a HEMT used in an exemplary embodiment.
圖33說明用於單石反相器的E型和D型HEMT的單石積體的積體製程流程。Figure 33 illustrates the process flow of a single-rock product of E-type and D-type HEMTs for a single-rock inverter.
圖34說明反相器和環形振盪器的示範幾何參數。Figure 34 illustrates exemplary geometric parameters of an inverter and a ring oscillator.
圖35說明所公開的示範D型和E型AlGaN/GaN HEMT的DCI-V轉移特性及輸出特性。Figure 35 illustrates the DCI-V transfer characteristics and output characteristics of the disclosed exemplary D-type and E-type AlGaN/GaN HEMTs.
圖36說明所製作E型和D型AlGaN/GaN HEMT的性能。Figure 36 illustrates the performance of the fabricated E-type and D-type AlGaN/GaN HEMTs.
圖37說明D型和E型HEMT的Ig -Vg 特性以及在D型HEMT和E型HEMT的閘極之下的類比導邊帶圖。Figure 37 D and E illustrate the HEMT I g -V g characteristics and the analog sidebands turned under the gate HEMT type D and E of the HEMT.
圖38說明傳統E/D HEMT反相器的靜態電壓轉移特性。Figure 38 illustrates the static voltage transfer characteristics of a conventional E/D HEMT inverter.
圖39說明根據各種公開實施例、具有β=6.7、10、25和50的E/D HEMT反相器的靜態電壓轉移特性。Figure 39 illustrates static voltage transfer characteristics of E/D HEMT inverters with β = 6.7, 10, 25, and 50, in accordance with various disclosed embodiments.
圖40說明具有不同β值的反相器的雜訊邊限。Figure 40 illustrates the noise margin of an inverter with different beta values.
圖41說明具有在不同電源電壓上所測量的β=10的E/D HEMT反相器的靜態電壓轉移特性。Figure 41 illustrates the quiescent voltage transfer characteristics of an E/D HEMT inverter with β = 10 measured at different supply voltages.
圖42說明對於具有β=10的反相器、在不同的VD D 所測量的雜訊邊限。Figure 42 illustrates the noise margins measured at different V D D for an inverter with β = 10.
圖43說明根據一個示範實施例、在VD D =2.5 V具有β=10的反相器的負載和輸入電流。Figure 43 illustrates the load and input current of an inverter having β = 10 at V D D = 2.5 V, according to an exemplary embodiment.
圖44說明具有在VD D =3.5 V偏壓的β=10的17級環形振盪器的頻譜,以及圖45說明它的時域特性。Figure 44 illustrates the spectrum of a 17-stage ring oscillator having β = 10 at a V D D = 3.5 V bias, and Figure 45 illustrates its time domain characteristics.
圖46說明一個電路實施例的傳播延遲和功率延遲乘積與電源電壓的相關性。Figure 46 illustrates the dependence of the propagation delay and power delay products of a circuit embodiment on the supply voltage.
圖47說明根據本創新的一個實施例的LDD-HEMT的製作的製程流程。Figure 47 illustrates a process flow for the fabrication of an LDD-HEMT in accordance with one embodiment of the present innovation.
圖47A說明根據本創新的一個實施例的LDD-HEMT的2DEG。Figure 47A illustrates a 2DEG of an LDD-HEMT in accordance with one embodiment of the innovation.
圖48說明本創新的一個實施例的截止狀態崩潰電壓。Figure 48 illustrates an off-state breakdown voltage for one embodiment of the innovation.
圖49說明對於本創新的多個實施例的崩潰電壓與固定閘極-吸極間隔LG D =3μm的LDD區域的長度的相關性。Figure 49 illustrates the correlation of the breakdown voltage to the length of the LDD region of the fixed gate-sucker spacing L G D = 3 μm for various embodiments of the present innovation.
圖50說明本創新的一個實施例的DC轉移特性。Figure 50 illustrates the DC transfer characteristics of one embodiment of the innovation.
圖51說明本創新的一個實施例的截止頻率。Figure 51 illustrates the cutoff frequency of one embodiment of the innovation.
圖52說明本創新的一個實施例的H2 1 和MSG/MAG。FIG 52 illustrates H 2 1 and MSG / MAG to one embodiment of the present innovations.
圖53說明本創新的一個實施例的DC輸出曲線。Figure 53 illustrates a DC output curve for one embodiment of the innovation.
圖54說明本創新的多個實施例的導通電阻和膝節電壓。Figure 54 illustrates the on-resistance and knee voltage of various embodiments of the innovation.
圖55說明本創新的一個實施例的閘極-吸極二極體I-V特性。Figure 55 illustrates the gate-sucker diode I-V characteristics of one embodiment of the innovation.
圖56說明本創新的多個實施例的DC和脈衝I-V特性。Figure 56 illustrates DC and pulsed I-V characteristics of various embodiments of the innovation.
圖57說明沒有本創新的幫助的大信號功率特性。Figure 57 illustrates the large signal power characteristics without the help of this innovation.
圖58說明本創新的一個實施例的大信號功率特性。Figure 58 illustrates the large signal power characteristics of one embodiment of the innovation.
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US8159002B2 (en) | 2007-12-20 | 2012-04-17 | General Electric Company | Heterostructure device and associated method |
US8124505B1 (en) | 2010-10-21 | 2012-02-28 | Hrl Laboratories, Llc | Two stage plasma etching method for enhancement mode GaN HFET |
US8853709B2 (en) | 2011-07-29 | 2014-10-07 | Hrl Laboratories, Llc | III-nitride metal insulator semiconductor field effect transistor |
US8941118B1 (en) | 2011-07-29 | 2015-01-27 | Hrl Laboratories, Llc | Normally-off III-nitride transistors with high threshold-voltage and low on-resistance |
US9337332B2 (en) | 2012-04-25 | 2016-05-10 | Hrl Laboratories, Llc | III-Nitride insulating-gate transistors with passivation |
US10276712B2 (en) | 2014-05-29 | 2019-04-30 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
US9812532B1 (en) | 2015-08-28 | 2017-11-07 | Hrl Laboratories, Llc | III-nitride P-channel transistor |
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