US11437249B2 - Showerhead device for semiconductor processing system - Google Patents
Showerhead device for semiconductor processing system Download PDFInfo
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- US11437249B2 US11437249B2 US16/930,800 US202016930800A US11437249B2 US 11437249 B2 US11437249 B2 US 11437249B2 US 202016930800 A US202016930800 A US 202016930800A US 11437249 B2 US11437249 B2 US 11437249B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4412—Details relating to the exhausts, e.g. pumps, filters, scrubbers, particle traps
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45559—Diffusion of reactive gas to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32357—Generation remote from the workpiece, e.g. down-stream
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
- H01J37/32449—Gas control, e.g. control of the gas flow
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
Definitions
- the field relates generally to a showerhead device for a semiconductor processing system.
- Vapor deposition processes such as atomic layer deposition (ALD) are well-known.
- ALD processes typically utilize alternating and sequential supply of vapor-phase reactants to a substrate to deposit up to a layer of material in a controlled and highly-conformal manner, where efficient removal of reactants between pulses is important to minimize undesired reactions in the gas phase.
- Thin films deposited by ALD are used in a wide variety of applications, such as in the formation of integrated circuits. Controlled removal of materials is also highly desirable.
- An example process that controllably removes materials to define circuitry and other structures is chemical vapor etching (CVE) or atomic layer etching (ALE).
- CVE processes employ a pulsed supply of etchants. For example, in some etch processes, sequential pulses of vapor phase reactants can remove minute amounts of material from a substrate in a controlled and/or selective manner.
- a semiconductor processing apparatus can comprise: a reaction chamber and a first exhaust port, the first exhaust port being configured to remove vapors from the reaction chamber.
- the apparatus can also comprise a showerhead device that is connected to the reaction chamber and being configured to deliver reactant vapors to the reaction chamber.
- the showerhead device can comprise: a gas inlet that is configured to supply the reactant vapors into the showerhead device; a first showerhead plate in fluid communication with the gas inlet, the first showerhead plate comprising a plurality of openings; and a second showerhead plate comprising: a plurality of inlet ports in fluid communication with the plurality of openings, the plurality of inlet ports configured to deliver the reaction vapors to the reaction chamber; and a plurality of second exhaust ports configured to remove vapors from the reaction chamber.
- the apparatus can also comprise one or more pumps connected to the first exhaust port and the plurality of second exhaust ports, the one or more pumps being configured to remove vapors from the reaction chamber through the first exhaust port and the plurality of second exhaust ports.
- a semiconductor processing apparatus can comprise: a reaction chamber; a reaction chamber exhaust port being configured to remove vapors from the reaction chamber; and a showerhead device that comprises: a plurality of distributed inlet apertures in fluid communication with a reaction vapor source and the reaction chamber; and a plurality of distributed exhaust apertures in fluid communication with a pump and the reaction chamber.
- a method for etching a substrate can comprise supplying a reactant vapor to a showerhead device; conveying the reactant vapor to a reaction chamber through a plurality of distributed inlet apertures in the showerhead device; removing vapors from the reaction chamber by way of a first exhaust port exposed to the reaction chamber; and removing vapors from the reaction chamber by way of a plurality of second exhaust ports in the showerhead device.
- FIG. 1 illustrates a schematic side view of a reactor with a dual showerhead device in accordance with some embodiments.
- FIG. 2 illustrates a side sectional view of a dual showerhead device in accordance with some embodiments.
- FIG. 3A illustrates a gas inlet for a showerhead device in accordance with some embodiments.
- FIG. 3B illustrates a schematic three-dimensional perspective view of the gas inlet of FIG. 3A .
- FIG. 3C illustrates the gas inlet of FIG. 3A that includes an insert.
- FIG. 4 illustrates a schematic side sectional view of a portion of a dual showerhead device in accordance with some embodiments.
- FIG. 5 illustrates an upper plan view of a second showerhead plate of the lower portion of the showerhead device FIG. 4 in accordance with some embodiments.
- FIG. 6 illustrates an upper plan view of a second showerhead plate in accordance with some embodiments.
- FIG. 7 illustrates a reactor with a dual showerhead and a movable susceptor in accordance with some embodiments.
- Chemical etching of microelectronics materials may have benefits over plasma etching.
- the partial pressures, residence times and temperatures of an etch reactant (such as an adsorbing reactant and/or an etchant) and by-products should not significantly vary spatially above the substrate (such as a wafer).
- showerhead type reactors can provide uniform distribution of the partial pressure of the incoming gas, but the partial pressures of the by-products and residence time of the gas molecules may not be constant across the wafer.
- the molecules entering from the center of the showerhead have longer residence times in the reactor compared to the molecules entering from the edge of the wafer, because pumping to exhaust from the reaction chamber is normally done from the perimeter of the wafer.
- etching processes e.g., CVE processes
- Any suitable etch chemistries can be used in the disclosed embodiments.
- the process can involve one or more etching cycles, where each cycle exposes a substrate to a first vapor-phase halide reactant having a first halide ligand to form adsorbed species on the substrate surface and subsequently exposing the substrate to a second vapor-phase halide reactant having a second halide ligand that converts the adsorbed species into volatile species such that at least some material is removed from the film.
- the film can include W, TiN, TiO 2 , TaN, SiN, AlO 2 , Al 2 O 3 , ZrO 2 , WO 3 , SiOCN, SiOC, SiCN, AlN or HfO 2 .
- the first vapor-phase halide can be a metal halide, such as Nb, Ta, Mo, Sn, V, Re, Te, W, and group 5 and 6 transition metals.
- the second vapor-phase halide can be a carbon-based halide, such as CCl 4 or CBr 4 . Further examples of various etch chemistries and processes that can be used in conjunction with the disclosed embodiments can be found throughout International Application No. PCT/US2017/065170, which is incorporated by reference herein in its entirety and for all purposes.
- a dual showerhead reactor can be used to create constant partial pressures of the by-products and uniform residence times of the gas molecules across the substrate.
- a dual showerhead structure can achieve spatially uniform partial pressures, residence times and temperatures both for the etch reactants and for the by-products, thus leading to a uniform etch rate across the wafer.
- This apparatus can be used either in steady state partial pressure mode, in partial pressure pulsing mode, or in total pressure pulsing mode, or combinations thereof, depending upon which mode is preferred to achieve desired etching conformality for the substrate.
- this apparatus can be integrated with differential pumping to the reactor. It is possible to tune the residence time distributions and partial pressure profiles within the reactor, and therefore, the etching profile of the substrate (e.g., wafer) by modulating the pumping speed and conductances of the showerhead device and reaction chamber.
- the substrate e.g., wafer
- the apparatus can be used in a steady state mode (e.g., constant etch reactant, for example etchant, flow) or a partial pressure pulsing mode (e.g., pulsing etchant flow while keeping the total pressure constant), a pressure pulsing mode (e.g., constant etchant flow, pulsing total pressure) or a total pulsing mode (e.g., pulsing partial pressure and total pressure) or combinations thereof.
- Pulsing mode and pumping mode may determine the partial pressure and residence time distributions of etchant gas above the wafer in dynamic flow conditions, and therefore, the conformality and uniformity of the etch process can be controlled.
- the etch conformality of etch processes used in conjunction with the disclosed embodiments can be: greater than 50%; greater than 80%; greater than 90%; greater than 95%; greater than 98%; or greater than 99%.
- etch selectivity can also be controlled. Etch selectivity can be given as a percentage, calculate by [(etched material on surface A) ⁇ (etched material on surface B)]/(etched material on surface A).
- the etch amount can be measured in a variety of ways. For example, etch amount may be given as the measured reduced thickness of the etched material, or may be given as the measured amount of material etched based on comparisons of what was originally present and what was left after the etch process.
- selectivity for the etch process is greater than about 10%, greater than about 50%, greater than about 75%, greater than about 85%, greater than about 90%, greater than about 93%, greater than about 95%, greater than about 98%, greater than about 99% or greater than about 99.5%.
- the aspect ratio of the etched features can be greater than about: 2:1, 3:1, 5:1, 10:1, 20:1, 40:1, or 100:1.
- the first, upper chamber of the showerhead device can have continuous flow
- the second, bottom reaction chamber can have continuous pumping with leaching out of the reaction by-product and precursor to reduce pressure spikes.
- the bottom reaction chamber can supply constant partial pressure within the precursor exposure times.
- FIG. 1 illustrates semiconductor processing apparatus 1 that includes a reactor 2 with a dual showerhead device 10 .
- the reactor 2 includes a reaction chamber 3 that has an interior portion 4 between the susceptor 5 and the showerhead device 10 .
- Within the reactor 2 and attached to the chamber 3 is a susceptor plate 5 .
- the susceptor plate 5 extends upwardly from the base of the chamber 3 .
- the susceptor plate 5 supports the substrate 6 (e.g., wafer) during processing.
- the dual showerhead device 10 can be disposed over the susceptor 5 and substrate 6 .
- a gas manifold can supply reactant and inactive gases to the showerhead device 10 , which can disperse the supplied gases across the width of the substrate 6 to etch material.
- the inlet manifold 11 can be fluidly connected to a reactant source, such as a source of etch reactant, e.g., an etchant or adsorbing reactant (see, e.g. FIG. 2 ).
- a reactant source such as a source of etch reactant, e.g., an etchant or adsorbing reactant (see, e.g. FIG. 2 ).
- the etchant source may be a gas bomb, and/or may include a vaporization device for vaporizing etchant chemicals that are naturally liquid or solid.
- the dual showerhead 10 can include a plurality of gas inlets 18 (apertures) and a plurality of gas outlets 20 (apertures) or exhaust ports.
- the inlet 18 and outlet apertures 20 may not be in direct communication with one another but can both fluidly communicate directly with the reaction chamber 3 below them.
- a second gas outlet line 26 or exhaust port can provide fluid communication directly with the reaction chamber 3 to remove gases from the reaction chamber 3 .
- reactant gas e.g., an etch gas
- the dual showerhead's 10 gas outlet apertures 20 remove vapors from the chamber 3 through a pump 9 connected to an internal, or lower, showerhead plenum 22 .
- the second gas outlet line 26 can also be utilized to remove vapors through the pump 9 .
- the same pump 9 can be used with both gas outlet lines 20 , 26 .
- both gas outlets 20 , 26 have a separate pump 9 connected to each of the gas outlet lines 20 , 26 .
- a valve 38 is connected to each gas outlet line 20 , 26 and works in tandem with a pump 9 to control the flow of gas out of the reactor chamber 3 .
- the semiconductor processing apparatus 1 can include a reaction chamber 3 and a reaction chamber exhaust port 7 configured to remove vapors from the reaction chamber 3 .
- the showerhead device 10 can include a plurality of distributed inlet apertures 18 in fluid communication with a reactant vapor source and the reaction chamber 3 .
- the showerhead device 10 can include a plurality of distributed exhaust apertures 20 in fluid communication with a pump 9 and the reaction chamber 3 .
- the same or different pumps 9 may connect to the showerhead 10 and the reaction chamber 3 .
- an internal plenum 22 within a lower portion 14 of the showerhead 10 (e.g., defined between two plates) can communicate with the pump 9 .
- the inlet apertures 18 can extend through the showerhead device 10 and can bypass the internal plenum 22 in some embodiments.
- the inlet apertures 18 can communicate with an upper plenum 24 , above the lower portion 14 of the showerhead 10 .
- FIG. 1 shows a simple side gas inlet 16 communicating with the upper plenum 24 .
- the upper plenum 24 can instead communicate with an inlet manifold distributing reactant vapors across the upper plenum 24 .
- One or a plurality of pumps 9 can draw residue gases from the exhaust ports 20 in the showerhead device 10 and from the reaction chamber 3 exhaust port 7 .
- the pumping speed of gases through the reaction chamber 3 exhaust port 7 in the showerhead device 10 can vary from about 25 m 3 /h to about 5000 m 3 /h., with the pump 9 speeds being between about 50 m 3 /h and about 2500 m 3 /h in some embodiments, for example, between about 100 m 3 /h and about 2000 m 3 /h.
- the pumping speed of gases through the reaction chamber 3 exhaust port 7 in the reaction chamber 3 can vary from about 25 m 3 /h to about 5000 m 3 /h, with the pump speeds being between about 50 m 3 /h and about 2500 m 3 /h, for example, between about 100 m 3 /h and about 2000 m 3 /h.
- the pump speeds (or valves 38 in communication with a common pump 9 ) can be modulated to draw different flow rates of exhaust gases from the showerhead device 10 and the reaction chamber 3 exhaust port 7 .
- the ratio of the pumping speed of gases through the exhaust ports 20 in the showerhead device 10 to the pumping speed of gases through the reaction chamber 3 exhaust port 7 in the reaction chamber 3 can be in a range of 100:1 to 1:100, in a range of 50:1 to 1:50, in a range of 10:1 to 1:10, in a range of 5:1 to 1:5, in a range of 2:1 to 1:2, or in a range of 1.5:1 to 1:1.5.
- the etch process can be modulated.
- the differential pumping systems and techniques disclosed herein and shown in FIG. 1 can improve the uniformity and conformality of etching techniques.
- the modulation of residence time of gaseous or plasma species can be used in plasma etching reactors.
- the apparatus 1 can be used with plasma etching reactors.
- a remote plasma can be formed within the showerhead 10 (the upper 12 and lower portions 14 of the showerhead 10 serving as plasma electrodes), or in situ within the reaction chamber 3 (the showerhead device 10 and the susceptor 5 and/or reaction chamber 3 walls serving as plasma electrodes).
- the embodiments disclosed herein can also be applied in modulating the plasma itself.
- the apparatus 1 disclosed herein can be used in etching reactors that are not plasma etch reactors, and/or in reactors that are not used for deposition processes.
- a throttle valve can be provided to regulate the pump(s) 9 to modulate the residence time by tuning effective pumping speeds and/or by using a showerhead device 10 with appropriate values of x, the spacing between the inlet 18 and outlet apertures 20 of the showerhead device 10 .
- s can be defined as total effective pumping speed and can be dependent on the number of holes in the showerhead device 10 and the distance x between the inlet 18 and outlet holes 20 of the showerhead device 10 . Residence times can describe how long a particular gas species spends inside the reaction space before being pumped out through exhaust lines 26 .
- the volume of the reaction space may be constant.
- the residence time can be in a range of 0.1 ms to 10 seconds.
- the residence time can be in a range of 0.1 ms to 1 ms, 1 ms to 10 ms, 10 ms to 1 s, 1 s to 5 s, 5 s to 10 s, or 5 s to 1 min.
- the spacing distance x can range from a few millimeters to a few centimeters, for example, in a range of 1 mm to 5 cm, in a range of 1 mm to 1 cm.
- FIG. 2 illustrates a sectional view of a semiconductor processing apparatus 1 that includes a dual showerhead device 10 for dispersing gas over a substrate 6 and exhausting, according to various embodiments.
- the dual showerhead 10 has an inlet manifold 11 (e.g. a conically shaped top portion) that feeds into an upper portion 12 of the showerhead device 10 .
- the upper portion 12 may include an upper showerhead plate 13 (which can comprise a cylindrical or disc-shaped body) and an upper plenum 24 below it.
- the upper showerhead plate 13 can be disposed over a second, lower portion 14 of the showerhead device 10 .
- the inlet manifold 11 and upper showerhead plate 13 can be manufactured separately and joined by welding both components together.
- the inlet manifold 11 and the upper showerhead plate 13 can be joined together with mechanical joints.
- the dual showerhead 10 can be manufactured from a single piece of material. The connection between the showerhead 10 components can lead to a vacuum or non-vacuum type of sealing. In some embodiments, a space is provided between the upper 12 and lower portions 14 of the showerhead device 10 , which creates the upper showerhead plenum 24 .
- the inlet manifold 11 can be installed near the upper portion 12 .
- the inlet manifold 11 can be connected to a reactant vapor source, which allows reactant gas from a tank or vaporizer to flow into the showerhead device 10 from the inlet manifold 11 .
- Several channels 42 or branches can be formed within the inlet manifold 11 and can be in fluid communication with one or multiple gas inlet apertures 18 , such as by way of the upper plenum 24 .
- Reactant vapor entering into the showerhead device 10 through the inlet manifold 11 can travel through the channels 15 defined in the upper showerhead plate 13 .
- the lower portion 14 of the showerhead device 10 can include both inlet ports 18 (apertures) and outlet or exhaust ports 20 (apertures).
- the reactant inlet apertures 18 are in fluid communication with the inlet manifold gas channels 42 and gas inlet 16 , by way of the upper plenum 24 , and as a result, allow the gas to flow from the showerhead device 10 to enter into the reaction chamber 3 .
- the outlet or exhaust apertures 20 can pull residue gases into the showerhead device 10 through vacuum pressure applied by a vacuum source such as a pump 9 .
- a reaction chamber gas outlet port 7 can draw gases from the reaction chamber 3 and can be in fluid communication with one or more pumps 9 .
- the gas outlet line 26 can be connected to one or a plurality of pumps 9 , which can create a vacuum pressure that draws residue and other gases into the exhaust ports 20 of the showerhead device 10 and into the reaction chamber exhaust port 7 .
- the gas inlet 16 and gas outlet 26 structure of the showerhead device 10 together with the reactant chamber exhaust port 7 , can enable the reactor 2 to have spatially uniform partial pressures, residence times, and temperatures for etchant gases and for the by-products thereof.
- FIGS. 3A-C illustrate various embodiments of a gas inlet manifold 11 above the showerhead device 10 .
- the gas inlet manifold 11 can have a main line 40 .
- the gas channels 42 can branch off the main line 40 .
- the gas channels 42 branch off in multiple direction at multiple points from the main line 40 .
- the main line 40 can have a slightly conical shape, in which the inner diameter d of the main line 40 reduces towards the center of the showerhead. By reducing the inner diameter d towards the center of the showerhead 10 , the gas entering into the showerhead 10 through the inlet 16 can travel to each channel 42 in a more uniform manner.
- an insert 44 is installed within the main line 40 to bifurcate the flow pathway, as can be seen in FIG. 3C .
- the insert 44 obstructs flow within the main line 40 , causing gas to flow to each branch 42 in a more uniform manner.
- FIGS. 4 and 5 shows that the lower portion 14 of the showerhead device 10 can include two plates 30 , 32 that define a lower or internal plenum 22 between them.
- FIG. 5 illustrates the second showerhead plate 32 shown in FIG. 4 .
- the illustrated lower or internal plenum 22 comprises hollow channels 23 forming several concentric rings on the base of the second showerhead plate 32 , while the first showerhead plate 30 can be flat to cover the channels 23 .
- the inlet apertures 18 formed in the second plate 32 are between the channels 23 and thus bypass the internal plenum 22 (or channels), and align with inlet apertures 18 in the first plate 30 .
- the gas outlet apertures 20 are formed through the bottom of the channels 23 .
- the channels 23 connect to a pump 9 , as explained above.
- the precursor inlet apertures 18 , the exhaust apertures 20 , the hollow channels 23 , and the connections 25 to the pump(s) 9 can be arranged in a distributed pattern across the lower portion of the showerhead device.
- the pattern illustrated in FIG. 5 for the reactant inlet apertures, the exhaust ports, and the hollow channels 23 is a circular pattern.
- the illustrated pattern of ports may be an incomplete pattern and that the pattern can be continued around the entire base of the showerhead plate.
- the precursor inlet ports 18 , the exhaust ports 20 , the hollow channels 23 , and the connections 25 to the pump 9 can be arranged in similar or different patterns from each other.
- the lower portion 14 of the showerhead device 10 can have four connections 25 to the pump(s) 9 at 90 degrees to one another. In other embodiments, the lower portion 14 of showerhead device 10 can have more or fewer than four connections 25 to the pump(s) 9 .
- FIG. 6 illustrates an upper plan view of the second showerhead plate 32 of the lower portion 14 of the showerhead device 10 , according to another embodiment.
- the second showerhead plate 32 of FIG. 6 can have channels 23 shaped in any suitable manner to define the lower or internal plenum 22 .
- the channels 23 can take on several different shapes and patterns.
- the hollow channel(s) 23 can be arranged in a zig-zag or labyrinth pattern as shown in FIG. 6 .
- the second showerhead plate 32 can contain multiple channels 23 , with each channel 23 having a different or similar pattern.
- Inlet apertures 18 can be formed outside the channel(s) 23 while the exhaust apertures 20 can formed in fluid communication with the channel(s) 23 , while the channel(s) 23 are connected to one or more pump(s) 9 .
- FIG. 7 illustrates a reactor 2 with a dual showerhead device 10 , as described above, and a movable susceptor plate 50 .
- the moveable susceptor 50 can create a reactor 2 with a dynamic reaction space.
- a dynamic reaction space can include adjusting the distance between the moveable susceptor plate 50 and the showerhead device 10 .
- the reaction space can be changed for every cycle, every half cycle, or periodically at any time if desired.
- the moveable susceptor plate 50 can be adjusted through an external motion driver unit 52 .
- the external motion driver unit 52 can comprise an analog or digital motor, and can be mechanically and electrically connected to the moveable susceptor plate 50 , whereby the external motion driver unit 52 can adjust (e.g., up and down) the moveable susceptor plate 50 .
- the gap between the wafer 6 and showerhead device 10 (or top plate, in the case of cross flow reactor,) can be changed over time, if desired.
- the moveable susceptor plate 50 can move a distance in a range of 1 mm to 200 mm; in a range of 2 mm to 100 mm; in a range of 2 mm to 50 mm; or in a range of 3 mm to 30 mm.
- the susceptor plate can move a distance of in a range of 0.1 mm to 50 mm; in a range of 0.1 mm to 30 mm; or in a range of 0.1 mm to 20 mm.
- the external motion driver 52 can rotate the moveable susceptor plate 50 .
- a control system can be in electrical communication with the motor drive, the control system configured to adjust the distance between the moveable susceptor plate 50 and the showerhead device 10 during etching.
- the control system can also be configured to control the processes being used in the apparatus 1 .
- the reactant e.g., etchant
- the exhaust processes can be pulsed or alternated during the process for dynamic pressure control.
- a reactant dose can thus be divided into multiple short pulses, which can improve the distribution of the reactant molecules into the reaction chamber, facilitating rapid gas spreading by diffusion and/or pressure gradient across the substrate during each reactant or purge pulse.
- the switch-on and switch-off stages can repeated at least two times for the reactant. As a result, the pressure of the reaction space fluctuates rapidly between the low level and higher level pressure.
- the resulting pressure gradient in the reaction space during the switch-on stage pushes the precursor molecules efficiently to all areas of the reaction space, while the resulting pressure gradient in the reaction space during the switch-off stage pulls gaseous reaction by-products away from the surfaces of the reaction space to the gas outlet.
- a conventional, relatively long pulse e.g., 1 second
- the pressure is allowed to equalize, such that dynamic spreading effect is lost and the main part of the gas flow tends to head directly to the gas outlet.
- several short pulses e.g., 3 times 0.3 seconds
- Local pressure gradients enhance the exchange of gases in the reaction space and enhance the exchange of molecules between the substrate surface and the gas phase of the reaction space. It has been found that multiple pulses of the same gas per step, whether purge step or reactant step, is particularly advantageous when processing (e.g., etching) wafers with high aspect ratio features, such as deep, narrow trenches or vias in semiconductor substrates. Thus, the process of multiple same-vapor pulses in a row, and the consequent pressure fluctuations, are particularly advantageous for etching surfaces that include vias and trenches of greater than 20:1 aspect ratio, and more particularly greater than 40:1 aspect ratio. The pressure fluctuations enable more uniform distribution and/or coverage of the surfaces within such vias and trenches in less overall time than a single prolonged pulse. Thus, overall process time (or cycle time for cyclical processing) is reduced.
- the gap between the wafer 6 and showerhead device 10 can be about 3 mm and can be optimized for delivery of reactant A.
- the gap between the wafer 6 and showerhead device 10 can be adjusted accordingly.
- reactant B exposure time the gap can be adjusted appropriately to deliver reactant B.
- the disclosed embodiment accordingly provides flexibility to each step of the process.
- the apparatuses described herein can be used in etching processes, including plasma etch processes.
- the plasma sheath width, ion bombardment, residence time, plasma density, etc. can be adjusted and optimized for any step of the processes.
- Conditional language such as “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to imply that features, elements, and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or steps are included or are to be performed in any particular embodiment.
- the terms “generally parallel” and “substantially parallel” refer to a value, amount, or characteristic that departs from exactly parallel by less than or equal to 15 degrees, 10 degrees, 5 degrees, 3 degrees, 1 degree, or 0.1 degree.
Abstract
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US16/930,800 US11437249B2 (en) | 2019-07-18 | 2020-07-16 | Showerhead device for semiconductor processing system |
US17/929,585 US11948813B2 (en) | 2019-07-18 | 2022-09-02 | Showerhead device for semiconductor processing system |
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US201962875909P | 2019-07-18 | 2019-07-18 | |
US16/930,800 US11437249B2 (en) | 2019-07-18 | 2020-07-16 | Showerhead device for semiconductor processing system |
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US17/929,585 Continuation US11948813B2 (en) | 2019-07-18 | 2022-09-02 | Showerhead device for semiconductor processing system |
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US20210020468A1 US20210020468A1 (en) | 2021-01-21 |
US11437249B2 true US11437249B2 (en) | 2022-09-06 |
Family
ID=74170629
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US16/930,800 Active US11437249B2 (en) | 2019-07-18 | 2020-07-16 | Showerhead device for semiconductor processing system |
US17/929,585 Active US11948813B2 (en) | 2019-07-18 | 2022-09-02 | Showerhead device for semiconductor processing system |
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US (2) | US11437249B2 (en) |
JP (1) | JP2021019201A (en) |
KR (1) | KR20210010829A (en) |
CN (1) | CN112242324A (en) |
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US11948813B2 (en) * | 2019-07-18 | 2024-04-02 | Asm Ip Holding B.V. | Showerhead device for semiconductor processing system |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10273584B2 (en) | 2016-12-09 | 2019-04-30 | Asm Ip Holding B.V. | Thermal atomic layer etching processes |
US10283319B2 (en) | 2016-12-22 | 2019-05-07 | Asm Ip Holding B.V. | Atomic layer etching processes |
US11574813B2 (en) | 2019-12-10 | 2023-02-07 | Asm Ip Holding B.V. | Atomic layer etching |
US20240096605A1 (en) * | 2022-09-16 | 2024-03-21 | Applied Materials, Inc. | Backside deposition for wafer bow management |
Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206088A (en) | 1992-01-29 | 1993-08-13 | Fujikura Ltd | Method of processing semiconductor |
JPH08176851A (en) | 1994-12-26 | 1996-07-09 | Nec Corp | Dry etching method |
US20020160125A1 (en) * | 1999-08-17 | 2002-10-31 | Johnson Wayne L. | Pulsed plasma processing method and apparatus |
JP2004063633A (en) | 2002-07-26 | 2004-02-26 | Fujitsu Ltd | Method of manufacturing semiconductor laser |
US20040216668A1 (en) * | 2003-04-29 | 2004-11-04 | Sven Lindfors | Showerhead assembly and ALD methods |
US20050103265A1 (en) * | 2003-11-19 | 2005-05-19 | Applied Materials, Inc., A Delaware Corporation | Gas distribution showerhead featuring exhaust apertures |
US20080318417A1 (en) * | 2006-09-01 | 2008-12-25 | Asm Japan K.K. | Method of forming ruthenium film for metal wiring structure |
US7537662B2 (en) | 2003-04-29 | 2009-05-26 | Asm International N.V. | Method and apparatus for depositing thin films on a surface |
US7911001B2 (en) | 2007-07-15 | 2011-03-22 | Samsung Electronics Co., Ltd. | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices |
US8632687B2 (en) | 2008-08-14 | 2014-01-21 | Carl Zeiss Sms Gmbh | Method for electron beam induced etching of layers contaminated with gallium |
US20140273492A1 (en) | 2013-03-13 | 2014-09-18 | Jeffrey W. Anthis | Methods Of Etching Films Comprising Transition Metals |
US8869742B2 (en) | 2010-08-04 | 2014-10-28 | Lam Research Corporation | Plasma processing chamber with dual axial gas injection and exhaust |
TW201525173A (en) | 2013-12-09 | 2015-07-01 | Applied Materials Inc | Methods of selective layer deposition |
US20150218695A1 (en) | 2012-12-18 | 2015-08-06 | Seastar Chemicals Inc. | Process and method for in-situ dry cleaning of thin film deposition reactors and thin film layers |
US9132436B2 (en) * | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
WO2015160412A2 (en) | 2014-01-24 | 2015-10-22 | The Regents Of The University Of Colorado | Novel methods of preparing nanodevices |
US9184028B2 (en) | 2010-08-04 | 2015-11-10 | Lam Research Corporation | Dual plasma volume processing apparatus for neutral/ion flux control |
US9257638B2 (en) | 2014-03-27 | 2016-02-09 | Lam Research Corporation | Method to etch non-volatile metal materials |
TW201608662A (en) | 2014-08-28 | 2016-03-01 | Beijing Nmc Co Ltd | Atomic layer etching device and atomic layer etching method using same |
WO2016100873A1 (en) | 2014-12-18 | 2016-06-23 | The Regents Of The University Of Colorado, A Body Corporate | Novel methods of atomic layer etching (ale) using sequential, self-limiting thermal reactions |
US9396956B1 (en) | 2015-01-16 | 2016-07-19 | Asm Ip Holding B.V. | Method of plasma-enhanced atomic layer etching |
US9425041B2 (en) | 2015-01-06 | 2016-08-23 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
US20160307764A1 (en) | 2013-09-09 | 2016-10-20 | American Air Liquide, Inc. | Method of etching semiconductor structures with etch gas |
US20160308112A1 (en) | 2015-04-20 | 2016-10-20 | Lam Research Corporation | Dry plasma etch method to pattern mram stack |
WO2016172740A2 (en) | 2015-11-10 | 2016-10-27 | L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Etching reactants and plasma-free oxide etching processes using the same |
US9637823B2 (en) | 2014-03-31 | 2017-05-02 | Asm Ip Holding B.V. | Plasma atomic layer deposition |
WO2017099718A1 (en) | 2015-12-08 | 2017-06-15 | Intel Corporation | Atomic layer etching of transition metals by halogen surface oxidation |
WO2017205658A1 (en) | 2016-05-25 | 2017-11-30 | The Regents Of The University Of Colorado, A Body Corporate | Atomic layer etching on microdevices and nanodevices |
WO2017213842A2 (en) | 2016-05-23 | 2017-12-14 | The Regents Of The University Of Colorado, A Body Corporate | Enhancement of thermal atomic layer etching |
WO2018106955A1 (en) | 2016-12-09 | 2018-06-14 | Asm Ip Holding B.V. | Thermal atomic layer etching processes |
US10283319B2 (en) | 2016-12-22 | 2019-05-07 | Asm Ip Holding B.V. | Atomic layer etching processes |
Family Cites Families (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4255230A (en) | 1980-02-22 | 1981-03-10 | Eaton Corporation | Plasma etching process |
JPH0387026A (en) | 1988-12-13 | 1991-04-11 | Fujitsu Ltd | Manufacture of semiconductor device |
KR970009860A (en) | 1995-08-07 | 1997-03-27 | 장수영 | How to remove moisture by compression |
JP3750231B2 (en) | 1996-11-20 | 2006-03-01 | ソニー株式会社 | Method for forming multilayer wiring |
US6494959B1 (en) * | 2000-01-28 | 2002-12-17 | Applied Materials, Inc. | Process and apparatus for cleaning a silicon surface |
KR20060098522A (en) | 2005-03-03 | 2006-09-19 | 삼성전자주식회사 | Organic thin film transistor array panel and method for manufacturing the same |
JP4506677B2 (en) | 2005-03-11 | 2010-07-21 | 東京エレクトロン株式会社 | Film forming method, film forming apparatus, and storage medium |
US7211477B2 (en) | 2005-05-06 | 2007-05-01 | Freescale Semiconductor, Inc. | High voltage field effect device and method |
KR100707983B1 (en) | 2005-11-28 | 2007-04-16 | 주식회사 에이이티 | Atomic layer etching method for silicon dioxide film |
EP2006414A2 (en) | 2006-03-30 | 2008-12-24 | Mitsui Engineering & Shipbuilding Co., Ltd. | Atomic layer growing apparatus |
US20090088547A1 (en) | 2006-10-17 | 2009-04-02 | Rpo Pty Limited | Process for producing polysiloxanes and use of the same |
US8528498B2 (en) * | 2007-06-29 | 2013-09-10 | Lam Research Corporation | Integrated steerability array arrangement for minimizing non-uniformity |
JP5432686B2 (en) * | 2009-12-03 | 2014-03-05 | 東京エレクトロン株式会社 | Plasma processing equipment |
KR20110098355A (en) | 2010-02-26 | 2011-09-01 | 성균관대학교산학협력단 | Mothod for etching atomic layer using neutral beam etching apparatus |
GB2480228B (en) | 2010-03-08 | 2015-05-20 | Gskolen I Buskerud Og Vestfold H | Speckle reduction |
US20130312663A1 (en) | 2012-05-22 | 2013-11-28 | Applied Microstructures, Inc. | Vapor Delivery Apparatus |
JP6297269B2 (en) | 2012-06-28 | 2018-03-20 | ローム アンド ハース エレクトロニック マテリアルズ エルエルシーRohm and Haas Electronic Materials LLC | Polymer composition, photoresist comprising the polymer composition, and coated article comprising the photoresist |
KR102153246B1 (en) | 2012-10-30 | 2020-09-07 | 레르 리키드 쏘시에떼 아노님 뿌르 레드 에렉스뿔라따시옹 데 프로세데 조르즈 클로드 | Method and etching gas for etching silicon-containing films |
US8894870B2 (en) | 2013-02-01 | 2014-11-25 | Asm Ip Holding B.V. | Multi-step method and apparatus for etching compounds containing a metal |
US9447497B2 (en) | 2013-03-13 | 2016-09-20 | Applied Materials, Inc. | Processing chamber gas delivery system with hot-swappable ampoule |
KR101465338B1 (en) | 2013-06-07 | 2014-11-25 | 성균관대학교산학협력단 | LOW-DAMAGE ATOMIC LAYER ETCHING METHOD TO Al2O3 |
JP2015032597A (en) | 2013-07-31 | 2015-02-16 | 日本ゼオン株式会社 | Plasma etching method |
US20170081345A1 (en) | 2014-03-18 | 2017-03-23 | The Regents Of The University Of California | Metal-organic frameworks characterized by having a large number of adsorption sites per unit volume |
WO2015153742A1 (en) | 2014-04-01 | 2015-10-08 | Montana State University | Process of converting natural plant oils to biofuels |
US9624578B2 (en) | 2014-09-30 | 2017-04-18 | Lam Research Corporation | Method for RF compensation in plasma assisted atomic layer deposition |
JP2016134569A (en) | 2015-01-21 | 2016-07-25 | 株式会社東芝 | Semiconductor manufacturing equipment |
SG11201707998TA (en) | 2015-03-30 | 2017-10-30 | Tokyo Electron Ltd | Method for atomic layer etching |
US9502238B2 (en) | 2015-04-03 | 2016-11-22 | Lam Research Corporation | Deposition of conformal films by atomic layer deposition and atomic layer etch |
US10056264B2 (en) | 2015-06-05 | 2018-08-21 | Lam Research Corporation | Atomic layer etching of GaN and other III-V materials |
US9735024B2 (en) | 2015-12-28 | 2017-08-15 | Asm Ip Holding B.V. | Method of atomic layer etching using functional group-containing fluorocarbon |
WO2017173212A1 (en) | 2016-04-01 | 2017-10-05 | Wayne State University | A method for etching a metal surface |
US10622189B2 (en) * | 2016-05-11 | 2020-04-14 | Lam Research Corporation | Adjustable side gas plenum for edge rate control in a downstream reactor |
US20200313093A1 (en) | 2016-05-20 | 2020-10-01 | Brown University | Method for Manufacturing Perovskite Solar Cells and Multijunction Photovoltaics |
JP6766184B2 (en) | 2016-06-03 | 2020-10-07 | インテグリス・インコーポレーテッド | Hafnia and zirconia vapor phase etching |
US11149349B2 (en) | 2016-10-25 | 2021-10-19 | Basf Se | Process for the generation of thin silicon-containing films |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
US20200368690A1 (en) | 2017-08-16 | 2020-11-26 | 3M Innovative Properties Company | Polymeric ionomer separation membranes and methods of use |
JP2022501832A (en) | 2018-10-05 | 2022-01-06 | ラム リサーチ コーポレーションLam Research Corporation | Removal of metal contaminants from the surface of the processing chamber |
JP2021019202A (en) | 2019-07-18 | 2021-02-15 | エーエスエム アイピー ホールディング ビー.ブイ. | Semiconductor vapor etching device with intermediate chamber |
JP2021019201A (en) * | 2019-07-18 | 2021-02-15 | エーエスエム アイピー ホールディング ビー.ブイ. | Showerhead device for semiconductor processing system |
US11574813B2 (en) | 2019-12-10 | 2023-02-07 | Asm Ip Holding B.V. | Atomic layer etching |
-
2020
- 2020-07-15 JP JP2020121149A patent/JP2021019201A/en active Pending
- 2020-07-16 TW TW109124028A patent/TW202113967A/en unknown
- 2020-07-16 US US16/930,800 patent/US11437249B2/en active Active
- 2020-07-16 KR KR1020200088108A patent/KR20210010829A/en unknown
- 2020-07-17 CN CN202010691019.0A patent/CN112242324A/en active Pending
-
2022
- 2022-09-02 US US17/929,585 patent/US11948813B2/en active Active
Patent Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206088A (en) | 1992-01-29 | 1993-08-13 | Fujikura Ltd | Method of processing semiconductor |
JPH08176851A (en) | 1994-12-26 | 1996-07-09 | Nec Corp | Dry etching method |
US20020160125A1 (en) * | 1999-08-17 | 2002-10-31 | Johnson Wayne L. | Pulsed plasma processing method and apparatus |
JP2004063633A (en) | 2002-07-26 | 2004-02-26 | Fujitsu Ltd | Method of manufacturing semiconductor laser |
US20040216668A1 (en) * | 2003-04-29 | 2004-11-04 | Sven Lindfors | Showerhead assembly and ALD methods |
US7537662B2 (en) | 2003-04-29 | 2009-05-26 | Asm International N.V. | Method and apparatus for depositing thin films on a surface |
US20050103265A1 (en) * | 2003-11-19 | 2005-05-19 | Applied Materials, Inc., A Delaware Corporation | Gas distribution showerhead featuring exhaust apertures |
US20080318417A1 (en) * | 2006-09-01 | 2008-12-25 | Asm Japan K.K. | Method of forming ruthenium film for metal wiring structure |
US7911001B2 (en) | 2007-07-15 | 2011-03-22 | Samsung Electronics Co., Ltd. | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices |
US8632687B2 (en) | 2008-08-14 | 2014-01-21 | Carl Zeiss Sms Gmbh | Method for electron beam induced etching of layers contaminated with gallium |
US9184028B2 (en) | 2010-08-04 | 2015-11-10 | Lam Research Corporation | Dual plasma volume processing apparatus for neutral/ion flux control |
US8869742B2 (en) | 2010-08-04 | 2014-10-28 | Lam Research Corporation | Plasma processing chamber with dual axial gas injection and exhaust |
US9132436B2 (en) * | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US20150218695A1 (en) | 2012-12-18 | 2015-08-06 | Seastar Chemicals Inc. | Process and method for in-situ dry cleaning of thin film deposition reactors and thin film layers |
US20140273492A1 (en) | 2013-03-13 | 2014-09-18 | Jeffrey W. Anthis | Methods Of Etching Films Comprising Transition Metals |
US20160307764A1 (en) | 2013-09-09 | 2016-10-20 | American Air Liquide, Inc. | Method of etching semiconductor structures with etch gas |
TW201525173A (en) | 2013-12-09 | 2015-07-01 | Applied Materials Inc | Methods of selective layer deposition |
WO2015160412A2 (en) | 2014-01-24 | 2015-10-22 | The Regents Of The University Of Colorado | Novel methods of preparing nanodevices |
US9257638B2 (en) | 2014-03-27 | 2016-02-09 | Lam Research Corporation | Method to etch non-volatile metal materials |
US9637823B2 (en) | 2014-03-31 | 2017-05-02 | Asm Ip Holding B.V. | Plasma atomic layer deposition |
TW201608662A (en) | 2014-08-28 | 2016-03-01 | Beijing Nmc Co Ltd | Atomic layer etching device and atomic layer etching method using same |
WO2016100873A1 (en) | 2014-12-18 | 2016-06-23 | The Regents Of The University Of Colorado, A Body Corporate | Novel methods of atomic layer etching (ale) using sequential, self-limiting thermal reactions |
US9425041B2 (en) | 2015-01-06 | 2016-08-23 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
US20160329221A1 (en) | 2015-01-06 | 2016-11-10 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
US9396956B1 (en) | 2015-01-16 | 2016-07-19 | Asm Ip Holding B.V. | Method of plasma-enhanced atomic layer etching |
US20160308112A1 (en) | 2015-04-20 | 2016-10-20 | Lam Research Corporation | Dry plasma etch method to pattern mram stack |
WO2016172740A2 (en) | 2015-11-10 | 2016-10-27 | L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Etching reactants and plasma-free oxide etching processes using the same |
WO2017099718A1 (en) | 2015-12-08 | 2017-06-15 | Intel Corporation | Atomic layer etching of transition metals by halogen surface oxidation |
WO2017213842A2 (en) | 2016-05-23 | 2017-12-14 | The Regents Of The University Of Colorado, A Body Corporate | Enhancement of thermal atomic layer etching |
WO2017205658A1 (en) | 2016-05-25 | 2017-11-30 | The Regents Of The University Of Colorado, A Body Corporate | Atomic layer etching on microdevices and nanodevices |
WO2018106955A1 (en) | 2016-12-09 | 2018-06-14 | Asm Ip Holding B.V. | Thermal atomic layer etching processes |
US10283319B2 (en) | 2016-12-22 | 2019-05-07 | Asm Ip Holding B.V. | Atomic layer etching processes |
Non-Patent Citations (54)
Title |
---|
"Chemicals Used in Chip Fabrication," GAPS Guidelines GAP.17.1.1.B, Global Asset Protection Services LLC, 2015, pp. 1-4. |
"Inorganic Analysis," Analyst, 1921,46, pp. 157-161. |
"Insights for Electronics Manufacturing", Solid State Technology, Jul. 2016, vol. 59, No. 5, pp. 1-52. |
"Safetygram #25", Air Products and Chemicals, Inc., 2004 in 8 pages. |
"SO3 Gas-Phase Cleaning Process," Final Report, ANON Inc., San Jose, California, 1999, in 19 pages. |
"Xenon Difluoride (XeF2)," Versum Materials, LLC, 2016, in 2 pages. |
Barton et al., "The Dissociation of Sulfur Monochloride Vapor," J. Am. Chem. Soc., Feb. 1935, vol. 57 (2), pp. 307-310. |
Bock et al., "Unstable Intermediates in the Gaseous Phase: The Thermal Decomposition of Acyl Chlorides RCOC1," Angew. Chem. Int. Ed. Engl., 16, (1977) No. 2, pp. 105-107. |
Brandão et al., "Synthesis, Characterization and use of Nb2O5 based Catalysts in Producing Biofuels by Transesterification, Esterification and Pyrolysis," J. Braz. Chern. Soc., 2009, vol. 20, No. 5, pp. 954-966. |
Chaiken et al., "Rate of Sublimation of Ammonium Halides," The Journal of Chemical Physics 37, 2311 (1962), in 9 pages. |
Chalker, P.R., "Photochemical Atomic Layer Deposition and Etching," Surface & Coatings Technology, 291, (2016), pp. 258-263. |
Coman et al., "NbF5—AlF3 Catalysts: Design, Synthesis, and Application in Lactic Acid Synthesis from Cellulose", ACS Catal., 2015, 5 (5), pp. 3013-3026. |
Dumont et al., "Competition Between Al2O3 Atomic Layer Etching and AlF3 Atomic Layer Deposition Using Sequential Exposures of Trimethylaluminum and Hydrogen Fluoride." The Journal of Chemical Physics, 146, (2017), pp. 052819-1-052819-10. |
Dumont et al., "Thermal Atomic Layer Etching of SiO2 by a "Conversion-Etch" Mechanism Using Sequential Reactions of Trimethylaluminum and Hydrogen Fluoride," ACS Appl. Mater. Interfaces, 2017, 9, pp. 10296-10307. |
File History of U.S. Appl. No. 15/835,212, filed Dec. 7, 2017. |
File History of U.S. Appl. No. 15/835,262, filed Dec. 7, 2017. |
File History of U.S. Appl. No. 15/835,272, filed Dec. 7, 2017. |
File History of U.S. Appl. No. 16/390,319, filed Apr. 22, 2019. |
File History of U.S. Appl. No. 16/390,385, filed Apr. 22, 2019. |
File History of U.S. Appl. No. 16/390,540, filed Apr. 22, 2019. |
File History of U.S. Appl. No. 16/881,718, filed May 22, 2020. |
File History of U.S. Appl. No. 16/881,868, filed May 22, 2020. |
File History of U.S. Appl. No. 16/881,885, filed May 22, 2020. |
File History of U.S. Appl. No. 16/930,867, filed Jul. 16, 2020. |
Huardyiting Zhang, et al., "Atomic Layer Etching of 3D Structures in Silicon: Self-limiting and Nonideal Reactions," Journal of Vacuum Science & Technology A, 2017, p. 031306-1-031306-15. |
Jackson et al., "Optimizing AlF3 Atomic Layer Deposition Using Trimethylaluminum and TaF5: Application to High Voltage Li-ion Battery Cathodes," Journal of Vacuum Science & Technology A 34, 2016, pp. 031503-1-031503-8. |
Johnson et al., "WO3 and W Thermal Atomic Layer Etching Using "Conversion Fluorination" and "Oxidation-Conversion-Fluorination" Mechanisms", ACS Appl. Mater. Interfaces, 2017, 9, pp. 34435-34447. |
Johnson et al., Thermal Atomic Layer Etching of Crystalline Aluminum Nitride Using Sequential, Selflimiting Hydrogen Fluoride and Sn(acac)2 Reactions and Enhancement by H2 and Ar. |
Kanarik et al., "Overview of Atomic Layer Etching in the Semiconductor Industry," Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 33, 2015, p. 020802-1-020802-14. |
Kastenmeier et al., "Remote Plasma Etching of Silicon Nitride and Silicon Dioxide Using NF3/02 Gas Mixtures," Journal of Vacuum Science & Technology A, 1998, pp. 2047-2056. |
Kastenmeier et al., "Surface Etching Mechanism of Silicon Nitride in Fluorine and Nitric Oxide Containing Plasmas," Journal of Vacuum Science & Technology A, 2001, pp. 25-30. |
Kepten, et al., "Studies of the Possible Reaction of WF6 with SiO2 and Si3N4 at Several Temperatures." J. Electrochem. Soc., vol. 139, No. 8, Aug. 1992, pp. 2331-2337. |
Knapas et al., "Etching of Nb2O5 Thin Films by NbCl5", Chemical Vapor Deposition, 2009, vol. 15, pp. 269-273. |
Kohli et al., "Methods for Removal of Particle Contaminants," Developments in Surface Contamination and Cleaning, vol. 3, 2011, in 259 pages. |
Kuhle, Engelbert, "One Hundred Years of Sulferic Acid Chemistry, 11b. Substitution and Cyclization Reactions of Sulfenyl Halides", Dec. 1971, pp. 617-638. |
Lee et al., "Atomic Layer Etching Al2O3 Using Sequential, Self-Limiting Thermal Reactions with Sn(acac)2 and Hydrogen Fluoride", ACS Nano, 9 (2), 2015, pp. 2061-2070. |
Lee et al., "Atomic Layer Etching of HfO2 Using Sequential, Self-Limiting Thermal Reactions with Sn(acac)2 and HF", ECS Journal of Solid State Science and Technology, 4 (6), 2015, pp. N5013-N5022. |
Lee et al., "Selectivity in Atomic Layer Etching Using Sequential, Self-Limiting Thermal Reactions," ACS Nano 9, 2061, 2015, in 29 pages. |
Lee et al., "Thermal Atomic Layer Etching of Titanium Nitride Using Sequential, Self-Limiting Reactions: Oxidation to TiO2 and Fluorination to Volatile TiF4", Chern. Mater., 2017, 29, pp. 8202-8210. |
Lenher, Victor, "Some Properties on Selenium Oxychloride", Contribution from the Department of Chemistry, University of Wisconsin, May 26, 1922, pp. 1664-1667. |
Luna, Adolfo E. Castro, "Vapor Pressure of WOCl4", J. Chem. Eng. Data, 1983, 28, p. 349. |
McDonald et al., "Corrosion of Steel and Nickel Alloys in Neutral and Acidic Solutions of Thionyl Chloride and Sulfuryl Chloride," Journal of the Electrochemical Society, Jun. 1988, pp. 1313-1316. |
Michalski et al., "A New Approach towards Organophosphorus Sulfenyl and Selenyl Halides, Phosphorus and Sulfur and the Related Elements", 30:1-2, Jan. 3, 2007, pp. 221-224. |
Nieder-Vahrenholz, et al., "Die Oxidfluoride des Niobs und Tantals", Journal of Inorganic and General Chemistry, Zeitschrift fur anorganische Chemie, vol. 544, 1, Jan. 1987, pp. 122-126. |
Oehrlein, et al., "Atomic Layer Etching at the Tipping Point: An Overview", ECS Journal of Solid State Science and Technology, 4 (6), Mar. 27, 2015, pp. N5041-N5053. |
Painter, Edgar Page, "The Chemistry and Toxicity of Selenium Compounds, with Special Reference to the Selenium Problem," Chern. Rev., Apr. 1941, 28 (2), pp. 179-213. |
Pop et al., "New Group 11 Complexes with Metal-Selenium Bonds of Methyldiphenylphosphane Selenide: A Solid State, Slution and Theoretical Investigation," Dalton Trans., 2011, 40, p. 12479-12490. |
Rivillon et al., "Chlorination of Hydrogen-Terminated Silicon (111) Surfaces," J. Vac. Sci. Technol. A 23, Jul./Aug. 2005, pp. 1100-1106. |
Shinoda et al., "Thermal Cyclic Etching of Silicon Nitride Using Formation and Desorption of Ammonium Fluorosilicate," Applied Physics Express 9, 2016, pp. 106201-1-106201-3. |
Société chimique de France. Auteur du texte, "Bulletin de la Socit chimique de Paris", L. Hachette; Masson, 1871, p. 47. |
Sprenger et al., "Electron-enhanced atomic layer deposition of silicon thin films at room temperature", J. Vac. Sci. Technol. A 36(1), Jan./Feb. 2018, pp. 01A118-1-01A118-10. |
Suresh B.S., et al., "A Study of the Reaction of Silicon Tetrahalides with Phosphorus Pentoxide and of Alkali Metal Fluorosilicates with Phosphorus Pentoxide and Sulphur Trioxide," Journal of Fluorine, 24, 1984, pp. 399-407. |
Svistunova, I.V., "Boron Difluoride Acetylacetonate Sulfenyl (Selenyl) Halides," Russian Journal of General Chemistry, 2010, vol. 80, No. 12, pp. 2430-2437. |
Vallée, et al., "Selective Deposition Process Combining PEALD and ALE ex: Ta2O5 and TiO2," Powerpoint presentation at the 2017 ALD Conference, in 53 pages. |
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