US11189635B2 - 3D-NAND mold - Google Patents

3D-NAND mold Download PDF

Info

Publication number
US11189635B2
US11189635B2 US16/833,899 US202016833899A US11189635B2 US 11189635 B2 US11189635 B2 US 11189635B2 US 202016833899 A US202016833899 A US 202016833899A US 11189635 B2 US11189635 B2 US 11189635B2
Authority
US
United States
Prior art keywords
layers
oxide
thickness
layer
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/833,899
Other languages
English (en)
Other versions
US20200312874A1 (en
Inventor
Chang Seok Kang
Tomohiko Kitajima
Mukund Srinivasan
Sanjay Natarajan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US16/833,899 priority Critical patent/US11189635B2/en
Priority to KR1020217034385A priority patent/KR102688125B1/ko
Priority to PCT/US2020/026067 priority patent/WO2020205908A1/en
Priority to CN202080024449.5A priority patent/CN113632231A/zh
Priority to JP2021558829A priority patent/JP7443393B2/ja
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KITAJIMA, TOMOHIKO, KANG, CHANG SEOK, NATARAJAN, SANJAY, SRINIVASAN, MUKUND
Publication of US20200312874A1 publication Critical patent/US20200312874A1/en
Application granted granted Critical
Publication of US11189635B2 publication Critical patent/US11189635B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H01L27/11582—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • Embodiments of the present disclosure pertain to the field of electronic devices and methods and apparatus for manufacturing electronic devices. More particularly, embodiments of the disclosure provide methods for forming 3D-NAND mold stacks.
  • NAND devices Semiconductor technology has advanced at a rapid pace and device dimensions have shrunk with advancing technology to provide faster processing and storage per unit space.
  • the string current needs to be high enough to obtain sufficient current to differentiate ON and OFF cells.
  • the string current is dependent on the carrier mobility which is enhanced by enlarging the grain size of the silicon channel.
  • a method of forming an electronic device comprises removing one or more first layers from a film stack comprising alternating second layers and first layers, the first layers removed from a first side of the first layers to leave an opening bounded on a second side by one or more films comprising a poly-silicon layer, the opening having a first thickness; trimming the adjacent second layers through the opening to increase the thickness of the opening from the first thickness to a second thickness and decrease a first oxide layer thickness to a second oxide layer thickness smaller than the first oxide layer thickness; and depositing a word line replacement material in the opening.
  • a semiconductor memory device comprises: a film stack comprising alternating nitride and oxide layers in a first portion of the device, the alternating nitride and oxide layers of the film stack having a nitride:oxide thickness ratio (N f :O f ); and a memory stack comprising alternating word line and oxide layers in a second portion of the device, the alternating word line and oxide layers of the memory stack having a word line:oxide thickness ratio (W m :O m ), wherein 0.1(W m :O m ) ⁇ N f :O f ⁇ 0.95(W m :O m ).
  • a processing tool comprises: a central transfer station comprising a robot configured to move a wafer; plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations comprising an oxide layer thinning chamber and a word line deposition chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between process stations, and to control a process occurring in each of the process stations.
  • FIG. 1 depicts a flow process diagram of one embodiment of a method of forming a memory device according to embodiments described herein;
  • FIG. 2 illustrates a cross-sectional view of a device with a memory stack according to one or more embodiments
  • FIG. 3 illustrates a cross-sectional view of a substrate after forming a staircase pattern of the memory stack according to one or more embodiments
  • FIG. 4A illustrates a cross-sectional view of a substrate after formation of a memory hole according to one or more embodiments
  • FIG. 4B illustrates a cross-sectional view region 103 of the substrate of FIG. 4A according to one of more embodiments
  • FIG. 5A illustrates a cross-sectional view of a substrate after selective oxidation of a nitride layer according to one or more embodiments
  • FIG. 5B illustrates an expanded view of region 101 according to one or more embodiments
  • FIG. 6A illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 6B illustrates an expanded view of region 101 after according to one or more embodiments
  • FIG. 7 illustrates a cross-sectional view of a substrate after formation of a bit line pad according to one or more embodiments
  • FIG. 8 illustrates a cross-sectional view of a substrate after deposition of an interlayer dielectric according to one or more embodiments
  • FIG. 9 illustrates a cross-sectional view of a substrate after slit patterning according to one or more embodiments
  • FIG. 10 illustrates a cross-sectional view of a substrate after a sacrificial layer is removed according to one or more embodiments
  • FIG. 11 illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 12 illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 13A illustrates a cross-sectional view of a substrate after etching the nitride according to one or more embodiments
  • FIG. 13B illustrates an expanded view of region 201 of FIG. 13A ;
  • FIG. 14A illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 14B illustrates an expanded view of region 201 of FIG. 14A ;
  • FIG. 15A illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 15B illustrates an expanded view of region 201 of FIG. 15A ;
  • FIG. 16 illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 17 illustrates a cross-sectional view of a substrate according to one or more embodiments
  • FIG. 18 illustrates a cross-sectional view of a substrate according to one or more embodiments.
  • FIG. 19 illustrates a cluster tool according to one or more embodiments.
  • the alternating layers are not limited to alternating layers if nitride and oxide but may comprise alternating layers of a first material and a second material.
  • metal deposition and other processes can be carried out in an isolated environment (e.g., a cluster process tool). Accordingly, some embodiments of the disclosure provide integrated tool systems with related process modules to implement the methods.
  • FIG. 1 illustrates a flowchart for an exemplary method 10 for forming a memory device.
  • the skilled artisan will recognize that the method 10 can include any or all of the processes illustrated. Additionally, the order of the individual processes can be varied for some portions. The method 10 can start at any of the enumerated processes without deviating from the disclosure.
  • a memory stack is formed.
  • a word line staircase is formed in the memory stack.
  • a memory hole channel is patterned into the word line staircase.
  • the first layers e.g. nitride layers, may be selectively oxidized through the memory hole channel.
  • the transistor layers are deposited.
  • the bit line pad is formed.
  • an interlayer dielectric is deposited.
  • the memory staircase is slit patterned.
  • the sacrificial layer is removed.
  • a semiconductor material is deposited.
  • the first layers e.g. nitride layers, are removed.
  • the second layers e.g. oxide layers, are trimmed.
  • the word line replacement material is deposited.
  • the slit is filled, and, at operation 85 , the word line contacts are formed.
  • FIGS. 2-18 illustrate a portion of a memory device 100 following the process flow illustrated for the method 10 in FIG. 1 .
  • FIG. 2 illustrates an initial or starting memory stack of an electronic device 100 in accordance with one or more embodiments of the disclosure.
  • the electronic device 100 shown in FIG. 2 is formed on the bare substrate 105 in layers, as illustrated.
  • the electronic device of FIG. 2 is made up of a substrate 105 , a semiconductor layer 110 , a sacrificial layer 120 , a memory stack 130 and an oxide layer 140 .
  • the substrate 105 can be any suitable material known to the skilled artisan.
  • substrate refers to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.
  • a “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process.
  • a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application.
  • Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and/or bake the substrate surface.
  • any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such under-layer as the context indicates.
  • substrate surface is intended to include such under-layer as the context indicates.
  • a semiconductor layer 110 is on the substrate 105 .
  • the semiconductor layer 110 may also be referred to as the common source line.
  • the semiconductor layer 110 can be formed by any suitable technique known to the skilled artisan and can be made from any suitable material including, but not limited to, poly-silicon (poly-Si).
  • the semiconductor layer 110 is a common source line that is made of a conductive or a semiconductor material.
  • the sacrificial layer 120 is formed on the semiconductor layer 110 and can be made of any suitable material.
  • the sacrificial layer 120 in some embodiments is removed and replaced in later processes. In some embodiments, the sacrificial layer 120 is not removed and remains within the memory device 100 .
  • the term “sacrificial” has an expanded meaning to include permanent layers and may be referred to as the conductive layer.
  • the sacrificial layer 120 is removed in operation 55 .
  • the sacrificial layer 120 comprises a material that can be removed selectively versus the neighboring semiconductor layer 110 and oxide layer 132 .
  • a memory stack 130 is formed on the sacrificial layer 120 .
  • the memory stack 130 in the illustrated embodiment comprises a plurality of alternating second layers 132 and first layers 134 .
  • the first layers 134 comprise nitride layers and the second layers 132 comprise oxide layers.
  • the memory stack 130 comprises a non-replacement gate such as alternating oxide and poly-Si(OP), or oxide and metal, or oxide and sacrificial layer.
  • the first layers 134 comprise a material that is etch selective relative to the second layers 132 so that the first layers 134 can be removed without substantially affecting the second layers 132 .
  • the first layers 134 comprise silicon nitride.
  • the second layers 132 comprise silicon oxide.
  • each second layer 132 is approximately equal. In one or more embodiments, each second layer 132 has a first second layer thickness. In some embodiments, the thickness of each first layer 134 is approximately equal. As used in this regard, thicknesses which are approximately equal are within +/ ⁇ 5% of each other.
  • a silicon layer (not shown) is formed between the second layers 132 and first layers 134 . The thickness of the silicon layer may be relatively thin as compared to the thickness of a layer of second layers 132 or first layers 134 .
  • the first layers 134 have a thickness in a range of from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.
  • the nitride layer 134 has a thickness in the range of from about 0.5 to about 40 nm.
  • a staircase formation 131 is created.
  • the staircase formation 131 exposes a top surface 135 of the second layers 132 .
  • the top surface 135 can be used to provide space for word line contacts to be formed, as described below.
  • a suitable fill material 137 can be deposited to occupy the space outside the staircase formation 131 .
  • a suitable fill material 137 can be any material that prevents electrical shorting between adjacent word lines.
  • a memory hole channel 150 is opened through the memory stack 130 .
  • opening the memory hole channel 150 comprises etching through the oxide layer 140 , memory stack 130 , sacrificial layer 120 , and into semiconductor layer 110 .
  • FIG. 4B which is an expanded view of region 103 , the memory hole channel 150 has sidewalls that extend through the memory stack 130 exposing surfaces 138 of the second layers 132 and surface 139 of the first layers 134 .
  • the sacrificial layer 120 has surfaces 122 exposed as sidewalls of the memory hole channel 150 .
  • the memory channel hole 150 extends a distance into the semiconductor layer 110 so that sidewall surface 112 and bottom 114 of the memory hole channel 150 are formed within the semiconductor layer 110 .
  • the bottom 114 of the memory hole channel 150 can be formed at any point within the thickness of the semiconductor layer 110 .
  • the memory hole channel 150 extends a thickness into the semiconductor layer 110 in the range of from about 10% to about 90%, or in the range of from about 20% to about 80%, or in the range of from about 30% to about 70%, or in the range of from about 40% to about 60% of the thickness of the semiconductor layer 110 .
  • the memory hole channel 150 extends a distance into the semiconductor layer 110 by greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80% of the thickness of the semiconductor layer 110 .
  • FIG. 5A shows operation 30 in which the first layers 134 , e.g. nitride layers, are selectively oxidized through the memory hole channel 150 .
  • the selective oxidation of the first layers 134 is optional.
  • FIG. 5B is an expanded view of region 101 of FIG. 5A .
  • the first layers 134 e.g. nitride layers, are selectively oxidized by in situ steam generation (ISSG) oxidation or radical plasma oxidation (RPO) at a temperature in a range of from about 700° C. to about 900° C.
  • ISSG in situ steam generation
  • RPO radical plasma oxidation
  • the ISSG oxide 155 is formed adjacent the memory hole channel 150 in the first layers 134 , e.g. nitride layers. Without intending to be bound by theory, it is thought that the ISSG oxide 155 protects the blocking oxide 176 from etching during the nitride pull-back by hot phosphorus. In one or more embodiments, the ISSG oxide layer 155 or RPO oxide layer 155 has a thickness of about 2 nm.
  • FIGS. 6A and 6B show operation 35 in which transistor layers 165 are conformally deposited into memory hole channel 150 adjacent the second layers 132 and the ISSG oxide layer 155 or RPO oxide layer 155 .
  • the transistor layers 165 can be formed by any suitable technique known to the skilled artisan.
  • the transistor layers 165 are formed by a conformal deposition process.
  • the transistor layers 165 are formed by one or more of atomic layer deposition or chemical vapor deposition.
  • the deposition of the transistor layers 165 is substantially conformal.
  • a layer which is “substantially conformal” refers to a layer where the thickness is about the same throughout (e.g., on the top, middle and bottom of sidewalls and on the bottom of the memory hole channel 150 ).
  • a layer which is substantially conformal varies in thickness by less than or equal to about 5%, 2%, 1% or 0.5%.
  • the transistor layers 165 comprises a blocking oxide layer 176 (or a first oxide layer 176 ), a nitride trap layer 174 on the first oxide layer 176 , a second oxide layer 172 (or the tunneling oxide layer 172 ) on the nitride trap layer 174 and a poly-silicon layer 170 in the memory hole channel 150 on the second oxide layer 172 .
  • the blocking oxide layer 176 , the charge trap nitride (SiN) layer 174 , and the tunneling oxide layer 172 are deposited in the memory hole channel 150 on the sidewalls of the memory hole channel 150 or on the semiconductor layer 110 .
  • a poly-silicon (poly-Si) layer 170 is formed in the memory hole channel 150 adjacent to the transistor layers 165 .
  • the poly-Si layer 170 can be formed directly on the transistor layers 165 .
  • the poly-Si layer 170 can be deposited by any suitable technique known to the skilled artisan, including, but not limited to, atomic layer deposition and chemical vapor deposition.
  • the poly-Si layer 170 is deposited as a conformal layer so that the poly-silicon layer is formed on sidewalls and exposed surface 138 , 139 , 122 , 112 and bottom 114 (see FIG. 4B ) of the memory hole channel 150 .
  • the poly-silicon layer 170 can have any suitable thickness depending on, for example, the dimensions of the memory hole channel 150 .
  • the poly-silicon layer 170 has a thickness in the range of from about 0.5 nm to about 50 nm, or in the range of from about 0.75 nm to about 35 nm, or in the range of from about 1 nm to about 20 nm.
  • the poly-silicon layer 170 is a continuous film.
  • the poly-silicon layer 170 is formed in a macaroni type with conformal deposition on the tunnel oxide layer 172 , the poly-silicon layer 170 having a thickness in a range of from about 1 nm to about 20 nm. Then, the memory hole channel 150 is filled with a dielectric material 160 .
  • FIG. 7 shows operation 40 of method 10 where a bit line pad 180 is formed in the poly-silicon (poly-Si) layer 160 .
  • the bit line pad 180 can be any suitable material known to the skilled artisan including, but not limited to, poly-silicon.
  • FIG. 8 shows operation 45 of method 10 where an interlayer dielectric 185 is deposited on a top surface of the oxide layer 140 and the bit line pad 180 .
  • the interlayer dielectric (ILD) 185 may be deposited by any suitable technique known to one of skill in the art.
  • the interlayer dielectric 185 may comprise any suitable material known to one of skill in the art.
  • the interlayer dielectric 185 is a low-K dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide (SiO 2 ), silicon nitride (SiN), or any combination thereof.
  • materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide (SiO 2 ), silicon nitride (SiN), or any combination thereof.
  • silicon oxide may be used to describe the interlayer dielectric 185
  • the skilled artisan will recognize that the disclosure is not restricted to a particular stoichiometry.
  • the terms “silicon oxide” and “silicon dioxide” may both be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same is true for the other materials listed in this disclosure, e.g. silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and the like.
  • FIG. 9 shows operation 50 of method 10 where the memory stack 130 is slit patterned to form slit pattern openings 190 that extend from a top surface of the interlayer dielectric 185 to the substrate 105 .
  • FIG. 10 shows operation 55 of method 10 where the sacrificial layer 120 and a portion 165 of the poly-silicon layer 160 are removed.
  • the sacrificial layer 120 can be removed by any suitable technique known to the skilled artisan including, but not limited to, selective etching.
  • FIG. 11 shows operation 60 of method 10 where a semiconductor material (e.g. nitride and poly-silicon fill) 195 is deposited in slit pattern opening 190 .
  • the semiconductor material may be any suitable material known to one of skill in the art.
  • FIG. 12 shows where the semiconductor material 195 is removed from the sidewalls of the slit pattern openings 190 .
  • the slit pattern openings 190 should be larger than common source line 110 (semiconductor layer 110 ) height so that there may be an opening in the slit pattern opening 190 in order to remove the semiconductor material 195 from the sidewalls.
  • the semiconductor material 195 is removed from the sidewalls of the slit pattern opening 190 by an isotropic etch process (e.g. wet etching using TMAH or the like).
  • FIGS. 13A and 13B show operation 65 of method 10 where one or more of the first layers 134 , e.g. nitride layers, are removed to form openings 210 and slit pattern opening 190 .
  • the openings 210 have a first thickness, t 1 , in a range of from about 1 nm to about 50 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, about 30 nm, about 32 nm, about 35 nm, about 37 nm, about 40 nm, about 42 nm, about 45 nm, about 47 nm, and about 50 nm.
  • FIG. 13B is an expanded view of a portion 201 of the substrate in FIG. 13A .
  • the first side of the first layers 134 e.g. nitride layers
  • the first side of the first layers 134 are exposed to an etchant through the slit pattern opening 190 .
  • FIGS. 14A and 14B show operation 70 of method 10 where the second layers 132 , e.g. oxide layers, are trimmed through the opening 210 to increase the thickness of the opening 210 from the first thickness, t 1 , to a second thickness, t 2 .
  • the second thickness, t 2 is greater than or equal to the about 50% to about 75% larger than the first thickness, t 1 .
  • the second thickness, t 2 is about 50%, or about 55%, or about 60%, or about 65%, or about 70%, or about 75% larger than the first thickness, t 1 .
  • when the second layers 132 e.g.
  • the second layers 132 e.g. oxide layers, of the memory stack 130 have an average thickness, second thickness of the second layers 132 , in the range of from about 5 nm to about 30 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.
  • the oxide layers 132 of the memory stack 130 have an average thickness, second oxide layer thickness, in the range of from about 5 nm to about 30 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.
  • the second layers 132 are trimmed by exposing the second layers 132 , e.g. oxide layers, to a fluorine-based gas phase dry cleaning process or a dilute hydrogen fluoride (HF) solution through the slit pattern opening 190 .
  • trimming the second layers 132 comprises exposing the second layers 132 to fluorine-based gas phase dry cleaning chemistry or dilute hydrogen fluoride (HF) chemistry through the slit pattern opening 190 .
  • the thickness of the second layers 132 e.g. oxide layers
  • the thickness of the openings 210 is increased/widened.
  • the thickness of the openings 210 is increased from a first thickness, t 1 , to a second thickness, t 2 , and the thickness of the second layers 132 , e.g. oxide layers, is decreased to a second thickness of the second layers 132 smaller than the first thickness of the second layers 132 .
  • FIGS. 15A and 15B show operation 75 of method 10 where an aluminum oxide layer 215 and a word line replacement material 225 are deposited in the opening 210 .
  • FIG. 15B is an expanded view of a portion 201 of the device of FIG. 15A .
  • the word line replacement material 225 comprises a nitride liner 220 (e.g.
  • the bulk metal comprises tungsten (W). In other embodiments, the bulk metal layer comprises ruthenium (Ru).
  • FIG. 16 shows operation 80 of method 10 where the slit pattern opening 190 is filled with a fill material 230 .
  • the fill material 230 may be any suitable material known to one of skill in the art.
  • the fill material 230 comprises one or more of a dielectric material or a conductor material.
  • dielectric material refers to a layer of material that is an electrical insulator that can be polarized in an electric field.
  • the dielectric material comprises one or more of oxides, carbon doped oxides, silicon oxide (SiO), porous silicon dioxide (SiO 2 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxide/silicon nitride, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH).
  • oxides silicon oxide
  • SiO porous silicon dioxide
  • SiO silicon oxide
  • SiN silicon nitride
  • silicon oxide/silicon nitride carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH).
  • FIG. 17 shows operation 85 of method 10 where word line contacts 235 are formed.
  • the word line contacts 235 extend through the memory stack 130 a distance sufficient to terminate at one of the word lines 225 .
  • the word line contacts 235 can comprise any suitable material known to the skilled artisan.
  • the word line contact 235 comprises one or more of a metal, a metal silicide, poly-silicon, amorphous silicon, or EPI silicon.
  • the word line contact is doped by either N type dopants or P type dopants in order to reduce contact resistance.
  • the metal of the word line contact 235 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).
  • FIG. 18 shows a semiconductor memory device according to one or more embodiments.
  • the memory device 100 comprises: a film stack 120 comprising alternating first layers 134 , e.g. nitride layers, and second layers 132 , e.g. oxide layers, in a first portion 300 of the device 100 , the alternating first layers 134 , e.g. nitride layers, and second layers 132 , e.g. oxide layers, of the film stack 120 having a nitride:oxide thickness ratio (N f :O f ).
  • a memory stack 130 comprising alternating word line 225 and second layers 132 , e.g.
  • the alternating word line 225 and second layers 132 e.g. oxide layers, of the memory stack 130 having a word line:oxide thickness ratio (W m :O m ), wherein 0.1(W m :O m ) ⁇ N f :O f ⁇ 0.95(W m :O m ). In one or more embodiments, 0.2(W m :O m ) ⁇ N f :O f ⁇ 0.9(W m :O m ). In other embodiments, 0.5(W m :O m ) ⁇ N f :O f ⁇ 0.75(W m :O m ).
  • the first layers 134 e.g. nitride layers, of the film stack 120 have a thickness in a range of from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.
  • W m :O m is in the range of from about 2.5:2 to about 3.5:2.
  • the first layers 134 e.g. nitride layers, of the film stack 120 has a thickness in the range of from about 0.5 to about 50 nm, including a range of from about 1 nm to about 50 nm, and a range of from 1 nm to about 30 nm.
  • the second layers 132 e.g. oxide layers, of the memory stack 130 have an average thickness in the range of from about 10 nm to about 20 nm.
  • a method of forming an electronic device comprises removing one or more first layers from a film stack comprising alternating second layers and first layers, the first layers removed from a first side of the first layers to leave an opening bounded on a second side by one or more films comprising a poly-silicon layer, the opening having a first thickness; trimming the adjacent second layers through the opening to increase the thickness of the opening from the first thickness to a second thickness and decrease a first second layer thickness to a second oxide layer thickness smaller than the first second layer thickness; and depositing a word line replacement material in the opening.
  • Additional embodiments of the disclosure are directed to processing tools 900 for the formation of the memory devices and methods described, as shown in FIG. 19 .
  • the cluster tool 900 includes at least one central transfer station 921 , 931 with a plurality of sides.
  • a robot 925 , 935 is positioned within the central transfer station 921 , 931 and is configured to move a robot blade and a wafer to each of the plurality of sides.
  • the cluster tool 900 comprises a plurality of processing chambers 902 , 904 , 906 , 908 , 910 , 912 , 914 , 916 , and 918 , also referred to as process stations, connected to the central transfer station.
  • the various processing chambers provide separate processing regions isolated from adjacent process stations.
  • the processing chamber can be any suitable chamber including, but not limited to, a preclean chamber, a buffer chamber, transfer space(s), a wafer orienter/degas chamber, a cryo cooling chamber, a deposition chamber, annealing chamber, etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber.
  • the particular arrangement of process chambers and components can be varied depending on the cluster tool and should not be taken as limiting the scope of the disclosure.
  • the cluster tool 900 includes an oxide layer thinning chamber.
  • the oxide layer thinning chamber of some embodiments comprises one or more a fluorine-based dry cleaning chamber.
  • the cluster tool 900 includes a pre-cleaning chamber connected to the central transfer station.
  • a factory interface 950 is connected to a front of the cluster tool 900 .
  • the factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on a front 951 of the factory interface 950 . While the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is merely representative of one possible configuration.
  • the size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrates being processed in the cluster tool 900 .
  • the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned within the cassette.
  • a robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956 .
  • the robot 952 is capable of transferring a wafer from a cassette in the loading chamber 954 through the factory interface 950 to load lock chamber 960 .
  • the robot 952 is also capable of transferring a wafer from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956 .
  • the factory interface 950 can have more than one robot 952 .
  • the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and load lock chamber 960 , and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956 .
  • the cluster tool 900 shown has a first section 920 and a second section 930 .
  • the first section 920 is connected to the factory interface 950 through load lock chambers 960 , 962 .
  • the first section 920 includes a first transfer chamber 921 with at least one robot 925 positioned therein.
  • the robot 925 is also referred to as a robotic wafer transport mechanism.
  • the first transfer chamber 921 is centrally located with respect to the load lock chambers 960 , 962 , process chambers 902 , 904 , 916 , 918 , and buffer chambers 922 , 924 .
  • the robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time.
  • the first transfer chamber 921 comprises more than one robotic wafer transfer mechanism.
  • the robot 925 in first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921 . Individual wafers are carried upon a wafer transport blade that is located at a distal end of the first robotic mechanism.
  • the wafer After processing a wafer in the first section 920 , the wafer can be passed to the second section 930 through a pass-through chamber.
  • chambers 922 , 924 can be uni-directional or bi-directional pass-through chambers.
  • the pass-through chambers 922 , 924 can be used, for example, to cryo cool the wafer before processing in the second section 930 , or allow wafer cooling or post-processing before moving back to the first section 920 .
  • a system controller 990 is in communication with the first robot 925 , second robot 935 , first plurality of processing chambers 902 , 904 , 916 , 918 and second plurality of processing chambers 906 , 908 , 910 , 912 , 914 .
  • the system controller 990 can be any suitable component that can control the processing chambers and robots.
  • the system controller 990 can be a computer including a central processing unit, memory, suitable circuits and storage.
  • Processes may generally be stored in the memory of the system controller 990 as a software routine that, when executed by the processor, causes the process chamber to perform processes of the present disclosure.
  • the software routine may also be stored and/or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the method of the present disclosure may also be performed in hardware.
  • the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware.
  • the software routine when executed by the processor, transforms the general purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.
  • the system controller 990 has a configuration to control the selective oxidation chamber to selectively oxidize the first layers, e.g. nitride layers, on a wafer at a temperature in the range of from about 400° C. to about 900° C. in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) gas at ambient pressure.
  • the controller 990 has a configuration to activate the oxide layer thinning chamber to remove portions of an oxide layer from the wafer using fluorine-based dry etching of hydrogen fluoride (HF) solution based etching.
  • HF hydrogen fluoride
  • a processing tool comprises: a central transfer station comprising a robot configured to move a wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations comprising an oxide layer thinning chamber and a word line deposition chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between process stations, and to control a process occurring in each of the process stations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US16/833,899 2019-04-01 2020-03-30 3D-NAND mold Active 2040-08-14 US11189635B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US16/833,899 US11189635B2 (en) 2019-04-01 2020-03-30 3D-NAND mold
KR1020217034385A KR102688125B1 (ko) 2019-04-01 2020-04-01 3-d nand 몰드
PCT/US2020/026067 WO2020205908A1 (en) 2019-04-01 2020-04-01 3-d nand mold
CN202080024449.5A CN113632231A (zh) 2019-04-01 2020-04-01 3-d nand模具
JP2021558829A JP7443393B2 (ja) 2019-04-01 2020-04-01 ３ｄ－ｎａｎｄモールド

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962827360P 2019-04-01 2019-04-01
US16/833,899 US11189635B2 (en) 2019-04-01 2020-03-30 3D-NAND mold

Publications (2)

Publication Number Publication Date
US20200312874A1 US20200312874A1 (en) 2020-10-01
US11189635B2 true US11189635B2 (en) 2021-11-30

Family

ID=72604843

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/833,899 Active 2040-08-14 US11189635B2 (en) 2019-04-01 2020-03-30 3D-NAND mold

Country Status (5)

Country Link
US (1) US11189635B2 (zh)
JP (1) JP7443393B2 (zh)
KR (1) KR102688125B1 (zh)
CN (1) CN113632231A (zh)
WO (1) WO2020205908A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189635B2 (en) 2019-04-01 2021-11-30 Applied Materials, Inc. 3D-NAND mold
US11638377B2 (en) 2019-09-13 2023-04-25 Applied Materials, Inc. Self-aligned select gate cut for 3D NAND
US11587796B2 (en) 2020-01-23 2023-02-21 Applied Materials, Inc. 3D-NAND memory cell structure
US11114462B1 (en) * 2020-02-19 2021-09-07 Sandisk Technologies Llc Three-dimensional memory device with composite charge storage structures and methods for forming the same
US11101289B1 (en) 2020-02-19 2021-08-24 Sandisk Technologies Llc Three-dimensional memory device with composite charge storage structures and methods for forming the same
US11930637B2 (en) 2020-06-19 2024-03-12 Applied Materials, Inc. Confined charge trap layer

Citations (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070042548A1 (en) 2005-08-19 2007-02-22 Jin-Tae Noh Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed
US20110291190A1 (en) 2009-09-28 2011-12-01 Semiconductor Manufacturing International (Shanghai) Corporation System and method for integrated circuits with cylindrical gate structures
US8188445B2 (en) 2009-04-03 2012-05-29 Varian Semiconductor Equipment Associates, Inc. Ion source
US20120258600A1 (en) 2011-04-07 2012-10-11 Varian Semiconductor Equipment Associates, Inc. Method and system for post-etch treatment of patterned substrate features
US8536029B1 (en) 2012-06-21 2013-09-17 International Business Machines Corporation Nanowire FET and finFET
US20130306935A1 (en) 2011-06-15 2013-11-21 International Business Machines Corporation Double gate planar field effect transistors
US8623171B2 (en) 2009-04-03 2014-01-07 Varian Semiconductor Equipment Associates, Inc. Plasma processing apparatus
US20140034611A1 (en) 2009-04-03 2014-02-06 Varian Semiconductor Equipment Associates, Inc. Enhanced etch and deposition profile control using plasma sheath engineering
US20140175530A1 (en) 2010-06-30 2014-06-26 Sandisk Technologies Inc. Three dimensional nand device with silicide containing floating gates and method of making thereof
US20140262036A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing substrates in load lock locations
US20150041879A1 (en) * 2013-08-12 2015-02-12 Micron Technology, Inc. Semiconductor structures and methods of fabrication of same
US20150123189A1 (en) 2013-11-01 2015-05-07 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
US20150325411A1 (en) 2014-05-06 2015-11-12 Applied Materials, Inc. Directional treatment for multi-dimensional device processing
US9190498B2 (en) 2012-09-14 2015-11-17 Varian Semiconductor Equipment Associates, Inc. Technique for forming a FinFET device using selective ion implantation
US20160111513A1 (en) 2014-06-23 2016-04-21 Stmicroelectronics, Inc. Multi-channel gate-all-around fet
US20160118403A1 (en) 2014-05-13 2016-04-28 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20160190312A1 (en) 2014-12-31 2016-06-30 Stmicroelectronics, Inc. Vertical gate all-around transistor
US9385195B1 (en) 2015-03-31 2016-07-05 Stmicroelectronics, Inc. Vertical gate-all-around TFET
US20160307912A1 (en) 2014-08-26 2016-10-20 Sandisk Technologies Llc Multiheight contact via structures for a multilevel interconnect structure
US20160322381A1 (en) 2015-04-30 2016-11-03 Sandisk Technologies Inc. Multilevel memory stack structure employing support pillar structures
US20170062455A1 (en) 2015-08-28 2017-03-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US20170069637A1 (en) 2015-09-08 2017-03-09 Yong-Hoon Son Nonvolatile memory device and a method for fabricating the same
US20170278864A1 (en) 2015-05-05 2017-09-28 Semiconductor Manufacturing International (Shanghai) Corporation 3d nand device
US20180090307A1 (en) 2016-09-28 2018-03-29 International Business Machines Corporation Wafer stress control and topography compensation
US9960045B1 (en) 2017-02-02 2018-05-01 Applied Materials, Inc. Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure
US20180144977A1 (en) 2016-11-23 2018-05-24 Lam Research Corporation Staircase encapsulation in 3d nand fabrication
US10043819B1 (en) 2017-05-17 2018-08-07 Macronix International Co., Ltd. Method for manufacturing 3D NAND memory using gate replacement, and resulting structures
WO2018195423A1 (en) 2017-04-20 2018-10-25 Micromaterials Llc Structure with selective barrier layer
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10354916B2 (en) 2017-05-31 2019-07-16 Applied Materials, Inc. Methods for wordline separation in 3D-NAND devices
US10410869B2 (en) 2016-06-28 2019-09-10 Applied Materials, Inc. CVD based oxide-metal multi structure for 3D NAND memory devices
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10553604B2 (en) 2017-03-08 2020-02-04 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
US20200051994A1 (en) 2018-08-10 2020-02-13 Applied Materials, Inc. Memory device improvement
US20200118822A1 (en) 2018-10-10 2020-04-16 Applied Materials, Inc. Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation
US20200185408A1 (en) 2018-12-07 2020-06-11 Yangtze Memory Technologies Co., Ltd. Novel 3d nand memory device and method of forming the same
US20200203373A1 (en) 2018-12-20 2020-06-25 Applied Materials, Inc. Memory cell fabrication for 3d nand applications
US20200266211A1 (en) 2018-05-03 2020-08-20 Yangtze Memory Technologies Co., Ltd. Through array contact (tac) for three-dimensional memory devices
US10790298B2 (en) 2019-01-11 2020-09-29 Applied Materials, Inc. Methods and apparatus for three-dimensional NAND structure fabrication
US20200312874A1 (en) 2019-04-01 2020-10-01 Applied Materials, Inc. 3d-nand mold
US20200350014A1 (en) 2019-04-30 2020-11-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with embedded dynamic random-access memory
US20200350287A1 (en) 2019-04-30 2020-11-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with three-dimensional phase-change memory
US20200402562A1 (en) 2019-05-17 2020-12-24 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with static random-access memory
US20200411509A1 (en) 2019-06-28 2020-12-31 Yangtze Memory Technologies Co., Ltd. Computation-in-memory in three-dimensional memory device
US20210025737A1 (en) 2018-04-05 2021-01-28 Continental Automotive France Method for automatic calibration of a camshaft sensor in order to correct a reluctor runout
US20210043643A1 (en) 2017-03-08 2021-02-11 Yangtze Memory Technologies Co., Ltd. Interconnect structure of three-dimensional memory device
US10964717B2 (en) 2019-01-21 2021-03-30 Applied Materials, Inc. Methods and apparatus for three-dimensional NAND structure fabrication
US10998329B2 (en) 2019-05-23 2021-05-04 Applied Materials, Inc. Methods and apparatus for three dimensional NAND structure fabrication
US11024371B2 (en) 2019-10-12 2021-06-01 Yangtze Memory Technologies Co., Ltd. Method of programming memory device and related memory device
US11049695B2 (en) 2017-08-04 2021-06-29 Micromaterials Llc Metal contact landing structure
US20210225865A1 (en) 2020-01-17 2021-07-22 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device and fabrication method thereof
US20210233779A1 (en) 2020-01-23 2021-07-29 Applied Materials, Inc. 3D-NAND Memory Cell Structure
US20210249436A1 (en) 2017-11-16 2021-08-12 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and fabricating methods thereof
US20210257385A1 (en) 2019-08-05 2021-08-19 Micron Technology, Inc. Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias
US20210257386A1 (en) 2020-01-28 2021-08-19 Yangtze Memory Technologies Co., Ltd. Vertical memory devices
US20210257387A1 (en) 2016-04-15 2021-08-19 Micron Technology, Inc. Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102031182B1 (ko) * 2011-11-29 2019-10-14 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
US10354860B2 (en) 2015-01-29 2019-07-16 Versum Materials Us, Llc Method and precursors for manufacturing 3D devices
US9449985B1 (en) * 2015-05-26 2016-09-20 Sandisk Technologies Llc Memory cell with high-k charge trapping layer
US9812463B2 (en) * 2016-03-25 2017-11-07 Sandisk Technologies Llc Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
CN108922891B (zh) 2018-07-23 2019-12-10 长江存储科技有限责任公司 三维存储器及其制作方法
CN113345910B (zh) 2018-08-14 2024-02-27 长江存储科技有限责任公司 3d存储器中的堆叠连接件及其制造方法

Patent Citations (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070042548A1 (en) 2005-08-19 2007-02-22 Jin-Tae Noh Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed
US8623171B2 (en) 2009-04-03 2014-01-07 Varian Semiconductor Equipment Associates, Inc. Plasma processing apparatus
US8188445B2 (en) 2009-04-03 2012-05-29 Varian Semiconductor Equipment Associates, Inc. Ion source
US20140034611A1 (en) 2009-04-03 2014-02-06 Varian Semiconductor Equipment Associates, Inc. Enhanced etch and deposition profile control using plasma sheath engineering
US20110291190A1 (en) 2009-09-28 2011-12-01 Semiconductor Manufacturing International (Shanghai) Corporation System and method for integrated circuits with cylindrical gate structures
US20140175530A1 (en) 2010-06-30 2014-06-26 Sandisk Technologies Inc. Three dimensional nand device with silicide containing floating gates and method of making thereof
US20120258600A1 (en) 2011-04-07 2012-10-11 Varian Semiconductor Equipment Associates, Inc. Method and system for post-etch treatment of patterned substrate features
US20130306935A1 (en) 2011-06-15 2013-11-21 International Business Machines Corporation Double gate planar field effect transistors
US8536029B1 (en) 2012-06-21 2013-09-17 International Business Machines Corporation Nanowire FET and finFET
US9190498B2 (en) 2012-09-14 2015-11-17 Varian Semiconductor Equipment Associates, Inc. Technique for forming a FinFET device using selective ion implantation
US20140262036A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing substrates in load lock locations
US20150041879A1 (en) * 2013-08-12 2015-02-12 Micron Technology, Inc. Semiconductor structures and methods of fabrication of same
US20150123189A1 (en) 2013-11-01 2015-05-07 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
US20150325411A1 (en) 2014-05-06 2015-11-12 Applied Materials, Inc. Directional treatment for multi-dimensional device processing
US20160118403A1 (en) 2014-05-13 2016-04-28 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20160111513A1 (en) 2014-06-23 2016-04-21 Stmicroelectronics, Inc. Multi-channel gate-all-around fet
US9502518B2 (en) 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US20160307912A1 (en) 2014-08-26 2016-10-20 Sandisk Technologies Llc Multiheight contact via structures for a multilevel interconnect structure
US20160190312A1 (en) 2014-12-31 2016-06-30 Stmicroelectronics, Inc. Vertical gate all-around transistor
US9953983B2 (en) 2015-03-31 2018-04-24 Stmicroelectronics, Inc. Vertical gate-all-around TFET
US9385195B1 (en) 2015-03-31 2016-07-05 Stmicroelectronics, Inc. Vertical gate-all-around TFET
US20160322381A1 (en) 2015-04-30 2016-11-03 Sandisk Technologies Inc. Multilevel memory stack structure employing support pillar structures
US20170278864A1 (en) 2015-05-05 2017-09-28 Semiconductor Manufacturing International (Shanghai) Corporation 3d nand device
US20170062455A1 (en) 2015-08-28 2017-03-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US20170069637A1 (en) 2015-09-08 2017-03-09 Yong-Hoon Son Nonvolatile memory device and a method for fabricating the same
US20210257387A1 (en) 2016-04-15 2021-08-19 Micron Technology, Inc. Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures
US20190393042A1 (en) 2016-06-28 2019-12-26 Applied Materials, Inc. Cvd based oxide-metal multi structure for 3d nand memory devices
US10410869B2 (en) 2016-06-28 2019-09-10 Applied Materials, Inc. CVD based oxide-metal multi structure for 3D NAND memory devices
US20180090307A1 (en) 2016-09-28 2018-03-29 International Business Machines Corporation Wafer stress control and topography compensation
US20180144977A1 (en) 2016-11-23 2018-05-24 Lam Research Corporation Staircase encapsulation in 3d nand fabrication
US20180330985A1 (en) 2016-11-23 2018-11-15 Lam Research Corporation Staircase encapsulation in 3d nand fabrication
US10468259B2 (en) 2017-02-02 2019-11-05 Applied Materials, Inc. Charge-trap layer separation and word-line isolation in a 3-D NAND structure
US9960045B1 (en) 2017-02-02 2018-05-01 Applied Materials, Inc. Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure
US10325923B2 (en) 2017-02-08 2019-06-18 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10529737B2 (en) 2017-02-08 2020-01-07 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US20210043643A1 (en) 2017-03-08 2021-02-11 Yangtze Memory Technologies Co., Ltd. Interconnect structure of three-dimensional memory device
US20210126005A1 (en) 2017-03-08 2021-04-29 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
US10553604B2 (en) 2017-03-08 2020-02-04 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
WO2018195423A1 (en) 2017-04-20 2018-10-25 Micromaterials Llc Structure with selective barrier layer
US10043819B1 (en) 2017-05-17 2018-08-07 Macronix International Co., Ltd. Method for manufacturing 3D NAND memory using gate replacement, and resulting structures
US10622251B2 (en) 2017-05-31 2020-04-14 Applied Materials, Inc. Methods for wordline separation in 3D-NAND devices
US10886172B2 (en) 2017-05-31 2021-01-05 Applied Materials, Inc. Methods for wordline separation in 3D-NAND devices
US10354916B2 (en) 2017-05-31 2019-07-16 Applied Materials, Inc. Methods for wordline separation in 3D-NAND devices
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US11049695B2 (en) 2017-08-04 2021-06-29 Micromaterials Llc Metal contact landing structure
US20210249436A1 (en) 2017-11-16 2021-08-12 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and fabricating methods thereof
US20210025737A1 (en) 2018-04-05 2021-01-28 Continental Automotive France Method for automatic calibration of a camshaft sensor in order to correct a reluctor runout
US20200266211A1 (en) 2018-05-03 2020-08-20 Yangtze Memory Technologies Co., Ltd. Through array contact (tac) for three-dimensional memory devices
US20200051994A1 (en) 2018-08-10 2020-02-13 Applied Materials, Inc. Memory device improvement
US20200118822A1 (en) 2018-10-10 2020-04-16 Applied Materials, Inc. Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation
US20200185408A1 (en) 2018-12-07 2020-06-11 Yangtze Memory Technologies Co., Ltd. Novel 3d nand memory device and method of forming the same
US20210217773A1 (en) 2018-12-20 2021-07-15 Applied Materials, Inc. Memory cell fabrication for 3d nand applications
US20200203373A1 (en) 2018-12-20 2020-06-25 Applied Materials, Inc. Memory cell fabrication for 3d nand applications
US10790298B2 (en) 2019-01-11 2020-09-29 Applied Materials, Inc. Methods and apparatus for three-dimensional NAND structure fabrication
US10964717B2 (en) 2019-01-21 2021-03-30 Applied Materials, Inc. Methods and apparatus for three-dimensional NAND structure fabrication
US20200312874A1 (en) 2019-04-01 2020-10-01 Applied Materials, Inc. 3d-nand mold
US20200350014A1 (en) 2019-04-30 2020-11-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with embedded dynamic random-access memory
US20200350287A1 (en) 2019-04-30 2020-11-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with three-dimensional phase-change memory
US20210210142A1 (en) 2019-04-30 2021-07-08 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with embedded dynamic random-access memory
US20200402562A1 (en) 2019-05-17 2020-12-24 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device with static random-access memory
US10998329B2 (en) 2019-05-23 2021-05-04 Applied Materials, Inc. Methods and apparatus for three dimensional NAND structure fabrication
US20210233918A1 (en) 2019-05-23 2021-07-29 Applied Materials, Inc. Methods and apparatus for three dimensional nand structure fabrication
US20200411509A1 (en) 2019-06-28 2020-12-31 Yangtze Memory Technologies Co., Ltd. Computation-in-memory in three-dimensional memory device
US20210257385A1 (en) 2019-08-05 2021-08-19 Micron Technology, Inc. Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias
US11024371B2 (en) 2019-10-12 2021-06-01 Yangtze Memory Technologies Co., Ltd. Method of programming memory device and related memory device
US20210225865A1 (en) 2020-01-17 2021-07-22 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device and fabrication method thereof
US20210233779A1 (en) 2020-01-23 2021-07-29 Applied Materials, Inc. 3D-NAND Memory Cell Structure
US20210257386A1 (en) 2020-01-28 2021-08-19 Yangtze Memory Technologies Co., Ltd. Vertical memory devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Kataria, Himanshu , et al., "Speeding Up Silicon With Infrared Lasers", Silicon Semiconductor Magazine, Oct. 3, 2014, 22 pages.
Kongetira, Poonacha P., et al., "Modeling of Growth Rates of Selective Epitaxial Growth (SEG) and Epitaxial Lateral Overgrowth (ELO) of Silicon in the SIH2CL2—HCLH2 System", Purdue University e-Pubs, Oct. 1, 1994, pp. 1-67.
PCT International Search Report and Written Opinion in PCT/US2020/026067 dated Jul. 15, 2020, 12 pages.

Also Published As

Publication number Publication date
KR102688125B1 (ko) 2024-07-23
CN113632231A (zh) 2021-11-09
KR20210130850A (ko) 2021-11-01
WO2020205908A1 (en) 2020-10-08
US20200312874A1 (en) 2020-10-01
JP2022521842A (ja) 2022-04-12
JP7443393B2 (ja) 2024-03-05

Similar Documents

Publication Publication Date Title
US11189635B2 (en) 3D-NAND mold
US11587796B2 (en) 3D-NAND memory cell structure
US20240206172A1 (en) Confined charge trap layer
US20220367270A1 (en) Self-aligned contact and contact over active gate structures
US20220367560A1 (en) Poly-silicon based word line for 3d memory
US20220319601A1 (en) Selection gate separation for 3d nand
TWI851903B (zh) 形成電子元件的方法
US20230164993A1 (en) Nand cell structure with charge trap cut
US20240315025A1 (en) Selection gate structure and fabrication method for 3d nand
US20230040627A1 (en) Selection gate structure and fabrication method for 3d memory
US20220059555A1 (en) Selection gate separation for 3d nand

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, CHANG SEOK;KITAJIMA, TOMOHIKO;SRINIVASAN, MUKUND;AND OTHERS;SIGNING DATES FROM 20200427 TO 20200518;REEL/FRAME:052709/0243

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE