US11082061B2 - High-rate long LDPC codes - Google Patents

High-rate long LDPC codes Download PDF

Info

Publication number
US11082061B2
US11082061B2 US16/559,027 US201916559027A US11082061B2 US 11082061 B2 US11082061 B2 US 11082061B2 US 201916559027 A US201916559027 A US 201916559027A US 11082061 B2 US11082061 B2 US 11082061B2
Authority
US
United States
Prior art keywords
matrix
ldpc
rate
parity check
codeword
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/559,027
Other languages
English (en)
Other versions
US20190393890A1 (en
Inventor
Guido Montorsi
Sergio Benedetto
Yan Xin
Min Yan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Assigned to HUAWEI TECHNOLOGIES CO., LTD. reassignment HUAWEI TECHNOLOGIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAN, MIN, MONTORSI, GUIDO, BENEDETTO, SERGIO, XIN, YAN
Publication of US20190393890A1 publication Critical patent/US20190393890A1/en
Priority to US17/390,367 priority Critical patent/US11671115B2/en
Application granted granted Critical
Publication of US11082061B2 publication Critical patent/US11082061B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1157—Low-density generator matrices [LDGM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1174—Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6527—IEEE 802.11 [WLAN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Definitions

  • An LDPC encoder at a transmitter is used for encoding source words to generate codewords.
  • An LDPC decoder at a receiver is used for decoding the received codewords.
  • LDPC codes of various rates have been adopted in the IEEE 802.11ad standard and are currently proposed in respect of the developing IEEE 802.11ay standard.
  • the long LDPC codes proposed for the 7/8 LDPC code rate have a different codeword length from than the codeword lengths used for different code rates for long LDPC codes.
  • the use of different LDPC codeword length for different code rates for long LDPC codes can impact the implementation of the blocking and de-blocking processes at the transmitter and at the receiver respectively. Accordingly, it is desirable to have a codeword length that is consistent for different code rates.
  • a new high rate, long LDPC code including a rate 7/8 (1344, 1176) LDPC code that preserves the codeword length of 1344 that is used by other LDPC codes that have different code rates, so as to simplify the implementation and increase spectrum efficiency with padding fewer zeros in encoding and single carrier (SC) blocking compared to other possible solutions.
  • H I is:
  • FIG. 4A is a diagram illustrating an example single carrier frame format of 802.11ad
  • FIG. 10 illustrates a method for generating a length 1344 LDPC matrix H I of code rate 7/8 based on rate 3/4 LDPC in 802.11 according to the present disclosure
  • FIG. 14 shows an alternative lifting matrix for use in the method of FIG. 13 ;
  • FIG. 15B is a block diagram representing an example steps in a process of decoding a received signal according to one embodiment of the present disclosure
  • the present disclosure teaches methods, devices, and systems for encoding source words and decoding codewords in a wireless network. While described below primarily with respect to 802.11ay compatible networks, the present disclosure may also be applied to other blocking coding based systems.
  • [REF 1] proposes a rate 7/8 long LDPC code generated by puncturing the first 96 parity bits of the rate 13/16 LDPC codewords of length 1344 bits.
  • the AP 104 may comprise a base station (BS), evolved Node B (eNB), wireless router, or other network interface, which functions as a wireless transmission and/or reception point for STA 102 in the network 100 .
  • the AP 104 is connected to a backhaul network 110 which enables data to be exchanged between the AP 104 and other remote networks, nodes, APs, and devices (not shown).
  • the AP 104 may support communications with each STA 102 by establishing uplink and downlink communications channels with each STA 102 , as represented by the arrows in FIG. 1A . Communications in the network 100 may be unscheduled, scheduled by the AP 104 or by a scheduling or management entity (not shown) in the network 100 , or a mix of scheduled and unscheduled communications.
  • FIG. 1B illustrates an example processing system 150 , which may be used to implement methods and systems described herein, such as the STA 102 or the AP 104 .
  • the processing system 150 may be a base station, a wireless router, a mobile device, for example, or any suitable processing system.
  • Other processing systems suitable for implementing the present disclosure may be used, which may include components different from those discussed below.
  • FIG. 1B shows a single instance of each component, there may be multiple instances of each component in the processing system 150 .
  • P 1 is obtained by shifting the columns of P o to the right by one element
  • P 3 is obtained by shifting the columns of P o to the right by three elements.
  • the identity matrix P o includes Z “1”s arranged diagonally across the matrix, with all other values being “0”.
  • any non-zero value i submatrices P i in FIGS. 5B-5D can also be obtained from the respective identity matrix P o .
  • the blank entries represent Z ⁇ Z submatrices with all zero entries.
  • the lifting matrix 602 has the same number of rows and columns (3 ⁇ 16) as the rate 13/16 matrix 604 of 802.11ad.
  • Each cell element in the lifting matrix 602 is assigned one of the three possible values “1”, “0”, and “ ⁇ 1”. If a submatrix of the base matrix 604 is null (i.e. all zero entries), which is denoted as “4”, the corresponding entry in the lifting matrix 604 is also denoted as “ ⁇ 1”.
  • the entry at row 1, column 16 of the lifting matrix 604 corresponds to the submatrix at row 1, column 16 of the base matrix 602 .
  • Both the entry of the lifting matrix 604 and the submatrix of the base matrix 602 have the value of “ ⁇ 1”.
  • the corresponding entries of the lifting matrix 602 also have the value of “ ⁇ 1”. Applying the one entry with the value of “ ⁇ 1” in the lifting matrix 602 to the corresponding submatrix in the base matrix 604 generates four null submatrices.
  • the IEEE 802.11ad standard specifies an LDPC code with a high code rate of 7/8 (REF 2).
  • [REF 1] has proposed a rate 7/8 LDPC code with codeword length of 1248.
  • the rate 7/8, length 1248 LDPC code [REF 1] is generated by puncturing the first 96 parity bits from the rate 13/16 (1344, 1092) LDPC code represented by the matrix 606 shown in FIG. 6A , which as indicated above is derived from the rate 13/16 length 672 base LDPC code specified in 802.11ad.
  • a transmitter does not transmit the punctured bits, and the receiver puts equal likelihood for 1/0 for the punctured bits.
  • the proposed rate 7/8 LDPC code of FIG. 6A that is generated through puncturing results in a codeword length of 1248 rather than the codeword length of 1344 proposed for the long code, lower rate LDPC codes.
  • Every three SC data blocks (BLK 1 , BLK 2 , BLK 3 ), which each contain 448 symbols, are constructed from 2 symbol codewords (each block is constructed from 1 or 2 codewords).
  • QPSK QPSK
  • a 1248 bit codeword after modulation becomes a 624 symbol codeword.
  • the blocking process becomes more complex: every 39 data blocks are constructed from 28 codewords, and each data block is constructed from one or two codewords.
  • FIG. 7C shows examples of SC 64QAM blocking with (1344, 1176) LDPC (left side) as compared to (1248, 1092) LDPC (right side).
  • (1344, 1176) LDPC with 64QAM, one 1344 bit codeword after modulation becomes one 224 symbol codeword. Each 448 symbols data block is constructed from two 224 symbol codewords.
  • (1248, 1092) LDPC one 1248 bit codeword after modulation becomes one 208 symbol codeword.
  • the blocking process becomes more complex: every 13 data blocks are constructed from 28 codewords, and each data block is constructed from 3 or 4 codewords.
  • the rate 7/8 length 672 LPDC matrix Hn 860 in [REF 2] is derived by summing rows from the 802.11ad specified rate 3/4 length 672 (672, 504) LDPC matrix H 850 .
  • the sub-matrices from the first row R 1 and third row R 3 of base code matrix H 850 are summed to provide sub-matrices for corresponding column entries in the first row of new LDPC matrix Hn 850
  • the sub-matrices from the second row R 2 and the fourth row R 4 of base code matrix H 850 are summed using modulo-2 addition to provide sub-matrices for corresponding column entries in the second row of new LDPC matrix Hn 850 .
  • the 802.11ad specified rate 3/4 length 672 (672, 504) LDPC matrix H 850 is once again used as a base matrix, however, instead of using an extended lifting factor as discussed in the immediately preceding example, a lifting matrix 1110 is used to generate an intermediate matrix H int 1120 .
  • the lifting matrix 1110 is selected through an optimization search using criteria to yield an optimized error rate performance. In the illustrated embodiment lifting matrix 1110 is selected such that it first and third rows are complementary and its second and fourth rows are complementary.
  • the sub-matrices from the first row R 1 and fifth row R 5 of intermediate matrix H int 1120 are summed using modulo-2 addition to provide sub-matrices for corresponding column entries in the first row of new LDPC matrix H I 1130 .
  • FIG. 14 shows an example of a further optimized lifting matrix 1410 that may be used in some examples in place of lifting matrix 1310 .
  • a regular row-column interleaver is included between encoding at LDPC encoder and modulating at Bit-to-Symbol modulator 206 .
  • An LDPC encoded signal may be received at a receiver of the STA 102 or AP 104 .
  • the receiver includes an equalization and de-blocking module 1502 , a demodulator 180 , an LLR calculator 1506 , and an LDPC decoder 190 .
  • the LLR calculator 1506 can be a component of the demodulator 180 .
  • the equalization and de-blocking module 1502 first equalizes the received signal 1501 to reduce intersymbol interference caused by the channel through which the received signal is transmitted, and then de-blocks the equalized signal to recover the codewords symbols (step 1522 ).
  • FIG. 16 is an example LDPC decoder using message passing algorithm to decode the LDPC encoded source words.
  • Other decoding algorithm may also be used to implement the LDPC decoding.
  • the LDPC decoder 190 may include a controller 1602 , a check nodes module 1604 and a variable node module 1606 .
  • H n comprises a plurality of submatrices, and each submatrix has a size of Z ⁇ Z. The methods of generating the parity check matrix have been described in the encoding process.
  • each variable node 1704 sends a message (“extrinsic information”) to each check node 1702 to which the variable node 1704 is connected.
  • Each check node 1702 sends a message (“extrinsic information”) to variable nodes 1704 to which the check node 1702 is connected.
  • “Extrinsic” in this context means that the information the check nodes 1702 or variable nodes 1704 already possess is not passed to that node.
  • the cyclic shift structure simplifies the decoder architecture that allows to feed the parallel processors with a simple barrel shifter.
  • the present disclosure provides certain example algorithms and calculations for implementing examples of the disclosed methods and systems. However, the present disclosure is not bound by any particular algorithm or calculation. Although the present disclosure describes methods and processes with steps in a certain order, one or more steps of the methods and processes may be omitted or altered as appropriate. One or more steps may take place in an order other than that in which they are described, as appropriate.
  • the present invention may be implemented by using hardware only, or by using software and a necessary universal hardware platform, or by a combination of hardware and software. Based on such understandings, the technical solution of the present invention may be embodied in the form of a software product.
  • the software product may be stored in a non-volatile or non-transitory storage medium, which can be a compact disk read-only memory (CD-ROM), USB flash drive, or a hard disk.
  • the software product includes a number of instructions that enable a computer device (personal computer, server, or network device) to execute the methods provided in the embodiments of the present invention.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Dc Digital Transmission (AREA)
  • Optical Communication System (AREA)
US16/559,027 2017-03-03 2019-09-03 High-rate long LDPC codes Active US11082061B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/390,367 US11671115B2 (en) 2017-03-03 2021-07-30 High-rate long LDPC codes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/075616 WO2018157390A1 (en) 2017-03-03 2017-03-03 High-rate long ldpc codes

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/075616 Continuation WO2018157390A1 (en) 2017-03-03 2017-03-03 High-rate long ldpc codes

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/390,367 Division US11671115B2 (en) 2017-03-03 2021-07-30 High-rate long LDPC codes

Publications (2)

Publication Number Publication Date
US20190393890A1 US20190393890A1 (en) 2019-12-26
US11082061B2 true US11082061B2 (en) 2021-08-03

Family

ID=63369733

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/559,027 Active US11082061B2 (en) 2017-03-03 2019-09-03 High-rate long LDPC codes
US17/390,367 Active US11671115B2 (en) 2017-03-03 2021-07-30 High-rate long LDPC codes

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/390,367 Active US11671115B2 (en) 2017-03-03 2021-07-30 High-rate long LDPC codes

Country Status (7)

Country Link
US (2) US11082061B2 (de)
EP (2) EP3571770B1 (de)
JP (1) JP6873262B2 (de)
KR (1) KR102262186B1 (de)
CN (2) CN113676188A (de)
RU (1) RU2733826C1 (de)
WO (1) WO2018157390A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240063826A1 (en) * 2017-05-04 2024-02-22 Samsung Electronics Co., Ltd. Method and apparatus for channel encoding and decoding in communication or broadcasting system

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3588786B1 (de) 2017-06-15 2022-11-16 Huawei Technologies Co., Ltd. Qc-ldpc kodes für 3gpp 5g mobilfunk
CN118473422A (zh) * 2017-06-27 2024-08-09 华为技术有限公司 信息处理的方法、装置和通信设备
CN109150196B (zh) 2017-06-27 2024-06-18 华为技术有限公司 信息处理的方法、装置和通信设备
CN109639392B (zh) * 2018-11-09 2020-03-27 清华大学 广播信道传输的空间耦合ldpc码的构造方法及系统
CN113078911B (zh) 2020-01-03 2025-09-12 华为技术有限公司 Ldpc码的编码的方法和通信装置
CN114915297A (zh) * 2021-02-09 2022-08-16 华为技术有限公司 一种编码和译码方法及相关装置
US12191993B2 (en) 2021-03-18 2025-01-07 Qualcomm Incorporated Bit replacing for low density parity check encoding
US20250274218A1 (en) * 2024-02-28 2025-08-28 Avago Technologies International Sales Pte. Limited Multi-rate low-density parity check (ldpc) codes

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7346832B2 (en) 2004-07-21 2008-03-18 Qualcomm Incorporated LDPC encoding methods and apparatus
US20080178065A1 (en) * 2007-01-24 2008-07-24 Qualcomm Incorporated Ldpc encoding and decoding of packets of variable sizes
US20090204876A1 (en) 2006-04-28 2009-08-13 Elena Costa Method for Encoding a Data Message K' for Transmission from Sending Station to Receiving Station as Well as Method for Decoding, Sending Station, Receiving Station and Software
US20090259915A1 (en) 2004-10-12 2009-10-15 Michael Livshitz Structured low-density parity-check (ldpc) code
CN101951264A (zh) 2010-08-31 2011-01-19 宁波大学 一种多码率准循环低密度奇偶校验码解码器
JP2012505603A (ja) 2008-10-07 2012-03-01 クゥアルコム・インコーポレイテッド 高速構造化マルチレート低密度パリティチェックコードのための方法および装置
US20120084625A1 (en) 2010-08-12 2012-04-05 Samsung Electronics Co., Ltd. Apparatus and method for decoding ldpc codes in a communications system
CN102412842A (zh) 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
US8443254B2 (en) 2007-03-16 2013-05-14 Lg Electronics Inc. Method of generating a parity check matrix for LDPC encoding and decoding
US20130139024A1 (en) * 2011-11-29 2013-05-30 Thuy V. NGUYEN High order modulation protograph codes
CN104106230A (zh) 2011-07-06 2014-10-15 北京新岸线移动多媒体技术有限公司 一种用于数据传输的方法及装置
US8910025B2 (en) 2011-10-03 2014-12-09 Samsung Electronics Co., Ltd. Method and apparatus of QC-LDPC convolutional coding and low-power high throughput QC-LDPC convolutional encoder and decoder
EP2833553A1 (de) 2013-07-30 2015-02-04 Alcatel Lucent LDPC-Codierer und -Decodierer
US9160369B1 (en) 2013-03-01 2015-10-13 Proton Digital Systems, Inc. Method for iterative error correction with designed error floor performance
US20160380722A1 (en) 2015-06-25 2016-12-29 Mohamed K. Hassanin Access point (ap), user station (sta) and methods for variable length encoding and for iterative decoding

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050283707A1 (en) * 2004-06-22 2005-12-22 Eran Sharon LDPC decoder for decoding a low-density parity check (LDPC) codewords
US9100052B2 (en) * 2013-02-01 2015-08-04 Samsung Electronics Co., Ltd. QC-LDPC convolutional codes enabling low power trellis-based decoders
JP6542132B2 (ja) * 2013-02-13 2019-07-10 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計
US10523364B2 (en) * 2015-11-06 2019-12-31 Samsung Electronics Co., Ltd. Channel coding framework for 802.11AY and larger block-length LDPC codes for 11AY with 2-step lifting matrices and in-place property

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7346832B2 (en) 2004-07-21 2008-03-18 Qualcomm Incorporated LDPC encoding methods and apparatus
US20090259915A1 (en) 2004-10-12 2009-10-15 Michael Livshitz Structured low-density parity-check (ldpc) code
US20090204876A1 (en) 2006-04-28 2009-08-13 Elena Costa Method for Encoding a Data Message K' for Transmission from Sending Station to Receiving Station as Well as Method for Decoding, Sending Station, Receiving Station and Software
RU2438236C2 (ru) 2006-04-28 2011-12-27 Нокиа Сименс Нетворкс Гмбх Унд Ко. Кг Способ для кодирования сообщения k' данных для передачи от передающей станции к принимающей станции и способ для декодирования, передающая станция, принимающая станция и программное обеспечение
US8433984B2 (en) 2007-01-24 2013-04-30 Qualcomm Incorporated LDPC encoding and decoding of packets of variable sizes
US20080178065A1 (en) * 2007-01-24 2008-07-24 Qualcomm Incorporated Ldpc encoding and decoding of packets of variable sizes
KR20090113869A (ko) 2007-01-24 2009-11-02 콸콤 인코포레이티드 가변 크기들의 패킷들의 ｌｄｐｃ 인코딩 및 디코딩
US8443254B2 (en) 2007-03-16 2013-05-14 Lg Electronics Inc. Method of generating a parity check matrix for LDPC encoding and decoding
JP2012505603A (ja) 2008-10-07 2012-03-01 クゥアルコム・インコーポレイテッド 高速構造化マルチレート低密度パリティチェックコードのための方法および装置
US20120084625A1 (en) 2010-08-12 2012-04-05 Samsung Electronics Co., Ltd. Apparatus and method for decoding ldpc codes in a communications system
CN101951264A (zh) 2010-08-31 2011-01-19 宁波大学 一种多码率准循环低密度奇偶校验码解码器
CN102412842A (zh) 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
CN104106230A (zh) 2011-07-06 2014-10-15 北京新岸线移动多媒体技术有限公司 一种用于数据传输的方法及装置
CN104106230B (zh) 2011-07-06 2017-06-16 北京新岸线移动多媒体技术有限公司 一种用于数据传输的方法及装置
US8910025B2 (en) 2011-10-03 2014-12-09 Samsung Electronics Co., Ltd. Method and apparatus of QC-LDPC convolutional coding and low-power high throughput QC-LDPC convolutional encoder and decoder
US20130139024A1 (en) * 2011-11-29 2013-05-30 Thuy V. NGUYEN High order modulation protograph codes
US9160369B1 (en) 2013-03-01 2015-10-13 Proton Digital Systems, Inc. Method for iterative error correction with designed error floor performance
EP2833553A1 (de) 2013-07-30 2015-02-04 Alcatel Lucent LDPC-Codierer und -Decodierer
US20160380722A1 (en) 2015-06-25 2016-12-29 Mohamed K. Hassanin Access point (ap), user station (sta) and methods for variable length encoding and for iterative decoding

Non-Patent Citations (12)

* Cited by examiner, † Cited by third party
Title
Abu-Surra, Shadi et al. Length 1344 LDPC codes for 11ay, IEEE802.11-16/0676r1. May 2016. total 32 pages.
Andres I. Vila Casado et al, Multiple-rate low-density parity-check codes with constant blocklength, IEEE Transactions on Communications, vol. 57, No. 1, Jan. 2009, pp. 75-83.
D. Mackay, "Good Error-Correcting Codes Based on Very Sparse Matrices", IEEE Transactions on Information Theory, vol. 45, Mar. 1999, pp. 399-431 1999.
IEEE 802.11-16/1495-00-00ay-rate-7-8-ldpc-code-for-11ay 2016.
Kasher, Assaf:"Additional SC MCSs in clause 20 (DMG PHY)", IEEE802.11-16/0233r0, Feb. 2016. total 12 pages.
R. M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inform. Theory, vol. 27, pp. 533-547, Sep. 1981 1981.
Shadi Abu-Surra et al: "Length 1344 LDPC codes for 11ay", IEEE 802.11-16/0676r1, May 17, 2016 (May 17, 2016), pp. 1-32, XP055538100.
The 802 11 Working Group of the LAN/MAN Standards Committee of the IEEE Computer Society: "Draft Standard for Information Technology—Telecommunications and Information Exchange Between Systems—Local and Metropolitan Area—Networks—Specific Requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 7", IEEE Draft; Draft P802.11 AY D0.2, vol. 802.11 ay drafts, No. D0.2 Feb. 9, 2017 (Feb. 9, 2017), pp. 1-193, XP068137600, total 193 pages.
THE 802.11 WORKING GROUP OF THE: "P802.11ay™/D0.2 Draft Standard for Information Technology – Telecommunications and Information Exchange Between Systems – Local and Metropolitan Area Networks – Specific Requirements – Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications – Amendment 7: Enhanced t", IEEE DRAFT; DRAFT P802.11AY_D0.2, IEEE-SA, PISCATAWAY, NJ USA, vol. 802.11ay drafts, no. D0.2, Draft P802.11ay_D0.2, 9 February 2017 (2017-02-09), Piscataway, NJ USA, pages 1 - 193, XP068137600
Xin, Yan et al. Rate 7/8 LDPC Code for 11ay, IEEE802.11-16/1495r1, Nov. 2016. total 25 pages.
Zongwang Li et al: "Efficient encoding of quasi-cyclic low-density paritycheck codes", IEEE Transactions on Communications, IEEE Service Center, Piscataway, NJ. USA, vol. 54, No. 1, Jan. 1, 2006 (Jan. 1, 2006), pp. 71-81, XP002489550.
ZONGWANG LI, ET AL: "Efficient encoding of quasi-cyclic low-density parity-check codes", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA., vol. 54, no. 1, 1 January 2006 (2006-01-01), PISCATAWAY, NJ. USA., pages 71 - 81, XP002489550, ISSN: 0090-6778, DOI: 10.1109/TCOMM.2005.861667

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240063826A1 (en) * 2017-05-04 2024-02-22 Samsung Electronics Co., Ltd. Method and apparatus for channel encoding and decoding in communication or broadcasting system
US12176923B2 (en) * 2017-05-04 2024-12-24 Samsung Electronics Co., Ltd. Method and apparatus for channel encoding and decoding in communication or broadcasting system

Also Published As

Publication number Publication date
CN110249536A (zh) 2019-09-17
EP4373019A2 (de) 2024-05-22
EP3571770A1 (de) 2019-11-27
US20210376857A1 (en) 2021-12-02
US20190393890A1 (en) 2019-12-26
EP4373019A3 (de) 2024-07-10
KR102262186B1 (ko) 2021-06-08
JP6873262B2 (ja) 2021-05-19
CN110249536B (zh) 2021-07-20
KR20190112124A (ko) 2019-10-02
JP2020515125A (ja) 2020-05-21
WO2018157390A1 (en) 2018-09-07
US11671115B2 (en) 2023-06-06
EP3571770C0 (de) 2024-02-21
EP3571770A4 (de) 2020-06-03
RU2733826C1 (ru) 2020-10-07
CN113676188A (zh) 2021-11-19
EP3571770B1 (de) 2024-02-21

Similar Documents

Publication Publication Date Title
US10868567B2 (en) Methods and systems for encoding and decoding for LDPC codes
US11671115B2 (en) High-rate long LDPC codes
US11139835B2 (en) Method and apparatus for data processing with structured LDPC codes
US11664928B2 (en) Multi-label offset lifting method
EP3228034B1 (de) Sc-ldpc-codes für drahtloskommunikationssysteme
WO2018059588A1 (zh) 准循环ldpc编译码方法、装置及ldpc编译码器
US10868636B2 (en) MCS for long LDPC codes
US12149347B2 (en) Permutated extension and shortened low density parity check codes for hybrid automatic repeat request
US20220038115A1 (en) Method and apparatus for data processing with structured ldpc codes
JP7030932B2 (ja) Ｌｄｐｃ符号の符号化および復号化のための方法およびシステム
US20260100722A1 (en) Methods, systems, and apparatus for protograph-based low density parity check coding

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

AS Assignment

Owner name: HUAWEI TECHNOLOGIES CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MONTORSI, GUIDO;BENEDETTO, SERGIO;YAN, MIN;AND OTHERS;SIGNING DATES FROM 20191002 TO 20191016;REEL/FRAME:050879/0585

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: EX PARTE QUAYLE ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO EX PARTE QUAYLE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: AWAITING TC RESP., ISSUE FEE NOT PAID

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4