US10984745B2 - Driving method and device of display panel, and display device - Google Patents
Driving method and device of display panel, and display device Download PDFInfo
- Publication number
- US10984745B2 US10984745B2 US16/625,192 US201716625192A US10984745B2 US 10984745 B2 US10984745 B2 US 10984745B2 US 201716625192 A US201716625192 A US 201716625192A US 10984745 B2 US10984745 B2 US 10984745B2
- Authority
- US
- United States
- Prior art keywords
- pixels
- row
- edge moment
- rising edge
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0469—Details of the physics of pixel operation
- G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Definitions
- This disclosure relates to the technical field of a display panel, and more particularly to a driving method and a driving device of a display panel, and a display device.
- the thin film transistor liquid crystal display device (referred to as TFT-LCD) has become the important display platform in the modern IT and the video product.
- TFT thin film transistor
- the thin film transistor (referred to as TFT) has the phenomenon of insufficient charging time of pixels due to the too high scan frequency, and thus the poor display and picture distortion are caused.
- a main objective of this disclosure is to provide a driving method of a display panel, and aims to solve the problem that the charging time of the pixels of the display panel is insufficient, so the frame distortion is prevented and the display effect is improved.
- this disclosure provides a driving method of a display panel, comprising steps of: turning on gates of transistors of an N th row of pixels at a first rising edge moment of a clock signal; charging the N th row of pixels according to a data signal; turning on gates of transistors of an (N+1) th row of pixels before a second rising edge moment of the clock signal; and charging the (N+1) th row of pixels according to the data signal; wherein the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.
- the step of turning on gates of transistors of an (N+1) th row of pixels before a second rising edge moment of the clock signal comprises: turning on the gates of the transistors of the (N+1) th row of pixels at a falling edge moment between the first rising edge moment and the second rising edge moment.
- a time interval from the first rising edge moment to the falling edge moment is different from a time interval from the falling edge moment to the second rising edge moment.
- a duty cycle of the clock signal is unequal to 50%.
- the duty cycle of the clock signal is D, where 30% ⁇ D ⁇ 50% or 50% ⁇ D ⁇ 70%.
- a pre-charge time of even-numbered rows of pixels of the display panel is shorter than a pre-charge time of odd-numbered rows of pixels.
- a pre-charge time of even-numbered rows of pixels of the display panel is longer than a pre-charge time of odd-numbered rows of pixels.
- a polarity of the data signal is reversed periodically.
- this disclosure further provides a driving device of a display panel, comprising: a memory, a processor and a driver program of the display panel stored in the memory and run by the processor, wherein the driver program of the display panel, when being run by the processor, executes steps of: turning on gates of transistors of an N th row of pixels at a first rising edge moment of a clock signal; charging the N th row of pixels according to a data signal; turning on gates of transistors of an (N+1) th row of pixels before a second rising edge moment of the clock signal; and charging the (N+1) th row of pixels according to the data signal; wherein the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.
- the driver program of the display panel when being run by the processor, further executes steps of: turning on the gates of the transistors of the (N+1) th row of pixels at a falling edge moment between the first rising edge moment and the second rising edge moment.
- a time interval from the first rising edge moment to the falling edge moment is different from a time interval from the falling edge moment to the second rising edge moment.
- a duty cycle of the clock signal is unequal to 50%.
- the duty cycle of the clock signal is D, where 30% ⁇ D ⁇ 50% or 50% ⁇ D ⁇ 70%.
- a pre-charge time of even-numbered rows of pixels of the display panel is shorter than a pre-charge time of odd-numbered rows of pixels.
- a pre-charge time of even-numbered rows of pixels of the display panel is longer than a pre-charge time of odd-numbered rows of pixels.
- a polarity of the data signal is reversed periodically.
- this disclosure further provides a driving device, comprising: a display panel and a driving device of a display panel; the driving device of the display panel comprises a memory, a processor and a driver program of the display panel stored in the memory and run by the processor, wherein the driver program of the display panel, when being run by the processor, executes steps of: turning on gates of transistors of an N th row of pixels at a first rising edge moment of a clock signal; charging the N th row of pixels according to a data signal; turning on gates of transistors of an (N+1) th row of pixels before a second rising edge moment of the clock signal; and charging the (N+1) th row of pixels according to the data signal; wherein the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.
- the technical solution of this disclosure by turning on the gates of the transistors of the N th row of pixels at the first rising edge moment of the clock signal, charging the N th row of pixels according to the data signal, turning on the gates of the transistors of the (N+1) th row of pixels before the second rising edge moment of the clock signal, and charging the (N+1) th row of pixels according to the data signal, it is possible to implement the effect that the gates of the transistors of the (N+1) th row of pixels have been turned on and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged.
- the charging solves the problem that the charging time of the pixels of the display panel is insufficient, so the frame distortion is prevented and the display effect is improved.
- FIG. 1 is a schematic flow chart showing a first embodiment of a driving method of a display panel of this disclosure
- FIG. 2 is a schematic flow chart showing a second embodiment of the driving method of the display panel of this disclosure
- FIG. 3 is a schematic view showing a device structure of a hardware operating environment relating to the embodiment of the driving device of the display panel of this disclosure
- FIG. 4 is a schematic view showing waveforms of scan voltages of scan lines in the display panel of the second embodiment of the driving method of the display panel of this disclosure.
- FIG. 5 is a schematic view showing waveforms of scan voltages of scan lines in the display panel of a third embodiment of the driving method of the display panel of this disclosure.
- FIG. 1 is a schematic flow chart showing a first embodiment of a driving method of a display panel of this disclosure.
- the driving method of the display panel in the first embodiment of this disclosure includes the following steps.
- a step S 100 gates of transistors of an N th row of pixels are turned on at a first rising edge moment of a clock signal.
- a step S 200 the N th row of pixels are charged according to a data signal.
- the display panel is applied to the display device.
- the display panel is disposed opposite a backlight module, and the backlight module is used to provide a display light source for the display panel.
- the display panel includes a display area, a timing controller, a gate driver and a data driver.
- the display area includes multiple pixels arranged in the form of an array on the display area.
- the timing controller outputs a clock signal CLK and a gate enable signal STV to the gate driver, and the timing controller also outputs the data signal to the data driver.
- the gate driver receives the gate enable signal STV and the clock signal CLK outputted from the timing controller, and outputs control voltages of gates of transistors to a certain row of scan lines.
- the control voltages can turn on the gates of one row of transistors corresponding to the row of scan lines.
- the data driver receives the data signal outputted from the timing controller, and works in conjunction with the gate driver to output the control voltages of the gates of the transistors to a certain row of scan lines, the data signal is converted into the pixel voltage provided to one row of pixels corresponding to the row of scan lines, and the one row of pixels are charged.
- the gate driver when the gate driver receives the gate enable signal STV and the clock signal CLK outputted from the timing controller, the gate driver outputs the control voltages of gates of transistors to the N th row of scan lines at the first rising edge moment of the clock signal CLK according to the received clock signal CLK to use the control voltages to turn on the gates of the one row of transistors corresponding to the N th row of scan lines of the display area of the display panel, that is, to turn on the gates of the transistors of the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the N th row of scan lines, that is, the N th row of pixels are charged.
- a step S 300 the gates of transistors of an (N+1) th row of pixels are turned on before a second rising edge moment of the clock signal.
- a step S 400 the (N+1) th row of pixels are charged according to the data signal.
- the second rising edge moment follows after the first rising edge moment, and neighbors the first rising edge moment, where N is a positive integer. That is, the first rising edge moment and the second rising edge moment are two neighboring rising edge moments, wherein the first rising edge moment is before the second rising edge moment.
- the first rising edge moment may be the rising edge moment of the first cycle of the clock signal CLK, also may be the rising edge moment of the second cycle of the clock signal CLK, and further may be the rising edge moment of the M th cycle of the clock signal CLK.
- the second rising edge moment may be the rising edge moment of the second cycle of the clock signal CLK, may also be the rising edge moment of the third cycle of the clock signal CLK, and further may be the rising edge moment of the (M+1) th cycle of the clock signal CLK.
- the gate driver outputs the control voltages of gates of transistors to the (N+1) th row of scan lines (that is, one row of scan lines after the N th row of scan lines) to use the control voltages to turn on the gates of the one row of transistors corresponding to the (N+1) th row of scan lines of the display area of the display panel, that is, to turn on the gates of the transistors of the (N+1) th row of pixels, that is, to turn on the gates of the transistors of the one row of pixels after the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the (N+1) th row of scan lines.
- the (N+1) th row of pixels are charged, or the one row of pixels after the N th row of pixels are charged.
- the technical effect in which the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged, is achieved.
- N is a positive integer
- the pre-charge (except for initiating of the first charge of the row pixels) can be performed before any odd-numbered rows or even-numbered rows of pixels of the display area of the display panel are routinely charged every time.
- the driving method of the display panel of this disclosure by turning on the gates of the transistors of the N th row of pixels at the first rising edge moment of the clock signal, charging the N th row of pixels according to the data signal, turning on the gates of the transistors of the (N+1) th row of pixels before the second rising edge moment of the clock signal, and charging the (N+1) th row of pixels according to the data signal, it is possible to implement the effect, in which that the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged.
- the charging solves the problem that the charging time of the pixels of the display panel is insufficient, so the frame distortion is prevented and the display effect is improved.
- a second embodiment of the driving method of the display panel of this disclosure is provided based on the above-mentioned first embodiment.
- the step S 300 in this embodiment includes the following steps.
- a step S 310 gates of transistors of an (N+1) th row of pixels are turned on at the falling edge moment between the first rising edge moment and the second rising edge moment.
- the gate driver outputs the control voltages of gates of transistors to the (N+1) th row of scan lines (that is, one row of scan lines after the N th row of scan lines) to use the control voltages to turn on the gates of the one row of transistors corresponding to the (N+1) th row of scan lines of the display area of the display panel, that is, to turn on the gates of the transistors of the (N+1) th row of pixels, that is, to turn on the gates of the transistors of the one row of pixels after the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the (N+1) th row of scan lines, that is, the (N+1) th row of pixels are charged, that is, the one row of pixels after the N th row of pixels are charged.
- the technical effect in which the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged, is achieved.
- N is a positive integer
- the pre-charge (except for initiating of the first charge of the row pixels) can be performed before any one row of pixels of the display area of the display panel are routinely charged every time.
- the gate driver when the gate driver receives the gate enable signal STV and the clock signal CLK outputted from the timing controller, the gate driver outputs the control voltages of gates of transistors to the “G0” row of scan lines at the first rising edge moment of the clock signal CLK to turn on the gates of transistors of the “G0” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G0” row of pixels are charged.
- the gate driver outputs the control voltages of gates of transistors to the “G1” row of scan lines at the first falling edge moment of the clock signal CLK to turn on the gates of transistors of the “G1” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G1” row of pixels are charged.
- the gate driver stops outputting the control voltages of gates of transistors to the “G0” row of scan lines at the second rising edge moment of the clock signal CLK to turn off the gates of transistors of the “G0” row of pixels, so that the charging of the “G0” row of pixels ends.
- the gate driver outputs the control voltages of gates of transistors to the “G2” row of scan lines to turn on the gates of transistors of the “G2” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G2” row of pixels are charged.
- the technical effect in which the gates of the transistors of the “G2” row of pixels have been turned on, and the “G2” row of pixels have been charged for a certain period of time when the gates of the transistors of the “G1” row of pixels are not turned off and the “G1” row of pixels are still charged, is achieved.
- the same operations may be analogized to the N th row, and the charging processes from the “G0” row to the N th row of pixels are completed.
- a third embodiment of the driving method of the display panel of this disclosure is provided based on the above-mentioned second embodiment. As shown in FIG. 5 , the time interval from the first rising edge moment to the falling edge moment is unequal to the time interval from the falling edge moment to the second rising edge moment in this embodiment.
- the duty cycle of the clock signal is unequal to 50% (the duty cycle represents the ratio of the power-on time to the power-off time in one pulse loop).
- the ratio of the time interval from the rising edge moment of a certain cycle (pulse loop) of the clock signal CLK to its falling edge moment to the time interval from the falling edge moment to the rising edge moment of the next cycle (pulse loop) is unequal to 50%.
- the duty cycle of the clock signal is greater than 50%, so that the pre-charge times of even-numbered rows (such as “G1” row, “G3” row and the like) of pixels of the display panel are shorter than the pre-charge times of odd-numbered rows (such as “G0” row, “G2” row and the like) of pixels.
- the duty cycle of the clock signal may also be smaller than 50% in other embodiments, so that the pre-charge times of the even-numbered rows of pixels of the display panel are longer than the pre-charge times of the odd-numbered rows of pixels.
- a fourth embodiment of the driving method of the display panel of this disclosure is provided based on the above-mentioned third embodiment.
- the duty cycle of the clock signal is D, where 30% ⁇ D ⁇ 50% or 50% ⁇ D ⁇ 70%.
- the polarity of the data signal is reversed periodically.
- the overall polarization of the display panel is spatially weakened, and the dot inversion effect on the time is implemented to prevent the pixel data level in each of pixels from being kept at the same polarity for a long time, so that the display panel is affected by DC blocking effects and DC residuals, and thus the display effect of the display panel is further improved.
- This disclosure further provides a driving device of a display panel, and the driving method of the display panel is applied to the driving device of the display panel.
- the driving device of the display panel comprises a memory, a processor and a driving program of the display panel stored in the memory and executed by the processor.
- the driving program of the display panel is executed by the processor, the following steps are executed: turning on gates of transistors of an N th row of pixels at a first rising edge moment of a clock signal; charging the N th row of pixels according to a data signal; turning on gates of transistors of an (N+1) th row of pixels before a second rising edge moment of the clock signal, and charging the (N+1) th row of pixels according to the data signal.
- the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.
- the first rising edge moment and the second rising edge moment are two neighboring rising edge moments, wherein the first rising edge moment is before the second rising edge moment.
- the first rising edge moment may be the rising edge moment of the first cycle of the clock signal CLK, also may be the rising edge moment of the second cycle of the clock signal CLK, and further may be the rising edge moment of the M th cycle of the clock signal CLK.
- the second rising edge moment may be the rising edge moment of the second cycle of the clock signal CLK, may also be the rising edge moment of the third cycle of the clock signal CLK, and further may be the rising edge moment of the (M+1) th cycle of the clock signal CLK.
- the display panel is applied to the display device.
- the display panel is disposed opposite a backlight module, and the backlight module is used to provide a display light source for the display panel.
- the display panel includes a display area, a timing controller, a gate driver and a data driver.
- the display area includes multiple pixels arranged in the form of an array on the display area.
- the timing controller outputs a clock signal CLK and a gate enable signal STV to the gate driver, and the timing controller also outputs the data signal to the data driver.
- the gate driver receives the gate enabling signal STV and the clock signal CLK outputted from the timing controller, and outputs control voltages of gates of transistors to a certain row of scan lines.
- the control voltages can turn on the gates of one row of transistors corresponding to the row of scan lines.
- the data driver receives the data signal outputted from the timing controller, and works in conjunction with the gate driver to output the control voltages of the gates of the transistors to a certain row of scan lines.
- the data signal is converted into the pixel voltage provided to one row of pixels corresponding to the row of scan lines, and the one row of pixels are charged.
- the gate driver when the gate driver receives the gate enabling signal STV and the clock signal CLK outputted from the timing controller, the gate driver outputs the control voltages of gates of transistors to the N th row of scan lines at the first rising edge moment of the clock signal CLK according to the received clock signal CLK to use the control voltages to turn on the gates of the one row of transistors corresponding to the N th row of scan lines of the display area of the display panel. In other words, it is to turn on the gates of the transistors of the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the N th row of scan lines. In other words, the N th row of pixels are charged.
- the gate driver outputs the control voltages of gates of transistors to the (N+1) th row of scan lines (i.e., one row of scan lines after the N th row of scan lines) to use the control voltages to turn on the gates of the one row of transistors corresponding to the (N+1) th row of scan lines of the display area of the display panel.
- it is to turn on the gates of the transistors of the (N+1) th row of pixels, or, to turn on the gates of the transistors of the one row of pixels after the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the (N+1) th row of scan lines.
- the (N+1) th row of pixels are charged, or, the one row of pixels after the N th row of pixels are charged.
- the technical effect in which the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged, is achieved.
- N is a positive integer
- the pre-charge (except for initiating of the first charge of the row pixels) can be performed before any one row of pixels of the display area of the display panel are routinely charged every time.
- FIG. 3 is a schematic view showing a device structure of a hardware operating environment relating to the first embodiment of the driving device of the display panel of this disclosure.
- the device may include: a processor 1001 , such as a central processing unit (CPU); a network interface 1004 ; a user interface 1003 ; a memory 1005 ; and a communication bus 1002 .
- the communication bus 1002 is used to achieve the connection and communication between these elements;
- the user interface 1003 may include a display screen (or display), and an input unit such as keyboard, and the user interface 1003 may also optionally include a standard wired interface and a standard wireless interface;
- the network interface 1004 may optionally include a standard wired interface and a standard wireless interface (such as WI-FI interface);
- the memory 1005 may be a high-speed RAM memory, and may also be a non-volatile memory, such as a disk memory; and the memory 1005 may optionally be a storage device independent of the processor 1001 .
- FIG. 3 does not constitute a limitation on the above-mentioned device, and may include more or fewer components than those shown in the figures, or combine certain components, or different component arrangements may be adopted.
- the memory 1005 as a computer storage medium may include an operation system, a network communication module, a user interface module and a driver program of the display panel.
- the network interface 1004 is mainly used to connect to a background server to communicate with the background server;
- the user interface 1003 is mainly used to connect to a client to communicate data with the client;
- the processor 1001 may be used to load a driver program of the display panel stored in the memory 1005 , and execute the corresponding operation.
- the driving device of the display panel of this disclosure by turning on the gates of the transistors of the N th row of pixels at the first rising edge moment of the clock signal, charging the N th row of pixels according to the data signal, turning on the gates of the transistors of the (N+1) th row of pixels before the second rising edge moment of the clock signal, and charging the (N+1) th row of pixels according to the data signal, it is possible to implement the effect that the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged.
- the charging solves the problem that the charging time of the pixels of the display panel is insufficient, so the frame distortion is prevented and the display effect is improved.
- the following steps are further executed: turning on the gates of the transistors of the (N+1) th row of pixels at a falling edge moment between the first rising edge moment and the second rising edge moment.
- the gate driver outputs the control voltages of gates of transistors to the (N+1) th row of scan lines (that is, one row of scan lines after the N th row of scan lines) to use the control voltages to turn on the gates of the one row of transistors corresponding to the (N+1) th row of scan lines of the display area of the display panel, that is, to turn on the gates of the transistors of the (N+1) th row of pixels, that is, to turn on the gates of the transistors of the one row of pixels after the N th row of pixels.
- the data driver works in conjunction with the gate driver, and the received data signal is converted into the corresponding pixel voltage provided to one row of pixels corresponding to the (N+1) th row of scan lines.
- the (N+1) th row of pixels are charged, or, the one row of pixels after the N th row of pixels are charged.
- the technical effect in which the gates of the transistors of the (N+1) th row of pixels have been turned on, and the (N+1) th row of pixels have been charged for a certain period of time when the gates of the transistors of the N th row of pixels are not turned off and the N th row of pixels are still charged, is achieved.
- N is a positive integer
- the pre-charge (except for initiating of the first charge of the row pixels) can be performed before any one row of pixels of the display area of the display panel are routinely charged every time.
- the gate driver when the gate driver receives the gate enabling signal STV and the clock signal CLK outputted from the timing controller, the gate driver outputs the control voltages of gates of transistors to the “G0” row of scan lines at the first rising edge moment of the clock signal CLK to turn on the gates of transistors of the “G0” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G0” row of pixels are charged.
- the gate driver outputs the control voltages of gates of transistors to the “G1” row of scan lines at the first falling edge moment of the clock signal CLK to turn on the gates of transistors of the “G1” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G1” row of pixels are charged.
- the gate driver stops outputting the control voltages of gates of transistors to the “G0” row of scan lines at the second rising edge moment of the clock signal CLK to turn off the gates of transistors of the “G0” row of pixels, so that the charging of the “G0” row of pixels ends.
- the gate driver outputs the control voltages of gates of transistors to the “G2” row of scan lines to turn on the gates of transistors of the “G2” row of pixels.
- the data driver works in conjunction with the gate driver, and the “G2” row of pixels are charged.
- the technical effect in which the gates of the transistors of the “G2” row of pixels have been turned on, and the “G2” row of pixels have been charged for a certain period of time when the gates of the transistors of the “G1” row of pixels are not turned off and the “G1” row of pixels are still charged, is achieved.
- the same operations may be analogized to the N th row, and the charging processes from the “G0” row to the N th row of pixels are completed.
- the time interval from the first rising edge moment to the falling edge moment is unequal to the time interval from the falling edge moment to the second rising edge moment in this embodiment.
- the duty cycle of the clock signal is unequal to 50% (the duty cycle represents the ratio of the power-on time to the power-off time in one pulse loop).
- the ratio of the time interval from the rising edge moment of a certain cycle (pulse loop) of the clock signal CLK to its falling edge moment to the time interval from the falling edge moment to the rising edge moment of the next cycle (pulse loop) is unequal to 50%.
- the duty cycle of the clock signal is greater than 50%, so that the pre-charge times of even-numbered rows (such as “G1” row, “G3” row and the like) of pixels of the display panel are shorter than the pre-charge times of odd-numbered rows (such as “G0” row, “G2” row and the like) of pixels.
- the duty cycle of the clock signal may also be smaller than 50% in other embodiments, so that the pre-charge times of the even-numbered rows of pixels of the display panel are longer than the pre-charge times of the odd-numbered rows of pixels.
- the duty cycle of the clock signal is greater than 50%, so that the pre-charge times of even-numbered rows (such as “G1” row, “G3” row and the like) of pixels of the display panel are shorter than the pre-charge times of odd-numbered rows (such as “G0” row, “G2” row and the like) of pixels.
- the duty cycle of the clock signal may also be smaller than 50% in other embodiments, so that the pre-charge times of the even-numbered rows of pixels of the display panel are longer than the pre-charge times of the odd-numbered rows of pixels.
- the duty cycle of the clock signal is D, where 30% ⁇ D ⁇ 50% or 50% ⁇ D ⁇ 70%.
- the refresh frequency is also effectively guaranteed, the quality is also enhanced, and the better energy saving can be achieved.
- the polarity of the data signal is reversed periodically.
- the overall polarization of the display panel is spatially weakened, and the dot inversion effect on the time is implemented to prevent the pixel data level in each of pixels from being kept at the same polarity for a long time, so that the display panel is affected by DC blocking effects and DC residuals, and thus the display effect of the display panel is further improved.
- This disclosure further discloses a display device, which includes a display panel, and the driving device of the display panel as mentioned hereinabove. Because the display device adopts all the technical solutions of all the foregoing embodiments, all the beneficial effects brought by the technical solutions of the foregoing embodiments are at least obtained and are not described in detail herein.
- the terms “comprises”, “comprising”, “includes”, “including” or any other variation thereof intend to cover a non-exclusive inclusion, such that a process, method, article, article or device not only comprises those elements, but also other elements that are not explicitly listed, or further includes those inherent elements of the process, method, article or device.
- element(s) phrased by “include a” or “comprise a” does not exclude that there is/are other such element(s) existing in the process, method, article, or apparatus which already has one such element.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710497538.1 | 2017-06-26 | ||
CN201710497538.1A CN107068108B (en) | 2017-06-26 | 2017-06-26 | The driving method and device of display panel, display device |
PCT/CN2017/102425 WO2019000658A1 (en) | 2017-06-26 | 2017-09-20 | Driving method and device for display panel, and display device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200143763A1 US20200143763A1 (en) | 2020-05-07 |
US10984745B2 true US10984745B2 (en) | 2021-04-20 |
Family
ID=59613759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/625,192 Active US10984745B2 (en) | 2017-06-26 | 2017-09-20 | Driving method and device of display panel, and display device |
Country Status (3)
Country | Link |
---|---|
US (1) | US10984745B2 (en) |
CN (1) | CN107068108B (en) |
WO (1) | WO2019000658A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107068108B (en) | 2017-06-26 | 2019-06-28 | 惠科股份有限公司 | The driving method and device of display panel, display device |
CN113393797B (en) * | 2021-06-22 | 2022-11-04 | 惠科股份有限公司 | Display signal processing method, time sequence controller, display device and storage medium |
CN114203124B (en) * | 2021-11-30 | 2023-03-17 | 重庆惠科金渝光电科技有限公司 | Gate driving method, gate driving circuit and display |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040217935A1 (en) * | 2003-04-29 | 2004-11-04 | Jin Jeon | Gate driving circuit and display apparatus having the same |
US20070097057A1 (en) * | 2005-10-31 | 2007-05-03 | Shin Jung W | Liquid crystal display and driving method thereof |
US20070132673A1 (en) * | 2005-10-04 | 2007-06-14 | Yushi Jinno | Display device |
US20090040161A1 (en) * | 2007-08-07 | 2009-02-12 | Samsung Electronics Co., Ltd | Display apparatus and driving method thereof |
CN101399020A (en) | 2007-09-29 | 2009-04-01 | 北京京东方光电科技有限公司 | Drive method for pre-charging pixel by LCD device |
US20090174372A1 (en) * | 2006-05-24 | 2009-07-09 | Kazuhiro Maeda | Analog Output Circuit, Data Signal Line Driving Circuit, Display, and Potential Writing Method |
US20100164915A1 (en) | 2008-12-29 | 2010-07-01 | Hak-Gyu Kim | Gate driving circuit and display device having the gate driving circuit |
US20110228893A1 (en) | 2010-03-18 | 2011-09-22 | Mitsubishi Electric Corporation | Shift register circuit |
CN103236244A (en) | 2013-04-25 | 2013-08-07 | 深圳市华星光电技术有限公司 | Liquid crystal panel as well as method and liquid crystal display for performing voltage pre-charging on pixels of liquid crystal panel |
CN103413532A (en) | 2013-07-26 | 2013-11-27 | 京东方科技集团股份有限公司 | Pixel drive circuit, pixel drive method, array substrate and liquid display device |
CN106683630A (en) | 2016-12-29 | 2017-05-17 | 惠科股份有限公司 | Pixel charge method and pixel charge circuit |
CN107068108A (en) | 2017-06-26 | 2017-08-18 | 惠科股份有限公司 | The driving method and device of display panel, display device |
US20180012531A1 (en) * | 2016-07-07 | 2018-01-11 | Samsung Display Co., Ltd. | Method of driving display panel and display apparatus for performing the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3024397B2 (en) * | 1992-11-12 | 2000-03-21 | 日本電気株式会社 | Double edge trigger flip-flop |
CN101826311B (en) * | 2009-03-06 | 2012-08-29 | 华映视讯(吴江)有限公司 | LCD device capable of prolonging charging time and related driving method thereof |
CN105139823A (en) * | 2015-10-08 | 2015-12-09 | 友达光电股份有限公司 | Drive circuit for thin-film transistor liquid crystal display |
CN105206247B (en) * | 2015-11-05 | 2017-10-10 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and its driving method, display device |
-
2017
- 2017-06-26 CN CN201710497538.1A patent/CN107068108B/en active Active
- 2017-09-20 US US16/625,192 patent/US10984745B2/en active Active
- 2017-09-20 WO PCT/CN2017/102425 patent/WO2019000658A1/en active Application Filing
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040217935A1 (en) * | 2003-04-29 | 2004-11-04 | Jin Jeon | Gate driving circuit and display apparatus having the same |
US20070132673A1 (en) * | 2005-10-04 | 2007-06-14 | Yushi Jinno | Display device |
US20070097057A1 (en) * | 2005-10-31 | 2007-05-03 | Shin Jung W | Liquid crystal display and driving method thereof |
US20090174372A1 (en) * | 2006-05-24 | 2009-07-09 | Kazuhiro Maeda | Analog Output Circuit, Data Signal Line Driving Circuit, Display, and Potential Writing Method |
US20090040161A1 (en) * | 2007-08-07 | 2009-02-12 | Samsung Electronics Co., Ltd | Display apparatus and driving method thereof |
CN101399020A (en) | 2007-09-29 | 2009-04-01 | 北京京东方光电科技有限公司 | Drive method for pre-charging pixel by LCD device |
US20100164915A1 (en) | 2008-12-29 | 2010-07-01 | Hak-Gyu Kim | Gate driving circuit and display device having the gate driving circuit |
US20110228893A1 (en) | 2010-03-18 | 2011-09-22 | Mitsubishi Electric Corporation | Shift register circuit |
CN103236244A (en) | 2013-04-25 | 2013-08-07 | 深圳市华星光电技术有限公司 | Liquid crystal panel as well as method and liquid crystal display for performing voltage pre-charging on pixels of liquid crystal panel |
CN103413532A (en) | 2013-07-26 | 2013-11-27 | 京东方科技集团股份有限公司 | Pixel drive circuit, pixel drive method, array substrate and liquid display device |
US20180012531A1 (en) * | 2016-07-07 | 2018-01-11 | Samsung Display Co., Ltd. | Method of driving display panel and display apparatus for performing the same |
CN106683630A (en) | 2016-12-29 | 2017-05-17 | 惠科股份有限公司 | Pixel charge method and pixel charge circuit |
CN107068108A (en) | 2017-06-26 | 2017-08-18 | 惠科股份有限公司 | The driving method and device of display panel, display device |
Also Published As
Publication number | Publication date |
---|---|
WO2019000658A1 (en) | 2019-01-03 |
CN107068108B (en) | 2019-06-28 |
CN107068108A (en) | 2017-08-18 |
US20200143763A1 (en) | 2020-05-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10916213B2 (en) | Shift register and method for driving the same, gate driving circuit, and display device | |
US10332466B2 (en) | Method of driving display panel and display apparatus for performing the same | |
US10825537B2 (en) | Shift register unit, driving method, gate driving circuit and display device | |
US7403185B2 (en) | Liquid crystal display device and method of driving the same | |
US7924255B2 (en) | Gate driving method and circuit for liquid crystal display | |
US20150116308A1 (en) | Pixel driving circuit and method, array substrate and liquid crystal display apparatus | |
US20100220079A1 (en) | Liquid crystal display | |
US7893909B2 (en) | TFT LCD device and driving method with a chopper amplifier that allows offset voltage polarity interlace within one frame | |
US9030456B2 (en) | Driving device and driving method for liquid crystal display | |
WO2016155157A1 (en) | Display panel and drive method thereof, and liquid crystal display device | |
WO2018233368A1 (en) | Pixel circuit, display device, and driving method | |
US20200143763A1 (en) | Driving method and device of display panel, and display device | |
CN108319049B (en) | Liquid crystal display and driving method thereof | |
US20090085849A1 (en) | Fast Overdriving Method of LCD Panel | |
WO2017197745A1 (en) | Display panel, drive circuit thereof and drive method therefor | |
US10332471B2 (en) | Pulse generation device, array substrate, display device, drive circuit and driving method | |
JP2015018064A (en) | Display device | |
US11087707B2 (en) | Driving method and device for GOA circuit, and display device | |
US10297217B2 (en) | Liquid crystal display and the driving circuit thereof | |
CN107767837B (en) | Drive adjusting circuit, drive adjusting method and display device | |
KR101227405B1 (en) | LCD and driving unit and driving method thereof | |
US7358949B2 (en) | Liquid crystal display device pixel and drive circuit | |
KR101264703B1 (en) | LCD and drive method thereof | |
JP4198027B2 (en) | Driving method of liquid crystal display device | |
CN110544461B (en) | Driving method and driver of liquid crystal display panel and display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., CHINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, WENXIN;REEL/FRAME:051410/0054 Effective date: 20191106 Owner name: HKC CORPORATION LIMITED, CHINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, WENXIN;REEL/FRAME:051410/0054 Effective date: 20191106 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |