UA151093U - Computing unit - Google Patents

Abstract

A utility model relates to computer technology and is applicable in the creation of computer systems. The utility model improves the functionality and performance in case of failure of information processing units by reducing the system reconfiguration time delays. A block of buffer memory of unexecuted commands has been introduced into the device, as a result of which, if a computing unit fails during the execution of the command, that is, the waiting time for the execution of this command is exceeded, an unexecuted command is written to the block of the buffer memory of unexecuted commands and, regardless of the common queue available in the command generation environment, is first transferred for execution to a working computing unit.

Description

A useful model applies to computing and can be applied in the construction of high-performance computing systems.

A known computing device (1|), which contains data input and output blocks, information processing blocks, buffer memory blocks for data and commands, memory devices for control words and operands, address and data registers. The disadvantage of this device is that the output a failure of the information processing unit leads to an incorrect calculation result, because the device does not provide means to perform repeated calculations in case of incorrect execution of the command.

A known computing device (2) that includes information processing units, a data input unit, a data output unit, a data buffer memory unit, a command buffer memory unit, a data register, an address register, an operand memory unit, a memory unit memory of control words, switch, microprogram control unit, register of additional operand memory. In the event of a failure of the information processing unit, the operand of the unexecuted command is re-written to the command generation environment and transferred to a healthy information processing unit.

The disadvantage of this device is that when the information processing unit fails, only one operand is transferred to the command generation environment from the additional operand memory. It is assumed that the control word and the second operand are stored in the command generation environment until this point in time. However, this is possible only when control words and data with the same names (numbers) cannot enter the command formation environment until the given algorithm is fully completed. This limits the functionality of the device, because it does not allow algorithms to be executed in streaming mode (new calculations begin before the completion of old ones), as well as when the same calculation processes are repeated multiple times in cyclic mode (the same algorithms are implemented with different data). The impossibility of combining processes at the level of algorithms (tasks) also leads to a decrease in device performance.

The closest to a useful model in technical terms is a computing device IZ|, which contains n information processing blocks, n command registers, a data input block, a data output block, a data buffer memory block, a command buffer memory block, a data register, address register, memory block of operands, memory block of control words, n blocks of operation execution timers,

A switch, a firmware control unit, and the information input of the device is connected to the first information input of the data input unit, the output of which is connected to the first information input of the switch, the output of which is connected to the information input of the data buffer memory unit, the first information the output of which is connected to the information input of the data register, the second information output of the data buffer memory block is connected to the information input of the address register, the output of which is connected to the address input of the control word memory block and the address input of the memory block operands, the first output of the data register is connected to the information inputs of the control word memory block, the operand memory block and the first information input of the command buffer memory block, the second information input of which is connected to the information output of the operand memory block , the information output of the control word memory block is connected to the third information input of the command buffer memory block, the first output of which is connected connected to the information input of the data output block, the output of which is the output of the device, the second output of the command buffer memory block is connected to the information inputs of the information processing blocks, the information outputs of which are connected to the information inputs of the switch, the first output of the firmware control block with connected to the control input of the data input unit, the output of the data sign of which is connected to the first input of the mode of the firmware control unit, the second output of which is connected to the control input of the switch, each i-th output (1-1, ... n) of the third group of control outputs of the firmware control unit is connected to the control input of the i-th information processing unit, the signal output of which is connected to the i-th input of the second group of inputs of the firmware control unit mode, the output of the indication of the occupancy of the data buffer memory block from connected to the third mode input of the firmware control unit, the fourth output of which is connected to the control input of the data buffer memory unit, the fifth and w The eighth outputs of the firmware control unit are connected, respectively, to 3 write/read inputs of the address register and the data register, the sign output of which is connected to the fourth mode input of the firmware control unit, the seventh and eighth outputs of which are connected, respectively, to the write/read inputs of the memory block the seventh control words and operand memory block, the sign output of which is connected to the fifth mode input of the firmware control block, the ninth output of which is connected to the control input of the command buffer memory block, the sign output of which is connected to the sixth mode input of the firmware control unit, the tenth output of which is connected to the 60 control input of the output unit, the sign output of which is connected to the seventh mode input of the firmware control unit, the information outputs of the command registers are connected to the fourth information input of the buffer memory unit yati commands, the second information output of which is connected to the information inputs of each i-th command register (i-1,..., n), control inputs i which are connected to the i-th outputs of the eleventh group of control outputs of the firmware control unit, the information outputs of the operation timer blocks are connected to the fifth information input of the command buffer memory block, the third information output of which is connected to the information inputs of each of the i-th block of the operation execution timer (i-1,..., n), the control inputs of which are connected to the i-th outputs of the eighth group of control outputs of the firmware control unit, each i-th output (i-1, .. n) of the twelfth group of control outputs, which is connected to the control input of the i-th block of the command execution timer.

The advantage of this device is that in the event of failure of any computing unit, a system reconfiguration is performed, during which the unexecuted command is re-written into the buffer of ready commands, regardless of the information available in the command generation environment at the moment of time, and will be executed in a working computing unit . In the format of each command, the waiting time for the execution of this command is entered. When a command is sent to the data processing block for execution, the execution time of the command is loaded into the command execution timer block, which is started by loading the command word into the data processing block.

This makes it possible to reduce the delay time during system reconfiguration due to the failure of data processing units, due to the individual setting of operation timer units for the time required to perform each operation.

The disadvantage of this device is also unproductive spending of time on system reconfiguration during the failure of the computing unit. The unexecuted command is re-written to the command buffer memory block and put in the general queue together with other commands for transmission to the healthy information processing block. This introduces an additional time delay during system reconfiguration for the period of time the unexecuted command is in the general queue of the command buffer memory block .

The invention is based on the task of increasing the functional capabilities and productivity of the device when the information processing units fail by reducing the system reconfiguration time.

The problem is solved by the fact that in a computing device that contains n information processing blocks, n command registers, a data input block, a data output block, a data buffer memory block, a command buffer memory block, a data register, an address register, block of memory of operands, block of memory of control words, n blocks of operation execution timers, switch, block of firmware control, and the information input of the device is connected to the first information input of the data input block, the output of which is connected to the first information input of the switch , the output of which is connected to the information input of the data buffer memory block, the first information output of which is connected to the information input of the data register, the second information output of the data buffer memory block is connected to the information input of the address register, the output of which is connected to the address input of the control word memory block and the address input of the operand memory block, the first output of the data register is connected to the information inputs of the block control word memory, the operand memory block and the first information input of the command buffer memory block, the second information input of which is connected to the information output of the operand memory block, the information output of the control word memory block is connected to the third information input of the command buffer memory block, the first output of which is connected to the information input of the data output block, the output of which is the output of the device, the second output of the command buffer memory block is connected to the information inputs of information processing blocks, the information outputs of which are connected respectively to the information inputs of the switch, the first output of the firmware control unit is connected to the control input of the data input unit, the data sign output of which is connected to the first mode input of the firmware control unit, the second output of which is connected to the control input of the switch, each i-th output (i-1, ... n) of the third group of control outputs of the firmware control unit is connected to the control input and -th information processing block, the output of which signal is connected to the i-th input of the second group of inputs of the firmware control unit mode, the output of the signal of occupancy of the data buffer memory block is connected to the third input of the firmware control unit mode, the fourth output of which is connected to the control input of the data buffer memory unit, the fifth and sixth outputs of the firmware control unit are connected, respectively, to the write/read inputs of the address register and the data register, the sign output of which is connected to the fourth mode input of the firmware control unit, the seventh and the eighth outputs of which are connected respectively to the inputs of the write/read memory block of control words and the memory block of operands, the output of the sign of which is connected to the fifth input of the mode of the firmware control block, the ninth output of which is connected to the control input of the command buffer memory unit, whose characteristic output is connected to the sixth mode input of the firmware control unit, the tenth output of which is connected to the control input of the output block, the output of which is connected to the seventh mode input of the firmware control block, the second information output of the command buffer memory block is connected to the information inputs of each i-th command register (i-1,..., n) , the control inputs of which are connected to the i-th outputs of the eleventh group of control outputs of the firmware control unit, the third information output of the command buffer memory block is connected to the information inputs of each i-th block of the operation execution timer (I-1,... ., n), the control inputs of which are connected to the i-th outputs of the eighth group of control outputs of the firmware control unit, each i-th output (i-1, ... n) of the twelfth group of control outputs is connected to a control input i-th block of the command execution timer, which, according to the inventive idea, includes a buffer memory block of unexecuted commands, the first information input of which is connected to the information outputs of each i-th command register (i-1,..., n), information input and which are connected to the first information output of the buffer memory block of unexecuted commands, the second information input of which is connected to the information outputs of each i-th block of the operation execution timer (1-1,..., n), the information inputs of which connected to the second information output of the unexecuted command buffer memory block, the control input of which is connected to the eleventh output of the firmware control block, the eighth mode input of which is connected to the flag output of the unexecuted command buffer memory block.

The inventive idea is explained by graphic materials, where: in fig. 1 shows the structural diagram of the computing device; in fig. 2 presents the format of the control word; in fig. C - data word format; in fig. 4 - the algorithm for loading control words, data words and the results of command execution into the data buffer memory block; in fig. 5 - command distribution algorithm between information processing blocks.

The computing device includes a data input unit 1, the information output of which

Zo is connected to the first information input of switch 2, the output of which is connected to the information input of block Z of the data buffer memory. The control input and output of the data feature of the data input block 1 are connected to the corresponding input and output of the microprogram control block 4, the output of which is connected to the control input of the switch 2.

The control input of the Z block of the data buffer memory, which ensures the entry of information and the advancement of the queue, is connected to the output of the microprogram control block 4, the corresponding input of which is connected to the output of the signals of the Z block of the data buffer memory, which characterize the degree of its filling (" Buffer busy" and "Buffer empty"). The first and second information outputs of the Z data buffer memory block are connected to the information inputs of the data register 5 and the address register 6, respectively. The write/read inputs of the 5 data and 6 address registers are connected to the outputs of the firmware control unit 4, and the output of one bit of the data register 5 (a sign of the type of information) is connected to the corresponding input of the firmware control unit 4. The information output of the address register would be connected to the address inputs of block 7 of the operand memory and block 8 of the control word memory. The information output of the data register 5 is connected to the information inputs of block 7 of the operand memory, block 8 of the control word memory and to the first information input of the block 9 of the command buffer memory (input of the first operand). In unit 9 of the command buffer memory, a command, conventionally divided into three components (first operand, second operand, control word) is written. The second and third information inputs of block 9 of the command buffer memory are connected, respectively, to the information outputs of block 7 of operand memory (second operand) and block 8 of control word memory (control word).

The corresponding outputs of the microprogram control unit 4 are connected to the write/read inputs of the operand memory block 7 and the control word memory block 8. The output of block 4 is connected to the input of one information bit (signs of the presence of an operand) of block 7 of the operand memory, and the output of this bit is connected to the mode input of block 4. Outputs indicating the degree of filling, as well as control inputs recording and forwarding queue block 9 are connected to the corresponding inputs and outputs of block 4.

The first information output of the block 9 of the command buffer memory is connected to the information input of the data output block 13, the control input and output of the readiness indicator of which are connected to the corresponding output and input of the block 4.

The second information output of the block 9 of the command buffer memory is connected to 60 information inputs of the information processing blocks 10.1,..., 10.n and to the information inputs of the command registers 11.1,..., 11.n, the control inputs of which are connected to by the corresponding group of control outputs of block 4 of the firmware control.

The third information output of the block 9 of the command buffer memory is connected to the information inputs of the operation timer blocks 12.1,..., 12.n, the control inputs of which are connected to the corresponding group of control outputs of the block 4 of the firmware control.

Groups of control inputs and outputs of the microprogram control unit 4 are connected to the corresponding outputs and inputs of the information processing units 10.1,..., 10.n, the information outputs of which are connected to the information inputs of the switch 2.

The outputs of the command registers 11.1,..., 11.p are connected to the first information input of the block 16 of the buffer memory of unexecuted commands, the first information output of which is connected to the information inputs of the command registers 11.1,..., 11.p.

The information outputs of the operation timer blocks 12.1-42.p are connected to the second information input of block 16 of the buffer memory of unexecuted commands, the second information output of which is connected to the information inputs of the operation timer blocks 12.1 - 12.p.

The control input of block 16 of the buffer memory of unexecuted commands, which ensures the entry of information and the advancement of the queue of unexecuted commands, is connected to the output of block 4 of the firmware control, the corresponding input of which is connected to the output of the signals of block 16 of the buffer memory of unexecuted commands characterizing the degree its filling ("Buffer busy" and "Buffer empty").

The information input of the data input unit 1 is connected to the information input 14 of the device, the information output 15 of which is connected to the information output of the data output unit 13.

Any storage device operating on the first-in-first-out basis can be used to implement block C of the data buffer memory, block 9 of the command buffer memory, and block 16 of the buffer memory of unexecuted commands. .

For each of the blocks 10.1,..., 10.n of information processing, a timer is used that generates a signal corresponding to the time interval yg.

The computing device works as follows. The output information for calculations comes from the information input 14 of the device through the data input unit 1 and is a sequence of control words and data words. The control word whose format is represented

Zo in Fig. 2 contains a d-bit field of the operation code, a bit of the number of the operand to be calculated, a 5-bit field of the number of the next operation, a bit of the sign of the type of information, a t-bit field of the operation number (where ad, 5, t are natural numbers ). The control word contains the field T for waiting time for the result of a specific operation.

The information type flag bit for all control words has the value "1". Information that

C5 is written in other fields of the control word, determined by the given graph of the calculation algorithm, which is built regardless of the number n of information processing blocks.

The length of the 4 field of the operation code (Fig. 2) is determined by the number of M commands and must include at least Iov» M digits. Bit size t should ensure the possibility of recording the largest operation number, and bit size 5 - either the maximum number or the maximum difference in the number of operations by the modulus. The bit rate of the operand value field (Fig. 3) depends on the form and accuracy of the representation of the operands. This field can include sign digits, mantissa, and order.

In the initial state, blocks Z of the data buffer memory, 9 of the command buffer memory, and 16 of the unexecuted command buffer memory are empty (the "Buffer empty" signals are generated). Chains for setting the initial state are conditionally not shown. During the operation of the device, the following processes can be distinguished: input into the data buffer memory block of information from data input block 1 and from information processing blocks 10.1,...,10.p (in the case of proper operation of blocks 10.1,...,10 .n); forming a command and entering it into block 9 of the command buffer memory (in case of proper operation of blocks 10.1,...,10.p) and into block 16 of the buffer memory of unexecuted commands (in case of faulty operation of blocks 10.1,... , 10.p); distribution of commands between blocks 10.1,...,10...n of information processing (for further processing) and block 13 of data output.

Consider the operation of the device in the case when there are no failures of information blocks.

The first of these processes is illustrated by the algorithm in Fig. 4. Unit 4 analyzes the signal "Data buffer is full" of the Z block of the data buffer memory. In the absence of the specified signal, when information can be written to the Z data buffer memory block, block 4 checks the signal at the output of the data sign of the data input block 1 and the signals at the outputs of the sign of the completion of the operation of the information processing blocks 10.1,..., 10.p. The presence of the first of these signals indicates that the data input unit 1 received data from the information input 14 of the device. In this case, according to the control signals of block 4 of the microprogram control, information from block 1 is written to block 3 through switch 2. In a similar way, writing to block C from block 10 takes place.| in the case of its readiness to transfer data, that is, the readiness of the result. In the latter case, the "Result accepted" signal is sent to block 10. of information processing from block 4 of the firmware control, and block 10.) removes the signal indicating the completion of the operation. If block C is not ready for writing (full), then waiting for the moment when writing will be possible is performed (the "Data buffer full" signal will disappear).

If block 10.| processing of information does not signal the completion of the operation, then block 4 of the firmware control checks for the presence of a signal of the end of the command execution time from block 12 of the operation execution timer ("Time Out" signal), the timer is set to the time for which the result must be obtained , if unit 10.) has not failed. When block 10.| information processing works correctly, that is, the signal from the timer 12.| absent, the operation completion signal is checked in the next block 10.1) of information processing.

In the process of entering the output information from the data input block 1, first the control word is entered, and then the data word for the corresponding operation. The team formation process is carried out in the following way. The control word is written in block 8 of control words at the address corresponding to the operation number. The first of the incoming data words for this operation is written at the same address in block 7 of the operand memory. Next, the control word and one of the operands wait for the data of the missing operand to arrive from block 3, after which the command is composed. The command contains a control word, two operands, an operation number and is written in block 9 (in the queue for execution), and the operation number is written from register 6.

The team formation algorithm is as follows. Block 4 of the microprogram control analyzes the "Buffer empty" signal of the Z block of the data buffer memory. In the absence of the indicated signal (there is at least one word in the block), the word from its output is written into the address 6 and data registers 5, and the field of the operation number is written into the register 6 (see Fig. 2 and Fig. 3). Block 4 checks in the data register 5 the sign of the type of information, which has a single value for the control words and zero for the data word. If the sign of the information type is "1", then the control word is written in block 8. At the same time, in block 7, "1" is written in the digit of the presence sign

From the operand (this means that there is no operand for this control word in block 7).

The content of the register 6 is the address in the process of writing for the memory blocks of operands 7 and control words 8.

In block 8, data is written from register 5, in block 7, a single value is sent to the input of the bit indicating the presence of an operand from block 4 of the microprogram control.

If in register 5 the sign of the information type is equal to "0" (the word is data), the sign of the presence of an operand in block 7 of the operand memory is checked. To do this, blocks 7 and 8 are read and the sign of the presence of an operand is analyzed. If this sign is equal to "1" (there is no operand for this control word in block 7 of the operand memory), a word from register 5 is written to block 7. At the same time, a "0" is written to the sign of the presence of an operand (there is one operand for this operation ). If the operand presence sign is "0" and there is no "Buffer full" signal, the command is ready to be executed (the control word from block 8 of the control word memory, one operand from block 7, the second operand from data register 5 and the operation number from register 6 ) are recorded in block 9 of the command buffer memory. The bit of the indication of the presence of the operand in block 7 is set to "1".

If there is at least one command in block 9 (there is no "Buffer empty" signal), then block 4 analyzes the command type field at the outputs of block 9 and ensures the transfer of the command to the data output block 13 or to one of the information processing blocks 10.1. If the command has a computational nature (addition, multiplication, etc.), transfer it to block 10.). is carried out according to the algorithm shown in fig. 5. Unit 10 is ready to receive the command.| of information processing issues the "Command reception readiness" signal to unit 4. The specified signal is generated only after checking the functionality of the block by built-in control circuits or a test. Block 4 in turn analyzes the readiness of each information processing block 10.1,..., 10.p, capable of executing this command.

Block 4 transmits the ready block 10.) control signal "Accept the command". The command from block 9 of the command buffer memory is transferred to block 10.| information processing. At the same time, according to the corresponding signals of block 4 of the microprogram control, the command from block 9 is written into the command register 11., and the corresponding execution time of the command from the control word field is written into block 12.| operation execution timer. Next, block 10.) resets the "Ready to receive command" signal and starts executing its command. After the removal of the signal "Ready to receive the command", unit 4 of the firmware control produces the signal "Advance the queue" for the unit 9 of the command buffer memory. The described team formation process is repeated cyclically.

In the process of command processing, each block 10.| information processing unit exchanges two input and two output control signals with block 4 of the microprogram control.

One pair of signals (input and output) is used to input the command, and the other is used to output the result after the command is executed. Operands that do not have meaningful value are not processed in blocks 10.1,...,10.p.

During the operation of the computing device, failures may occur in the operation of one or more information processing units. Failures can occur after the "Ready to receive command" signal is set or after it is removed. In both cases, it is necessary to repeat the command that should have been executed or was executed in the faulty information processing unit.

Let's consider the case when the information processing unit 10 does not remove the signal "Ready to receive the command", that is, it failed before the execution of the command began. As can be seen from the algorithm in Fig. 5, block 4 of the microprogram control analyzes whether the "Command reception readiness" signal is removed during the IR time interval. Its time is selected in such a way that during the given time interval, the information processing unit, when functioning correctly, will necessarily accept the command and remove the "Command reception readiness" signal ". If at the end of the time it did not happen, then block 4 of the microprogram control repeats the procedure of transmitting the command to the next (ii-1) block of information processing.

Thus, if there is at least one viable unit, then the command will be transferred to it.

Consider the second case, when block 10.| fails after the signal "Ready to receive command" is removed. In this case, the timer implemented in block 12.) of the operation execution timer is used, configured individually for the execution time Ti of each individual operation. The timer in unit 12.) is started by the signal for recording the execution time of the corresponding command, which comes from the control unit 4 with a delay of yg time. When reading the result of the operation (Fig. 4), block 4 of the microprogram control in turn checks the signal "Ready to issue the result" in each block 10.i, and in its absence checks the signal "Time out" in each block 12.), which signals the end time Ti, which was allocated to perform this operation.

If the signal "Ready to issue the result" is generated during the time interval Ti, then the result is considered correct and is recorded in the Z block of the data buffer memory. If after finishing

Since block 10.) has not set the signal "Ready to issue a result", the command is recorded in block 16 of the buffer memory of unexecuted commands from the command register 11.) taking into account the state of the buffer. As a result, the unexecuted command is recorded in block 16 of the buffer memory of unexecuted commands and will be transferred to a valid information processing block. The command is written using the signal "Write from the command register 11.) to block 16", which comes from block 4 of the microprogram control to the control input of the corresponding command register 11...

If there is at least one command in block 16 (there is no "Buffer empty" signal), then block 4 ensures the priority transfer of an unexecuted command from block 16 to one of the information processing blocks 10.) similar to the process of command transfer from block 9.

In the proposed device, upon the failure of any computing unit, system reconfiguration is performed, during which the unexecuted command is re-written into an additional buffer of unexecuted commands, regardless of the information available in the environment of command formation at the moment of time, and will be executed first in a working computing unit.

This makes it possible to reduce the delay time during system reconfiguration in case of failure of data processing units due to the fact that an unexecuted command is not placed in the general queue of command execution, but is primarily transferred to a working computing unit.

This, in turn, provides a reduction in the time of information conversion, that is, in general, an increase in the performance of the device.

Thus, the set task is to increase the functional capabilities (and productivity of the device by reducing the delay time during system reconfiguration due to equipment failures, which is achieved with the help of the proposed technical solution.

Sources of information: 1. Pat. on the image Mo. 2030785 USSR, MKV SObE 15/16. Computing device / V.I.

Zhabin, G.V. Honcharenko, V.V. Makarov, V.V. Tkachenko (Ukraine) - Mo 4867678: Reported on 09/21/1990; Publ. 10.03.1995. - 23 p. 2. Dec. stalemate. Mo 7727 of Ukraine, MKV SObE 15/16, 15/76. Computing device / I.A. Zhukov,

V.I. Zhabin, I.A. Klymenko, V.V. Tkachenko (Ukraine) - Mo 20040907712: Reported on September 22, 2004;

Publ. 15.07.2005, Bull. Mo. 7. - 9 p.m.

Z. Pat. on the cor. fashion Mo 59112 of Ukraine, IPC SObE 15/16. Computing device / I.A.

Klymenko, V.V. Zhabina (Ukraine) - Mo y 201009793: Reported on 06.08.2010; Publ. 10.05.2011,

Bul. Me 7. - 9 p.

Claims (1)

USEFUL MODEL FORMULA A computing device containing n information processing blocks, n command registers, a data input block, a data output block, a data buffer memory block, a command buffer memory block, a data register, an address register, an operand memory block , memory block of control words, n blocks of operation execution timers, a switch, a firmware control block, and the information input of the device is connected to the first information input of the data input block, the output of which is connected to the first information input of the switch, the output of which is connected to the information input of the data buffer memory unit, the first information output of which is connected to the information input of the data register, the second information output of the data buffer memory unit is connected to the information input of the address register, the output of which is connected to the address input of the control word memory block and the address input of the operand memory block, the first output of the data register is connected to the information inputs of the control memory block left, the operand memory block and the first information input of the command buffer memory block, the second information input of which is connected to the information output of the operand memory block, the information output of the control word memory block is connected to the third information input of the block command buffer memory, the first output of which is connected to the information input of the data output unit, the output of which is the output of the device, the second output of the command buffer memory unit is connected to the information inputs of the information processing units, the information outputs of which are connected respectively with the information inputs of the switch, the first output of the firmware control unit is connected to the control input of the data input unit, the output of the data sign of which is connected to the first mode input of the firmware control unit, the second output of which is connected to the control input of the switch, each the output (i-1, ... n) of the third group of control outputs of the firmware control unit is connected to the control input of the ith information processing unit rmation, the signal output of which is connected to the i-th input of the second group of inputs of the Zo mode of the firmware control unit, the output of the indication of the occupancy of the data buffer memory block is connected to the third input of the mode of the firmware control unit, the fourth output of which is connected to the controller the input of the data buffer memory unit, the fifth and sixth outputs of the firmware control unit are connected, respectively, to 3 write/read inputs of the address register and the data register, the sign output of which is connected to the fourth mode input of the firmware control unit, the seventh and eighth outputs which are connected, respectively, to the write/read inputs of the control word memory block and the operand memory block, the sign output of which is connected to the fifth mode input of the firmware control block, the ninth output of which is connected to the control input command buffer memory block, the sign output of which is connected to the sixth mode input of the firmware control block, the tenth output of which is connected to the control input of the output block, whose sign output is connected to the seventh mode input of the firmware control unit, the second information output of the command buffer memory block is connected to the information inputs of each i-th command register (1-1, ..., n), the control inputs of which connected to the i-th outputs of the eleventh group of control outputs of the firmware control unit, the third information output of the command buffer memory block is connected to the information inputs of each i-th block of the operation execution timer (1-1, ..., n) , the control inputs of which are connected to the i-th outputs of the eighth group of control outputs of the firmware control unit, each i-th output (i-1, ... 7) of the twelfth group of control outputs is connected to the control input of the i-th block command execution timer, which differs in that the device includes a block of buffer memory for unexecuted commands, the first information input of which is connected to the information outputs of each i-th command register (i-1, ..., n), information the inputs of which are connected to the per th information output of the buffer memory block of unexecuted commands, the second information input of which is connected to the information outputs of each i-th block of the operation execution timer (i-1,..., n), the information inputs of which are connected to the second information input by the output of the buffer memory block of unexecuted commands, the control input of which is connected to the eleventh output of the firmware control block, the eighth mode input of which is connected to the output of the sign of the buffer memory block of unexecuted commands.