UA103956U - Generator of periodic sequence of three-pulse code groups with programmable number of pulses, programmable gap between pulses in a group and between groups - Google Patents

Abstract

A generator of periodic sequence of three-pulse code groups with programmable number of pulses, programmable gap between pulses in a group and between groups contains two reversible binary counters, each of which has an input feed clock pulses, the input to the debug mode of addition/subtraction , the enable input synchronous parallel load and inlet flow data, the enable input of the counting mode, the input of asynchronous setting to zero state, the output of the overflow; the first and second elements OR, and inverter; chain, consisting of series-connected resistor and capacitor; a synchronous D-trigger with the input of asynchronous setting to zero state, the first and second two-input AND elements. introduced: the third reversible binary counter which has an input feed clock pulses, the input to the debug mode of addition / subtraction, the enable input synchronous parallel load and inlet flow data , the enable input of the counting mode, the input of asynchronous setting to zero state, the output of the overflow; decoder; third, fourth and fifth OR elements, the second inverter; element AND-NOT, one input of which is connected to the output of the overflow of the second counter, the inputs of the second and third elements OR, the enable input of the counting mode of the third counter; a second input element AND-NOT connected to the output of the first inverter; a second input of the third element OR is connected to the output of the overflow of the third counter, the input of the first element OR the input of the second inverter, whose output is connected to the second input of the second OR element; the output of the third OR element with inputs permit the boot mode of the third counter; the output of element AND-NOT connected to the enable input of the counting mode of the second counter; inputs load data D0D1D2D3 third counter form inputs b0b1b2b3 changeover of the driver by a predetermined number of pulses in the series; the outputs of the third counter connected to the inputs of four-core decoder with 16 outputs (Y0-Y15) V2 × output connected to the first input of the fifth OR element; output Υ3 is connected to a first input of the fourth element OR and the download data input D2 of the first counter; the output Y4 is connected to other inputs of the fourth and fifth OR elements; the output of the fourth OR element is connected to the input of the load data D0 of the first counter; the output of the fifth OR element is connected to the input load data D3 of the first counter; input of download data D1 of the first counter connected to the logic 0 level; the input of asynchronous setting to zero state of the third counter connected to the output of the second And element; the clock input of the third counter connected to the input of the generator.