TWM656978U - Current balancing circuit and multi-phase voltage regulator circuit - Google Patents

Abstract

A multi-phase voltage regulator circuit applied in a multi-phase DC-DC converter is provided. The multi-phase voltage regulator circuit includes a plurality of comparison circuits. The comparison circuit is coupled to a power output stage circuit of the multi-phase DC-DC converter and is configured to generate a plurality of control signals so that the power output stage circuit generates a plurality of output currents. Each of the comparison circuits includes a comparator, and the comparator is configured to receive a compensation signal and a reference signal. The comparator receives a correction signal through a correction terminal to adjust a duty cycle of the corresponding control signal according to the correction signal. The correction signal for each phase is generated according to an error current for the corresponding phase, which represents the difference between a current threshold value and the output current for the corresponding phase.

Description

Current balancing circuit and multi-phase voltage regulator circuit

The present disclosure relates to current balancing technology, and more particularly to a current balancing circuit and a multi-phase regulator circuit.

A DC-to-DC converter is an electromechanical device used for power conversion, which is used to convert the voltage of a DC power source. DC-to-DC converters are widely used and can be used to supply power to low-power devices (such as batteries) or high-power devices (such as industrial machines). Among them, a multi-phase DC-to-DC converter includes multiple converters with different phases to output power to the output end in turn. Whether the output power between the converters of each phase is consistent will affect the power supply stability of the DC-to-DC converter. Therefore, there is a real need for a novel DC-to-DC converter to provide better power supply stability.

The present disclosure relates to a multi-phase voltage regulator circuit, which is applied to a multi-phase DC-DC converter and includes a plurality of comparator circuits. The comparator circuit is coupled to the power output stage circuit of the multi-phase DC-DC converter and is used to generate a plurality of control signals so that the power output stage circuit generates a plurality of output currents. One of the comparator circuits includes a comparator, which is used to receive a compensation signal and a reference signal. The comparator also receives a correction signal through a correction terminal to adjust the duty cycle of a corresponding one of the control signals according to the correction signal. The correction signal is generated based on an error current, which is the difference between a current threshold and an output current.

The present disclosure also relates to a current balancing circuit, which is applied to a multi-phase DC-DC converter, and includes a current detection circuit and a comparison circuit. The current detection circuit is coupled to a power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents and to calculate the average current of the output currents. The comparison circuit is coupled to the current detection circuit and is used to compare a compensation signal and a reference signal to output a control signal so that the power output stage circuit is used to adjust the first output current among the output currents. The comparison circuit is also used to use the difference between the average current and the first output current as a correction signal to adjust the duty cycle of the control signal according to the correction signal.

Accordingly, by generating a correction signal according to the error current and inputting the correction signal to the correction terminal of the comparator, the duty cycle of the control signal can be adjusted in real time to achieve balanced control of each phase current. In addition, since the present disclosure does not require a compensation signal, it does not require a complex circuit, nor does it require changing the operation mode of the multi-phase DC-DC converter, and can be easily applied and implemented.

The following will disclose multiple implementations of the present invention with diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the present invention, these practical details are not necessary. In addition, in order to simplify the diagrams, some commonly used structures and components will be depicted in the diagrams in a simple schematic manner.

In this article, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish between elements or operations described with the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit this creation.

The present disclosure is about a multi-phase DC-DC converter for converting input voltage to output different output voltages. In one embodiment, the multi-phase DC-DC converter is applied to a vehicle power source, for example, as a power transmission circuit, which can store power from a charging station into a battery, or provide the stored power of the battery to in-vehicle equipment. However, the present disclosure is not limited to this, and in other embodiments, the multi-phase DC-DC converter can also be applied to other devices and loads.

FIG. 1 is a schematic diagram of a multi-phase DC-DC converter 100 according to some embodiments of the present disclosure. The multi-phase DC-DC converter 100 includes a power output stage circuit 110, a current balancing circuit 120, and a compensation circuit 130. The power output stage circuit 110 includes a plurality of driving circuits DC and a switching circuit 111 formed by a plurality of transistor switches, wherein each driving circuit DC and the corresponding switching circuit 111 are used to generate a corresponding output current Is1 to Isn according to an input voltage Vin.

In the embodiment shown in FIG. 1, the power output stage circuit 110 includes a plurality of sub-circuits (e.g., two or more), each sub-circuit includes a driving circuit DC, and the switch circuit 111 includes an upper bridge switch Ta and a lower bridge switch Tb, and is coupled to the input voltage Vin. The driving circuit DC is used to control the upper bridge switch Ta and the lower bridge switch Tb to be turned on or off according to the received control signal to generate or adjust the corresponding output current Is1~Isn. The phases of the output currents Is1~Isn generated by each sub-circuit are different from each other. For example, when the power output stage circuit 110 includes a plurality of sub-circuits, there is a corresponding phase difference between the output currents Is1~Isn of each sub-circuit.

In one embodiment, the power output stage circuit 110 generates an output voltage Vout and a feedback voltage Vfb through an energy storage circuit 140 and a voltage divider circuit 150. The energy storage circuit 140 is coupled to the power output stage circuit 110 and includes a plurality of inductors L1-Ln and an output capacitor Cout. The voltage divider circuit 150 includes a plurality of voltage divider resistors R1 and R2. Since those skilled in the art can understand the method by which the power output stage circuit 110 generates the output voltage Vout, further details are not described here.

The current balancing circuit 120 is coupled to the power output stage circuit 110 and includes a plurality of comparison circuits 200. Each comparison circuit 200 is used to generate a control signal Spwm1-Spwmn corresponding to the output current Is1-Isn of the corresponding phase, so as to provide the control signal Spwm1-Spwmn to each driving circuit DC. The generation method of the control signal will be described in detail in the following paragraphs.

The compensation circuit 130 is coupled to the power output stage circuit 110 and the current balancing circuit 120 respectively to receive the feedback voltage Vfb from the power output stage circuit 110. In one embodiment, the feedback voltage Vfb is the voltage value of the output voltage Vout at the output end after being divided by the voltage dividing resistors R1 and R2. The compensation circuit 130 is also used to compare the feedback voltage Vfb with the reference voltage Vref to generate a compensation signal Vcomp according to the difference between the feedback voltage Vfb and the reference voltage Vref. The reference voltage Vref may be a fixed voltage value, and therefore, the compensation signal Vcomp is used to reflect the current state of the output voltage Vout (e.g., heavy load or light load state). The compensation signal Vcomp will be provided to the current balancing circuit 120, and the current balancing circuit 120 will generate control signals Spwm1-Spwmn to the driving circuit DC according to the compensation signal Vcomp.

As mentioned above, in one embodiment, the positive terminal of the compensation circuit 130 is used to receive the reference voltage Vref, and the negative terminal of the compensation circuit 130 is used to receive the feedback voltage Vfb. Therefore, the magnitude of the compensation signal Vcomp is positively correlated with the “difference between the reference voltage Vref and the feedback voltage Vfb”. However, the present disclosure is not limited thereto. In other embodiments, the signals received by the positive and negative terminals of the compensation circuit 130 can be interchanged according to the actual circuit design.

One embodiment of the present disclosure is to set up multiple comparison circuits 200 in the current balancing circuit 120 to adjust the control signals Spwm1~Spwmn provided to the power output stage circuit 110 in real time according to the power supply status of the multi-phase DC-DC converter 100 (such as: according to the compensation signal Vcomp and/or the output current) to ensure that the current of each phase output by the multi-phase DC-DC converter 100 can be maintained balanced (that is, the output power of each phase can be maintained substantially equal).

For ease of explanation, the multiple comparison circuits 200 in the multi-phase DC-DC converter 100 are collectively referred to as a multi-phase regulator circuit 122. The multi-phase regulator circuit 122 is used to generate and adjust a plurality of control signals Spwm1-Spwmn corresponding to different phases, so that the power output stage circuit 110 generates a plurality of output currents Is1-Isn of different phases, thereby keeping the currents of each phase balanced.

In some embodiments, the control signals Spwm1-Spwmn generated by each comparison circuit 200 are pulse-width modulation (PWM) signals, and the control signals Spwm1-Spwmn are provided to the driving circuit DC through the logic circuit CL. In addition, the comparison circuit 200 can also adjust the duty ratio (also known as the duty cycle) of the control signals Spwm1-Spwmn, thereby changing the output current Is1-Isn generated by the power output stage circuit 110. Since those skilled in the art can understand the way in which the logic circuit CL and the driving circuit DC transmit control signals using digital signals, it will not be further described here.

In some embodiments, the reference signals VR1-VRn may be a periodic signal whose signal size changes periodically within a time period. In other embodiments, the reference signals VR1-VRn may be a sawtooth wave with a fixed slope in the signal cycle. "Sawtooth wave" means that in each signal cycle, it will change from a fixed level (such as rising or falling), and when the current signal cycle ends and enters the next signal cycle, it will return to the original fixed level. In some embodiments, the signal slope of the ramp signal Vramp is positive, that is, in the signal cycle, the level of the ramp signal Vramp gradually increases. However, the present disclosure is not limited thereto, and in other embodiments, the ramp signal Vramp may also be a triangular wave according to different slopes. In addition, the phases of the reference signals VR1-VRn are also different to generate control signals Spwm1-Spwmn of different phases.

Here, the method of generating the control signals Spwm1-Spwmn by the comparison circuit 200 is described. As shown in FIG. 1 , in one embodiment, each comparison circuit 200 is coupled between the compensation circuit 130 and the power output stage circuit 110, and includes a comparator 210. The multiple input terminals of the comparator 210 are respectively used to receive the compensation signal Vcomp and the reference signals VR1-VRn, so as to generate the control signals Spwm1-Spwmn according to the relative relationship between the compensation signal Vcomp and the corresponding reference signal. The output of the comparator 210 is converted into control signals Spwm1-Spwmn through the logic circuit CL to be transmitted to the power output stage circuit 110, but in some embodiments of the present disclosure, the logic circuit CL can be omitted. In one embodiment, the positive input terminal of the comparator 210 is used to receive the compensation signal Vcomp, and the negative input terminal of the comparator 210 is used to receive the corresponding reference signal (one of the reference signals VR1-VRn, such as the reference signal VR1 shown in the figure), but the present disclosure is not limited to this.

Specifically, the comparison circuit 200 can adjust the corresponding control signal to a high level when the compensation signal Vcomp is greater than the corresponding reference signal, and adjust the corresponding control signal to a low level when the compensation signal Vcomp is less than the corresponding reference signal. Since the compensation signal Vcomp reflects the state of the output voltage Vout, when the compensation signal Vcomp changes, the comparison circuit 200 can instantly adjust the duty cycle of the corresponding control signal to change the output current and thus change the output voltage Vout.

For example, when the output voltage Vout is too large, the feedback voltage Vfb also increases, making the difference between the reference voltage Vref and the feedback voltage Vfb smaller, causing the compensation signal Vcomp to decrease.

As mentioned above, the comparison circuit 200 is used to compare the compensation signal Vcomp with the corresponding reference signal (i.e., the corresponding one of the reference signals VR1 to VRn) to generate the corresponding one of the control signals Spwm1 to Spwmn, and then adjust the corresponding output current. However, since the compensation signal Vcomp only reflects the overall load level of the multi-phase DC-DC converter 100, and does not reflect the "difference between the output currents of different phases", the comparator 210 of the comparison circuit 200 of this embodiment will also receive the corresponding correction signals Sc1 to Scn through the correction terminal, and adjust/correct the duty cycle of the generated control signal according to the corresponding correction signals Sc1 to Scn.

The correction signals Sc1~Scn are generated based on the error currents Idiff1~Idiffn, which are the difference between the output currents Is1~Isn and the current threshold. For example, the control signal Spwm1 generated by the comparison circuit 200 is used to enable the power output stage circuit 110 to generate the first phase output current Is1. The difference between the first phase output current Is1 and the specific current threshold is the error current Idiff1. The error currents Idiff1~Idiffn can be directly used as the correction signals Sc1~Scn, or can be used as the correction signals Sc1~Scn after conversion.

In one embodiment, the current threshold may be a preset fixed current value, such as an ideal value of the output current when the multi-phase DC-DC converter 100 operates normally. In another embodiment, the current threshold may be an average value or a median value of a plurality of driving currents generated by the power output stage circuit 110, but the present disclosure is not limited thereto. In some variations of the present disclosure, the current threshold may be a preset value, or may be obtained by looking up a table.

The present disclosure does not directly change the signal received by the comparison circuit 200 (i.e., the compensation signal Vcomp and the corresponding reference signals VR1~VRn), but receives the correction signals Sc1~Scn through a correction terminal other than the input terminal (positive input terminal and negative input terminal) of the comparison circuit 200, thereby affecting the comparison result of the comparison circuit 200 to change the duty cycle of the control signal.

In one embodiment, the comparator 210 uses the correction signals Sc1-Scn as its own correction voltage to compare the compensation signal Vcomp and the corresponding reference signal according to the correction voltage. The correction voltage can be regarded as a reference standard for the comparator 210 to compare signals. Therefore, when the correction signals Sc1-Scn form a correction voltage on the correction terminal, it will indirectly affect the comparison result of the comparator 210 (i.e., change the duty cycle of the control signal). In other words, the comparator 210 adjusts the duty cycle of the corresponding control signal according to the corresponding correction voltage. The generation method of the correction signals Sc1-Scn will be described in detail in the following paragraphs.

In one embodiment, the current balancing circuit 120 further includes a current detection circuit 121. The current detection circuit 121 is coupled to the power output stage circuit 110 to obtain a plurality of output currents Is1 to Isn generated by the power output stage circuit 110, and is used to calculate a current threshold value according to the output currents Is1 to Isn. In another embodiment, the current detection circuit 121 can detect the phase nodes N1 to Nn between the upper bridge switch Ta and the lower bridge switch Tb in the power output stage circuit 110 to obtain the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and then calculate the corresponding output current. At the same time, the current detection circuit 121 can also calculate the average current of the plurality of output currents as the current threshold value. The current detection circuit 121 can directly output the current threshold and the output current of the corresponding phase to the corresponding comparison circuit 200, or after calculating the error currents Idiff1-Idiffn, output the error currents Idiff1-Idiffn of the corresponding phase to the corresponding comparison circuit 200.

FIG. 2 is a schematic diagram of a current detection circuit 121 according to some embodiments of the present disclosure. As shown in FIGS. 1 and 2, the current detection circuit 121 includes a transconductance circuit 121a, an adder circuit 121b, a divider circuit 121c, and a subtractor circuit 121d. The transconductance circuit 121a is coupled to the power output stage circuit 110 to receive the output currents Is1 to Isn. In one embodiment, the transconductance circuit 121a includes a transconductance amplifier to receive the voltages Lx1 to Lxn of the phase nodes N1 to Nn and then calculate the output currents Is1 to Isn.

The adder circuit 121b is coupled to the transfer circuit 121a to receive the output currents Is1 to Isn and calculate the average current Iavg of the output currents Is1 to Isn through the divider circuit 121c. The subtractor circuit 121d is coupled to the divider circuit 121c to calculate the difference between the output current of the corresponding phase and the average current Iavg to generate error currents Idiff1 to Idiffn.

In one embodiment, the comparison circuit 200 further includes a calibration conversion circuit 220 coupled between the current detection circuit 121 and the comparator 210. The calibration conversion circuit 220 is used to receive a corresponding one of the error currents Idiff1-Idiffn from the current detection circuit 121 and directly use the corresponding error current as a calibration signal, or convert the corresponding error current into a voltage signal or a current signal to provide the calibration signal to the calibration terminal of the comparator 210.

In another embodiment, the calibration conversion circuit 220 can receive the current threshold and the corresponding output current from the current detection circuit 121, and then calculate/generate the corresponding calibration signal. For example, the calibration conversion circuit 220 converts the current threshold and the corresponding output current into a voltage signal or a current signal, and provides the calibration signal to the calibration terminal of the comparator 210.

The correction conversion circuit 220 inputs the error current/correction signal to the correction terminal of the comparator 210 to form a correction voltage, so that the comparator 210 can compare the compensation signal Vcomp and the reference signals VR1-VRn according to the correction voltage. Specifically, the correction conversion circuit 220 may include a current mirror to transmit the corresponding one of the error currents Idiff1-Idiffn to the corresponding comparator 210. In other embodiments, the correction conversion circuit 220 may also include a transconductance amplifier to perform voltage-current conversion, or a transimpedance amplifier or a current amplifier to perform current-voltage conversion. Specific implementation examples of the correction conversion circuit 220 will be introduced in Figures 3A, 3B, 4A, 4B, 5A, and 5B.

For ease of understanding, the operation of the comparator circuit is described here according to the embodiment disclosed in FIG. 3A. FIG. 3A shows a schematic diagram of a comparator circuit according to some embodiments of the present disclosure, which can be applied to the multi-phase DC-DC converter 100 shown in FIG. 1. The comparator circuit shown in FIG. 3A can be an example of the comparator circuit 200 shown in FIG. 1, and the comparator 310A and the correction circuit 320A included therein can be an example of the comparator 210 and the correction conversion circuit 220 shown in FIG. 1, respectively. The two input terminals of the comparator 310A are respectively used to receive the compensation signal Vcomp and the reference signal (VR1 is used as an example here), and the compensation signal Vcomp and the reference signal VR1 are compared according to the correction voltage formed by the error current. In addition, the comparator 310A further has a plurality of nodes N31A-N34A, wherein the voltage level of the node N31A may be an example of the aforementioned calibration voltage.

In this embodiment, the comparator 310A is a second-order/secondary comparator, including a first-order comparator 311A and a second-order comparator 312A. The first-order comparator 311A and the second-order comparator 312A are respectively coupled to the power supply Vcc, and have a current source M31/M32 and a plurality of transistors T31A~T38A. Taking the first-order comparator 311A as an example, the control end of the transistor T31A is the node N31A, which serves as a correction end. Transistors T33A and T34A are coupled to the current source M31. However, the comparator 310A is not limited to a second-order comparator. In other embodiments, the comparator 310A can also be implemented as a single-stage comparator.

The correction circuit 320A includes a first correction circuit 321A and a second correction circuit 322A. The first correction circuit 321A and the second correction circuit 322A may include a current mirror (but the present disclosure is not limited thereto) to receive the first output current Is1 and the average current Iavg (e.g., through the current detection circuit 121 and the correction conversion circuit 220 shown in FIG. 1) and generate currents of the same magnitude at the node N31A, wherein the average current Iavg may also be changed to a fixed current threshold to replace real-time calculation. The first correction circuit 321A and the second correction circuit 322A are coupled to the same correction terminal of the comparator 310A, so the current value of the node N31A will depend on the "relative relationship between the first output current Is1 and the average current Iavg (i.e., the aforementioned error current or correction signal)".

The correction circuit 320A is used to adjust the duty cycle of the control signal (such as the control signals Spwm1 to Spwmn shown in FIG. 1) so that the output current of the corresponding phase can be consistent with the output current of other phases. Please refer to FIG. 1, FIG. 3A and FIG. 3C together, wherein FIG. 3C illustrates the waveforms of the compensation signal Vcomp and the reference signal VR1, the waveform Spwm-A of the control signal Spwm1 when "the first output current Is1 is equal to the average current Iavg", the waveform Spwm-B of the control signal Spwm1 when "the first output current Is1 is greater than the average current Iavg", and the waveform Spwm-C of the control signal Spwm1 when "the first output current Is1 is less than the average current Iavg".

Please refer to FIG. 3A. For example, in the positive half cycle of the control signal Spwm1, when the control signal Spwm1 is at a high level and the reference signal VR1 is lower than the compensation signal Vcomp, the upper bridge switch Ta is turned on and the lower bridge switch Tb is turned off, and the input voltage Vin charges the output capacitor Cout and the inductor L1, forming an output current Is1 flowing from the phase node N1 to the output capacitor Cout. Then, the current detection circuit 121 receives the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and calculates the output currents Is1 to Isn according to the voltages Lx1 to Lxn. As shown in FIGS. 1 and 2 , the current detection circuit 121 compares the output currents Is1 to Isn with the average current value of these currents (ie, the average current Iavg or the current threshold value mentioned above). If the first output current Is1 is equal to the average current Iavg, then as shown in the time point P2 of FIG. 3C , the time point when the control signal Spwm1 changes to a high level is equal to the time point when the compensation signal Vcomp is equal to the reference signal VR1 .

When the detected first output current Is1 is greater than the average current Iavg, the correction circuit 320A will reduce the duty cycle of the control signal Spwm1 to reduce the first output current Is1 so that it is equal to the output currents of other phases, as shown in the waveform Spwm-B of FIG. 3C. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the correction circuit 320A will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 so that it is equal to the output currents of other phases, as shown in the waveform Spwm-C of FIG. 3C.

As shown in FIG. 3A, when the first output current Is1 is greater than the average current Iavg, the current will flow from the node N31A to the transistor T35A, so the voltage of the node N31A will gradually rise, causing the control end of the transistor T35A to have a high level and conduct, forming a current path from the node N33A to the ground end via the current source M32, so that the level of the node N33A is quickly pulled down to a low level, thereby pulling down the control signal Spwm1, which is equivalent to slowing down the time for the control signal Spwm1 to enter a high level, that is, reducing the duty cycle of the control signal Spwm1. As shown in FIG. 3C at time point P3, the control signal Spwm1 will be delayed to enter a high level at time point P3, rather than entering a high level at time point P2. In addition, because the currents flowing through nodes N31A and N32A compete with each other for the current from current source M31, when node N31A has a high level, node N32A will have a low level and transistor T32A will be turned off. At this time, node N34A has a high level and transistors T37A and T38A will be turned off.

Please note that the buffer circuit 330A is an example of the logic circuit CL in Figure 1, which may include but is not limited to two inverters connected in series to provide a digital signal with a logic level equal to the level of the node N33A as the control signal Spwm1. In some embodiments of the present invention, if the buffer circuit 330A is coupled to the node N34A instead of the node N33A, the buffer circuit 330A must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 321A and the second correction circuit 322A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 330A must also be designed to include only a single inverter to maintain the same output phase.

In addition, the control signal Spwm1 generated by the buffer circuit 330A also has a better signal thrust. However, the setting of the buffer circuit 330A can be omitted in some embodiments of the present disclosure. The present disclosure corrects the setting of the circuit 320A. When the first output current Is1 is greater than the average current Iavg, the node N33A will quickly enter the low level, slowing down the time for the control signal Spwm1 to enter the high level (refer to Figure 3C, the control signal Spwm1 is delayed to enter the high level at time point P3, not time point P2), so as to reduce the duty cycle of the control signal Spwm1, thereby reducing the output current (such as: the first output current Is1) output by the switch circuit 111, so as to achieve the purpose of equalizing the current of each phase.

On the other hand, when the first output current Is1 is less than the average current Iavg, the current will flow from the node N31A to the correction circuit 320A, so that the node N31A is at a low level, so that the control end of the transistor T35A has a low level and the transistor T35A is not turned on. In addition, because the currents flowing from the current source to the nodes N31A and N32A are in a competitive relationship (that is, when the current flowing to one increases, the current flowing to the other decreases), when the node N31A is at a low level, the node N32A will have a high level, so that the transistors T32A and T36A are turned on. At this time, the potential of the node N34A is pulled down by the ground end through the current source M32 and has a low level, so that the transistors T37A and T38A are turned on. Therefore, the node N33A is pulled to a high level in advance, which is equivalent to making the control signal Spwm1 enter a high level in advance (as shown in Figure 3C, at this time, the control signal Spwm1 enters a high level in advance at time point P1, rather than at time point P2), so that the duty cycle of the control signal Spwm1 is increased.

In other words, the present disclosure sets the correction circuit 320A so that when the first output current Is1 is less than the average current Iavg, the node N33A will quickly enter a high level to increase the duty cycle of the control signal Spwm1 provided to the driving circuit DC, thereby increasing the output current (such as the first output current Is1) generated by the switching circuit 111, thereby achieving the purpose of equalizing the current of each phase.

According to the above content, the present disclosure does not adjust the received signal at the two input terminals of the comparator 310A (or the comparator 210), that is, the compensation signal or the reference signal received by the comparator is not adjusted, but the duty cycle of the control signal is adjusted according to the difference between the output current of the corresponding phase (such as the first output current Is1) and the average current Iavg through the correction terminal (such as the node N31A), thereby increasing or decreasing the output current of the power output stage circuit 110 of the phase, and finally achieving the effect of equal output current of each phase power output stage circuit 110. Please note that the working principles of Figures 3A, 3B, 4A, 4B, 5A and 5B are all illustrated with the positive half-cycle of the control signal Spwm1 in Figure 3C as an example.

FIG. 3B is a schematic diagram of a comparator circuit according to some embodiments of the present disclosure. The difference between FIG. 3B and FIG. 3A is that the comparator 310B is a first-order/first-stage comparator. The comparator circuit includes a comparator 310B, a correction circuit 320B, and a buffer circuit 330B. The correction circuit 320B includes a first correction circuit 321B and a second correction circuit 322B. Similar to FIG. 3A, the comparator 310B is coupled to a power supply Vcc and has a current source M33 and a plurality of transistors T31B~T34B.

The correction circuit 320B is used to adjust the duty cycle of the control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output current of other phases. Therefore, when the detected first output current Is1 is greater than the average current Iavg, the correction circuit 320B will reduce the duty cycle of the control signal Spwm1 to reduce the first output current Is1 and keep it equal to the output current of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the correction circuit 320B will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 and keep it equal to the output current of other phases.

As shown in Figure 3B, when the first output current Is1 is greater than the average current Iavg, the current will flow from the node N31B to the transistor T32B. At this time, the voltage of the node N31B rises, causing the control end of the transistor T32B to have a high level and turn on. The voltage level of the node N31B can be an example of the aforementioned correction voltage.

Since transistor T32B is turned on, node N32B is pulled down quickly, thus slowing down the time for control signal Spwm1 to enter a high level (refer to Figure 3C, control signal Spwm1 enters a high level at time point P3, not time point P2), thus reducing the duty cycle of control signal Spwm1, thereby reducing the first output current Is1 of the DC output of the driving circuit, achieving the purpose of controlling the current of each phase to be equal.

Correction circuit 320B of FIG. 3B may be the same as correction circuit 320A of FIG. 3A, and buffer circuit 330B may be the same as 330A of FIG. 3A. Note that buffer circuit 330B may include two inverters in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if buffer circuit 330B is changed to couple node N31B instead of coupling node N32B, buffer circuit 330B must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 321B and the second correction circuit 322B are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 330B must also be designed to include only a single inverter to maintain the same output phase.

On the other hand, if the first output current Is1 is less than the average current Iavg, the current will flow from the node N31B to the correction circuit 320B, so that the node N31B is at a low level, so that the control end of the transistor T32B has a low level and the transistor T32B is not turned on. At this time, the node N32B will be pulled to a high level in advance, advancing the time when the control signal Spwm1 enters a high level (refer to FIG. 3C, the control signal Spwm1 enters a high level in advance at the time point P1, not the time point P2), so that the duty cycle of the control signal Spwm1 is increased. In other words, the error current/correction signal/correction voltage causes the node N32B to enter a high level faster, and the time that the control signal Spwm1 is at a high level becomes longer, making the duty cycle of the control signal Spwm1 larger, thereby increasing the first output current Is1 and achieving the goal of making each phase current equal.

FIG. 4A is a schematic diagram of a comparison circuit according to a partial embodiment of the present disclosure, which can be applied to the multi-phase DC-DC converter 100 shown in FIG. 1. The comparison circuit includes a comparator 410A, a correction circuit 420A, and a buffer circuit 430A. The two input terminals of the comparator 410A are used to receive the compensation signal Vcomp and the reference signal VR1, respectively, and also have a plurality of nodes N41A to N44A, wherein the voltage level of the node N41A can be an example of the aforementioned correction voltage. The comparison circuit shown in FIG. 4A can be an example of the comparison circuit 200 shown in FIG. 1, and the comparator 410A and the correction circuit 420A included therein can be an example of the correction conversion circuit 220 shown in FIG. 1, respectively.

In this embodiment, the comparator 410A is a second-order/secondary comparator, including a first-order comparator 411A and a second-order comparator 412A. The comparator 410A may be the same as the comparator 310A shown in FIG. 3A, including a plurality of transistors T41A-T48A and current sources M41, M42. However, the present disclosure is not limited thereto, and in other embodiments, the comparator 410A may also be implemented as a single-stage comparator.

The correction circuit 420A includes a first correction circuit 421A and a second correction circuit 422A. The first correction circuit 421A and the second correction circuit 422A include current mirrors and are respectively coupled to different correction terminals (e.g., nodes N41A and N42A) of the comparator 310A. The correction circuit 420A receives the first output current Is1 and the average current Iavg through the first correction circuit 421A and the second correction circuit 422A, i.e., obtains the error current between the first output current Is1 and the average current Iavg.

Specifically, the first correction circuit 421A is coupled to a correction terminal (i.e., node N41A) of the comparator 410A, and is used to input the first output current Is1 as the first correction signal to the node N41A. The second correction circuit 422A is coupled to another correction terminal (i.e., node N42A) of the comparator 410A, and is used to input the current threshold (e.g., average current Iavg) as the second correction signal to the node N42A. Accordingly, the comparator 410A compares the compensation signal Vcomp and the reference signal VR1 according to the plurality of correction voltages formed by the first correction signal and the second correction signal.

The correction circuit 420A is used to adjust the duty cycle of the control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output current of other phases. When the detected first output current Is1 is greater than the average current Iavg, the correction circuit 320A will reduce the duty cycle of the control signal Spwm1 to reduce the first output current Is1 and keep it equal to the output current of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the correction circuit 320A will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 and keep it equal to the output current of other phases.

As shown in FIG. 4A , when the first output current Is1 and the average current Iavg are input to nodes N41A and N42A, and the first output current Is1 is greater than the average current Iavg, node N41A has a high level, thereby turning on transistor T45A, forming a current path from node N43A to the ground via current source M42, so that the level of node N43A is pulled down, which is equivalent to slowing down the time for the control signal Spwm1 to enter a high level (refer to FIG. 3C , the control signal Spwm1 is delayed to enter a high level at time point P3, not time point P2). In addition, because the currents flowing through the nodes N41A and N42A compete with each other for the current from the current source M41, when the node N41A has a high level, the node N42A will have a low level and turn off the transistor T46A. At this time, the node N44A has a high level and turns off the transistors T47A and T48A. In other words, the error current/correction signal/correction voltage pulls down the level of the node N43A, thereby reducing the duty cycle of the control signal Spwm1, and further reducing the output current (such as the first output current Is1) output by the switch circuit 111, so as to achieve the purpose of equalizing the current of each phase.

On the other hand, when the first output current Is1 and the average current Iavg are input to the nodes N41A and N42A, and the first output current Is1 is less than the average current Iavg, the voltage of the node N41A will be at a low level, so that the control end of the transistor T45A has a low level and the transistor T45A is not turned on. In addition, because the currents flowing from the current source M41 to the nodes N41A and N42A are in a competitive relationship, when the node N41A is at a low level, the node N42A will have a high level, so that the transistors T42A and T46A are turned on. At this time, the potential of the node N44A is pulled down by the ground end through the current source M41 and has a low level, so that the transistors T47A and T48A are turned on. Therefore, the node N43A is pulled to a high level in advance, which is equivalent to making the control signal Spwm1 enter a high level in advance (refer to FIG. 3C , the control signal Spwm1 enters a high level in advance at time point P1, not at time point P2), so that the duty cycle of the control signal Spwm1 is increased.

Please note that the buffer circuit 430A may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 430A is changed to couple the node N44A instead of coupling the node N43A, the buffer circuit 430A must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 421A and the second correction circuit 422A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 430A must also be designed to include only a single inverter to maintain the same output phase.

FIG. 4B is a schematic diagram of a comparator circuit according to some embodiments of the present disclosure. The difference between FIG. 4B and FIG. 4A is that the comparator 410B is a first-order/first-stage comparator. The correction circuit 420B includes a first correction circuit 421B and a second correction circuit 422B. Similar to FIG. 4A, the comparator 410B is coupled to a power supply Vcc and has a current source M43 and a plurality of transistors T41B-T44B.

The correction circuit 420B is used to adjust the duty cycle of the control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output current of other phases. Therefore, when the detected first output current Is1 is greater than the average current Iavg, the correction circuit 420B will reduce the duty cycle of the control signal Spwm1 to reduce the first output current Is1 and keep it equal to the output current of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the correction circuit 420B will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 and keep it equal to the output current of other phases.

As shown in Figure 4B, when the first output current Is1 and the average current Iavg are input to nodes N41B and N42B, and the first output current Is1 is greater than the average current Iavg, the node N41B has a high level to turn on the transistor T42B (wherein the voltage level of the node N41B can be an example of the aforementioned correction voltage), so that the level of the node N42B is pulled down, which is equivalent to slowing down the time for the control signal Spwm1 to enter the high level (refer to Figure 3C, the control signal Spwm1 is delayed to enter the high level at time point P3, not time point P2), that is, the duty cycle of the control signal Spwm1 is reduced, so that the first output current Is1 is also reduced, achieving the purpose of controlling the current of each phase to be equal.

Similarly, when the first output current Is1 and the average current Iavg are input to nodes N41B and N42B, and the first output current Is1 is less than the average current Iavg, the voltage of node N42B will enter the high level faster, that is, the time for the control signal Spwm1 to enter the high level is advanced, so that the duty cycle of the control signal Spwm1 is increased, thereby increasing the first output current Is1, achieving the purpose of controlling the current of each phase to be equal.

Please note that the buffer circuit 430B may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 430B is changed to couple the node N41B instead of coupling the node N42B, the buffer circuit 430B must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 421B and the second correction circuit 422B are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 430B must also be designed to include only a single inverter to maintain the same output phase.

FIG. 5A is a schematic diagram of a comparator circuit according to some embodiments of the present disclosure, which can be applied to the multi-phase DC-DC converter 100 shown in FIG. 1. The comparator circuit includes a comparator 510A, a correction circuit 520A, and a buffer circuit 530A. The comparator circuit shown in FIG. 5A can be an example of the comparator circuit 200 shown in FIG. 1, and the comparator 510A and the correction circuit 520A included therein are examples of the comparator 210 and the correction conversion circuit 220 shown in FIG. 1, respectively. The two input terminals of the comparator 510A are used to receive the compensation signal Vcomp and the reference signal VR1, respectively, and also include a plurality of nodes N51A~N54A.

In this embodiment, the comparator 510A is a second-order/secondary comparator, including a first-order comparator 511A and a second-order comparator 512A. The comparator 510A may be the same as the comparator 310A shown in FIG. 3A, including a plurality of transistors T51A~T58A and current sources M51 and M52. However, the present disclosure is not limited thereto, and in other embodiments, the comparator 510A may also be implemented as a single-stage comparator.

The correction circuit 520A includes a first correction circuit 521A and a second correction circuit 522A. The first correction circuit 521A and the second correction circuit 522A may include a current mirror (but the present disclosure is not limited thereto) to receive the first output current Is1 and the average current Iavg, wherein the average current Iavg may also be changed to a fixed current threshold. The first correction circuit 521A and the second correction circuit 522A are coupled to the same correction terminal (e.g., node N51A) of the comparator 510A, so the current value of the node N51A will depend on the "relative relationship between the average current Iavg and the first output current Is1 (i.e., the aforementioned error current or correction signal)".

As shown in FIG. 5A, when the first output current Is1 is greater than the average current Iavg, the current will flow from the node N51A to the correction circuit 520A, so the voltage of the node N51A will gradually decrease, and the voltage of the node N52A will gradually increase (wherein the voltage level of the node N52A can be one of the correction voltages mentioned above), so that the control end of the transistor T55A has a high level and is turned on, and the node N53A is pulled down by the current source M52, which is equivalent to slowing down the time for the control signal Spwm1 to enter the high level (refer to Figure 3C, the control signal Spwm1 is delayed to enter the high level at time point P3, not time point P2), that is, the duty cycle of the control signal Spwm1=1 is reduced, so that the first output current Is1 is also reduced, achieving the purpose of controlling the current of each phase to be equal. In addition, when the node N51A has a low level, the transistor T56A will be turned off, and at this time the node N54A is at a high level, which makes the transistors T57A and T58A turned off.

On the other hand, if the first output current Is1 is less than the average current Iavg, the current will flow from the correction circuit 520A to the node N51A. Since the currents flowing from the current source M51 to the nodes N51A and N52A are in a competitive relationship, the voltage of the node N51A will gradually increase, and the voltage of the node N52A will gradually decrease, so that the control end of the transistor T51A has a low level and is turned off. In addition, when the node N51A has a high level, the transistor T56A will be turned on, and at this time, the node N54A is pulled down to a low level by the current source M52, so that the transistors T57A and T58A are turned on. Therefore, the node N53A is at a high level, which advances the time when the control signal Spwm1 enters a high level (refer to Figure 3C, the control signal Spwm1 enters a high level at time point P1, not time point P2), that is, the duty cycle of the control signal Spwm1 is increased, so that the first output current Is1 is also increased, and the purpose of making each phase current equal can be achieved.

Please note that the buffer circuit 530A may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 530A is changed to couple the node N54A instead of coupling the node N53A, the buffer circuit 530A must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 521A and the second correction circuit 522A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 530A must also be designed to include only a single inverter to maintain the same output phase.

FIG. 5B is a schematic diagram of a comparator circuit according to some embodiments of the present disclosure. The difference between FIG. 5B and FIG. 5A is that the comparator 510B is a first-order/first-stage comparator. The comparator circuit includes a comparator 510B, a correction circuit 520B, and a buffer circuit 530B. The correction circuit 520B includes a first correction circuit 521B and a second correction circuit 522B. Similar to FIG. 5A, the comparator 510B is coupled to a power supply Vcc and has a current source M53 and a plurality of transistors T51B-T54B.

As shown in FIG. 5B , when the first output current Is1 is greater than the average current Iavg, the current will flow from the node N51B to the correction circuit 520B, wherein the voltage level of the node N51B may be an example of the correction voltage mentioned above. At this time, since the currents flowing from the current source to the nodes N51B and N52B are in competition, the voltage of the node N51B will gradually decrease, while the voltage of the node N52B will gradually increase. The control signal Spwm1 is pulled down to a low level in advance, which is equivalent to slowing down the time for the control signal Spwm1 to enter a high level (refer to Figure 3C, the control signal Spwm1 is delayed to enter a high level at time point P3, not time point P2), that is, reducing the duty cycle of the control signal Spwm1, thereby reducing the first output current Is1, thereby achieving the purpose of controlling the current of each phase to be equal.

On the other hand, when the first output current Is1 is less than the average current Iavg, the current will flow from the correction circuit 520B to the node N51B, so the voltage of the node N51B will gradually increase, and the voltage of the node N52B will gradually decrease, thereby advancing the time for the control signal Spwm1 to enter a high level (refer to Figure 3C, the control signal Spwm1 enters a high level in advance at time point P1, not time point P2), that is, the duty cycle of the control signal Spwm1 is extended, so that the first output current Is1 is also increased, thereby achieving the purpose of controlling the current of each phase to be equal.

Please note that the buffer circuit 530B may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 530B is changed to couple the node N52B instead of coupling the node N51B, the buffer circuit 530B must be designed to include only a single inverter to maintain the same output phase. For another example, if the first correction circuit 521B and the second correction circuit 522B are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 530B must also be designed to include only a single inverter to maintain the same output phase.

The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other and are not limited to the order of textual description or the order of diagram presentation in this disclosure.

Although the contents of this disclosure have been disclosed as above in the form of implementation, it is not intended to limit the contents of this disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the contents of this disclosure. Therefore, the protection scope of the contents of this disclosure shall be subject to the scope defined by the attached patent application.

100: Multiphase DC-DC converter 110: Power output stage circuit 111: Switching circuit 120: Current balancing circuit 121: Current detection circuit 121a: Transduction circuit 121b: Adder circuit 121c: Divider circuit 121d: Subtractor circuit 122: Multiphase voltage regulator circuit 130: Compensation circuit 140: Energy storage circuit 150: Voltage divider circuit 200: Comparator circuit 210: Comparator 220: Correction conversion circuit 310A: Comparator 311A: First-order comparator 312A: Second-order comparator 320A: correction circuit 321A: first correction circuit 322A: second correction circuit 310B: comparator 320B: correction circuit 321B: first correction circuit 322B: second correction circuit 330A: buffer circuit 330B: buffer circuit 410A: comparator 411A: first-order comparator 412A: second-order comparator 420A: correction circuit 421A: first correction circuit 422A: second correction circuit 410B: comparator 420B: correction circuit 421B: first correction circuit

422B: Second correction circuit

430A: Buffer circuit

430B: Buffer circuit

510A: Comparator

511A: First-order comparator

512A: Second-order comparator

520A: Calibration circuit

521A: First correction circuit

522A: Second correction circuit

510B: Comparator

520B: Calibration circuit

521B: First correction circuit

522B: Second correction circuit

530A: Buffer circuit

530B: Buffer circuit

CL:Logic Circuit

Cout: output capacitance

DC: drive circuit

Iavg: average current

Idiff1~Idiffn: Error current

Is1~Isn: output current

L1~Ln: Inductor

Lx1~Lxn: voltage

M31~M33: Current source

M41~M43: Current source

M51~M53: Current source

N1~Nn: Phase nodes

N31A~N34A: Node

N31B~N32B: Node

N41A~N44A: Node

N41B~N42B: Node

N51A~N54A: Node

N51B~N52B: Node

P1~P3: Time point

R1~R2: voltage divider resistor

Sc1~Scn: calibration signal

Spwm1~Spwmn: control signal

Spwm-A: Waveform

Spwm-B: Waveform

Spwm-C: Waveform

Ta: Bridge switch

Tb: Down bridge switch

T31A~T38A: Transistor

T31B~T34B: Transistor

T41A~T48A: Transistor

T41B~T44B: Transistor

T51A~T58A: Transistor

T51B~T54B: Transistor

Vcomp: compensation signal

VR1~VRn: Reference signal

Vfb: Feedback voltage

Vref: reference voltage

Vin: Input voltage

Vout: output voltage

Vcc: power supply

FIG. 1 is a schematic diagram of a multiphase DC-DC converter according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of a current detection circuit according to some embodiments of the present disclosure. FIG. 3A is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. FIG. 3B is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. FIG. 3C is a waveform diagram of a control signal according to some embodiments of the present disclosure. FIG. 4A is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. FIG. 4B is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. FIG. 5A is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. Figure 5B is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

100:Multiphase DC-DC converter

110: Power output stage circuit

111: Switching circuit

120: Current balancing circuit

121: Current detection circuit

122:Multi-phase voltage regulator circuit

130: Compensation circuit

140: Energy storage circuit

150: Voltage divider circuit

200: Comparison circuit

210: Comparator

220: Correction conversion circuit

CL:Logic Circuit

Cout: output capacitance

DC: drive circuit

Idiff1~Idiffn: Error current

Is1~Isn: output current

L1~Ln: Inductor

Lx1~Lxn: voltage

N1~Nn: Phase nodes

R1~R2: voltage divider resistor

Sc1~Scn: calibration signal

Spwm1~Spwmn: control signal

Ta: Bridge switch

Tb: Down bridge switch

Vcomp: compensation signal

VR1~VRn: Reference signal

Vfb: Feedback voltage

Vref: reference voltage

Vin: Input voltage

Vout: output voltage

Claims (10)

A multi-phase voltage regulator circuit is applied to a multi-phase DC-DC converter, comprising: a plurality of comparison circuits coupled to a power output stage circuit of the multi-phase DC-DC converter and used to generate a plurality of control signals so that the power output stage circuit generates a plurality of output currents; wherein one of the comparison circuits comprises: a comparator, wherein the comparator is used to receive a A compensation signal and a reference signal, and the comparator also receives a correction signal through a correction terminal to adjust a duty cycle of a corresponding one of the control signals according to the correction signal; and a correction conversion circuit coupled to the comparator and used to generate the correction signal according to an error current, wherein the error current is the difference between a current threshold and a corresponding one of the output currents. A multi-phase voltage regulator circuit as described in claim 1, wherein the compensation signal is a difference between a feedback voltage provided by an output terminal of the multi-phase DC-DC converter and a reference voltage. A multi-phase voltage regulator circuit as described in claim 1, wherein the correction signal is used to form a correction voltage at the correction end, and the comparator adjusts the duty cycle of the corresponding one of the control signals according to the correction voltage. A multi-phase voltage regulator circuit as described in claim 3, wherein the multi-phase DC-DC converter further comprises: a current detection circuit coupled to the power output stage circuit for receiving the output currents to calculate the current threshold. A multi-phase voltage regulator circuit as described in claim 4, wherein the current threshold is an average value of the output currents. A multi-phase voltage regulator circuit as described in claim 3, wherein the correction conversion circuit comprises: a first correction circuit coupled to the correction terminal of the comparator and used to input the corresponding one of the output currents as a first correction signal to the correction terminal; and a second correction circuit coupled to the other correction terminal of the comparator and used to input the current threshold as a second correction signal to the other correction terminal; wherein the comparator compares the compensation signal and the reference signal according to a plurality of correction voltages formed by the first correction signal and the second correction signal. A multi-phase voltage regulator circuit as described in claim 1, wherein: the correction conversion circuit is also coupled to a current detection circuit of the multi-phase DC-DC converter, and is used to receive the current threshold and the corresponding one of the output currents, or to receive the error current; wherein the correction conversion circuit is used to convert the current threshold and the corresponding one of the output currents into a voltage signal or a current signal, or to convert the error current into a voltage signal or a current signal. A multi-phase voltage regulator circuit as described in claim 7, wherein the correction conversion circuit includes a transconductance amplifier, a transimpedance amplifier or a current amplifier. A multi-phase voltage regulator circuit as described in claim 1, wherein the reference signal is a periodic signal. A current balancing circuit is applied to a multi-phase DC-DC converter, comprising: a current detection circuit coupled to a power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents and to calculate an average current of the output currents; and a comparison circuit coupled to the current detection circuit and used to compare a compensation signal and a reference signal to output a control signal so that the power output stage circuit is used to adjust a first output current among the output currents; wherein the comparison circuit is also used to use the difference between the average current and the first output current as a correction signal to adjust a duty cycle of the control signal according to the correction signal.

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