TWM629645U - High stability power supply circuit, power management chip and information processing device - Google Patents

High stability power supply circuit, power management chip and information processing device Download PDF

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TWM629645U
TWM629645U TW111203840U TW111203840U TWM629645U TW M629645 U TWM629645 U TW M629645U TW 111203840 U TW111203840 U TW 111203840U TW 111203840 U TW111203840 U TW 111203840U TW M629645 U TWM629645 U TW M629645U
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resistance
power supply
supply circuit
ohm
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李偉江
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大陸商北京集創北方科技股份有限公司
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Abstract

本創作主要揭示具高穩定性的一種供電電路,其具有至少一低壓差線性穩壓器、耦接一電壓輸出端的一輸出電阻、以及耦接該輸出電阻的一電壓輸出腳位。此供電電路進一步具有複數個等效電阻調整腳位,其各自透過一電阻調整元件耦接該電壓輸出端。在一外部電容耦接至該電壓輸出腳位之後,該輸出電阻、複數個所述電阻調整元件和該電壓輸出腳位與該外部電容之間的一線路電阻一同構成一等效電阻。依此設計,即使供電電路被應用在不同的電子產品之中而使該線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化,該等效電阻的電阻值仍舊可以被控制在0.9歐姆至1.1歐姆之間,從而能夠確保負回授環路的穩定性以及保證輸出電壓信號不出現毛刺。 The present invention mainly discloses a power supply circuit with high stability, which has at least one low dropout linear regulator, an output resistor coupled to a voltage output end, and a voltage output pin coupled to the output resistor. The power supply circuit further has a plurality of equivalent resistance adjustment pins, each of which is coupled to the voltage output terminal through a resistance adjustment element. After an external capacitor is coupled to the voltage output pin, the output resistor, a plurality of the resistance adjustment elements and a line resistance between the voltage output pin and the external capacitor together form an equivalent resistance. According to this design, even if the power supply circuit is used in different electronic products and the resistance value of the line resistance varies between 0.1 ohm and 0.9 ohm, the resistance value of the equivalent resistance can still be controlled between 0.9 ohm and 1.1 ohm. between ohms, so as to ensure the stability of the negative feedback loop and ensure that the output voltage signal does not appear glitches.

Description

高穩定性供電電路、電源管理晶片及資訊處理裝置High stability power supply circuit, power management chip and information processing device

本創作係關於電子電路之技術領域,尤指用於實現資訊處理裝置之電源管理的一種高穩定性供電電路。This creation relates to the technical field of electronic circuits, especially to a high-stability power supply circuit for realizing power management of information processing devices.

應知道,電子產品包含一電源供應裝置(例如:鋰電池),用以提供適合的驅動電源至內部的各種晶片及電子元件。然而,由於不同晶片及電子元件所需驅動電源(即,工作電壓)會有所差異,因此,現有的電子產品同時包含一電源管理晶片,用以將鋰電池輸出的電源進行一電源轉換處理後,接著提供適合的驅動電源至對應的晶片及電子元件。It should be known that an electronic product includes a power supply device (eg, a lithium battery) for providing suitable driving power to various chips and electronic components inside. However, since the driving power (ie, operating voltage) required by different chips and electronic components will be different, the existing electronic products also include a power management chip for converting the power output from the lithium battery after a power conversion process. , and then provide suitable driving power to the corresponding chips and electronic components.

圖1顯示習知的一種智慧型手機之顯示裝置的架構圖。目前,智慧型手機的顯示螢幕已朝向全屏設計發展,使得包含閘極驅動電路與源極驅動電路的顯示驅動晶片1a以及包含至少一個低壓差線性穩壓器(Low-dropout regulator, LDO)的供電晶片3a必須透過COF技術與顯示面板4a進行整合。其中,COF為薄膜覆晶封裝(Chip On Film),用以將顯示驅動晶片1a和供電晶片3a整合在一COF電路板5a之上。進一步地,如圖1所示,所述COF電路板5a耦接一軟性電路板(Flexible printed circuit, FPC)6a,從而透過該軟性電路板6a和智慧型手機內部的主板耦接。FIG. 1 shows a structure diagram of a conventional display device of a smart phone. At present, the display screen of a smart phone has been developed towards a full-screen design, so that the display driver chip 1a including the gate driver circuit and the source driver circuit and the power supply including at least one low-dropout regulator (LDO) The chip 3a must be integrated with the display panel 4a by COF technology. The COF is Chip On Film, which is used to integrate the display driver chip 1a and the power supply chip 3a on a COF circuit board 5a. Further, as shown in FIG. 1 , the COF circuit board 5a is coupled to a flexible printed circuit (FPC) 6a, so as to be coupled to the main board inside the smartphone through the flexible printed circuit 6a.

圖2顯示習知的包含至少一低壓差線性穩壓器的供電晶片3a的電路拓樸結構圖。如圖2所示,該供電晶片3a包含至少一個低壓差線性穩壓器,其中該低壓差線性穩壓器包括:一運算放大器31a、一P型MOS電晶體32a、包含一第一分壓電阻R1a和一第二分壓電阻R2a的一回授單元、以及一輸出電阻R3a。值得注意的是,應用此供電晶片3a時,通常會在該供電晶片3a的一電壓輸出腳位33a串接一外部電容C La,且該外部電容C La和該電壓輸出腳位33a之間具有一線路電阻R4a。此時,該低壓差線性穩壓器的輸出電壓V Y=V REF*(R 1a+R 2a)/R 2a。熟悉智慧型手機之設計與製作的電子工程師應當知道,外部電容C La的電容值約為1μF,其本身具有的等效串聯電阻(equivalent series resistor, ESR)可以對所述低壓差線性穩壓器執行頻率補償。可惜的是,外部電容C La的ESR值無法精確的控制,例如:陶瓷電容具有較低的ESR約為10mΩ,而鉭質電容的ESR約為100mΩ。此外,當應用在不同的電子產品之中時,如平板電腦,所述供電晶片3a的封裝方式也會有所差異,導致該供電晶片3a的電壓輸出腳位33a至該外部電容C La之間的線路電阻R4a之阻值也會跟著出現變化,變化範圍約為0.1~1Ω。 FIG. 2 shows a circuit topology diagram of a conventional power supply chip 3a including at least one low dropout linear regulator. As shown in FIG. 2, the power supply chip 3a includes at least one low dropout linear regulator, wherein the low dropout linear regulator includes: an operational amplifier 31a, a P-type MOS transistor 32a, including a first voltage dividing resistor A feedback unit of R1a and a second voltage dividing resistor R2a, and an output resistor R3a. It is worth noting that, when the power supply chip 3a is applied, an external capacitor C La is usually connected in series with a voltage output pin 33a of the power supply chip 3a, and there is an external capacitor C La and the voltage output pin 33a between the external capacitor C La and the voltage output pin 33a. A line resistance R4a. At this time, the output voltage of the low dropout linear regulator V Y =V REF *(R 1a +R 2a )/R 2a . Electronic engineers who are familiar with the design and manufacture of smart phones should know that the capacitance value of the external capacitor C La is about 1 μF, and the equivalent series resistance (ESR) of the external capacitor C La can affect the low dropout linear regulator. Perform frequency compensation. Unfortunately, the ESR value of the external capacitor C La cannot be precisely controlled. For example, ceramic capacitors have a low ESR of about 10mΩ, while tantalum capacitors have an ESR of about 100mΩ. In addition, when applied to different electronic products, such as tablet computers, the packaging method of the power supply chip 3a will also be different, resulting in the voltage output pin 33a of the power supply chip 3a to the external capacitor C La . The resistance value of the line resistance R4a will also change accordingly, and the change range is about 0.1~1Ω.

因此,為了穩定該低壓差線性穩壓器的輸出電壓,需要確保該運算放大器31a之負回授環路的穩定。圖2顯示該運算放大器31a之負回授環路的複數平面(complex plane)圖。其中,圖1所標示之Y點對應於圖2所標示之主極點p1,X點對應於次極點p2,且輸出電阻R3a、線路電阻R4a以及外部電容C La在複數平面的左半平面形成一個零點z1。因此,零點z1可係用下式(a)計算而得。

Figure 02_image001
………………………(a) Therefore, in order to stabilize the output voltage of the low dropout linear regulator, it is necessary to ensure the stability of the negative feedback loop of the operational amplifier 31a. FIG. 2 shows a complex plane diagram of the negative feedback loop of the operational amplifier 31a. Among them, the Y point marked in Figure 1 corresponds to the main pole p1 marked in Figure 2, the X point corresponds to the secondary pole p2, and the output resistance R3a, the line resistance R4a and the external capacitor C La form a left half plane of the complex plane. Zero point z1. Therefore, the zero point z1 can be calculated by the following formula (a).
Figure 02_image001
……………………(a)

圖3為圖2之具有至少一低壓差線性穩壓器的供電晶片3a的波德圖。其中,波德圖(Bode plot)之中的增益(gain)-頻率圖顯示,當R3a+R4a的阻值較小時,零點z1遠大於次極點p2,從而導致波德圖之中的相位(phase)-頻率圖顯示出相位裕度(phase margin, PM)小於45 o的現象。在此情況下,該供電晶片3a之相位裕度不足。 FIG. 3 is a Bode plot of the power supply chip 3a of FIG. 2 having at least one low dropout linear regulator. Among them, the gain-frequency diagram in the Bode plot shows that when the resistance value of R3a+R4a is small, the zero point z1 is much larger than the secondary pole p2, resulting in the phase in the Bode diagram ( phase) -frequency plot showing a phase margin (PM) of less than 45o. In this case, the phase margin of the power supply chip 3a is insufficient.

圖4顯示該供電晶片3a的輸出電壓V Y和一負載電流I load的工作時序圖。在實務操作方面,增加R3a+R4a的阻值是可以達成可接受的頻率補償從而提升該供電晶片3a的相位裕度。可惜的是,如圖4所示,當負載電流I load瞬間變大或變小時,由該供電晶片3a所輸出的輸出電壓V Y的信號上會出現毛刺,其中該毛刺的振幅和(R 3a+R 4a)*I load成相關。 FIG. 4 shows the operation timing diagram of the output voltage V Y and a load current I load of the power supply chip 3 a. In practical operation, increasing the resistance of R3a+R4a can achieve acceptable frequency compensation and improve the phase margin of the power supply chip 3a. Unfortunately, as shown in FIG. 4, when the load current I load increases or decreases instantaneously, a burr will appear on the signal of the output voltage V Y output by the power supply chip 3a, wherein the amplitude of the burr and (R 3a +R 4a )*I load is correlated.

由前述說明可知,由於該供電晶片3a會被應用至不同的電子產品之終,因此外部電容C La類型以及該供電晶片3a的電壓輸出腳位33a至該外部電容C La之間的線路電阻R 4a都會隨著改變,導致難以同時確保該運算放大器31a之負回授環路的穩定性以及保證該輸出電壓信號上不出現毛刺。 As can be seen from the above description, since the power supply chip 3a will be applied to different electronic products, the type of the external capacitor C La and the line resistance R between the voltage output pin 33a of the power supply chip 3a and the external capacitor C La 4a will be changed accordingly, making it difficult to simultaneously ensure the stability of the negative feedback loop of the operational amplifier 31a and ensure that no glitches appear on the output voltage signal.

由上述說明可知,本領域亟需一種高穩定性供電電路。It can be seen from the above description that there is an urgent need in the art for a power supply circuit with high stability.

本創作之主要目的在於提供一種高穩定性供電電路,其具有至少一低壓差線性穩壓器、耦接所述低壓差線性穩壓器之一電壓輸出端的一輸出電阻、以及耦接該輸出電阻的一電壓輸出腳位;其特徵在於,所述供電電路進一步具有複數個等效電阻調整腳位,且各所述等效電阻調整腳位透過一電阻調整元件耦接所述低壓差線性穩壓器的該電壓輸出端。在一外部電容耦接至該電壓輸出腳位之後,該電壓輸出腳位和該外部電容之間係具有一線路電阻,此時該輸出電阻、複數個所述電阻調整元件和該線路電阻一同構成一等效電阻。如此設計,即使所述供電電路被應用在不同的電子產品之中而使該線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化,該等效電阻的電阻值仍舊可以被控制在0.9歐姆至1.1歐姆之間變化,從而能夠確保該供電電路所具有之運算放大器的負回授環路的穩定性以及同時保證輸出電壓信號不出現毛刺。The main purpose of the present invention is to provide a high-stability power supply circuit, which has at least one low dropout linear regulator, an output resistor coupled to a voltage output end of the low dropout linear regulator, and the output resistor coupled to the a voltage output pin; it is characterized in that the power supply circuit further has a plurality of equivalent resistance adjustment pins, and each of the equivalent resistance adjustment pins is coupled to the low dropout linear voltage regulator through a resistance adjustment element the voltage output of the device. After an external capacitor is coupled to the voltage output pin, there is a line resistance between the voltage output pin and the external capacitor. At this time, the output resistance, a plurality of the resistance adjustment elements and the line resistance are formed together an equivalent resistance. With this design, even if the power supply circuit is applied in different electronic products and the resistance value of the line resistance varies from 0.1 ohm to 0.9 ohm, the resistance value of the equivalent resistance can still be controlled from 0.9 ohm to 0.9 ohm The change between 1.1 ohms can ensure the stability of the negative feedback loop of the operational amplifier of the power supply circuit and at the same time ensure that the output voltage signal does not appear glitches.

為達成上述目的,本創作提出所述供電電路的一實施例,其具有至少一低壓差線性穩壓器、耦接所述低壓差線性穩壓器之一電壓輸出端的一輸出電阻、以及耦接該輸出電阻的一電壓輸出腳位;其特徵在於,所述供電電路進一步具有複數個等效電阻調整腳位以及複數個電阻調整元件,其中各個所述等效電阻調整腳位透過至少一電阻調整元件耦接所述低壓差線性穩壓器的該電壓輸出端。In order to achieve the above object, the present invention proposes an embodiment of the power supply circuit, which has at least one low dropout linear regulator, an output resistor coupled to a voltage output end of the low dropout linear regulator, and a A voltage output pin of the output resistor; characterized in that the power supply circuit further has a plurality of equivalent resistance adjustment pins and a plurality of resistance adjustment elements, wherein each of the equivalent resistance adjustment pins is adjusted by at least one resistor The element is coupled to the voltage output terminal of the low dropout linear regulator.

在一實施例中,所述電阻調整元件為選自於由金屬電阻器和多晶矽電阻器所組成群組之中的一種被動元件。In one embodiment, the resistance adjusting element is a passive element selected from the group consisting of metal resistors and polysilicon resistors.

在一實施例中,所述電阻調整元件之電阻值係介於0.2歐姆至0.8歐姆之間,且各所述電阻調整元件皆具有不同電阻值。In one embodiment, the resistance value of the resistance adjustment element is between 0.2 ohm and 0.8 ohm, and each of the resistance adjustment elements has different resistance values.

在一實施例中,當一外部電容耦接至該電壓輸出腳位之後,該電壓輸出腳位和該外部電容之間係具有一線路電阻,此時該輸出電阻、複數個所述電阻調整元件和該線路電阻一同構成一等效電阻。In one embodiment, after an external capacitor is coupled to the voltage output pin, there is a line resistance between the voltage output pin and the external capacitor. At this time, the output resistor, a plurality of the resistance adjustment elements Together with the line resistance, an equivalent resistance is formed.

在另一實施例中,在一外部電容耦接至一個所述等效電阻調整腳位之後,該等效電阻調整腳位和該外部電容之間具有一線路電阻,且該線路電阻、複數個所述電阻調整元件和該輸出電阻一同構成一等效電阻。In another embodiment, after an external capacitor is coupled to one of the equivalent resistance adjustment pins, there is a line resistance between the equivalent resistance adjustment pin and the external capacitor, and the line resistance, a plurality of The resistance adjustment element and the output resistance together form an equivalent resistance.

在一實施例中, 當所述線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化時,該等效電阻之電阻值係對應地在0.9歐姆至1.1歐姆之間變化。In one embodiment, when the resistance value of the line resistor varies from 0.1 ohm to 0.9 ohm, the resistance value of the equivalent resistor varies from 0.9 ohm to 1.1 ohm correspondingly.

在可行的實施例中,複數個所述等效電阻調整腳位之中的至少兩個係相互耦接。In a feasible embodiment, at least two of the plurality of equivalent resistance adjustment pins are coupled to each other.

本創作同時提供一種電源管理晶片,其特徵在於,該電源管理晶片包括如前所述本創作之供電電路。The present invention also provides a power management chip, characterized in that, the power management chip includes the power supply circuit of the present invention as described above.

本創作同時提供一種資訊處理裝置,其包含至少一如前所述本創作之電源管理晶片。The present invention also provides an information processing device comprising at least one power management chip of the present invention as described above.

在一實施例中,該資訊處理裝置是選自於由智慧型手機、智慧手錶、智慧手環、平板電腦、筆記型電腦、一體式電腦、門禁裝置、桌上型電腦、和工業電腦所組成群組之中的一種電子裝置。In one embodiment, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop computers, and industrial computers. An electronic device in a group.

為使  貴審查委員能進一步瞭解本創作之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your reviewers to further understand the structure, features, purposes, and advantages of the present creation, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

本創作提出包含至少一低壓差線性穩壓器的一高穩定性供電電路。其特徵在於,除了具有耦接所述低壓差線性穩壓器之一電壓輸出端的一輸出電阻以及耦接該輸出電阻的一電壓輸出腳位之外,本創作令該供電電路進一步具有複數個等效電阻調整腳位,其中各所述等效電阻調整腳位透過一電阻調整元件耦接該電壓輸出端。如此設計,將此供電電路應用至不同的電子裝置之中時,可依據補償需求而將一外部電容耦接至該電壓輸出腳位或是一個所述等效電阻調整腳位,從而利用所述電阻調整元件補償(調整)該外部電容和該電壓輸出腳位之間的一線路(寄生)電阻。依此設計,即使所述供電電路被應用在不同的電子產品之中而使該線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化,由該輸出電阻、複數個所述電阻調整元件和該線路電阻所一同構成的等效電阻仍舊可以被控制在0.9歐姆至1.1歐姆之間變化,從而能夠確保該供電電路的負回授環路的穩定性以及同時保證該供電電路的輸出電壓信號不出現毛刺。The present invention proposes a high stability power supply circuit including at least one low dropout linear voltage regulator. It is characterized in that, in addition to having an output resistor coupled to a voltage output end of the low dropout linear regulator and a voltage output pin coupled to the output resistor, the present invention makes the power supply circuit further have a plurality of etc. Effective resistance adjustment pins, wherein each of the equivalent resistance adjustment pins is coupled to the voltage output end through a resistance adjustment element. In this way, when the power supply circuit is applied to different electronic devices, an external capacitor can be coupled to the voltage output pin or an equivalent resistance adjustment pin according to compensation requirements, so as to utilize the The resistance adjustment element compensates (adjusts) a line (parasitic) resistance between the external capacitor and the voltage output pin. According to this design, even if the power supply circuit is applied in different electronic products and the resistance value of the line resistance varies between 0.1 ohm and 0.9 ohm, the output resistance, a plurality of the resistance adjustment elements and the The equivalent resistance formed by the line resistance can still be controlled to vary between 0.9 ohms and 1.1 ohms, thereby ensuring the stability of the negative feedback loop of the power supply circuit and ensuring that the output voltage signal of the power supply circuit does not appear. glitch.

圖5為本創作之一種高穩定性供電電路的電路拓樸結構圖。如圖5所示,該供電電路3包括至少一低壓差線性穩壓器(Low-dropout regulator, LDO)30,且該低壓差線性穩壓器30包括:一運算放大器31、一P型MOS電晶體32、包含一第一分壓電阻R1和一第二分壓電阻R2的一回授單元、以及一輸出電阻R3。本創作之該供電電路3主要包含於一電源管理晶片或一(直流)供電晶片之中,因此晶片本身會具有至少一電壓輸出腳位33,且該輸出電阻R3耦接於該低壓差線性穩壓器的一電壓輸出端和該電壓輸出腳位33之間。特別地,本創作令該供電電路3進一步包含複數個等效電阻調整腳位34~35,其中各所述等效電阻調整腳位R32~R33透過一電阻調整元件R M1~R M2耦接所述低壓差線性穩壓器30的該電壓輸出端。 FIG. 5 is a circuit topology structure diagram of a high-stability power supply circuit created by the present invention. As shown in FIG. 5 , the power supply circuit 3 includes at least one low-dropout regulator (LDO) 30 , and the LDO 30 includes: an operational amplifier 31 , a P-type MOS circuit The crystal 32, a feedback unit including a first voltage dividing resistor R1 and a second voltage dividing resistor R2, and an output resistor R3. The power supply circuit 3 of the present invention is mainly included in a power management chip or a (DC) power supply chip, so the chip itself has at least one voltage output pin 33, and the output resistor R3 is coupled to the low dropout linear stabilizer between a voltage output terminal of the voltage regulator and the voltage output pin 33 . In particular, in the present invention, the power supply circuit 3 further includes a plurality of equivalent resistance adjustment pins 34-35, wherein each of the equivalent resistance adjustment pins R32-R33 is coupled to the other through a resistance adjustment element R M1 -R M2 . the voltage output terminal of the low dropout linear regulator 30 .

利用積體電路製程製作本創作之供電電路3的晶片時,所述電阻調整元件R M1~R M2可以是金屬電阻器或多晶矽電阻器。並且,在一實施例中,所述電阻調整元件之電阻值係介於0.2歐姆至0.8歐姆之間,且各所述電阻調整元件R M1~R M2皆具有不同電阻值。舉例而言,供電電路3共包含四個電阻調整元件R M1~R M4,則四個電阻調整元件R M1~R M4的電阻值可以分別為0.2Ω、0.4Ω、0.6Ω、以及0.8Ω。 When the chip of the power supply circuit 3 of the present invention is fabricated by an integrated circuit process, the resistance adjustment elements R M1 -R M2 may be metal resistors or polysilicon resistors. Moreover, in one embodiment, the resistance value of the resistance adjustment element is between 0.2 ohm and 0.8 ohm, and each of the resistance adjustment elements R M1 -R M2 has different resistance values. For example, the power supply circuit 3 includes four resistance adjustment elements R M1 -R M4 in total, and the resistance values of the four resistance adjustment elements R M1 -R M4 may be 0.2Ω, 0.4Ω, 0.6Ω, and 0.8Ω, respectively.

應用包含此供電電路3的電源管理晶片或供電晶片時,通常會在該電壓輸出腳位33串接一外部電容C L。應知道,當應用在不同的電子產品之中時,如智慧型手機、平板電腦、平面顯示器等,所述晶片封裝方式也會有所差異,導致該電壓輸出腳位33至該外部電容C L之間的一線路電阻R4的電阻值也會跟著出現變化,變化範圍約為0.1~1Ω。由於本創作特別令該供電電路3進一步包含複數個所述等效電阻調整腳位34~35以及複數個所述電阻調整元件R M1~R M2,因此,如圖5所示,在外部電容C L耦接至電壓輸出腳位33之後,該輸出電阻R3、複數個所述電阻調整元件R M1~R M2和該線路電阻R4一同構成一等效電阻。此時,由於所述電阻調整元件R M1~R M2之電阻值係介於0.2歐姆至0.8歐姆之間,因此,即使在不同的應用中使得線路電阻R4的電阻值於0.1歐姆至0.9歐姆之間變化,該等效電阻的電阻值仍舊被控制0.9歐姆至1.1歐姆之間變化。 When applying a power management chip or a power supply chip including the power supply circuit 3 , an external capacitor CL is usually connected in series with the voltage output pin 33 . It should be known that when applied to different electronic products, such as smart phones, tablet computers, flat panel displays, etc., the chip packaging method will also be different, resulting in the voltage output pin 33 to the external capacitor CL The resistance value of a line resistance R4 between them will also change accordingly, and the change range is about 0.1~1Ω. Because the present invention specifically makes the power supply circuit 3 further include a plurality of the equivalent resistance adjusting pins 34-35 and a plurality of the resistance adjusting elements R M1 -R M2 , therefore, as shown in FIG. 5, the external capacitor C After L is coupled to the voltage output pin 33 , the output resistor R3 , a plurality of the resistance adjusting elements R M1 ˜R M2 and the line resistor R4 together form an equivalent resistor. At this time, since the resistance values of the resistance adjustment elements R M1 ˜R M2 are between 0.2 ohms to 0.8 ohms, even in different applications, the resistance value of the line resistor R4 is set between 0.1 ohms and 0.9 ohms. The resistance value of the equivalent resistance is still controlled to vary between 0.9 ohms and 1.1 ohms.

請重複參閱圖3和圖5,其中,圖5所標示之Y點對應於圖3所標示之主極點p1,X點則對應於次極點p2,且輸出電阻R3、線路電阻R4以及外部電容C L形成對應於圖3所標示之零點z1。圖6為圖5之具有至少一低壓差線性穩壓器的供電電路的波德圖。在實務操作方面,增加R3+R4的阻值是有機會達成可接受的頻率補償從而提升該低壓差線性穩壓器30的相位裕度(phase margin, PM)。可惜的是,如圖4所示,當負載電流I load瞬間變大或變小時,由該低壓差線性穩壓器30所輸出的輸出電壓的信號上會出現毛刺,其中該毛刺的振幅和(R 3+R 4)*I load成相關。因此,本創作利用複數個所述電阻調整元件R M1~R M2和該輸出電阻R3以及和該線路電阻R4一同構成一等效電阻。如此,即使在不同的應用中使得線路電阻R4的電阻值於0.1歐姆至0.9歐姆之間變化(即,變化電阻值變化量高達0.8Ω),還是可以將等效電阻的電阻值控制在0.9歐姆至1.1歐姆之間,即將該電阻值變化量調降至低於0.2Ω的範圍內。依此設計,如圖6所示,有機會調整零點z1而使其與次極點p2重和,即,利用零點z1補償極點,進而大幅提升該低壓差線性穩壓器30的相位裕度,實現理想補償。如此,便能夠能夠確保該供電電路的負回授環路的穩定性,且同時保證該供電電路的輸出電壓信號不出現毛刺。 Please refer to FIG. 3 and FIG. 5 repeatedly, wherein the Y point indicated in FIG. 5 corresponds to the main pole p1 indicated in FIG. 3 , the X point corresponds to the secondary pole p2 , and the output resistor R3 , the line resistor R4 and the external capacitor C L forms a zero point z1 corresponding to that indicated in FIG. 3 . FIG. 6 is a Bode plot of the power supply circuit of FIG. 5 having at least one low dropout linear regulator. In practical operation, increasing the resistance value of R3+R4 has the opportunity to achieve acceptable frequency compensation and improve the phase margin (PM) of the low dropout linear regulator 30 . Unfortunately, as shown in FIG. 4, when the load current I load increases or decreases instantaneously, a burr will appear on the output voltage signal output by the low dropout linear regulator 30, wherein the amplitude of the burr and ( R 3 +R 4 )*I load is correlated. Therefore, the present invention utilizes a plurality of the resistance adjustment elements R M1 ˜R M2 , the output resistance R3 and the line resistance R4 to form an equivalent resistance together. In this way, even if the resistance value of the line resistor R4 is changed between 0.1 ohm and 0.9 ohm in different applications (that is, the variation of the resistance value is as high as 0.8 ohm), the resistance value of the equivalent resistance can still be controlled at 0.9 ohm to 1.1 ohms, that is, the change in the resistance value is adjusted to a range below 0.2Ω. According to this design, as shown in FIG. 6, there is an opportunity to adjust the zero point z1 to make it re-sum with the secondary pole p2, that is, the zero point z1 is used to compensate the pole, thereby greatly improving the phase margin of the low dropout linear regulator 30, achieving Ideal compensation. In this way, the stability of the negative feedback loop of the power supply circuit can be ensured, and at the same time, the output voltage signal of the power supply circuit can be guaranteed not to have glitches.

圖7為本創作之一種高穩定性供電電路的電路拓樸結構圖。如圖7所示,應用在不同的電子產品或晶片封裝方式變更時,也可以選擇將外部電容C L耦接至一個所述等效電阻調整腳位34,此時該等效電阻調整腳位34和該外部電容C L之間具有一線路電阻R4,且該線路電阻R4、複數個所述電阻調整元件R M1~R M2和該輸出電阻R3一同構成一等效電阻。簡單地說,線路電阻R4會因為應用方案改變而跟著變化,此時可以選擇將外部電容C L耦接至一個等效電阻調整腳位34,而非耦接至習慣使用的電壓輸出腳位33。 FIG. 7 is a circuit topology structure diagram of a high-stability power supply circuit created by the present invention. As shown in FIG. 7 , when different electronic products or chip packaging methods are changed, the external capacitor CL can also be selected to be coupled to one of the equivalent resistance adjustment pins 34 . At this time, the equivalent resistance adjustment pins There is a line resistance R4 between 34 and the external capacitor CL , and the line resistance R4, a plurality of the resistance adjustment elements RM1 ˜RM2 and the output resistance R3 together form an equivalent resistance. Simply put, the line resistance R4 will change as the application scheme changes. At this time, the external capacitor CL can be selected to be coupled to an equivalent resistance adjustment pin 34 instead of the customary voltage output pin 33. .

圖8為本創作之一種高穩定性供電電路的電路拓樸結構圖。如圖8所示,應用在不同的電子產品或者晶片封裝方式變更之時,可以將外部電容C L耦接至該電壓輸出腳位33,且同時令複數個所述等效電阻調整腳位34~35之中的至少兩個係相互耦接,如此可以更進一步降地所述電阻值變化量,提升負回授環路的穩定度。 FIG. 8 is a circuit topology structure diagram of a high-stability power supply circuit created by the present invention. As shown in FIG. 8 , when different electronic products or chip packaging methods are changed, an external capacitor CL can be coupled to the voltage output pin 33 , and at the same time, a plurality of the equivalent resistance adjustment pins 34 can be connected. At least two of ~35 are coupled to each other, so that the variation of the resistance value can be further reduced, and the stability of the negative feedback loop can be improved.

如此,上述已完整且清楚地說明本創作之一種高穩定性供電電路;並且,經由上述可得知本創作具有下列優點:In this way, the above has completely and clearly described a high-stability power supply circuit of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1)本創作揭示一種高穩定性供電電路,其具有至少一低壓差線性穩壓器、耦接所述低壓差線性穩壓器之一電壓輸出端的一輸出電阻、以及耦接該輸出電阻的一電壓輸出腳位;其特徵在於,所述供電電路進一步具有複數個等效電阻調整腳位,且各所述等效電阻調整腳位透過一電阻調整元件耦接所述低壓差線性穩壓器的該電壓輸出端。在一外部電容耦接至該電壓輸出腳位之後,該電壓輸出腳位和該外部電容之間係具有一線路電阻,此時該輸出電阻、複數個所述電阻調整元件和該線路電阻一同構成一等效電阻。如此設計,即使所述供電電路被應用在不同的電子產品之中而使該線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化,該等效電阻的電阻值仍舊可以被控制在0.9歐姆至1.1歐姆之間變化,從而能夠確保該供電電路所具有之運算放大器的負回授環路的穩定性以及同時保證輸出電壓信號不出現毛刺。(1) The present invention discloses a high-stability power supply circuit, which has at least one low-dropout linear regulator, an output resistor coupled to a voltage output end of the low-dropout linear regulator, and an output resistor coupled to the output resistor a voltage output pin; characterized in that the power supply circuit further has a plurality of equivalent resistance adjustment pins, and each of the equivalent resistance adjustment pins is coupled to the low-dropout linear regulator through a resistance adjustment element of this voltage output. After an external capacitor is coupled to the voltage output pin, there is a line resistance between the voltage output pin and the external capacitor. At this time, the output resistance, a plurality of the resistance adjustment elements and the line resistance are formed together an equivalent resistance. With this design, even if the power supply circuit is used in different electronic products and the resistance value of the line resistance varies from 0.1 ohm to 0.9 ohm, the resistance value of the equivalent resistance can still be controlled from 0.9 ohm to 0.9 ohm The change between 1.1 ohms can ensure the stability of the negative feedback loop of the operational amplifier of the power supply circuit and at the same time ensure that the output voltage signal does not appear glitches.

(2)本創作同時提供一種電源管理晶片,其特徵在於,該電源管理晶片包括如前所述本創作之供電電路。(2) The present invention also provides a power management chip, characterized in that, the power management chip includes the power supply circuit of the present invention as described above.

(3)本創作同時提供一種資訊處理裝置,其包含至少一如前所述本創作之電源管理晶片。其中,該資訊處理裝置是選自於由智慧型手機、智慧手錶、智慧手環、平板電腦、筆記型電腦、一體式電腦、門禁裝置、桌上型電腦、和工業電腦所組成群組之中的一種電子裝置。(3) The present invention also provides an information processing device comprising at least one power management chip of the present invention as described above. Wherein, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop computers, and industrial computers of an electronic device.

必須加以強調的是,前述本案所揭示者乃為較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先創作合於實用,確實符合新型之專利要件,懇請  貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。In summary, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first creation is suitable for practical use, and it does meet the requirements of a new type of patent. Society is to pray for the best.

1a:顯示驅動晶片 3a:供電晶片 31a:運算放大器 32a:P型MOS電晶體 33a:電壓輸出腳位 4a:顯示面板 5a:COF電路板 6a:軟性電路板 R1a:第一分壓電阻 R2a:第二分壓電阻 R3a:輸出電阻 R4a:線路電阻 C La:外部電容 3:供電電路 30:低壓差線性穩壓器 31:運算放大器 32:P型MOS電晶體 33:電壓輸出腳位 34:等效電阻調整腳位 35:等效電阻調整腳位 R1:第一分壓電阻 R2:第二分壓電阻 R3:輸出電阻 R4:線路電阻 RM1:電阻調整元件 RM2:電阻調整元件 C L:外部電容 1a: Display driver chip 3a: Power supply chip 31a: Operational amplifier 32a: P-type MOS transistor 33a: Voltage output pin 4a: Display panel 5a: COF circuit board 6a: Flexible circuit board R1a: First voltage dividing resistor R2a: No. 1 Two voltage divider resistor R3a: Output resistor R4a: Line resistance C La : External capacitor 3: Power supply circuit 30: Low dropout linear regulator 31: Operational amplifier 32: P-type MOS transistor 33: Voltage output pin 34: Equivalent Resistance adjustment pin 35: Equivalent resistance adjustment pin R1: First voltage dividing resistor R2: Second voltage dividing resistor R3: Output resistor R4: Line resistance RM1: Resistance adjustment element RM2: Resistance adjustment element CL : External capacitor

圖1為習知的一種智慧型手機之顯示裝置的架構圖; 圖2為習知的包含至少一低壓差線性穩壓器的一供電晶片的電路拓樸結構圖; 圖3為圖2之具有至少一低壓差線性穩壓器的供電晶片的波德圖; 圖4為圖2之供電晶片的一輸出電壓和一負載電流的工作時序圖; 圖5為本創作之一種高穩定性供電電路的電路拓樸結構圖; 圖6為圖5之具有至少一低壓差線性穩壓器的供電電路的波德圖; 圖7為本創作之一種高穩定性供電電路的電路拓樸結構圖;以及 圖8為本創作之一種高穩定性供電電路的電路拓樸結構圖。 FIG. 1 is a schematic diagram of a display device of a conventional smart phone; 2 is a circuit topology diagram of a conventional power supply chip including at least one low dropout linear voltage regulator; 3 is a Bode plot of the power supply chip of FIG. 2 having at least one low dropout linear regulator; FIG. 4 is a working timing diagram of an output voltage and a load current of the power supply chip of FIG. 2; Figure 5 is a circuit topology structure diagram of a high-stability power supply circuit created by the present invention; 6 is a Bode plot of the power supply circuit of FIG. 5 having at least one low dropout linear regulator; FIG. 7 is a circuit topology diagram of a high-stability power supply circuit of the present creation; and FIG. 8 is a circuit topology structure diagram of a high-stability power supply circuit created by the present invention.

3:供電電路 3: Power supply circuit

30:低壓差線性穩壓器 30: Low dropout linear regulator

31:運算放大器 31: Operational Amplifier

32:P型MOS電晶體 32: P-type MOS transistor

33:電壓輸出腳位 33: Voltage output pin

34:等效電阻調整腳位 34: Equivalent resistance adjustment pin

35:等效電阻調整腳位 35: Equivalent resistance adjustment pin

R1:第一分壓電阻 R1: The first voltage divider resistor

R2:第二分壓電阻 R2: The second voltage divider resistor

R3:輸出電阻 R3: output resistance

R4:線路電阻 R4: Line resistance

RM1:電阻調整元件 R M1 : Resistance adjustment element

RM2:電阻調整元件 R M2 : Resistance adjustment element

CL:外部電容 C L : External capacitor

Claims (10)

一種供電電路,其具有至少一低壓差線性穩壓器、耦接所述低壓差線性穩壓器之一電壓輸出端的一輸出電阻、以及耦接該輸出電阻的一電壓輸出腳位;其特徵在於,所述供電電路進一步具有複數個等效電阻調整腳位以及複數個電阻調整元件,其中各個所述等效電阻調整腳位透過至少一電阻調整元件耦接所述低壓差線性穩壓器的該電壓輸出端。 A power supply circuit has at least one low dropout linear regulator, an output resistor coupled to a voltage output end of the low dropout linear regulator, and a voltage output pin coupled to the output resistor; it is characterized in that , the power supply circuit further has a plurality of equivalent resistance adjustment pins and a plurality of resistance adjustment elements, wherein each of the equivalent resistance adjustment pins is coupled to the low dropout linear regulator through at least one resistance adjustment element. voltage output. 如請求項1所述之供電電路,其中,所述電阻調整元件為選自於由金屬電阻器和多晶矽電阻器所組成群組之中的一種被動元件。 The power supply circuit of claim 1, wherein the resistance adjusting element is a passive element selected from the group consisting of metal resistors and polysilicon resistors. 如請求項2所述之供電電路,其中,所述電阻調整元件之電阻值係介於0.2歐姆至0.8歐姆之間,且各所述電阻調整元件皆具有不同電阻值。 The power supply circuit of claim 2, wherein the resistance value of the resistance adjustment element is between 0.2 ohm and 0.8 ohm, and each of the resistance adjustment elements has different resistance values. 如請求項2所述之供電電路,其中,在一外部電容耦接至該電壓輸出腳位之後,該電壓輸出腳位和該外部電容之間係具有一線路電阻,此時該輸出電阻、複數個所述電阻調整元件和該線路電阻一同構成一等效電阻。 The power supply circuit of claim 2, wherein after an external capacitor is coupled to the voltage output pin, there is a line resistance between the voltage output pin and the external capacitor. At this time, the output resistance, the complex number Each of the resistance adjustment elements and the line resistance together constitute an equivalent resistance. 如請求項2所述之供電電路,其中,在一外部電容耦接至一個所述等效電阻調整腳位之後,該等效電阻調整腳位和該外部電容之間具有一線路電阻,且該線路電阻、複數個所述電阻調整元件和該輸出電阻一同構成一等效電阻。 The power supply circuit of claim 2, wherein after an external capacitor is coupled to one of the equivalent resistance adjustment pins, there is a line resistance between the equivalent resistance adjustment pins and the external capacitor, and the The line resistance, a plurality of the resistance adjustment elements and the output resistance together form an equivalent resistance. 如請求項4或5所述之供電電路,其中,當所述線路電阻的電阻值於0.1歐姆至0.9歐姆之間變化時,該等效電阻之電阻值係對應地在0.9歐姆至1.1歐姆之間變化。 The power supply circuit according to claim 4 or 5, wherein when the resistance value of the line resistance varies between 0.1 ohm and 0.9 ohm, the resistance value of the equivalent resistor is correspondingly between 0.9 ohm and 1.1 ohm. change between. 如請求項2所述之供電電路,其中,複數個所述等效電阻調整腳位之中的至少兩個係相互耦接。 The power supply circuit of claim 2, wherein at least two of the plurality of equivalent resistance adjustment pins are coupled to each other. 一種電源管理晶片,其特徵在於,該電源管理晶片包括如請求項1至請求項7之中任一項所述之供電電路。 A power management chip, characterized in that the power management chip includes the power supply circuit described in any one of claim 1 to claim 7. 一種資訊處理裝置,其包含至少一如請求項8所述之電源管理晶片。 An information processing device comprising at least one power management chip as described in claim 8. 如請求項9所述之資訊處理裝置,其中,該資訊處理裝置為選自於由智慧型手機、智慧手錶、智慧手環、平板電腦、筆記型電腦、一體式電腦、門禁裝置、桌上型電腦、和工業電腦所組成群組之中的一種電子裝置。The information processing device according to claim 9, wherein the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop An electronic device in the group consisting of computers, and industrial computers.
TW111203840U 2020-12-25 2020-12-25 High stability power supply circuit, power management chip and information processing device TWM629645U (en)

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