TWM627599U - Package structure - Google Patents

Abstract

A package structure includes a substrate, a stacked structure, a plurality of conductive bumps and a heat dissipation filler. The stacked structure includes a plurality of chips stacked over the substrate. The conductive bumps are disposed between the stacked structure and the substrate. The heat dissipation filler is filled between the stacked structure and the substrate or between the chips. The heat dissipation filler includes a plurality of thermal conductive particles.

Description

Package structure

The novel creation relates to a package structure with heat-dissipating filling glue.

Semiconductor devices are used in various electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). To a large extent, the increase in integration density stems from the continued shrinking of the minimum feature size, which enables more components to be integrated into a given area

With the further development of semiconductor technology, stacked semiconductor devices (eg, three dimensional integrated circuits (3DICs)) have emerged as another effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits, such as logic circuits, memory circuits, processor circuits, etc., are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be mounted or stacked on top of each other to further reduce the form factor of the semiconductor device. One of the three-dimensional integrated circuits is stacked packaging A package-on-package (POP) device in which a die is packaged and then packaged with another packaged die or dies. However, due to the high thermal resistance of the above-mentioned stacked structure, it is easy to make it difficult for the heat generated by the lower chip to be conducted to the outside through the upper chip, which easily leads to heat accumulation and reduces the heat dissipation efficiency of the package structure.

The novel creation provides a package structure, which includes a substrate, a stack structure, a plurality of first conductive bumps, and a heat-dissipating filler. The stacked structure includes a plurality of wafers stacked on a substrate. The first conductive bumps are disposed between the stacked structure and the substrate. The heat-dissipating filler is filled between the substrate and the stacked structure or between a plurality of chips, wherein the heat-dissipating filler includes a plurality of thermally conductive particles.

Based on the above, the package structure created by the present invention mixes the underfill with high fluidity into the thermally conductive particles, and fills it between the substrate and the stacked structure and/or among the plurality of chips in the stacked structure. In this way, the heat-dissipating filler can not only have the fluidity of the underfill, so that it can easily penetrate between the chips of the stacked structure and/or between the substrate and the stacked structure by capillary action, and the thermally conductive particles can improve the thermal conductivity of the heat-dissipating filler. , so that the heat generated by the chip can be conducted and dissipated smoothly, thereby improving the heat dissipation efficiency of the package structure.

100: Package structure

110: Substrate

120: Stacked Structure

122: wafer, first wafer

124: wafer, second wafer

126, 128: Package

130: first conductive bump

140: Second conductive bump

150: heat dissipation filler

160: Connector

h1: spacing

R1: Central area

R2: Peripheral area

FIG. 1 is a cross-sectional view of a package structure according to an embodiment of the present invention. intention.

FIG. 2 is a schematic diagram of a manufacturing process of an intermediate stage of a packaging structure according to an embodiment of the present invention.

3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention.

FIG. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a manufacturing process of an intermediate stage of a packaging structure according to an embodiment of the present invention. Referring first to FIG. 1 , in this embodiment, the package structure 100 includes a substrate 110 , a stack structure 120 , a plurality of first conductive bumps 130 and a heat dissipation filler 150 . In some embodiments, the substrate 110 may be a package substrate such as a printed circuit board (PCB), an interposer, or a flexible printed circuit board (FPCB), which may include a die side and a pad side, wherein, The die side is used to carry the stacked structure 120 including, for example, a chip, and the pad side can be coupled to external devices or systems through a plurality of connectors 160 (eg, solder balls or bumps, etc.). An "external device or system" as used herein may refer to a device or system that is external or close to the external for a handheld electronic device such as a wireless communicator. In one embodiment, the substrate 110 may also be a wafer, and its material may include glass, silicon (eg, silicon wafer), silicon oxide, metal patch, ceramic material, and the like. The new creation is not limited to this.

In some embodiments, the stacked structure 120 is disposed on the die side of the substrate 110 and includes a plurality of wafers stacked on top of each other. Specifically, the stack structure 120 may include It includes at least one first chip 122 and at least one second chip 124 . Although only one first wafer 122 and one second wafer 124 are shown in FIG. 1 , those skilled in the art should understand that the stack structure 120 may include more than two wafers. In this embodiment, the first wafer 122 is disposed on the substrate 110 and can be used as a master wafer, such as a processing wafer. The second chip 124 can be stacked on the first chip 122 and can serve as a slave chip. In this embodiment, the first wafer 122 may include a processing (logic) wafer, and the second wafer 124 may include a memory wafer.

For example, the first chip (processing chip) 122 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC) chip) or a system-on-chip (SoC), a graphics processing unit (graphics processing unit) ; GPU), the like, or a combination thereof. A process (logic) wafer may include logic circuits integrated on its semiconductor substrate. The second chip (memory chip) 124 may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, flash memory circuits, magnetic random access memory (MAG) circuits integrated on its semiconductor substrate Memory (MRAM) circuits, Resistive Random Access Memory (ReRAM) circuits, Ferroelectric Random Access Memory (FeRAM) circuits, or Phase Change Random Access Memory (PcRAM) circuits. In one embodiment, the first chip 122, which is a handle chip, may include a plurality of memory cells for storing data. However, these memory cells are not required. Additionally, the first chip 122 may include control circuitry for controlling memory operations of the second chip 124 .

In some embodiments, the first wafer 122 and the second wafer 124 may be vertically stacked on the substrate 110 . In one embodiment, the first wafer 122 is opposite to the second The stacking between wafers 124 is asymmetric. In other words, the central axes of the first wafer 122 and the second wafer 124 may not overlap. Also, the first wafer 122 and the second wafer 124 may have different shapes. In this embodiment, the second wafer 124 may be disposed on the first wafer 122 and may be approximately equal to or smaller than the first wafer 122 in size. When the second wafer 124 is disposed on the first wafer 122 , the thickness of the first wafer 122 may be approximately equal to or greater than the thickness of the second wafer 124 .

In some embodiments, the stacked structure 120 may be electrically connected to the substrate 110 through a plurality of first conductive bumps 130 disposed between the stacked structure 120 and the substrate 110 . In this embodiment, the first conductive bumps 130 may include Controlled Collapse Chip Connection (C4) bumps, micro-bumps or other suitable connectors. The material of the C4 bump may include copper, tin, lead-tin (pb-Sn) compound, a combination thereof, or other suitable materials, which are not limited in this embodiment. In some embodiments, the plurality of chips 122 and 124 of the stacked structure 120 may also be electrically connected through the plurality of second conductive bumps 140 . That is, the package structure 100 may further include a plurality of second conductive bumps 140 disposed between the plurality of chips 122 and 124 . In one embodiment, the second conductive bumps 140 may include micro bumps, C4 bumps, or other suitable connectors. The material of the microbumps may be selected from gold, copper, nickel, silver, combinations thereof, or other suitable materials.

In some embodiments, the first wafer 122 may include a central region R1 and a peripheral region R2 surrounding the central region R1, and the second conductive bumps 140 are disposed on the peripheral region R2. Further, the second conductive bumps 140 are only disposed in the peripheral region R2 and not disposed in the central region R1 of the first wafer 122 . Furthermore, in an implementation For example, the vertical distance h1 between the wafers 122 and 124 is about 0.1 mm to 0.25 mm. Under such a configuration, since the vertical distance h1 between the chips 122 and 124 of the stacked structure 120 is extremely small, if only a polymer thermal interface material (TIM) is used to coat the chip surface or the device interface to To help dissipate heat, due to the low fluidity of TIM, it is difficult to fully fill the gap between the wafers 122 and 124 (for example, the central region R1 cannot be filled and there is an air gap), thus resulting in the gap between the wafers 122 and 124 . The thermal resistance of the chips 122 and 124 cannot be effectively reduced, and the heat generated by the chips 122 and 124 cannot be effectively transferred to the outside.

FIG. 2 is a schematic diagram of a manufacturing process of an intermediate stage of a packaging structure according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 , in view of this, in this embodiment, the heat-dissipating filler 150 is filled between the substrate 110 and the stack structure 120 and/or between the plurality of chips 122 and 124 to encapsulate the first conductive The bumps 130 and/or the second conductive bumps 140 fill the gaps therebetween. In this embodiment, the heat-dissipating filler 150 may include a plurality of thermally conductive particles mixed into an insulating base, wherein the material of the insulating base of the heat-dissipating filler 150 includes epoxy or other suitable insulating sealing materials . Specifically, the insulating base of the heat-dissipating filler 150 may include an underfill base material. The thermal conductivity of the thermally conductive particles is substantially equal to or greater than 5 W/mk. In one embodiment, the thermally conductive particles may be diamond particles or other particles containing carbon. In other embodiments, the thermally conductive particles may also include metal particles (eg, silver, copper), ceramic particles, or other thermally conductive particles with high thermal conductivity.

In this configuration, the heat-dissipating filler 150 mixed with thermally conductive particles can have the fluidity of underfill, so that it can easily penetrate into the crystals of the stacked structure 120 by capillary action. Between the sheets 122 , 124 and/or between the substrate 110 and the stacked structure 120 . In this embodiment, the heat-dissipating filler can be filled in the central region R1 and the peripheral region R2 , thereby removing or at least reducing the air gap existing between the chips 122 and 124 and reducing the thermal resistance between the chips 122 and 124 . Similarly, the heat-dissipating filler can also sufficiently fill the space between the substrate 110 and the stacked structure 120 to reduce the thermal resistance between the substrate 110 and the stacked structure 120 . In addition, the thermally conductive particles can improve the thermal conductivity of the heat-dissipating filler 150, so that the heat generated by the chips 122 and 124 can be smoothly conducted upward through the heat-dissipating filler 150 to, for example, a heat-dissipating fin disposed above, and then dissipated by, for example, a fan. The device dissipates heat from the device, so the heat dissipation efficiency of the package structure 100 can be improved. Experiments have confirmed that the package structure 100 filled between the chips 122 and 124 of the stacked structure 120 and between the substrate 110 and the stacked structure 120 with the heat-dissipating filler 150 mixed with thermally conductive particles can dissipate heat for 60 minutes. The temperature of the structure 100 is reduced by more than 4 degrees.

In some embodiments, the step of filling the thermal paste 150 may be performed together after the stacked structure 120 is bonded to the substrate 110 via the conductive bumps. For example, the bonded stacked structure 120 and the substrate 110 may be heated to the temperature of the filling process. At this time, the above-mentioned bonding structure can be placed horizontally or obliquely, and then the heat-dissipating filler 150 can be dispensed in the central area R1 by the dispensing tool 200 . The adhesive is dispensed on the peripheral region R2, so that the heat-dissipating filler is fully filled in the central region R1 and the peripheral region R2 between the chips 122 and 124. The same dispensing method can also be used to fill the heat dissipation filler 150 between the substrate 110 and the stacked structure 120 . After that, the package structure is heated to the curing temperature of the heat-dissipating filler 150 to cure the heat-dissipating filler 150, and the package structure can be substantially completed. Construct 100 production.

3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention. It must be noted here that the package structure 100 of this embodiment is similar to the package structure 100 of FIG. 1 . Therefore, this embodiment uses the component numbers and parts of the foregoing embodiments, and the same numbers are used to indicate the same or similar components. elements, and the description of the same technical content is omitted. Please refer to FIG. 1 and FIG. 3 , the following will describe the differences between the package structure 100 of the present embodiment and the package structure 100 of FIG. 1 .

In this embodiment, the stack structure 120 may be formed by stacking a plurality of packages 126 and 128 on each other, and the packages 126 and 128 may each include at least one chip. In this embodiment, the package 126 can include the chip 122, and the package 128 can package the chip 124. Of course, this embodiment is not limited thereto. In this embodiment, the package 126 may further include an encapsulation compound covering the chip 122 , a conductive column penetrating the encapsulation compound, and a reconfigured circuit layer disposed on the chip 122 and the encapsulation compound. The package 128 may include a plurality of memory chips stacked on top of each other and encapsulated with an encapsulant. Of course, this embodiment is only used for illustration, and the stack structure 120 may be formed by stacking packages in various forms. In this way, the heat-dissipating filler 150 mixed with thermally conductive particles can be filled between the substrate 110 and the stacked structure 120 and/or between the plurality of packages 126 and 128 to cover the first conductive bumps 130 and/or the first conductive bumps 130 and/or the second The two conductive bumps 140 fill the space between them.

To sum up, the package structure created by the present invention mixes the underfill with high fluidity into the thermally conductive particles, and fills it between the substrate and the stacked structure and/or among the plurality of chips in the stacked structure. In this way, the heat-dissipating filler can have the fluidity of the underfill, making it easy to use capillary action to penetrate between the chips in the stacked structure and/or Or between the substrate and the stacked structure, and the thermally conductive particles can improve the thermal conductivity of the heat-dissipating filler, so that the heat generated by the chip can be conducted and dissipated smoothly, thereby improving the heat-dissipation efficiency of the package structure.

100: Package structure

110: Substrate

120: Stacked Structure

122: wafer, first wafer

124: wafer, second wafer

130: first conductive bump

140: Second conductive bump

150: heat dissipation filler

160: Connector

h1: spacing

R1: Central area

R2: Peripheral area

Claims (11)

A package structure including: a substrate; a stack structure including a plurality of chips stacked on the substrate; a plurality of first conductive bumps disposed between the stacked structure and the substrate; and A heat-dissipating filler is filled between the substrate and the stacked structure or between the plurality of chips, wherein the heat-dissipating filler includes a plurality of thermally conductive particles. The package structure of claim 1, wherein the plurality of chips include a handle chip disposed on the substrate and a memory chip stacked on the handle chip. The package structure of claim 1, wherein the thermal conductivity of the plurality of thermally conductive particles is substantially equal to or greater than 5W/mk. The package structure of claim 1, wherein the thermally conductive particles comprise diamond particles. The package structure according to claim 1, wherein the material of the heat dissipation filler further comprises epoxy resin. The package structure of claim 1, wherein a vertical distance between the plurality of chips is substantially between 0.1 mm and 0.25 mm. The package structure of claim 1, wherein the plurality of first conductive bumps comprise a plurality of Controlled Collapse Chip Connection (C4) bumps. The package structure of claim 1, further comprising a plurality of second conductive bumps disposed between the plurality of chips. The package structure of claim 8, wherein the plurality of second conductive bumps comprise a plurality of micro bumps. The package structure of claim 8, wherein the plurality of chips comprise a handle chip disposed on the substrate and a memory chip stacked on the handle chip, and the plurality of second conductive bumps are disposed on the handle A peripheral area of the wafer, and the peripheral area surrounds a central area of the handle wafer. The package structure of claim 10, wherein the heat dissipation filler is filled in the peripheral region and the central region.

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