TWM627184U - Semiconductor package structure - Google Patents

Abstract

The present invention discloses a semiconductor package structure, which includes a substrate, a first semiconductor chip, a second semiconductor chip, and a package, wherein the first semiconductor chip and the second semiconductor chip are electrically arranged on the substrate, and the package The body completely covers the semiconductor chip bodies, wherein the first semiconductor chip can be further used to control the action or not of the second semiconductor chip.

Description

Semiconductor package structure

The novel creation relates to a packaging structure, in particular to a semiconductor packaging structure.

With the development of science and technology, the development of products used in information, communication and consumer electronic products in recent years has also moved towards the trend of high density, high performance, lightness, thinness, shortness and smallness. , such as a single light-emitting diode (Light Emitted Diode, LED), small signal transistors, resistors, capacitors, inductors, or metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and so on are widely used in various fields, in order to meet the requirements of light, thin, short and high density. A common technical means for electronic devices at present, usually, each semiconductor element packaging module needs to be packaged one by one in advance, and then arranged on the printed circuit board. In addition, components such as transistors on the driving circuit board also need to be packaged before being disposed on the driving circuit board. As a result, the cost of packaging each component is very wasteful, and miniaturization cannot be achieved, and the current common Wafer Level Chip Scale Package (WLCSP) process is expensive to manufacture. If the surface mount technology is used The (Surface Mount Technology, SMT) process needs to consider whether each component can be soldered accurately and whether it can achieve miniaturization. As mentioned above, how to provide a semiconductor packaging structure that can solve the above problems is one of the current important issues.

In view of the above problems, the present invention is directed to a semiconductor packaging structure that can package semiconductor chips of different properties in the same package to save packaging process costs.

According to an embodiment of the present invention, the present invention mainly provides a semiconductor package structure, which includes a substrate, a first semiconductor chip, a second semiconductor chip, and a package, wherein the substrate has a mounting surface, and the first semiconductor chip and the first semiconductor chip have a mounting surface. The two semiconductor chips are arranged on the mounting surface of the substrate, and the package body completely covers the semiconductor chip bodies. After the second semiconductor chip and the first semiconductor chip are electrically connected to each other, the first semiconductor chip can be further used to control The opening and closing of the second semiconductor chip.

Preferably, the first semiconductor wafer can be a field effect transistor or a metal oxide semiconductor field effect transistor.

Preferably, the second semiconductor chip can be a light emitting diode or a laser diode.

Preferably, the second semiconductor wafer can be stacked on the first semiconductor wafer.

Preferably, a groove is formed on the mounting surface, and the first semiconductor chip is disposed in the groove.

Based on the above, the first semiconductor chip and the second semiconductor chip are respectively disposed on the substrate according to the semiconductor package structure created in the present invention, and are further located in the same package body. Compared with the prior art, the package size can be reduced. Process cost and space saving at the same time.

To sum up, the present creation will be described in detail below with specific embodiments, and the following embodiments are for illustrative purposes only, and do not limit the protection scope of the present creation. Those skilled in the art will readily understand that various non-critical parameters can be varied or adjusted to produce substantially the same result.

10: Semiconductor packaging structure

101: Substrate

1011: Mounting Surface

1012: Groove

102: First semiconductor wafer

103: Second semiconductor wafer

104: Package body

1041: The first package body

1042: the second package

1043: light-emitting surface

Figure 1 is a schematic diagram (1) of the semiconductor package structure of this novel creation.

FIG. 2 is a schematic diagram (2) of the semiconductor package structure of this novel creation.

FIG. 3 is a schematic diagram of a semiconductor package structure according to an embodiment of the novel invention.

FIG. 4 is a schematic diagram of a semiconductor package structure according to another embodiment of the novel invention.

The aforementioned and other technical contents, features and effects of the novel creation will be clearly presented in the following detailed description of each embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the attached drawings. Therefore, the directional terms used are intended to illustrate, rather than limit, the present invention. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

The semiconductor package structure according to the preferred embodiment of the present invention will be described below with reference to the related drawings, wherein the same components will be described with the same reference symbols. Please refer to FIG. 1 and FIG. 2 at the same time, which are schematic diagrams (1) and (2) of the semiconductor package structure of the novel creation. The semiconductor package structure 10 includes a substrate 101 , a first semiconductor chip 102 , a second semiconductor chip 103 and A package body 104, wherein the first semiconductor chip 102 and the second semiconductor chip 103 are located in the same package body 104. In this embodiment, the substrate 101 is not limited, and the substrate 101 can be a printed circuit board, a metal substrate, Ceramic substrate, quartz substrate, sapphire substrate or glass fiber substrate (such as FR-4, FR-5, G-10, G-11, etc.), in this embodiment, the substrate 101 is made of a thin and light printed circuit board, A circuit layer (not shown) is laid on the mounting surface 1011 of the substrate 101 , and the package body 104 is made of a transparent or light-transmitting material, such as transparent epoxy resin, acrylic resin, or silicone ( silicone), etc., not limited to this, the first semiconductor chip 102 described in this embodiment can be a field effect transistor, a metal oxide semiconductor field effect transistor, a junction field effect transistor, etc., but not Limited to this, and in this embodiment, the second semiconductor chip 103 may include a III-V group compound semiconductor or a II-VI group compound semiconductor, such as gallium nitride (GaN), Indium Nitride (InN), Aluminum Nitride (AlN), Indium Gallium Nitride (InGaN), Aluminum Gallium Nitride (AlGaN), Aluminum Indium Gallium Nitride (InAlGaN), Aluminum Indium Nitride (AlInN), Aluminum Arsenide Gallium (AlGaAs), Indium Gallium Arsenide (InGaAs), Aluminum Indium Gallium Arsenide (AlInGaAs), Gallium Phosphide (GaP), Aluminum Gallium Phosphide (AlGaP), Indium Gallium Phosphide (InGaP), Aluminum Indium Gallium Phosphide At least one of (AlInGaP) or indium phosphide (InP) is directly disposed on the substrate 101 in the form of a wafer or a crystal grain (die), and the second semiconductor wafer 103 and the first semiconductor wafer 102 They are electrically connected to each other and disposed on the mounting surface 1011 of the substrate 101 through bonding wires. The bonding methods can use gold wires, copper wires, conductive alloy wires or other wires with good conductivity and are not easy to produce oxidation or chemical reactions. The active metal wires are connected to each other in a connection manner, so that the first semiconductor chip 102 can control the action of the second semiconductor chip 103. In this embodiment, after the semiconductor package structure 10 is turned on by an external power, when an external signal controls When the first semiconductor chip 102 is in the "on state", the current can pass through the second semiconductor chip 103, so that the semiconductor package structure 10 is in a light-emitting state. On the contrary, when the first semiconductor chip 102 is in the "off state", its The current cannot pass through the second semiconductor chip 103, so that the semiconductor package structure 10 exhibits a non-luminous state. Through the above method, semiconductor chips with different properties can be arranged on the same package, thereby improving the conventional one that requires a single element to be arranged in the circuit. board, thereby achieving miniaturization.

Please continue to refer to FIG. 3 , which is a semiconductor package according to an embodiment of the new invention. A schematic diagram of the mounting structure, a mounting surface 1011 of the substrate 101 is formed with a groove 1012 , the first semiconductor chip 102 is electrically connected and disposed in the groove 1012 , and the second semiconductor chip 103 is stacked on the first semiconductor chip 102 , and are electrically connected to each other, and the package body 104 is disposed on the substrate 101 to cover at least part of the circuit layer (not shown), and completely encapsulate the first semiconductor chip 102 and the second semiconductor chip 103, as shown in the figure As shown, when the second semiconductor chip 103 is stacked on the first semiconductor chip 102, not only the area of the substrate 101 can be reduced, but also the light emitted by the second semiconductor chip 103 can be prevented from being shielded, thereby improving the light extraction efficiency. In addition, through the above-mentioned stacking method, the size of the substrate 101 can be made smaller than the range of 1 millimeter by 1 millimeter.

Please continue to refer to FIG. 4 , which is a schematic diagram of a semiconductor package structure according to another embodiment of the novel invention. A mounting surface 1011 of the substrate 101 is formed with a groove 1012 , and the first semiconductor chip 102 is electrically connected to the groove. In 1012 , the second semiconductor chip 103 is stacked on the first semiconductor chip 102 and is electrically connected to each other. Compared with the above-mentioned embodiment, this embodiment is different in that the package body 104 includes the first package body 1041 and the The second package body 1042, wherein the first package body 1041 is used to cover the first semiconductor chip 102, and the second package body 1042 is used to cover the second semiconductor chip 103. Specifically, when the first semiconductor chip 102 is disposed on the After entering the groove 1012 , the first package body 1041 will encapsulate the first semiconductor chip 102 and fill the groove 1012 . Further, the height of the first package body 1041 needs to be higher than the mounting surface of the substrate 101 . 1011, preferably, the height of the first package body 1041 and the distance between the mounting surface 1011 are less than 0.5 mm, and the second semiconductor chip 103 is disposed on the first package body 1041, and the second package body 1042 is then encapsulated and packaged The second semiconductor chip 103 and its covering at least part of the circuit layer, as shown in the figure, the first package body 1041 is made of a light-transmitting or non-light-transmitting material, and the second package body 1042 is a light-transmitting material. When the first package body 1041 is made of a non-translucent material, the light emitted by the second semiconductor chip 103 can be prevented from being damaged. influence, and the difference between the refractive index of the first package body 1041 and the refractive index of the second package body 1042 is less than 0.2, preferably, the difference between the refractive indexes of the two is between 0.01 and 0.1. For example, the surface of the second package body 1042 may be a light emitting surface 1043, and the light emitting surface 1043 may be a spherical surface, an aspherical surface, an arcuate surface, a paraboloid, a hyperboloid or a free-form surface.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the new creation should be determined by the scope of the appended patent application.

10: Semiconductor packaging structure

101: Substrate

102: First semiconductor wafer

103: Second semiconductor wafer

104: Package body

Claims (10)

A semiconductor packaging structure, comprising: a base plate, one side of which is formed with a mounting surface; a first semiconductor chip electrically arranged on the mounting surface; a second semiconductor chip electrically disposed on the mounting surface and electrically connected to the first semiconductor chip; and a package body that completely covers the first semiconductor chip and the second semiconductor chip; Wherein, the first semiconductor chip is used for synchronously controlling the action of the second semiconductor chip. The semiconductor package structure of claim 1, wherein the first semiconductor chip and the second semiconductor chip are connected in series. The semiconductor package structure of claim 2, wherein the first semiconductor chip is a metal oxide semiconductor field effect transistor, and the second semiconductor chip is a light emitting diode chip. A semiconductor packaging structure, comprising: a base plate, wherein a mounting surface is formed with a groove; a first semiconductor chip electrically arranged in the groove; a second semiconductor chip electrically connected to the first semiconductor chip; and a package body, which completely wraps the first semiconductor chip and the second semiconductor chip; Wherein, the first semiconductor chip is used to control the action or not of the second semiconductor chip. The semiconductor package structure of claim 4, wherein the first semiconductor chip and the second semiconductor chip are connected in series. The semiconductor package structure of claim 5, wherein the first semiconductor chip is a metal oxide semiconductor field effect transistor, and the second semiconductor chip is a light emitting diode chip. The semiconductor package structure according to claim 4, wherein the package body further comprises a first package body and a second package body, the first package body is used to encapsulate the first semiconductor chip, and the second package body for wrapping the second semiconductor chip. The semiconductor package structure of claim 7, wherein the height of the first package body is higher than the mounting surface. The semiconductor package structure of claim 8, wherein the difference between the refractive index of the first package body and the refractive index of the second package body is less than 0.2. The semiconductor package structure of claim 8, wherein the first package body can be a light-transmitting or opaque material.

Images