TWM627144U - Single power supply level shifter, and power management chip and information processing device using the same - Google Patents

Abstract

A single power supply level shifter has a first input circuit formed by stacking a first PMOS (P-type metal-oxide-semiconductor) transistor and a first NMOS (N-type metal-oxide-semiconductor) transistor to receive a For the control of the input signal, the high potential of the input signal is determined by a first DC voltage; a second input circuit is formed by stacking a second PMOS transistor and a second NMOS transistor to receive an inverting input Signal control, the high potential of the inverting input signal is determined by the first DC voltage; and a bistable circuit unit, characterized in that: the bistable circuit unit is biased between a second DC voltage and a Between the high-side reference voltages, the gates of the first PMOS transistor and the second PMOS transistor are both coupled to the high-side reference voltage, the level of the second DC voltage is higher than the level of the high-side reference voltage, and The level of the high-side reference voltage is higher than that of the first DC voltage.

Description

Single power supply level shifter and power management chip and information processing device using the same set

The utility model relates to a power supply level shifter, in particular to a level shifter which can maintain the output signal level with only a single power supply.

A level shifter is generally installed in a chip to transmit logic signals between logic circuits of two different levels, while a conventional level shifter requires dual power supplies for normal operation.

Please refer to FIG. 1 , which shows a circuit diagram of a conventional level shifter. As shown in FIG. 1, the conventional level shifter has a low-order inverter 11, a first NMOS (N-type metal oxide semiconductor) transistor 12a, a second NMOS transistor 12b, a first PMOS (P-type MOSFET 13a and a second PMOS transistor 13b, wherein the low-level inverter 11 is biased between a first DC voltage V _DDL and a reference ground; the first PMOS transistor 13a is connected to the second An NMOS transistor 12a is connected in series between a second DC voltage V _DDH and the reference ground, the second DC voltage V _DDH is higher than the first DC voltage V _DDL ; the second PMOS transistor 13b is connected to the second NMOS transistor 12b connected in series between the second DC voltage V _DDH and the reference ground; the gate of the first NMOS transistor 12a and the input of the low-level inverter 11 are both used to couple an input signal A, and the gate of the second NMOS transistor 12b The gate is coupled to the output of the low-level inverter 11 to receive the inverted signal A _b of the input signal A; the drain of the second PMOS transistor 13b and the drain of the second NMOS transistor 12b and the first PMOS The gate of the transistor 13a is coupled to provide an output signal Y, and the drain of the first PMOS transistor 13a is coupled to the drain of the first NMOS transistor 12a and the gate of the second PMOS transistor 13b to provide An inverted output signal Y _b of the output signal Y, wherein the logic 1 level of the output signal Y is higher than the logic 1 level of the input signal A.

Please refer to FIG. 2 , which illustrates a working waveform diagram of the conventional level shifter of FIG. 1 . As shown in Figure 2, when V _DDH is equal to 5.5V and V _DDL is equal to 2.5V, the logic 1 level of the input signal A will be equal to 2.5V, the logic 1 level of the output signal Y will be equal to 5.5V, and the output The logic state of signal Y changes in phase with the logic state of input signal A.

However, the logic state of the output signal Y must be ensured when both the first NMOS transistor 12a and the second NMOS transistor 12b are normally driven. If V _DDL disappears, the first NMOS transistor 12a and the second NMOS transistor 12b 12b cannot work normally, so that the logic state of the drive output signal Y cannot be maintained correctly.

To solve the above problems, a novel level shifter is urgently needed in the art.

One object of the present invention is to provide a level shifter used in a power management chip, which can effectively maintain the logic state of an output signal only by the bias of a high voltage power supply after a low voltage power supply disappears.

Another object of the present invention is to provide a power management chip, which can allow a low voltage power supply without a normal state by using a power supply level shifter that can effectively maintain a logic state of an output signal with a high voltage power supply output voltage for further power savings.

Another object of the present invention is to provide an information processing device, which can further save power consumption by using the above-mentioned power management chip.

To achieve the aforementioned objects, a single-supply level shifter is proposed, which has: A first NMOS transistor has a gate, a drain and a source, the gate is used for coupling an input signal, and the source is coupled to a reference ground; a first PMOS transistor, It has a gate, a source and a drain, the gate is coupled to a high-side reference voltage, the source is coupled to an inverting output signal that is inverted to an output signal, and the drain is coupled to is coupled to the drain of the first NMOS transistor; a low-level inverter is biased between a first DC voltage and the reference ground, and is used to generate a phase opposite to the input signal according to the input signal an inverting input signal; a second NMOS transistor with a gate, a drain and a source, the gate is coupled to the inverting input signal, and the source is coupled to the reference ground; a The second PMOS transistor has a gate, a source and a drain, the gate is coupled to the high-side reference voltage, the source is coupled to the output signal, and the drain is coupled to the first the drains of the two NMOS transistors are coupled; and A bistable circuit unit biased between a second DC voltage and the high-side reference voltage, and has two terminals to generate the output signal and the inverted output signal respectively, wherein the second DC voltage The level of the voltage is higher than that of the high-side reference voltage, and the level of the high-side reference voltage is higher than that of the first DC voltage.

In one embodiment, the bistable circuit unit is implemented by two cross-coupled inverters.

In one embodiment, the bistable circuit unit has: a first inverter composed of a first NMOS transistor and a first PMOS transistor; and a second NMOS transistor and a second PMOS transistor The transistor forms a second inverter, the first inverter and the second inverter are cross-coupled, and the first inverter and the second inverter are both biased to the second DC voltage and the high-side reference voltage.

In order to achieve the aforementioned purpose, the present invention further provides a power management chip, which has at least one single power level shifter to reduce power consumption, wherein the single power level shifter has: a first NMOS transistor with a gate, a drain and a source, the gate is used for coupling an input signal, the source is coupled with a reference ground; a first PMOS transistor has a gate and a source and a drain, the gate is coupled to a high-side reference voltage, the source is coupled to an inverting output signal that is inverse to an output signal, and the drain is coupled to the first NMOS transistor the drain electrode is coupled; a low-level inverter is biased between a first DC voltage and the reference ground, and is used for generating an inverting input signal that is inverse to the input signal according to the input signal; a first Two NMOS transistors have a gate, a drain and a source, the gate is coupled to the inverting input signal, and the source is coupled to the reference ground; a second PMOS transistor has a gate, a source and a drain, the gate is coupled to the high-side reference voltage, the source is coupled to the output signal, and the drain is coupled to the drain of the second NMOS transistor pole coupling; and A bistable circuit unit biased between a second DC voltage and the high-side reference voltage, and has two terminals to generate the output signal and the inverted output signal respectively, wherein the second DC voltage The level of the voltage is higher than that of the high-side reference voltage, and the level of the high-side reference voltage is higher than that of the first DC voltage.

In one embodiment, the bistable circuit unit is implemented by two cross-coupled inverters.

In one embodiment, the bistable circuit unit has: a first inverter composed of a first NMOS transistor and a first PMOS transistor; and a second NMOS transistor and a second PMOS transistor The transistor forms a second inverter, the first inverter and the second inverter are cross-coupled, and the first inverter and the second inverter are both biased to the second DC voltage and the high-side reference voltage.

In order to achieve the aforementioned object, the present invention further provides an information processing device, which has a power management chip, and the power management chip has at least one single power level shifter to reduce power consumption, wherein the single power level shifter The device has: a first NMOS transistor with a gate, a drain and a source, the gate is used for coupling an input signal, the source is coupled with a reference ground; a first PMOS The transistor has a gate, a source and a drain, the gate is coupled to a high-side reference voltage, the source is coupled to an inverting output signal that is inverse to an output signal, and the drain The pole is coupled to the drain pole of the first NMOS transistor; a low-level inverter is biased between a first DC voltage and the reference ground for generating and matching the input signal according to the input signal Inverting an inverting input signal; a second NMOS transistor with a gate, a drain and a source, the gate is coupled to the inverting input signal, and the source is coupled to the reference ground A second PMOS transistor has a gate, a source and a drain, the gate is coupled to the high-side reference voltage, the source is coupled to the output signal, and the drain is coupled to the output signal coupled to the drain of the second NMOS transistor; and A bistable circuit unit biased between a second DC voltage and the high-side reference voltage, and has two terminals to generate the output signal and the inverted output signal respectively, wherein the second DC voltage The level of the voltage is higher than that of the high-side reference voltage, and the level of the high-side reference voltage is higher than that of the first DC voltage.

In one embodiment, the bistable circuit unit is implemented by two cross-coupled inverters.

In one embodiment, the bistable circuit unit has: a first inverter composed of a first NMOS transistor and a first PMOS transistor; and a second NMOS transistor and a second PMOS transistor The transistor forms a second inverter, the first inverter and the second inverter are cross-coupled, and the first inverter and the second inverter are both biased to the second DC voltage and the high-side reference voltage.

In a possible embodiment, the information processing device may be a portable computer or a smart handheld device.

11: low inverter

12a: first NMOS transistor

12b: Second NMOS transistor

13a: first PMOS transistor

13b: Second PMOS transistor

100: Single Supply Level Shifter

110: NMOS transistor

110a: PMOS transistor

111: low inverter

112: NMOS transistor

112a: PMOS transistor

120: Bistable circuit unit

V _DDL : DC voltage

V _DDH : DC voltage

V _SSH : High-side reference voltage

Y: output signal

Y _b : Inverted output signal

A: Input signal

A _b : Inverted input signal

121a: first NMOS transistor

121b: Second NMOS transistor

122a: first PMOS transistor

122b: Second PMOS transistor

200: Power management chip

200a: Single Supply Level Shifter

300: Information processing device

300a: Power Management Chip

In order to further disclose the specific technical content of the present invention, please refer to the drawings first, wherein:

FIG. 1 is a circuit diagram of a conventional level shifter.

FIG. 2 is a working waveform diagram of the conventional level shifter of FIG. 1 .

FIG. 3 is a circuit diagram illustrating an embodiment of the single power supply level shifter of the present invention.

FIG. 4 is a working waveform diagram of the single power level shifter of FIG. 3 .

FIG. 5 is a circuit diagram illustrating an embodiment of the bistable circuit unit of the single power supply level shifter of FIG. 3 .

FIG. 6 is a block diagram illustrating an embodiment of the power management chip of the present invention.

FIG. 7 is a block diagram illustrating an embodiment of the information processing apparatus of the present invention.

The principle of this new model is:

(1) Using a first PMOS (P-type metal-oxide-semiconductor) transistor and a first NMOS (N A first input circuit formed by stacking PMOS transistors is controlled by an input signal, wherein the high potential of the input signal is determined by a first DC voltage, and the gate of the first PMOS transistor is controlled by an input signal. The pole is coupled to a high-side reference voltage; (2) a second input circuit formed by stacking a second PMOS transistor and a second NMOS transistor is used to receive the control of an inverting input signal, the inverting input The high potential of the signal is determined by the first DC voltage, and the gate of the second PMOS transistor is coupled to the high-side reference voltage; and (3) setting a bistable circuit unit and making the bistable circuit unit The bias voltage is between a second DC voltage and the high-side reference voltage, wherein the level of the second DC voltage is higher than the level of the high-side reference voltage, and the level of the high-side reference voltage is higher than the level of the high-side reference voltage The level of the first DC voltage.

According to this design, the novel level shifter can effectively isolate the high-side signal and the low-side signal, and can effectively maintain the logic state of the output signal only by the bias of a high-voltage power supply after a low-voltage power supply disappears. .

Please refer to FIG. 3 , which shows a circuit diagram of an embodiment of the single power supply level shifter of the present invention. As shown in FIG. 3, a single power level shifter 100 has an NMOS transistor 110, a PMOS transistor 110a, a low inverter 111, another NMOS transistor 112, another PMOS transistor 112a, and a dual The steady state circuit unit 120 makes an output signal Y with a high-level logic react in phase with an input signal A with a low-level logic.

The NMOS transistor 110 has a gate, a drain and a source, the gate is used for coupling the input signal A, the drain is coupled with the PMOS transistor 110a, and the source is connected with a reference coupled to ground; the PMOS transistor 110a has a gate, a source and a drain, the gate is coupled to a high-side reference voltage V _SSH , and the source is inverse to one of the inversions of the output signal Y The phase output signal Y _b is coupled, and the drain is coupled to the drain of the NMOS transistor 110 .

The low-order inverter 111 is biased between the DC voltage V _DDL and the reference ground, and is used for generating an inverting input signal A _b which is inverse to the input signal A according to the input signal A .

The NMOS transistor 112 has a gate, a drain and a source, the gate is coupled to the inverting input signal _Ab , the drain is coupled to the PMOS transistor 112a, and the source is coupled to the reference ground The PMOS transistor 112a has a gate, a source and a drain, the gate is coupled to the high-side reference voltage V _SSH , the source is coupled to the output signal Y, and the drain is is coupled to the drain of the NMOS transistor 112 .

The bistable circuit unit 120 is biased between the DC voltage V _DDH and the high-side reference voltage V _SSH , and can be implemented by two cross-coupled inverters, which have two terminals to generate output signals Y and Inverting the output signal Y _b , the level of the DC voltage V _DDH is higher than the level of the high-side reference voltage V _SSH , and the level of the high-side reference voltage V _SSH is higher than the level of the DC voltage V _DDL . In addition, the channels of the NMOS transistor 110 , the PMOS transistor 110 a , the NMOS transistor 112 and the PMOS transistor 112 a must be able to withstand the level of the DC voltage V _DDH to ensure the normal operation of the single power supply level shifter 100 .

During operation, when the DC voltage V _DDL disappears after the input signal A exhibits a logic 1 level for a period of time, the low-order inverter 111 will make its output inverting input signal _Ab present a logic 0 level during this period of time. The NMOS transistor 110 will pull down the level of the inverting output signal Y _b through the turned-on PMOS transistor 110a during this period of time, and the NMOS transistor 112 will present a high-impedance state during this period of time, so that the The level of the output signal Y rises smoothly; and when the DC voltage V _DDL disappears, the level of the input signal A will drop to the reference ground, so that the channel of the NMOS transistor 110 presents a high impedance, and the low-level inverter 111 has a high impedance. The output will fail, so that the channel of the NMOS transistor 112 also presents a high impedance, so that the output signal Y and the inverted output signal Y _b of the bistable circuit unit 120 can still be maintained at a high level (close to V _DDH ) and a low level, respectively. level (closer to V _SSH ). In addition, when the DC voltage V _DDL disappears after the input signal A exhibits a logic 0 level for a period of time, the low-order inverter 111 will make its output inverting input signal A _b present a logic 1 level during the period of time. The NMOS transistor 112 will pull down the level of the output signal Y through the turned-on PMOS transistor 112a during this period of time, and the NMOS transistor 110 will present a high impedance state during this period of time, so that the output signal Y is inverted. The level of _b rises smoothly; and when the DC voltage V _DDL disappears, the output of the low-level inverter 111 will fail, so that the channel of the NMOS transistor 112 also presents a high impedance, so that the output signal of the bistable circuit unit 120 The Y and inverted output signals _Yb can still be maintained at a low level (near V _SSH ) and a high level (near V _DDH ), respectively. That is, the single power supply level shifter 100 allows the DC voltage V _DDL used to generate the input signal A and the inverting input signal _Ab to be maintained for only a short period of time to ensure the effective transfer and retention of a logic state, thereby reducing the overall power consumption of the circuit. Please refer to FIG. 4 , which illustrates a working waveform diagram of the single power level shifter of FIG. 3 . As shown in Figure 4, when V _DDL disappears and the input signal A also disappears, the level of the output signal Y remains correct.

In addition, please refer to FIG. 5 , which illustrates a circuit diagram of an embodiment of the bistable circuit unit 120 of the single power supply level shifter of FIG. 3 . As shown in FIG. 5 , the bistable circuit unit 120 is biased between the DC voltage V _DDH and the high-side reference voltage V _SSH , and has one of a first NMOS transistor 121 a and a first PMOS transistor 122 a The first inverter and a second inverter composed of a second NMOS transistor 121b and a second PMOS transistor 122b, and the first inverter and the second inverter are cross-coupled.

In addition, according to the above design, the present invention further provides a power management chip. Please refer to FIG. 6 , which shows a block diagram of an embodiment of the power management chip of the present invention. As shown in FIG. 6, a power management chip 200 has at least one single power level shifter 200a, wherein the single power level shifter 200a is implemented by the single power level shifter 100 to effectively reduce the power management chip 200 power consumption.

In addition, the present invention further provides an information processing device. Please refer to FIG. 7 , which shows a block diagram of an embodiment of the information processing apparatus of the present invention. As shown in FIG. 7 , an information processing device 300 has a power management chip 300 a, wherein the power management chip 300 a is implemented by the power management chip 200 to effectively reduce the power consumption of the information processing device 300 . In addition, the information processing device 300 can be a portable computer or a smart handheld device.

According to the above description, the present invention can provide the following advantages:

1. The novel level shifter can effectively maintain the logic state of the output signal only by the bias of a high-voltage power supply after a low-voltage power supply disappears.

2. The new power management chip can use a power level shifter that can effectively maintain the logic state of an output signal with a high-voltage power supply, allowing a low-voltage power supply to not require a normal output voltage to further save power consumption.

3. The information processing device of the present invention can further save power consumption by using the above-mentioned power management chip.

What is disclosed in this new model is one of the preferred embodiments, and any partial changes or modifications originating from the technical ideas of this new model and easily inferred by those who are familiar with the technology are within the scope of the patent right of this new model.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first creation is suitable for practical use, and it does meet the requirements of a new type of patent. Society is to pray for the best.

100: Single Supply Level Shifter

110: NMOS transistor

110a: PMOS transistor

111: low inverter

112: NMOS transistor

112a: PMOS transistor

120: Bistable circuit unit

V _DDL : DC voltage

V _DDH : DC voltage

V _SSH : High-side reference voltage

Y: output signal

Y _b : Inverted output signal

A: Input signal

A _b : Inverted input signal

Claims (10)

A single power supply level shifter, which has: a first N-type metal oxide semi-transistor, with a gate, a drain and a source, the gate is used for coupling an input signal, the source is coupled to a reference ground; a first P-type MOSFET has a gate, a source and a drain, the gate is coupled to a high-side reference voltage, and the source is connected to a An inverting output signal of inversion of the output signal is coupled, and the drain electrode is coupled to the drain electrode of the first N-type MOSFET; a low-level inverter is biased at a first between the DC voltage and the reference ground, for generating an inverting input signal which is inverse to the input signal according to the input signal; a second N-type metal oxide semiconductor transistor has a gate, a drain and a a source electrode, the gate electrode is coupled to the inverting input signal, and the source electrode is coupled to the reference ground; a second P-type MOSFET has a gate electrode, a source electrode and a drain electrode, the gate is coupled to the high-side reference voltage, the source is coupled to the output signal, and the drain is coupled to the drain of the second NMOS transistor; and a pair of The steady-state circuit unit is biased between a second DC voltage and the high-side reference voltage, and has two terminals to generate the output signal and the inverted output signal respectively, wherein the second DC voltage is The level is higher than that of the high-side reference voltage, and the level of the high-side reference voltage is higher than that of the first DC voltage. The single power supply level shifter as described in claim 1, wherein the bistable circuit unit is realized by two cross-coupled inverters. The single power supply level shifter as described in claim 1, wherein the bistable circuit unit has: a first inverter; and a second inverter, the first inverter and the first inverter Two inverters are cross-coupled, and both the first inverter and the second inverter are biased between the second DC voltage and the high-side reference voltage. A power management chip having at least one single power level shifter to reduce power consumption, wherein the single power level shifter has: A first N-type MOSFET has a gate, a drain and a source, the gate is used for coupling an input signal, the source is coupled with a reference ground; a first P-type MOSFET has a gate, a source and a drain, the gate is coupled to a high-side reference voltage, and the source is coupled to an inverting output signal that is inverse to an output signal connected, and the drain is coupled to the drain of the first N-type MOSFET; a low-level inverter is biased between a first DC voltage and the reference ground for According to the input signal, an inversion input signal is generated which is inversion of the input signal; a second N-type MOSFET has a gate, a drain and a source, and the gate is coupled to the inversion input signal, the source is coupled to the reference ground; a second P-type MOSFET has a gate, a source and a drain, the gate is coupled to the high-side reference voltage, The source is coupled to the output signal, and the drain is coupled to the drain of the second N-type MOSFET; and a bistable circuit unit biased on a second between the DC voltage and the high-side reference voltage, and it has two terminals to generate the output signal and the inverted output signal respectively, wherein the level of the second DC voltage is higher than the level of the high-side reference voltage and the level of the high-side reference voltage is higher than that of the first DC voltage. The power management chip of claim 4, wherein the bistable circuit unit is implemented by two cross-coupled inverters. The power management chip of claim 4, wherein the bistable circuit unit has: a first inverter; and a second inverter, the first inverter and the second inverter The inverters are cross-coupled, and the first inverter and the second inverter are both biased between the second DC voltage and the high-side reference voltage. An information processing device has a power management chip, and the power management chip has at least one single power level shifter to reduce power consumption, wherein the single power level shifter has: A first N-type MOSFET has a gate, a drain and a source, the gate is used for coupling an input signal, the source is coupled with a reference ground; a first P-type MOSFET has a gate, a source and a drain, the gate is coupled to a high-side reference voltage, and the source is coupled to an inverting output signal that is inverse to an output signal connected, and the drain is coupled to the drain of the first N-type MOSFET; a low-level inverter is biased between a first DC voltage and the reference ground for According to the input signal, an inversion input signal is generated which is inversion of the input signal; a second N-type MOSFET has a gate, a drain and a source, and the gate is coupled to the inversion input signal, the source is coupled to the reference ground; a second P-type MOSFET has a gate, a source and a drain, the gate is coupled to the high-side reference voltage, The source is coupled to the output signal, and the drain is coupled to the drain of the second N-type MOSFET; and a bistable circuit unit biased on a second between the DC voltage and the high-side reference voltage, and it has two terminals to generate the output signal and the inverted output signal respectively, wherein the level of the second DC voltage is higher than the level of the high-side reference voltage and the level of the high-side reference voltage is higher than that of the first DC voltage. The information processing device as described in claim 7, wherein the bistable circuit unit is realized by two cross-coupled inverters. The information processing device of claim 7, wherein the bistable circuit unit has: a first inverter; and a second inverter, the first inverter and the second inverter The inverters are cross-coupled, and the first inverter and the second inverter are both biased between the second DC voltage and the high-side reference voltage. The information processing device described in item 7 of the scope of the application is a portable computer or a smart handheld device.

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