TWM626936U - Dual e-type hall magnetic device - Google Patents
Dual e-type hall magnetic deviceInfo
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Abstract
Description
本創作涉及一種霍爾磁場感測元件,特別是雙E型霍爾磁場感測元件。The present invention relates to a Hall magnetic field sensing element, especially a double E-type Hall magnetic field sensing element.
近年來,隨著半導體製程的蓬勃發展,導致各種電子元件的微小化、積體化已不再是夢想。In recent years, with the vigorous development of semiconductor manufacturing process, the miniaturization and integration of various electronic components is no longer a dream.
一般而言,傳統的霍爾磁場感測元件主要是以勞侖茲力(Lorentz force)為主要的原理。其原理是當有一個外加電流沿水平軸施加時,會在垂直軸之間產生霍爾電壓,其電壓大小會隨著霍爾磁場感測元件的厚度、截面積、外加電流與磁場大小而改變。倘若要感測較小的磁場,可以藉由提升外加電流、改變厚度或者改變載子濃度來實現。目前市售的霍爾磁場感測元件大都以雙極性接面型電晶體(Bipolar Junction Transistor, BJT)技術或磁性材料製成,其讀出電路與訊號處理電路無法結合,故需要個別製造,再行整合,如此將導致製造成本提高、產品體積增大等缺點。另一方面,由於霍爾磁場感測元件的輸出信號通常很小,所以需要低輸入偏移電壓及低雜訊特性。因此,如何有效減少體積且增加整合電路的方便性,便成為各家廠商急欲解決的問題之一。Generally speaking, the traditional Hall magnetic field sensing element is mainly based on the principle of Lorentz force. The principle is that when an external current is applied along the horizontal axis, a Hall voltage will be generated between the vertical axes, and its voltage will change with the thickness, cross-sectional area, applied current and magnetic field of the Hall magnetic field sensing element. . If a smaller magnetic field is to be sensed, it can be achieved by increasing the applied current, changing the thickness, or changing the carrier concentration. At present, most of the Hall magnetic field sensing elements on the market are made of Bipolar Junction Transistor (BJT) technology or magnetic materials. The readout circuit and the signal processing circuit cannot be combined, so they need to be manufactured separately. This will lead to disadvantages such as increased manufacturing cost and increased product volume. On the other hand, since the output signal of the Hall magnetic field sensing element is usually small, low input offset voltage and low noise characteristics are required. Therefore, how to effectively reduce the volume and increase the convenience of the integrated circuit has become one of the problems that manufacturers are eager to solve.
綜上所述,可知先前技術中一直存在感測靈敏度不佳及電路整合不便之問題,因此實有必要提出改進的技術手段,來解決此一問題。To sum up, it can be seen that the problems of poor sensing sensitivity and inconvenient circuit integration have always existed in the prior art. Therefore, it is necessary to propose an improved technical means to solve this problem.
首先,本創作揭露一種雙E型霍爾磁場感測元件,係以標準互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程製作完成,此元件包含:半導體基板、二個E型深層佈植層、多個導體接墊及電流阻擋層。其中,所述E型深層佈植層設置在半導體基板上以作為電流傳導的載體層,所述E型深層佈植層包含第一E型深層佈植層及第二E型深層佈植層,此第一E型深層佈植層的位置與第二E型深層佈植層的位置係以鏡射軸呈鏡射關係;每一導體接墊皆包含淺層佈植層及N型井區(N-well),所述導體接墊分別設置在第一E型深層佈植層及第二E型深層佈植層的上表面且以鏡射軸呈鏡射關係,以及允許電流經由導體接墊通過E型深層佈植層中間相連之導線形成電流路徑;電流阻擋層以保護環(Guard Ring)結構覆蓋第一E型深層佈植層及第二E型深層佈植層以阻擋電流及提高磁靈敏度。First, the present invention discloses a double E-type Hall magnetic field sensing device, which is fabricated by a standard complementary metal-oxide-semiconductor (CMOS) process. The device includes a semiconductor substrate, two E-type deep layers An implant layer, a plurality of conductor pads and a current blocking layer. Wherein, the E-type deep implantation layer is disposed on the semiconductor substrate as a carrier layer for current conduction, and the E-type deep implantation layer includes a first E-type deep implantation layer and a second E-type deep implantation layer, The position of the first E-type deep implantation layer and the position of the second E-type deep implantation layer are in a mirroring relationship with the mirror axis; each conductor pad includes a shallow implantation layer and an N-type well area ( N-well), the conductor pads are respectively arranged on the upper surfaces of the first E-type deep implantation layer and the second E-type deep implantation layer in a mirrored relationship with a mirror axis, and allow current to pass through the conductor pads The current path is formed by the wires connected in the middle of the E-type deep implantation layer; the current blocking layer covers the first E-type deep implantation layer and the second E-type deep implantation layer with a Guard Ring structure to block the current and improve the magnetic field. sensitivity.
本創作所揭露之元件如上,與先前技術的差異在於本創作是透過在半導體基板上設置第一E型深層佈植層及第二E型深層佈植層以作為電流傳導的載體層,其中,第一E型深層佈植層的位置與該第二E型深層佈植層的位置係以鏡射軸呈鏡射關係,接著將包含N型井區及淺層佈植層的多個導體接墊分別設置在第一E型深層佈植層及第二E型深層佈植層的上表面且以鏡射軸呈鏡射關係,再以保護環覆蓋第一E型深層佈植層及第二E型深層佈植層作為電流阻擋層以阻擋電流及提高磁靈敏度。The elements disclosed in the present invention are as above, and the difference from the prior art is that the present invention uses a first E-type deep implant layer and a second E-type deep implant layer on a semiconductor substrate to serve as a carrier layer for current conduction, wherein, The position of the first E-type deep implantation layer and the position of the second E-type deep implantation layer are in a mirroring relationship with the mirror axis, and then a plurality of conductors including the N-type well area and the shallow implantation layer are connected. The pads are respectively arranged on the upper surfaces of the first E-type deep implantation layer and the second E-type deep implantation layer and are in a mirrored relationship with the mirror axis, and then cover the first E-type deep implantation layer and the second E-type deep implantation layer with a protection ring. The E-type deep implant layer acts as a current blocking layer to block current and improve magnetic sensitivity.
透過上述的技術手段,本創作可以達成提高磁場感測靈敏度及電路整合的便利性之技術功效。Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the sensitivity of magnetic field sensing and the convenience of circuit integration.
以下將配合圖式及實施例來詳細說明本創作之實施方式,藉此對本創作如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The following will describe the implementation of the present creation in detail with the drawings and examples, so as to fully understand and implement the implementation process of how to apply technical means to solve technical problems and achieve technical effects in the present creation.
在說明本創作所揭露之雙E型霍爾磁場感測元件之前,先對本創作圖式的網點進行說明,在實際實施上,為了簡單說明及簡化圖式,本創作圖式中使用相同的網點或元件符號來代表相同的元件、材料或結構。Before describing the double E-type Hall magnetic field sensing element disclosed in this creation, the mesh points of this creation drawing will be explained first. In actual implementation, in order to simplify the description and simplify the drawing, the same mesh point is used in this creation drawing. or symbol to represent the same element, material or structure.
以下配合圖式對本創作雙E型霍爾磁場感測元件做進一步說明,請先參閱「第1圖」。「第1圖」為本創作雙E型霍爾磁場感測元件的第一實施例之示意圖,所述雙E型霍爾磁場感測元件100係以標準 CMOS 製程製作完成,其元件包含:半導體基板110、二個E型深層佈植層(111、112)、多個導體接墊120及電流阻擋層130。所述E型深層佈植層(111、112)設置在半導體基板110上以作為電流傳導的載體層,其中,所述E型深層佈植層(111、112)包含第一E型深層佈植層111及第二E型深層佈植層112,第一E型深層佈植層111的位置與第二E型深層佈植層112的位置係以鏡射軸113呈鏡射關係。在實際實施上,所述E型深層佈植層(111、112)的轉角為R角,用以降低電流受磁場介入時,載子偏轉而撞擊佈植層的機率,其R角半徑可為1.8μm。另外,所述E型深層佈植層(111、112)係採用多晶矽(Polysilicon)的霍爾平面,其上方覆蓋電流阻擋層130。實際上,所述E型深層佈植層(111、112)的寬度可分別在 15μm 至 30μm 之中任選其一,而第一E型深層佈植層111及第二E型深層佈植層112則分別包含相互平行的三個突出部140,所述突出部140的長度減去導體接墊120的寬度係在 0μm 至 30μm 之間。除此之外,所述E型深層佈植層(111、112)係為N型井區(N-well)佈植層、T-well 佈植層及P型井區(P-well)佈植層至少其中之一,當E型深層佈植層(111、112)為 N-well 佈植層或 T-well 佈植層時,電流阻擋層130係為 P+ 阻擋層與 P+ 保護環結構,當E型深層佈植層(111、112)為 P-well 佈植層時,電流阻擋層130為 N+ 阻擋層與 N+ 保護環結構。The following diagrams are used to further describe the dual E-type Hall magnetic field sensing element of this creation. Please refer to "Figure 1" first. "FIG. 1" is a schematic diagram of a first embodiment of creating a double-E-type Hall magnetic field sensing device. The double-E-type Hall magnetic
多個導體接墊120,每一導體接墊120皆包含淺層佈植層121及N型井區122,所述導體接墊120分別設置在第一E型深層佈植層111及第二E型深層佈植層112的上表面且以鏡射軸113呈鏡射關係,以及允許電流經由導體接墊120通過所述E型深層佈植層(111、112)中間相連之導線(151、152)形成電流路徑。在實際實施上,所述導體接墊120包含偏壓電流源輸入端(I
bias+)、偏壓電流源輸出端(I
bias-)、第一電壓感測端(V
H1)及第二電壓感測端(V
H2),所述導體接墊120係為 N+ 佈植層,並且長度及寬度係分別在 15μm 至 30μm 之中任選其一,所述導線(151、152)係為導電線(如:金屬導線)。另外,所述電流路徑的長度同樣可在 15μm 至 30μm 之中任選其一。
A plurality of
電流阻擋層130以保護環結構覆蓋第一E型深層佈植層111及第二E型深層佈植層112以阻擋電流及提高磁靈敏度。在實際實施上,電流阻擋層130係為 P+ 阻擋層、N+ 阻擋層、N型井區(N-well)佈植層、T-well 佈植層及P型井區(P-well)佈植層至少其中之一。The
特別要說明的是,在「第1圖」的雙E型霍爾磁場感測元件100係以標準尺寸(或簡稱為代號:F30_31.8)架構布局,並且以正方形之布局架構實現。其中,「30」及「31.8」分別代表 30μm 及 31.8μm(即:30μm 加上R角半徑 1.8μm)。在實際實施上,可基於標準尺寸再延伸出三種規格。第一種延伸規格(或簡稱為代號:F15_16.8),其寬度及邊長縮減為一半,R角半徑為1.8μm不變;第二種延伸規格(或簡稱為代號:F30_1.8),其維持導體接墊寬度 30μm,取消 30μm 邊長,僅保留R角半徑 1.8μm;第三種延伸規格(或簡稱為代號:F15_1.8),其導體接墊寬度為 15μm,額外取消邊長僅保留R角半徑 1.8μm,以下配合圖式分別說明延伸的三種規格。It should be noted that the double-E-type Hall magnetic
請參閱「第2圖」,「第2圖」為本創作雙E型霍爾磁場感測元件的第二實施例之示意圖。在此實施例中,所述雙E型霍爾磁場感測元件200(其規格為代號:F15_16.8)與「第1圖」所示的雙E型霍爾磁場感測元件100大同小異,為了減化圖式及說明,相同的部份便不再重複贅述,而兩者的差異在於突出部的長度減去導體接墊的寬度係在15μm,以及E型深層佈植層的寬度如左下標示同樣為15μm,其有別於「第1圖」所示的雙E型霍爾磁場感測元件100皆為30μm。Please refer to “FIG. 2”, “FIG. 2” is a schematic diagram of a second embodiment of creating a double E-type Hall magnetic field sensing device. In this embodiment, the double-E-type Hall magnetic field sensing element 200 (the specification of which is code: F15_16.8) is similar to the double-E-type Hall magnetic
請參閱「第3圖」,「第3圖」為本創作雙E型霍爾磁場感測元件的第三實施例之示意圖。在此實施例中,所述雙E型霍爾磁場感測元件300的規格為代號:F30_1.8,其與「第1圖」所示的雙E型霍爾磁場感測元件100大同小異,為了減化圖式及說明,相同的部份便不再重複贅述,而兩者的差異在於突出部的長度減去導體接墊的寬度係在1.8μm,也就是僅剩R角半徑,至於E型深層佈植層的寬度則如左下標示,其與「第1圖」所示的雙E型霍爾磁場感測元件100同為30μm。Please refer to “FIG. 3”, “FIG. 3” is a schematic diagram of a third embodiment of creating a double E-type Hall magnetic field sensing device. In this embodiment, the specification of the double-E-type Hall magnetic
請參閱「第4圖」,「第4圖」為本創作雙E型霍爾磁場感測元件的第四實施例之示意圖。在此實施例中,所述雙E型霍爾磁場感測元件400的規格為代號:F15_1.8,其與「第3圖」所示的雙E型霍爾磁場感測元件300大同小異,為了減化圖式及說明,相同的部份便不再重複贅述,而兩者的差異在於雙E型霍爾磁場感測元件400的E型深層佈植層的寬度如左下標示為15μm,有別於「第3圖」所示的雙E型霍爾磁場感測元件300的30μm。Please refer to "FIG. 4". "FIG. 4" is a schematic diagram of a fourth embodiment of creating a double E-type Hall magnetic field sensing device. In this embodiment, the specification of the double-E-type Hall magnetic
在實際實施上,雙E型霍爾磁場感測元件(100、200、300及400)使用「UMC 0.18 UM Mixed-Mode and RFCMOS 1.8V/3.3V 1P6M Metal Capacitor Process」製程技術與規範進行佈植層設計,形成基於磁電阻效應(Magnetoresistance, MR)的Z軸垂直方向的一維雙E型霍爾磁場感測元件。要補充說明的是,上述四個實施例均可使用三種佈植結構:(1) N 型井區覆蓋 P+ 佈植層為阻擋層,以 N-well 佈植層為電流傳導載體,並且利用 N+ 佈植層作為連接 N-well 佈植層的導體接墊,元件之間的絕緣以 P+ 保護環的電流阻擋層(或稱為隔離層)作為阻擋電流阻擋層;(2)使用 T-well 佈植層覆蓋 P+ 佈植層為阻擋層,並且藉由 N+ 佈植層作為連接 N-well 佈植層的導體接墊,元件之間的絕緣同樣以 P+ 保護環結構的電流阻擋層作為阻擋電流的阻擋層;(3)使用 P 型井區(P-well)覆蓋 N+ 佈植層為阻擋層,其採用 P-well 佈植層當作電流傳導載體,以 N+ 作為阻擋電流的阻擋層。In practice, the dual E-type Hall magnetic field sensing elements (100, 200, 300 and 400) are implanted using the process technology and specifications of "UMC 0.18 UM Mixed-Mode and RFCMOS 1.8V/3.3V 1P6M Metal Capacitor Process" Layer design to form a one-dimensional double E-type Hall magnetic field sensing element based on the magnetoresistance effect (Magnetoresistance, MR) in the vertical direction of the Z axis. It should be added that three implantation structures can be used in the above four embodiments: (1) The N-type well area is covered with the P+ implantation layer as the barrier layer, the N-well implantation layer is used as the current conduction carrier, and the N+ implantation layer is used as the current conduction carrier. The implantation layer is used as a conductor pad connecting the N-well implantation layer, and the current blocking layer (or isolation layer) of the P+ guard ring is used as the insulation between the components to block the current blocking layer; (2) T-well cloth is used. The implanted layer covers the P+ implanted layer as a barrier layer, and the N+ implanted layer is used as the conductor pad connecting the N-well implanted layer. The insulation between the components also uses the current blocking layer of the P+ guard ring structure as the current blocking layer. (3) The N+ implantation layer is covered with a P-type well region (P-well) as a barrier layer, which uses the P-well implantation layer as a current conduction carrier and N+ as a current blocking layer.
接下來,在平面型霍爾磁場感測元件的定電壓量測方面,在使用 1.8V 及 3.3V 定電壓下,施以垂直於半導體基板之Z軸方向磁場變化之量測結果的基礎上,兩者的定電壓量測參數分別如表1、表2所示:Next, in the constant voltage measurement of the planar Hall magnetic field sensing element, on the basis of the measurement results of the magnetic field change in the Z-axis direction perpendicular to the semiconductor substrate under the constant voltage of 1.8V and 3.3V, The constant voltage measurement parameters of the two are shown in Table 1 and Table 2 respectively:
表1:雙E型霍爾磁場感測元件 1.8V 定電壓量測參數比較
表2:雙E型霍爾磁場感測元件 3.3V 定電壓量測參數比較
上表1及表2各為 1.8V 與 3.3V 定電壓量測參數結果比較,在平面型的五種規格架構(「F15_1.8P」為並聯「F15_1.8」的架構)中,磁場感測元件代號「F30_31.8」與「F15_16.8」之電流靈敏度表現最佳,其中又以代號「F15_16.8」所占面積最小,而且線性誤差與對稱誤差表現較為突出。另以工作電壓差異進行比較,將電壓從 1.8V 提升至 3.3V,對於電壓靈敏度與電流靈敏度不僅沒有提升,甚至使得靈敏度大幅下降。Table 1 and Table 2 above are the comparison of the measurement parameters of 1.8V and 3.3V constant voltage respectively. In the five specifications of the planar structure ("F15_1.8P" is the structure of parallel "F15_1.8"), the magnetic field sensing The current sensitivity of the component codes "F30_31.8" and "F15_16.8" is the best, and the code "F15_16.8" occupies the smallest area, and the linearity error and symmetry error are more prominent. In addition, compared with the difference in operating voltage, increasing the voltage from 1.8V to 3.3V not only did not improve the voltage sensitivity and current sensitivity, but even greatly reduced the sensitivity.
綜上所述,可知本創作與先前技術之間的差異在於透過在半導體基板上設置第一E型深層佈植層及第二E型深層佈植層以作為電流傳導的載體層,其中,第一E型深層佈植層的位置與該第二E型深層佈植層的位置係以鏡射軸呈鏡射關係,接著將包含N型井區及淺層佈植層的多個導體接墊分別設置在第一E型深層佈植層及第二E型深層佈植層的上表面且以鏡射軸呈鏡射關係,再以保護環覆蓋第一E型深層佈植層及第二E型深層佈植層作為電流阻擋層以阻擋電流及提高磁靈敏度,藉由此一技術手段可以解決先前技術所存在的問題,進而達成提高磁場感測靈敏度及電路整合的便利性之技術功效。To sum up, it can be seen that the difference between the present invention and the prior art is that the first E-type deep implantation layer and the second E-type deep implantation layer are provided on the semiconductor substrate as the carrier layer for current conduction, wherein the first E-type deep implantation layer and the second E-type deep implantation layer are arranged on the semiconductor substrate. The position of an E-type deep implant layer and the position of the second E-type deep implant layer are in a mirrored relationship with a mirror axis, and then a plurality of conductor pads including the N-type well area and the shallow implant layer are connected They are respectively arranged on the upper surfaces of the first E-type deep implantation layer and the second E-type deep implantation layer and in a mirroring relationship with the mirror axis, and then cover the first E-type deep implantation layer and the second E-type deep implantation layer with a protection ring The deep implanted layer acts as a current blocking layer to block current and improve magnetic sensitivity. By this technical means, the problems existing in the prior art can be solved, thereby achieving the technical effect of improving magnetic field sensing sensitivity and convenience of circuit integration.
雖然本創作以前述之實施例揭露如上,然其並非用以限定本創作,任何熟習相像技藝者,在不脫離本創作之精神和範圍內,當可作些許之更動與潤飾,因此本創作之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。Although this creation is disclosed in the above-mentioned embodiments, it is not intended to limit this creation. Anyone who is familiar with the similar arts can make some changes and modifications without departing from the spirit and scope of this creation. The scope of patent protection shall be determined by the scope of the patent application attached to this specification.
100,200,300,400:雙E型霍爾磁場感測元件
110:半導體基板
111,112:E型深層佈植層
113:鏡射軸
120:導體接墊
121:淺層佈植層
122:N型井區
130:電流阻擋層
140:突出部
151,152:導線
100, 200, 300, 400: Double E-type Hall magnetic field sensing element
110: Semiconductor substrate
111,112: E-type deep implantation layer
113: Mirror axis
120: Conductor pads
121: Shallow Implant Layer
122: N-type well area
130: Current blocking layer
140:
第1圖為本創作雙E型霍爾磁場感測元件的第一實施例之示意圖。 第2圖為本創作雙E型霍爾磁場感測元件的第二實施例之示意圖。 第3圖為本創作雙E型霍爾磁場感測元件的第三實施例之示意圖。 第4圖為本創作雙E型霍爾磁場感測元件的第四實施例之示意圖。 FIG. 1 is a schematic diagram of a first embodiment of creating a double E-type Hall magnetic field sensing device. FIG. 2 is a schematic diagram of a second embodiment of creating a double E-type Hall magnetic field sensing device. FIG. 3 is a schematic diagram of a third embodiment of creating a double E-type Hall magnetic field sensing device. FIG. 4 is a schematic diagram of a fourth embodiment of creating a double E-type Hall magnetic field sensing device.
100:雙E型霍爾磁場感測元件 100: Double E-type Hall magnetic field sensing element
110:半導體基板 110: Semiconductor substrate
111,112:E型深層佈植層 111,112: E-type deep implantation layer
113:鏡射軸 113: Mirror axis
120:導體接墊 120: Conductor pads
121:淺層佈植層 121: Shallow Implant Layer
122:N型井區 122: N-type well area
130:電流阻擋層 130: Current blocking layer
140:突出部 140: Protrusion
151,152:導線 151, 152: Wire
Claims (10)
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