TWM619857U - High speed sync trigger bus circuit - Google Patents

Abstract

The high-speed synchronous trigger bus circuit is divided into a central control board part and a test board part. Each part includes a field programmable gate array (FPGA) chip, a circuit interface and a high-speed communication interface. The FPGA chip has a two-port synchronization signal output terminal and a two-port synchronization signal receiver. The FPGA chip of the central control board part is connected to the communication bus of the host computer through the circuit interface, and the FPGA chip of the test board part is connected to the functional unit of the chip testing device through the circuit interface. The synchronization signal output end of the central control board part and the synchronization signal receiving end of the test board part, the synchronization signal output end of the test board part and the synchronization signal receiving end of the central control board part are all connected to each other via a high-speed communication cable. This case utilizes the LVDS port signal characteristics of the FPGA chip to provide high-speed triggering and synchronization signal input and output.

Description

High-speed synchronous trigger bus circuit

This case belongs to the technical field of wafer test devices, and relates to a high-speed synchronous trigger bus circuit.

Automatic test equipment (ATE) is usually used in the field of wafer manufacturing to perform logical tests on the manufactured wafers to ensure that the performance of the wafers meets the design requirements. In the automatic testing machine, there are usually different test projects, and different test boards are designed. The central control board and each test board are triggered synchronously through the bus. The internal communication of synchronous trigger communication is divided into two types: parallel communication and serial communication. Parallel communication usually uses multiple data lines to transmit each element of the data byte at the same time, but requires multiple data lines and control lines, which occupies more resources for the system as a whole, and the operating speed is due to the difficulty of data bit alignment. And be restricted. Serial communication is usually a mode of splitting data into one bit, and transmitting on a single data line. The advantage is that it saves system resources and the single line transmission rate is extremely fast (up to 5Gbps). However, due to the common grounding between the boards, the low-frequency disturbances between the boards at both ends of the communication affect each other, which does not meet the needs of high-speed synchronous triggering in the chip test.

This case provides a high-speed synchronous trigger bus circuit to solve the problem of safe and high-speed communication between the central control board and each test board.

In order to achieve the above objectives, the case provides the following technical solutions:

A high-speed synchronous trigger bus circuit, a central control board part and a test board part, the central control board part and the test board part each include a field programmable gate array chip, a circuit interface and a high-speed communication interface , Where the field programmable gate array chip has two ports of synchronization signal output and two ports of synchronization signal receiving end, the field programmable gate array chip of the central control board part is connected to a host computer via the circuit interface A communication bus connection, the field programmable gate array chip of the test board part is connected to a functional unit of a chip test device via the circuit interface, the synchronization signal output terminal of the central control board part and the test board The synchronization signal receiving end of the card part, the synchronization signal output end of the test board card part and the synchronization signal receiving end of the central control board part are all connected to each other via a high-speed communication cable.

Furthermore, the central control board part and the test board part do not share grounding, so as to effectively isolate the low-frequency disturbance between the boards.

Further, the synchronization signal output terminal and the synchronization signal receiving terminal of the field programmable gate array chip are low-voltage differential signal signal ports.

Further, the high-speed communication cable is a differential coaxial cable.

Further, a capacitor is connected to each of the two-port synchronization signal receiving end of the field programmable gate array chip for DC isolation.

Furthermore, the capacitance of the capacitor is 10 nanofarads.

The beneficial effects of this case:

1) In this case, the high-speed port LVDS (low-voltage differential signal) signal characteristics of FPGA (Field Programmable Gate Array) chip are used to provide high-speed trigger and synchronous signal input and output. No additional drive circuit is required, which reduces the cost.

2) Trigger and synchronize signal upload and distribution through the cooperation of high-speed port LVDS and high-speed differential coaxial cable to achieve extremely low delay (with and only a fixed delay of one clock), which improves the test efficiency of the entire ATE test system. At the same time, when there are multiple instrument boards working together, they all work under the same delay conditions, which can ensure strict synchronous triggering of large systems. It avoids the traditional trigger bus, and it is impossible to avoid the trigger asynchronous problem between multiple boards.

3) The capacitor at the receiving end isolates DC and performs filtering to ensure DC isolation between boards, support boards with different voltages to be connected to each other and avoid common ground interference.

The case will be described in detail below in conjunction with the drawings and specific embodiments:

As shown in Figure 1, a high-speed synchronous trigger bus circuit includes a central control board part 1 and a test board part 2. Each part includes a field programmable gate array (FPGA) chip 3. Circuit interface and high-speed communication interface. Among them, FPGA chip 3 has a two-port synchronization signal output terminal and a two-port synchronization signal receiver. The FPGA chip 3 of the central control board part 1 is connected to the communication bus of the host computer 6 through a circuit interface, and the FPGA chip 3 of the test board part 2 is connected to the functional unit 7 of the chip testing device through the circuit interface. The synchronization signal output end of the central control board part 1 and the synchronization signal receiving end of the test board part 2, the synchronization signal output end of the test board part 2 and the synchronization signal receiving end of the central control board part 1 are mutually connected through the high-speed communication cable 4 connect.

The central control board part 1 and the test board part 2 do not share the ground, which effectively isolates the low-frequency disturbance between the boards.

The synchronization signal output terminal and the synchronization signal receiving terminal of the FPGA chip 3 are low voltage differential signaling (LVDS) signal ports.

The high-speed communication cable 4 is a differential coaxial cable.

A capacitor 5 is connected to each of the two-port synchronization signal receiving ends of the FPGA chip 3 for DC isolation.

The capacitance of the capacitor 5 is 10 nanofarads (nF).

Example 1: The FPGA chip connected to the central control board part of the main computer transmits the internal trigger and synchronization signals transmitted by the ATE test device via the bus to the test board part through the high-speed communication cable, and the test board feedback The signal is also transmitted to the central control board via a high-speed communication cable. The FPGA chip at the synchronous signal receiving end uses a 10nF capacitor to DC-isolate the received signal to ensure that the voltage between the central control board and the test board is floating, thereby making the transmitted signal The data is not disturbed.

The above are only the preferred embodiments of this case, and are not used to limit the case. Any modification, equivalent replacement and improvement made within the principles and spirit of this case should be included in the scope of protection of this case.

1: Central control panel part 2: Test board part 3: On-site programmable gate array chip 4: High-speed communication cable 5: Capacitance 6: Main computer 7: functional unit

[Figure 1] The structure diagram of the high-speed synchronous trigger bus circuit of this case; and [Figure 2] A schematic diagram of an embodiment of this case.

1: Central control panel part

2: Test board part

3: On-site programmable gate array chip

4: High-speed communication cable

5: Capacitance

6: Main computer

7: functional unit

Claims (6)

A high-speed synchronous trigger bus circuit includes a central control board part and a test board part. The central control board part and the test board part each include a field programmable gate array chip, a circuit interface and a high-speed communication Interface, where the field programmable gate array chip has two ports of synchronous signal output and two ports of synchronous signal receiver, the field programmable gate array chip of the central control board part is connected to a host computer via the circuit interface The field programmable gate array chip of the test board part is connected to a functional unit of a chip test device via the circuit interface, and the synchronization signal output terminal of the central control board part is connected to the test The synchronization signal receiving end of the board part, the synchronization signal output end of the test board part and the synchronization signal receiving end of the central control board part are all connected to each other via a high-speed communication cable. For example, the high-speed synchronous trigger bus circuit of claim 1, wherein the central control board part and the test board part do not share the ground, so as to effectively isolate the low-frequency disturbance between the boards. For example, the high-speed synchronization trigger bus circuit of claim 1, wherein the synchronization signal output terminal and the synchronization signal receiving terminal of the field programmable gate array chip are low voltage differential signal (LVDS) signal ports. For example, the high-speed synchronous trigger bus circuit of claim 1, wherein the high-speed communication cable is a differential coaxial cable. For example, the high-speed synchronization trigger bus circuit of claim 1, wherein a capacitor is connected to each of the two-port synchronization signal receiving ends of the field programmable gate array chip for DC isolation. For example, the high-speed synchronous trigger bus circuit of claim 5, wherein the capacitance of the capacitor is 10 NaFarads.

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