TWM607959U - Structure of wafer holding plate - Google Patents

Abstract

This creation provides a wafer support structure with a base, two walls extending from above the base, and a plurality of blocking surfaces extending from below the base. The walls define a carrying space. The structure of the wall and the blocking surfaces of another wafer holder structure is engaged, characterized in that the walls are spaced apart and the cross-section of the walls is ㄇ-shaped, so that the contour of the wall surrounding the wafer Increase, because the lateral width of the wall itself is increased, the structural strength of the wall can be improved, and the cracking damage during stacking can be reduced.

Description

Wafer carrier structure

This creation is about a support structure for carrying miniaturized chips, which has the advantage of not being easily damaged.

The semiconductor wafer carrier is used to carry and transport the wafer during the semiconductor manufacturing process. When designing the carrier structure, if the carrier wafer is more stable, the process yield can be relatively ensured. In addition, the wafer carrier is usually stacked Set up to facilitate transportation, therefore, the strength of the load-bearing structure during stacking also needs to be considered.

The new patent M529268 discloses a tray structure, which has a base protruding to form a ring, and is used to carry round wafers. On the side (upper side) carrying the wafers, there are a plurality of convex stoppers and the bottom of the other tray. The limit grooves are clamped and can be stacked in sequence, and the convex limit part is clamped with the limit groove to form a ring-shaped wall above the bearing position. However, as the size of the chip becomes smaller, the lateral width of the convex limit part and the limit groove will be correspondingly reduced, which tends to make the wall formed by the clamping part too thin, which reduces the structural strength and is easy to crack during lamination. damage.

This creation provides a wafer support structure with a base, two walls extending from above the base, and a plurality of blocking surfaces extending from below the base. The walls define a carrying space. The structure of the wall and the blocking surfaces of another wafer holder structure is engaged, characterized in that the walls are spaced apart and the cross-section of the walls is ㄇ-shaped. This structure makes the surrounding chip The increase of the wall contour can increase the horizontal width of the wall itself, improve the structural strength, and reduce the damage caused by the rupture during stacking.

Furthermore, a limiting bump is extended above the wall surface to limit the position of the chip. In addition, a limiting protrusion is extended below the blocking surfaces, and the limiting protrusion is clamped to the space between the two wall surfaces, which facilitates the stacking of a plurality of supporting plate structures.

Further, an inner side surface of the walls defines two inclined planes. The two planes are a straight surface approaching the base and a bearing surface away from the base. The angle between the vertical surface and a bearing direction is between 0 The angle between the bearing surface and a bearing direction is between 20° and 50°.

Further, the thickness of the walls is greater than 0.8 cm to improve the structural strength.

In the following description, the bearing surface of the bearing structure is described as the upper side; when the bearing surface of the bearing structure is placed horizontally, the direction perpendicular to the ground is defined as the bearing direction, which conforms to the common understanding of those skilled in the art.

Please refer to Figures 1 and 2, respectively drawing the upper structure and the lower structure of the wafer carrier structure. The carrier structure has a base 10, two walls 11 extending from the top of the base 10 and spaced apart, and a plurality of The blocking surface 12 extends from below the base 10. The space surrounded by the walls 11 defines a carrying space 20 for accommodating square chips 25 (as shown in FIG. 4).

The two walls 11 are arranged at intervals, and each wall 11 has a long wall and two short walls extending away from the two ends of the long wall, so that the cross-section of the wall 11 is ㄇ-shaped, in other words, the long wall Located on one side of the chip 25 and conforming to the contour of the side of the chip 25, two short walls (of the two walls 11) surround the other side of the chip 25 to locate the other side of the chip 25. The design of the wall 11 structure can increase the lateral width of the wall itself and increase the contour of the wall surrounding the chip, which can improve the structural strength and reduce the cracking damage during lamination. In addition, the thickness of the walls 11 can be greater than 0.8 cm to improve the structural strength.

1 and 4, an inner side surface of the wall 11 defines two inclined planes, a vertical surface 15 close to the base 10 and a bearing surface 16 away from the base 10, the vertical surface 15 and the bearing direction The angle is between 0° and 10°, and the angle between the bearing surface and a bearing direction is between 20° and 50°, so as to reduce the contact position between the bearing surface 16 and the chip 25, and make the chip 25 in the bearing space 20 roughly equal to The state of dangling.

Please refer to Figures 1 to 3, the long walls of the walls 11 are extended upwards with a limiting protrusion 13, which can be engaged with the structure of the blocking surfaces 12 of another wafer carrier structure. The blocking surface 12 extends downwards with a limiting protrusion 14 to engage with the groove between the two short walls, so that the supporting plate structure can be stacked toward the bearing direction, and the limiting protrusion 13 can be used to limit the bearing space 20 In the position where the chip 25 is carried, the limiting bump 14 can shield the chip 25 exposed by the gap between the two walls 11 to protect the chip 25.

10: Pedestal 11: Wall 12: Blocking surface 13,14: Limit bump 15: Upright 16: bearing surface 20: Carrying space 25: chip θ1, θ2: angle

Fig. 1 is a schematic structural view of one side of the bearing structure.

Figure 2 is a schematic structural view of the other side of the bearing structure.

Fig. 3 is a schematic diagram of the assembly of the laminated support plate structure.

Figure 4 is a cross-sectional view of the retainer structure when in use.

10: Pedestal

11: Wall

13: Limit bump

15: Upright

16: bearing surface

20: Carrying space

Claims (7)

A wafer support structure has a base, two walls extending from above the base, and a plurality of blocking surfaces extending from below the base. The walls define a bearing space, and the walls are connected to the base. The structural engagement of the blocking surfaces of another wafer carrier structure is characterized in that the wall surfaces are arranged at intervals and the cross section of the wall surfaces is in the shape of a ㄇ. In the wafer carrier structure of claim 1, wherein at least one of the walls is extended with a limiting bump. According to claim 1, in the wafer carrier structure, a limit bump extends below at least one of the blocking surfaces, and the limit bump is clamped to the space between the two walls. The wafer carrier structure according to claim 1, wherein an inner side of the walls defines two inclined planes. The wafer carrier structure according to claim 1, wherein an inner side surface of the walls defines a straight surface close to the base, and an angle between the vertical surface and a bearing direction is between 0° and 10°. The wafer carrier structure according to claim 1, wherein an inner side surface of the walls defines a bearing surface away from the base, and an angle between the bearing surface and a bearing direction is between 20 degrees and 50 degrees. The wafer carrier structure according to any one of claims 1 to 6, wherein the thickness of the walls is greater than 0.8 cm.

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